Display device, electronic device, and method for manufacturing display device

Abstract

The invention relates to a display device, an electronic device, and a method for manufacturing the display device. The display device includes: a substrate including a light emitting area; an anode electrode on the light emitting region of the substrate and including silver; and an element insulating layer covering an edge of the anode electrode and defining a light emitting opening, in which the anode electrode includes: a first layer on the substrate; a second layer on the first layer; and a third layer on the second layer and including a protruding portion that protrudes further than a side surface of the second layer, and a width of the protruding portion of the third layer is 0.1 [mu] m or less.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0154703, filed on November 4, 2024, and Korean Patent Application No. 10-2025-0008596, filed on January 21, 2025, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to display devices, electronic devices, and methods for manufacturing display devices. Background Technology

[0004] With the development of the information society, the demand for various forms of display devices for displaying images is increasing. For example, display devices are already used in various electronic devices (such as smartphones, digital cameras, laptops, navigation devices, and smart TVs). Such display devices can include flat panel displays (such as liquid crystal displays, field emission displays, or organic light-emitting diode (OLED) displays). Among flat panel displays, OLED displays can include light-emitting elements in each pixel of the display panel that are themselves capable of emitting light, thereby displaying images without the need for a backlight unit that provides light to the display panel. Summary of the Invention

[0005] This disclosure provides a method for patterning an anode electrode suitable for a high-resolution display device and an electronic device for using a high-resolution display device.

[0006] However, the aspects of this disclosure are not limited to those set forth herein. The foregoing and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the specific embodiments of this disclosure given below.

[0007] Details of other implementation methods are included in the detailed embodiments and accompanying drawings.

[0008] In embodiments of this disclosure, the display device includes: a substrate including a light-emitting region; an anode electrode located on the light-emitting region of the substrate and including silver; and an element insulating layer covering the edge of the anode electrode and defining a light-emitting opening, wherein the anode electrode includes: a first layer located on the substrate; a second layer located on the first layer; and a third layer located on the second layer and including a protruding portion that further protrudes compared to the side surface of the second layer, and the width of the protruding portion of the third layer is 0.1 micrometers or less.

[0009] In one embodiment, the first layer may include an upper surface, the upper surface of the first layer including a first portion that does not contact the second layer and a second portion that contacts the second layer, and the width of the first portion is 0.1 micrometers or less.

[0010] In an implementation, the thickness of the second layer may be greater than the thickness of the first layer and the thickness of the third layer.

[0011] In an implementation, the first layer and the third layer may each comprise a transparent conductive material.

[0012] In an embodiment, the light-emitting region may include a first light-emitting region and a second light-emitting region that are adjacent to each other. The display device further includes: a first resonant auxiliary layer that overlaps with the first light-emitting region and is located between the first layer of the anode electrode and the substrate; and a second resonant auxiliary layer that overlaps with the second light-emitting region and is spaced apart from the first resonant auxiliary layer. The thickness of the first resonant auxiliary layer and the thickness of the second resonant auxiliary layer may be different from each other.

[0013] In one embodiment, the display device may include an anode electrode, and the anode electrode is provided in multiple forms to include multiple anode electrodes. A first anode electrode of the multiple anode electrodes may be located on a first resonant auxiliary layer, a second anode electrode of the multiple anode electrodes may be located on a second resonant auxiliary layer, and the first anode electrode and the second anode electrode may be located at different heights.

[0014] In an embodiment, the display device may include an anode electrode, and the anode electrode is provided in multiple forms to include multiple anode electrodes. A first anode electrode of the multiple anode electrodes may overlap with a first light-emitting region, a second anode electrode of the multiple anode electrodes may overlap with a second light-emitting region, and the gap between the second layer of the first anode electrode overlapping with the first light-emitting region and the second layer of the second anode electrode overlapping with the second light-emitting region may be 1.86 micrometers or less.

[0015] In one embodiment, the display device may further include a residual pattern positioned to contact a third layer of the anode electrode and positioned such that the residual pattern surrounds the light-emitting opening, wherein the residual pattern overlaps with a protrusion included in the third layer of the anode electrode.

[0016] In embodiments of this disclosure, a method for manufacturing a display device is provided, the method comprising: forming a first layer, a second layer, and a third layer of an anode electrode on the surface of a resonant auxiliary layer; removing a portion of the third layer by performing a dry etching process; subjecting a portion of the second layer to plasma treatment; performing a cleaning process after plasma treatment; and removing a portion of the first layer by performing a dry etching process.

[0017] In one embodiment, the first and third layers each comprise a transparent conductive material, and the second layer may comprise silver.

[0018] In one embodiment, plasma treatment can be performed using plasma, and the plasma treatment can use a bias power of 0W in the process parameter values ​​of the plasma treatment, wherein the plasma daughter body includes a fluorine-containing gas.

[0019] In one embodiment, the plasma further includes oxygen, and a portion of the plasma-treated second layer may include silver fluoride.

[0020] In one embodiment, the cleaning process may include the use of an organic stripping agent and at least one dissolved silver fluoride in deionized water.

[0021] In one embodiment, the third layer may include a protruding portion that extends further beyond the side surface of the second layer, and the width of the protruding portion may be 0.1 micrometers or less.

[0022] In this implementation, the side surfaces of the first layer, the second layer, and the third layer may be located on the same line.

[0023] In embodiments of this disclosure, an electronic device includes: at least one display device including a substrate, the substrate including a light-emitting region; and a display module, a processor, a memory, and a power module, wherein at least one of the display module, processor, memory, and power module is connected to at least one display device, wherein the at least one display device further includes: an anode electrode located on the light-emitting region of the substrate and comprising silver; and an element insulating layer covering the edge of the anode electrode and defining a light-emitting opening, the anode electrode including: a first layer located on the substrate; a second layer located on the first layer; and a third layer located on the second layer and including a protruding portion that further protrudes compared to the side surface of the second layer, and the width of the protruding portion of the third layer is 0.1 micrometers or less.

[0024] According to the display device and method for manufacturing the display device according to the embodiment, the anode electrode can be patterned by performing a plasma treatment process and a cleaning process. The display device according to the embodiment can form a gap between adjacent light-emitting elements within a suitable range for high-resolution products (e.g., high-resolution display devices and high-resolution electronic devices) by minimizing the overhang structure of the anode electrode.

[0025] It should be noted that the effects of this disclosure are not limited to those described herein, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. Attached Figure Description

[0026] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, wherein:

[0027] Figure 1 An exploded perspective view illustrating the display device according to an embodiment;

[0028] Figure 2 A block diagram illustrating a display device according to an embodiment;

[0029] Figure 3 This is an equivalent circuit diagram of a pixel according to an embodiment.

[0030] Figure 4 To explain the setting Figure 2 A plan view showing the arrangement of multiple pixels in the display area;

[0031] Figure 5 For along Figure 4 A cross-sectional view of the display device according to the embodiment, taken by line X1-X1';

[0032] Figure 6 for Figure 5 An enlarged cross-sectional view of the display element layer that overlaps with the first and second light-emitting regions;

[0033] Figure 7 for Figure 5 Enlarged cross-sectional view of the anode electrode;

[0034] Figure 8 According to another embodiment Figure 5 Enlarged cross-sectional view of the anode electrode;

[0035] Figure 9 A flowchart illustrating a method for manufacturing an anode electrode according to an embodiment;

[0036] Figures 10 to 12 To explain Figure 9 The cross-sectional view of step S100;

[0037] Figure 13 and Figure 15 To explain in Figure 9 A cross-sectional view of the plasma processing procedure during step S200;

[0038] Figure 14 A cross-sectional view illustrating the mechanism of silver fluoride formation;

[0039] Figures 16 to 18 To explain in Figure 9 A cross-sectional view of the cleaning process during step S200;

[0040] Figure 19 and Figure 20 To explain Figure 9 The cross-sectional view of step S300;

[0041] Figure 21 This is a block diagram of an electronic device according to an embodiment; and

[0042] Figure 22 Schematic diagrams illustrating electronic devices according to various embodiments are provided. Detailed Implementation

[0043] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the aspects supported by this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary aspects of this disclosure to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0044] It will be understood that when an element is referred to as "on" another element, it can be directly on the other element, or there can be an intermediary element between them. In contrast, when an element is referred to as "directly on" another element, there is no intermediary element.

[0045] It will be understood that although the terms “first,” “second,” and “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this document, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second part.”

[0046] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a(a)”, “an(an)”, and “the” are intended to include the plural forms (including “at least one”). Thus, when “a” element is referred to in a claim, followed by “the” element, it includes both one element and multiple elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element”. “At least one” is not construed as limited to “a(a)” or “an(an)”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated items. It will be further understood that, when used in this specification, the terms “comprises” and / or “comprising” or “includes” and / or “including” indicate the presence of the described features, areas, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components and / or groups thereof.

[0047] Furthermore, relative terms (e.g., "below" or "bottom" and "above" or "top") may be used herein to describe the relationship between one element and another illustrated in a figure. It will be understood that relative terms are intended to encompass different orientations of a device beyond those depicted in the figure. For example, if a device in a figure is flipped, an element described as being "below" to other elements will then be oriented "above" to those elements. Thus, based on a specific orientation in the figure, the term "below" can encompass both "below" and "above" orientations. Similarly, if a device in a figure is flipped, an element described as being "below" or "under" other elements will then be oriented "above" to those elements. Thus, the term "below" or "under" can encompass both "above" and "below" orientations.

[0048] As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviations determined by a person skilled in the art, considering the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system), for a particular value. For example, the term “about” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] The embodiments are described herein with reference to illustrative cross-sectional illustrations as preferred embodiments. Therefore, variations in the shape of the illustrated area should be anticipated due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to a specific shape of the area as illustrated herein, but rather include deviations in shape due to factors such as manufacturing. For example, an illustrated or described flat area may generally have rough and / or non-linear characteristics. Furthermore, the sharp corners of the illustrated area may be rounded. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the area and are not intended to limit the scope of the claims.

[0051] The embodiments will now be described in detail with reference to the accompanying drawings.

[0052] Figure 1 An exploded perspective view illustrating a display device according to an embodiment. Figure 2 A block diagram illustrating a display device according to an embodiment.

[0053] refer to Figure 1 and Figure 2 The display device 10 according to the embodiment is a device for displaying moving or still images. The display device 10 according to the embodiment can be applied to portable electronic devices (e.g., mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebook computers, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs)). For example, the display device 10 according to the embodiment can be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Optionally, the display device 10 according to the embodiment can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual reality and augmented reality.

[0054] The display device 10 according to the embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0055] The display panel 100 may be formed in a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). In the display panel 100, the angle where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect each other may be formed as a right angle or as a rounded shape with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral and may be formed as other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0056] like Figure 2 As explained herein, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0057] Multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL1 and EL2), and multiple data lines (DL) can be located in the portion overlapping with the display area (DAA).

[0058] Multiple scan lines SL and multiple emit control lines EL1 and EL2 may extend in a first direction (X-axis direction) and may be separated from each other in a second direction (Y-axis direction). In some aspects, multiple data lines DL may extend in the second direction (Y-axis direction) and may be separated from each other in the first direction (X-axis direction). In an embodiment, the multiple scan lines SL may include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines EBL. The multiple emit control lines EL1 and EL2 may include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0059] Multiple pixels PX can be arranged in a matrix in a first direction (X-axis direction) and a second direction (Y-axis direction). Each pixel PX can be connected to any one of the multiple write scan lines GWL, any one of the multiple control scan lines GCL, any one of the multiple bias scan lines EBL, any one of the multiple first emission control lines EL1, any one of the multiple second emission control lines EL2, and any one of the multiple data lines DL. Each pixel PX can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and can emit light from the light-emitting element according to the data voltage.

[0060] The scan driver 610, the light-emitting driver 620, and the data driver 700 may be located in the portion overlapping with the non-display area NDA.

[0061] The scan driver 610 includes multiple scan transistors, and the light-emitting driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed using semiconductor processes and can be formed on a semiconductor substrate (…). Figure 5 On the SUB in the image. For example, multiple scanning transistors and multiple light-emitting transistors can be formed of complementary metal-oxide-semiconductor (CMOS). Figure 2 The present invention describes that the scan driver 610 is disposed on the left side of the display area DAA and the light-emitting driver 620 is disposed on the right side of the display area DAA, but the embodiments thereof are not limited thereto. For example, each of the scan driver 610 and the light-emitting driver 620 may be disposed on both the left and right sides of the display area DAA.

[0062] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0063] The light-emitting driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal according to the transmit timing control signal ECS and output the first transmit control signal sequentially to the first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal according to the transmit timing control signal ECS and output the second transmit control signal sequentially to the second transmit control line EL2.

[0064] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed by semiconductor processes and may be formed on a semiconductor substrate. Figure 5 On the SUB in the CMOS. For example, multiple data transistors can be formed by CMOS.

[0065] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the converted analog data voltage to the data line DL. In this case, at least one of a plurality of pixels PX can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected pixel PX.

[0066] In a third direction (Z-axis direction) that is the thickness direction of the display panel 100, the heat dissipation layer 200 may overlap with the display panel 100. The heat dissipation layer 200 may be located on one surface of the display panel 100 (e.g., the rear surface of the display panel 100). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or metal (e.g., silver (Ag), copper (Cu), or aluminum (Al)) having a high thermal conductivity.

[0067] The circuit board 300 can be electrically connected to the pad portion of the display panel 100 using conductive adhesive components (e.g., anisotropic conductive film). The circuit board 300 can be a flexible printed circuit board or a flexible film formed of a flexible material. Figure 1 The diagram illustrates that the circuit board 300 is unfolded, but it can also be bent. In this case, one end of the circuit board 300 can be located on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. This end of the circuit board 300 can be the opposite end of the circuit board 300 that is electrically connected to the pad portion of the display panel 100 using a conductive adhesive member.

[0068] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the light-emitting driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0069] The power supply circuit 500 can generate multiple panel driving voltages based on an external power supply voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply the generated driving voltages VSS, VDD, and VINT to the display panel 100. (See later...) Figure 3Describe the details of the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT.

[0070] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 via the circuit board 300. In some aspects, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 via the circuit board 300.

[0071] Optionally, similar to the scan driver 610, the light-emitting driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed by semiconductor processes and may be formed on a semiconductor substrate (…). Figure 5 On the SUB in the CMOS. For example, multiple sequential transistors and multiple power transistors can be formed by CMOS.

[0072] Figure 3 This is an equivalent circuit diagram of a pixel according to an embodiment.

[0073] refer to Figure 3 Pixel PX can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. In some aspects, pixel PX can be connected to a first drive voltage line VSL with a first drive voltage VSS corresponding to a low potential voltage, a second drive voltage line VDL with a second drive voltage VDD corresponding to a high potential voltage, and a third drive voltage line VIL with a third drive voltage VINT corresponding to an initialization voltage. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be a voltage lower than the third drive voltage VINT. The second drive voltage VDD can be a voltage higher than the third drive voltage VINT.

[0074] The pixel PX includes multiple transistors T1 to T6, a light-emitting element ED, a first capacitor CP1, and a second capacitor CP2.

[0075] The light-emitting element (ED) emits light according to the driving current (hereinafter referred to as the "source-drain current") flowing through the channel of the first transistor T1. The amount of light emitted from the ED is proportional to the driving current. The ED may be located between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the ED may be connected to the first driving voltage line VSL. The first electrode of the ED may be an anode electrode, and the second electrode may be a cathode electrode. The ED may be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes, but embodiments of this disclosure are not limited thereto. For example, the ED may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the ED may be a miniature light-emitting diode.

[0076] The first transistor T1 may be a drive transistor that controls the source-drain current flowing between the source and drain electrodes according to the voltage applied to the gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0077] The second transistor T2 may be located between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL and connects one electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL may be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0078] The third transistor T3 may be located between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal controlling the scan line GCL and connects the first node N1 to the second node N2. Accordingly, when the gate electrode and drain electrode of the first transistor T1 are connected to each other, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0079] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal via the first emitter control line EL1, connecting the second node N2 to the third node N3. Correspondingly, the drive current of the first transistor T1 can be supplied to the light-emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0080] The fifth transistor T5 may be located between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL and connects the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light-emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0081] A sixth transistor T6 may be located between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal via the second emitter control line EL2 and connects the source electrode of the first transistor T1 to the second drive voltage line VDL. Correspondingly, a second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0082] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0083] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0084] The first node N1 is the contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element ED.

[0085] Each of the first transistor T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the embodiments of this disclosure are not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Optionally, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0086] Figure 3 The diagram illustrates that pixel PX comprises six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of pixel PX is not limited to... Figure 3 The equivalent circuit diagram is illustrated in the diagram. For example, the number of transistors and capacitors in pixel PX is not limited to... Figure 3 The quantity explained in the text.

[0087] Figure 4 To explain the setting Figure 2 A plan view showing the arrangement of multiple pixels in the display area.

[0088] refer to Figure 4 In this implementation, multiple pixels PX may be located in the portion overlapping with the display area DAA. As an example, pixel PX may include a first pixel SP1, a second pixel SP2, and a third pixel SP3, and the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be spaced apart from each other.

[0089] In one implementation, the first pixel SP1, the second pixel SP2, and the third pixel SP3 may form a pixel group PXG. The pixel group PXG may be the smallest unit that emits white light. However, the type and / or number of pixels PX constituting the pixel group PXG may vary depending on the implementation.

[0090] The first pixel SP1, the second pixel SP2, and the third pixel SP3 may include different light-emitting regions EA. As an example, the first light-emitting region EA1 included in the first pixel SP1 may emit red light of the first color, the second light-emitting region EA2 included in the second pixel SP2 may emit green light of the second color, and the third light-emitting region EA3 included in the third pixel SP3 may emit blue light of the third color, but is not limited thereto.

[0091] The accompanying drawings illustrate that each of the first to third light-emitting regions EA1, EA2, and EA3 has the same size and shape, but the embodiments disclosed herein are not limited thereto. The size and shape of each of the first to third light-emitting regions EA1, EA2, and EA3 can be freely adjusted according to the target or desired characteristics.

[0092] In this embodiment, the light-emitting region EA can be defined by the light-emitting opening OP. This can be achieved by the first element insulating layer (described later). Figure 5 The DIL1 in the diagram defines the light-emitting opening OP.

[0093] According to the embodiment, the non-emitting region NLA can be positioned such that the non-emitting region NLA surrounds each of the first to third emitting regions EA1, EA2, and EA3. The non-emitting region NLA can help prevent the mixing of light emitted from each of the first to third emitting regions EA1, EA2, and EA3.

[0094] Figure 5 For along Figure 4 A cross-sectional view of the display device according to the embodiment, taken along line X1-X1'. Below, Figure 5 The diagram illustrates a schematic cross-sectional structure of the display device 10 that overlaps with the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0095] refer to Figure 5 The display device 10 may include a semiconductor substrate SUB, a transistor layer TFTL, a display element layer EML, a packaging layer TFEL, and a color filter layer CFL.

[0096] The semiconductor substrate SUB can be a substrate or a substrate component. The semiconductor substrate SUB may include a polymer resin (e.g., polyimide (PI)), glass material, or metal material, and may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. As an example, the glass substrate may be a rigid substrate that cannot be bent, and the polymer resin substrate may be a flexible substrate that can be bent or flexibly bent.

[0097] In this implementation, multiple well regions WA may be located within the semiconductor substrate SUB. Depending on the implementation, the well regions WA may also be omitted. The well regions WA may be regions doped with impurities.

[0098] As an example, when the semiconductor substrate SUB includes well regions WA, the semiconductor substrate SUB may be doped with a first type of impurity, and the multiple well regions WA may be regions doped with a second type of impurity. In an example where the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Optionally, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0099] The transistor layer (TFTL) may be located on the semiconductor substrate (SUB). The TFTL may include multiple conductive layers and multiple insulating layers. As an example, the multiple conductive layers may include transistor layers (TR) or connection electrodes (CNE), and the multiple insulating layers may include: an insulating layer (ILD) comprising inorganic materials or a through-hole layer (VA) comprising organic materials.

[0100] In an implementation, the transistor layer TR may include a first transistor layer TR1, a second transistor layer TR2, and a third transistor layer TR3.

[0101] The first transistor layer TR1 may be a transistor provided in the first pixel SP1. For example, the first transistor layer TR1 may be... Figure 3 Any of the transistors illustrated herein. The first transistor layer TR1 may include a first gate G1, a first source S1, and a first drain D1. The channel of the first transistor layer TR1 may be formed in a well region WA between the first source S1 and the first drain D1. The first source S1 and the first drain D1 may be located in the well region WA. The gate insulating layer GTI may be located between the first gate G1 and the well region WA.

[0102] The second transistor layer TR2 may be a transistor provided in the second pixel SP2. The second transistor layer TR2 may include a second gate G2, a second source S2, and a second drain D2. The second source S2 and the second drain D2 may be located in the well region WA. The channel of the second transistor layer TR2 may be formed in the well region WA between the second source S2 and the second drain D2. The gate insulating layer GTI may be located between the second gate G2 and the well region WA.

[0103] The third transistor layer TR3 may be a transistor provided in the third pixel SP3. The third transistor layer TR3 may include a third gate G3, a third source S3, and a third drain D3. The third source S3 and the third drain D3 may be located in the well region WA. The channel of the third transistor layer TR3 may be formed in the well region WA between the third source S3 and the third drain D3. The gate insulating layer GTI may be located between the third gate G3 and the well region WA.

[0104] The insulating layer ILD may be located on the transistor layer TR. The insulating layer ILD may completely cover the transistor layer TR. The insulating layer ILD may include multiple stacked structures.

[0105] The insulating layer ILD may include inorganic insulating materials, such as silicon nitrides (e.g., Si3N4 or SiN). x ), silicon oxide (e.g., SiO2 or SiO) x At least one of ) and silicon oxynitrides (e.g., SiON).

[0106] The connection electrode CNE may be located on the insulating layer ILD. Multiple connection electrodes CNE may be formed, and each connection electrode CNE may be connected to the transistor layer TR through a contact hole penetrating the insulating layer ILD. Specifically, the connection electrode CNE may be connected to at least one of the first drain D1 of the first transistor layer TR1, the second drain D2 of the second transistor layer TR2, and the third drain D3 of the third transistor layer TR3 through a contact hole penetrating the insulating layer ILD.

[0107] The via layer VA can cover the connecting electrode CNE. The via layer VA can flatten the step difference of the underlying structure.

[0108] The through-pore layer VA may include organic materials. As an example, the through-pore layer VA may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0109] The display element layer (EML) may be located on the transistor layer (TFTL). The display element layer (EML) may include a metal pattern (RM), a resonant auxiliary layer (PVX), a first element insulating layer (DIL1), a second element insulating layer (DIL2), and a light-emitting element (ED).

[0110] The metallic pattern RM can be located on the via layer VA in the portion overlapping with the light-emitting region EA. The metallic pattern RM can reflect light emitted from the light-emitting element ED or light incident from the outside.

[0111] The metal pattern RM can be connected to the connection electrode CNE through contact holes in the through-hole layer VA. For example, the metal pattern RM can be electrically connected to the transistor layer TR through the connection electrode CNE.

[0112] The metal pattern RM may be a metal layer comprising a metal (e.g., silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or alloys thereof). In some aspects, the metal pattern RM may include a titanium (Ti) layer and a titanium nitride (TiN) layer located on top of or under the metal layer. In some aspects, the metal pattern RM may further include a transparent conductive material layer (e.g., a metal oxide layer) located on top of or under the metal layer.

[0113] Multiple metal patterns RM can be formed, and the multiple metal patterns RM can be located in the portions overlapping with the first to third light-emitting regions EA1, EA2 and EA3. The metal patterns RM overlapping with each of the first to third light-emitting regions EA1, EA2 and EA3 can be spaced apart from each other.

[0114] The resonant auxiliary layer PVX can be located on the metal pattern RM. Depending on the implementation, the resonant auxiliary layer PVX can completely cover the upper surface of the metal pattern RM, and can also cover the side surface of the metal pattern RM.

[0115] The resonant auxiliary layer PVX may include an inorganic insulating material. For example, the resonant auxiliary layer PVX may include silicon nitrides (e.g., Si3N4 or SiN). x ), silicon oxide (e.g., SiO2 or SiO) x At least one of ) and silicon oxynitrides (e.g., SiON).

[0116] The resonant auxiliary layer PVX can enhance the resonant structure of the light-emitting element ED. As an example, the resonant auxiliary layer PVX may have a height or thickness that can cause constructive interference when light emitted from the light-emitting element ED is reflected by the metallic pattern RM. Accordingly, the display device 10 according to the embodiment can increase the luminous efficiency of the light-emitting element ED.

[0117] The resonant auxiliary layer PVX may include a first resonant auxiliary layer PVX1 overlapping with the first luminescent region EA1, a second resonant auxiliary layer PVX2 overlapping with the second luminescent region EA2, and a third resonant auxiliary layer PVX3 overlapping with the third luminescent region EA3. The first resonant auxiliary layer PVX1, the second resonant auxiliary layer PVX2, and the third resonant auxiliary layer PVX3 may be spaced apart from each other.

[0118] The first resonant auxiliary layer PVX1, the second resonant auxiliary layer PVX2, and the third resonant auxiliary layer PVX3 may have different thicknesses. As an example, the second resonant auxiliary layer PVX2 may have a greater thickness than the first resonant auxiliary layer PVX1, and the third resonant auxiliary layer PVX3 may have a greater thickness than the second resonant auxiliary layer PVX2. However, this is an example, and the embodiments of this disclosure are not limited thereto.

[0119] The light-emitting element (ED) may be located on the resonant auxiliary layer PVX. The ED may include a first light-emitting element ED1 overlapping with a first light-emitting region EA1, a second light-emitting element ED2 overlapping with a second light-emitting region EA2, and a third light-emitting element ED3 overlapping with a third light-emitting region EA3. The first light-emitting element ED1 may include an anode electrode AE, a first light-emitting layer ELL1, and a cathode electrode CE; the second light-emitting element ED2 may include an anode electrode AE, a second light-emitting layer ELL2, and a cathode electrode CE; and the third light-emitting element ED3 may include an anode electrode AE, a third light-emitting layer ELL3, and a cathode electrode CE.

[0120] Figure 6 for Figure 5 An enlarged cross-sectional view of the display element layer that overlaps with the first and second light-emitting regions.

[0121] refer to Figure 5 and Figure 6The anode electrode AE ​​may be located on the resonant auxiliary layer PVX. The anode electrode AE ​​may be located in the portion overlapping with the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, and the anode electrodes AE located in each of the overlapping portions of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be spaced apart from each other.

[0122] The anode electrode AE ​​located in the portions overlapping with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be located at different heights. As an example, the anode electrode AE ​​located in the portion overlapping with the first light-emitting region EA1 can be positioned relatively closest to the semiconductor substrate SUB, and the anode electrode AE ​​located in the portion overlapping with the third light-emitting region EA3 can be positioned relatively farthest from the semiconductor substrate SUB. This can be due to the difference in thickness of the resonant auxiliary layer PVX located beneath the anode electrode AE.

[0123] The anode electrode AE ​​may include a conductive material containing silver (Ag).

[0124] The anode electrode AE ​​may include a first layer A11, a second layer A22, and a third layer A33. The first layer A11, the second layer A22, and the third layer A33 may be stacked in sequence.

[0125] The first layer A11 can be placed as a contact resonant auxiliary layer PVX. The accompanying drawings illustrate that the first layer A11 only covers the upper surface of the resonant auxiliary layer PVX, but the embodiments disclosed herein are not limited to this. The first layer A11 can completely cover the resonant auxiliary layer PVX.

[0126] The first layer A11 can be electrically connected to the metal pattern RM through the contact holes of the penetrating resonant auxiliary layer PVX.

[0127] The first layer A11 may include a transparent conductive material (TCM). As an example, the first layer A11 may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0128] The second layer A22 may be located on the first layer A11. The second layer A22 may include a metal with high reflectivity that can improve the luminous efficiency of the display device 10. As an example, the second layer A22 may include silver (Ag).

[0129] According to the embodiment, the display device 10 can pattern the second layer A22 by a cleaning process following fluorine (F) plasma treatment in the manufacturing process. The manufacturing process will be described later.

[0130] The third layer A33 can be located on the second layer A22.

[0131] The third layer A33 may include a transparent conductive material (TCM). As an example, the third layer A33 may include indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto.

[0132] The thickness of the second layer A22 may be greater than the thickness of the first layer A11 and the thickness of the third layer A33. In this document, the meaning of thickness may be the same as that of height.

[0133] The display device 10 according to the embodiment can be patterned by performing a dry etching process in the manufacturing process to form the first layer A11 and the third layer A33. The manufacturing process will be described later.

[0134] The display device 10 according to the embodiment can be applied to high-resolution electronic devices. This may mean that multiple light-emitting elements ED are located in a small area. In other words, the display device 10 according to the embodiment may include an embodiment in which a narrow gap is formed between the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3.

[0135] In this embodiment, the gap between adjacent light-emitting elements ED can be defined as the gap between adjacent anode electrodes AE. Specifically, the gap between adjacent light-emitting elements ED can be defined as the gap between adjacent second layers A22. That is, the gap between adjacent second layers A22 in the first direction (X-axis direction) can be defined as the element gap Wed between adjacent anode electrodes AE among the first to third light-emitting elements ED1, ED2 and ED3.

[0136] In other words, because the display device 10 according to the embodiment is applied to a high-resolution electronic device, a narrow component gap (Wed) can be formed. As an example, the component gap (Wed) suitable for high-resolution products can be 1.86 micrometers or less. However, this is an example, and the embodiments of this disclosure are not limited thereto.

[0137] The first element insulating layer DIL1 may be located on the via layer VA in the portion overlapping with the non-light-emitting region NLA. The first element insulating layer DIL1 may cover the edge of the resonant auxiliary layer PVX and the edge of the anode electrode AE.

[0138] The first element insulating layer DIL1 can define the light-emitting opening OP and can be positioned such that the first element insulating layer DIL1 surrounds the light-emitting opening OP. The first element insulating layer DIL1 can expose the anode electrode AE ​​in the portion that overlaps with the light-emitting opening OP.

[0139] The first element insulating layer DIL1 may include organic or inorganic insulating materials.

[0140] As an example, when the first element insulating layer DIL1 comprises an organic material, the first element insulating layer DIL1 may comprise acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0141] As an example, when the first element insulating layer DIL1 comprises an inorganic insulating material, the first element insulating layer DIL1 may comprise a silicon nitride (e.g., Si3N4 or SiN). x ), silicon oxide (e.g., SiO2 or SiO) x ), silicon oxynitrides (e.g., SiON), titanium oxides, aluminum oxides or other inorganic insulating materials.

[0142] The second element insulating layer DIL2 may be located on the first element insulating layer DIL1 in the portion overlapping with the non-luminescent region NLA. The second element insulating layer DIL2 may serve as a separator separating the first to third luminescent layers ELL1, ELL2 and ELL3.

[0143] The second element insulating layer DIL2 may include organic or inorganic insulating materials.

[0144] As an example, when the second element insulating layer DIL2 comprises an organic material, the second element insulating layer DIL2 may comprise acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0145] As an example, when the second element insulating layer DIL2 comprises an inorganic insulating material, the second element insulating layer DIL2 may comprise a silicon nitride (e.g., Si3N4 or SiN). x ), silicon oxide (e.g., SiO2 or SiO) x ), silicon oxynitrides (e.g., SiON), titanium oxides, aluminum oxides or other inorganic insulating materials.

[0146] In an example where the first element insulating layer DIL1 and the second element insulating layer DIL2 are made of the same material, the first element insulating layer DIL1 and the second element insulating layer DIL2 may be integrally formed.

[0147] In the third direction (Z-axis direction), the residual pattern TP can be located between the anode electrode AE ​​and the first element insulating layer DIL1. The residual pattern TP can be positioned such that the residual pattern TP surrounds the light-emitting opening OP.

[0148] The residual pattern TP serves as a temporary protective layer to protect the anode electrode AE ​​from the etching process during the manufacturing process of the display device 10, and a portion of the residual pattern TP can be removed by a subsequent etching process, while another portion can retain its currently interpreted form.

[0149] The residual pattern TP may include a transparent conductive material (TCM). As an example, the residual pattern TP may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0150] The residual pattern TP can be located in the portions overlapping the outer peripheries of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, and the residual pattern TP in each of the overlapping portions can be located at different heights. As an example, the residual pattern TP in the portion overlapping the first light-emitting region EA1 can be positioned relatively closest to the semiconductor substrate SUB, and the residual pattern TP in the portion overlapping the third light-emitting region EA3 can be positioned relatively farthest from the semiconductor substrate SUB. This can be due to the difference in thickness of the resonant auxiliary layer PVX located below the anode electrode AE.

[0151] The light-emitting layer ELL can be located on the anode electrode AE. The light-emitting layer ELL may include a first light-emitting layer ELL1 overlapping with the first light-emitting region EA1, a second light-emitting layer ELL2 overlapping with the second light-emitting region EA2, and a third light-emitting layer ELL3 overlapping with the third light-emitting region EA3. The first light-emitting layer ELL1, the second light-emitting layer ELL2, and the third light-emitting layer ELL3 may be spaced apart from each other, and the second element insulating layer DIL2 is inserted between the first light-emitting layer ELL1, the second light-emitting layer ELL2, and the third light-emitting layer ELL3. However, this specification is not limited thereto, and based on the embodiments, the first light-emitting layer ELL1, the second light-emitting layer ELL2, and the third light-emitting layer ELL3 may also be integrally formed.

[0152] For example, the first light-emitting layer ELL1, the second light-emitting layer ELL2, and the third light-emitting layer ELL3 can emit light of the same color or different colors.

[0153] As an example, when the first emitting layer ELL1, the second emitting layer ELL2, and the third emitting layer ELL3 emit light of different colors, the first emitting layer ELL1 can emit red light, the second emitting layer ELL2 can emit green light, and the third emitting layer ELL3 can emit blue light. However, this specification is not limited to this.

[0154] As an example, when the first light-emitting layer ELL1, the second light-emitting layer ELL2, and the third light-emitting layer ELL3 emit light of the same color, the first light-emitting layer ELL1, the second light-emitting layer ELL2, and the third light-emitting layer ELL3 may emit at least one of blue light and white light.

[0155] The cathode electrode CE can be located on the light-emitting layer ELL. The cathode electrode CE can be formed to overlap with the light-emitting region EA and the non-light-emitting region NLA. In other words, the cathode electrode CE can be a common electrode.

[0156] The cathode electrode CE may include a transparent conductive material (TCM) capable of transmitting light (e.g., ITO or IZO) or a semi-transmissive conductive material (e.g., magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)).

[0157] The encapsulation layer TFEL can be located on the display element layer EML. The encapsulation layer TFEL can prevent oxygen or moisture from penetrating into the display element layer EML and can mitigate physical shocks applied to the display element layer EML.

[0158] The encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 may be disposed on the cathode electrode CE, the second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1, and the third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2.

[0159] The first encapsulation layer TFE1 may cover the display element layer EML with the same thickness along the contour of the underlying structure. The first encapsulation layer TFE1 may include an inorganic insulating material. As an example, the first encapsulation layer TFE1 may include a silicon nitride (e.g., Si3N4 or SiN...). x ), silicon oxide (e.g., SiO2 or SiO) x ), silicon oxynitrides (e.g., SiON), titanium oxides, aluminum oxides or other inorganic insulating materials.

[0160] The second encapsulation layer TFE2 can flatten the step difference in the underlying structure. The second encapsulation layer TFE2 may include an organic material. As an example, the second encapsulation layer TFE2 may be an organic film formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0161] The third encapsulation layer TFE3 may include an inorganic insulating material. As an example, the third encapsulation layer TFE3 may include a silicon nitride (e.g., Si3N4 or SiN...). x ), silicon oxide (e.g., SiO2 or SiO) x ), silicon oxynitrides (e.g., SiON), titanium oxides, aluminum oxides or other inorganic insulating materials.

[0162] In this embodiment, the color filter layer CFL may be located on the encapsulation layer TFEL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0163] In one embodiment, the first color filter CF1 may be located in the portion overlapping with the first light-emitting region EA1. The first color filter CF1 may transmit light of a first color (e.g., red light). Accordingly, the first color filter CF1 may transmit light of a first color emitted from the first light-emitting element ED1.

[0164] In one embodiment, the second color filter CF2 may be located in the portion overlapping with the second light-emitting region EA2. The second color filter CF2 may transmit light of a second color (e.g., green light). Accordingly, the second color filter CF2 may transmit light of a second color emitted from the second light-emitting element ED2.

[0165] In one embodiment, the third color filter CF3 may be located in the portion overlapping with the third light-emitting region EA3. The third color filter CF3 may transmit light of a third color (e.g., blue light). Accordingly, the third color filter CF3 may transmit light of a third color emitted from the third light-emitting element ED3.

[0166] Accordingly, light of a first color (e.g., red light) can be emitted from the first light-emitting region EA1, light of a second color (e.g., green light) can be emitted from the second light-emitting region EA2, and light of a third color (e.g., blue light) can be emitted from the third light-emitting region EA3.

[0167] Figure 7 for Figure 5 Enlarged cross-sectional view of the anode electrode.

[0168] Apart from Figures 1 to 6 In addition, refer to Figure 7 The first layer A11 of the anode electrode AE ​​included in the display device 10 may have an upper surface 1a and a side surface 1c. The upper surface 1a of the first layer A11 may be a surface that contacts the second layer A22.

[0169] In one embodiment, the side surface 2c of the second layer A22 may be recessed in the first direction (X-axis direction) compared to the side surface 1c of the first layer A11. Accordingly, a step-like horizontal difference may be formed between the first layer A11 and the second layer A22 of the anode electrode AE ​​included in the display device 10.

[0170] Figure 7 The previous description explained that the side surface 2c of the second layer A22 is a surface in the third direction (Z-axis direction), but the embodiments of this disclosure are not limited to this. Based on the embodiments, the side surface 2c of the second layer A22 may be an inclined surface between the first direction (X-axis direction) and the third direction (Z-axis direction).

[0171] In an embodiment, the upper surface 1a of the first layer A11 may include a first portion ap1 and a second portion ap2. The first portion ap1 may be an exposed portion that is not covered by the second layer A22 (i.e., does not contact the second layer A22), and the second portion ap2 may be a portion that contacts the second layer A22 and is covered by the second layer A22.

[0172] In an implementation, the width Wap1 of the first portion ap1 can be 0.1 micrometers or less. The width Wap1 of the first portion ap1, formed to be 0.1 micrometers or less, can be a major factor in forming a high-resolution product. As a comparative example, when the width Wap1 of the first portion ap1 is formed to be larger than the range described herein, the element gap Wed of the light-emitting element ED may be outside the range suitable for high-resolution products, and therefore, it may be difficult to form the required resolution.

[0173] The third layer A33 of the anode electrode AE ​​can be placed to contact the second layer A22.

[0174] In this embodiment, compared to the side surface 2c of the second layer A22, the side surface 3c of the third layer A33 may protrude in the first direction (X-axis direction). Accordingly, compared to the side surface 2c of the second layer A22, the third layer A33 may have a further protruding tip (also referred to as a protrusion or tip) in the first direction (X-axis direction). In the third direction (Z-axis direction), the tip of the protrusion included in the third layer A33 may overlap with the residual pattern TP.

[0175] In this implementation, the width Wtip of the protruding tip can be 0.1 micrometers or less. The fact that the width Wtip of the protruding tip is 0.1 micrometers or less can be a major factor in forming a high-resolution product. As a comparative example, when the width Wtip of the protruding tip is formed to be greater than the range described herein, the element gap Wed of the light-emitting element ED may be outside the range suitable for high-resolution products, and therefore, it may be difficult to achieve the required resolution.

[0176] Generally, when the anode electrode AE ​​is patterned using a wet etching process, the first layer A11, the second layer A22, and the third layer A33, which include different materials, can have different etching rates. Therefore, compared to the first layer A11 and the third layer A33, the second layer A22 of the anode electrode AE ​​can form a recess of 0.3 micrometers or larger in the first direction (X-axis direction). Due to the characteristics of wet etching processes that use liquid etching solutions, it may be difficult to adjust the width of the second layer A22 recess to less than 0.3 micrometers.

[0177] As another example, when an anode electrode AE ​​containing silver (Ag) is patterned during the manufacturing process by performing a dry etching process, the manufacturing efficiency can be reduced because the reaction temperature of silver (Ag) ions is above 500 degrees Celsius.

[0178] The display device 10 according to an embodiment is characterized in that the anode electrode AE ​​is patterned during the manufacturing process by plasma treatment and cleaning processes. The display device 10 according to an embodiment minimizes the overhang structure of the anode electrode AE ​​by patterning the anode electrode AE ​​during the manufacturing process by plasma treatment and cleaning processes. Specifically, the anode electrode AE ​​included in the display device 10 can be formed such that the width Wap1 of the first portion ap1 included in the first layer A11 and the width Wtip of the protruding tip included in the third layer A33 are 0.1 micrometers or less. Accordingly, the display device 10 according to an embodiment can form an element gap Wed between adjacent light-emitting elements ED within the range suitable for high-resolution products, and can have a resolution of at least 1700 ppi.

[0179] Due to the patterning process conditions, the anode electrode AE ​​can have various shapes.

[0180] Figure 8 According to another embodiment Figure 5 Enlarged cross-sectional view of the anode electrode.

[0181] Apart from Figures 1 to 7 In addition, refer to Figure 8 The first layer A11 of the anode electrode AE ​​included in the display device 10n may have an upper surface 1a and a side surface 1c. The upper surface 1a of the first layer A11 may be a surface that contacts the second layer A22. The upper surface 1a of the first layer A11 included in the display device 10n may be completely covered by the second layer A22.

[0182] The second layer A22 of the anode electrode AE ​​may be located on the upper surface 1a of the first layer A11. The second layer A22 included in the display device 10n may include an upper surface 2a and a side surface 2c.

[0183] The side surface 2c of the second layer A22 included in the display device 10n can be located on the same line as the side surface 1c of the first layer A11. That is, the side surface 1c of the first layer A11 and the side surface 2c of the second layer A22 of the anode electrode AE ​​included in the display device 10n can be free from a step-like horizontal difference, and can be positioned such that the side surface 1c of the first layer A11 and the side surface 2c of the second layer A22 are aligned.

[0184] The third layer A33 can be positioned to contact the second layer A22. The upper surface 2a of the second layer A22 included in the display device 10n can be completely covered by the third layer A33.

[0185] The side surface 3c of the third layer A33 included in the display device 10n can be located on the same line as the side surface 2c of the second layer A22. That is, the side surface 2c of the second layer A22 and the side surface 3c of the third layer A33 of the anode electrode AE ​​included in the display device 10n can be free from step-like horizontal differences, and can be positioned such that the side surface 2c of the second layer A22 and the side surface 3c of the third layer A33 are aligned.

[0186] In other words, the first layer A11, the second layer A22, and the third layer A33 of the anode electrode AE ​​included in the display device 10n may have the same width Wae in the first direction (X-axis direction). However, the meaning of the same width Wae described herein may include values ​​within ±5% of the process tolerance.

[0187] By forming the anode electrode AE ​​during the manufacturing process through plasma treatment and cleaning, the display device 10n may not include a hanging structure for the anode electrode AE. As an example, by forming a first layer A11, a second layer A22, and a third layer A33 such that the widths of the first layer A11, the second layer A22, and the third layer A33 are the same, the anode electrode AE ​​included in the display device 10n may not include a hanging structure for the anode electrode AE. Therefore, the display device 10n can form an element gap Wed between adjacent light-emitting elements ED within the range suitable for high-resolution products. As an example, the element gap Wed between the light-emitting elements ED included in the display device 10n may be 1.86 micrometers or less.

[0188] Figure 9 A flowchart illustrating a method for manufacturing an anode electrode according to an embodiment.

[0189] In describing the methods and processes herein, operations may be performed in a different order than those shown and / or described, or in a different order or at different times. Certain operations may be omitted from the flowchart, one or more operations may be repeated, or additional operations may be added. Following the example aspects described herein, the description of “settable” and “formable” elements, etc., includes methods, processes, and techniques for setting and forming elements, etc.

[0190] refer to Figure 9 According to the embodiment, a display device 10 is used for manufacturing ( Figure 1The method M1 may include: step S100 of forming a first layer, a second layer and a third layer of an anode electrode on the surface of a resonant auxiliary layer, and then removing a portion of the third layer by performing a dry etching process; step S200 of performing a cleaning process after plasma treatment of a portion of the second layer; and step S300 of removing a portion of the first layer by performing a dry etching process.

[0191] Figures 10 to 12 To explain Figure 9 The cross-sectional view of step S100.

[0192] Reference Figures 9 to 12 The step S100 describes forming a first, second, and third layer of an anode electrode on the surface of a resonant auxiliary layer, and then removing a portion of the third layer by performing a dry etching process.

[0193] First, method M1 may include forming a plurality of metal patterns RM on a transistor layer TFTL, and forming a resonant auxiliary layer PVX covering each metal pattern RM. In this process, a first resonant auxiliary layer PVX1, a second resonant auxiliary layer PVX2, and a third resonant auxiliary layer PVX3 with different thicknesses may be formed. Repeated descriptions will be omitted.

[0194] Next, method M1 may include sequentially forming a first conductive layer AE11, a second conductive layer AE22, and a third conductive layer AE33 on the resonant auxiliary layer PVX. The first conductive layer AE11, the second conductive layer AE22, and the third conductive layer AE33 may be deposited over the entire surface. The first conductive layer AE11 and the third conductive layer AE33 may each include a transparent conductive material (TCM), and the second conductive layer AE22 may include silver (Ag).

[0195] The first conductive layer AE11, the second conductive layer AE22, and the third conductive layer AE33 described herein can be formed respectively by the processes described herein. Figures 6 to 8 The first conductive layer A11, the second conductive layer A22, and the third conductive layer A33 are explained in the specification. That is, in this specification, the first conductive layer AE11 and the first conductive layer A11, the second conductive layer AE22 and the second conductive layer A22, and the third conductive layer AE33 and the third conductive layer A33 may each have the same configuration.

[0196] Although not illustrated in the accompanying drawings, method M1 may include placing a temporary protective layer (TPL) on the third conductive layer AE33 of the anode electrode AE, based on an embodiment. The temporary protective layer (TPL) contacts and covers the upper surface of the anode electrode AE, and thus prevents the anode electrode AE ​​from being damaged during subsequent etching processes. In examples that include a temporary protective layer (TPL), the temporary protective layer (TPL) may be formed by subsequent processes as follows: Figure 5 The shape of the residual pattern TP as explained in the text.

[0197] Next, method M1 may include forming a photoresist PR on the third conductive layer AE33, and then performing an etching process. In this process, multiple photoresist PRs may be formed and spaced apart from each other. The etching process in this process may be a dry etching process.

[0198] As an example, a dry etching process can be performed using reactive ion etching (RIE) processes that employ reactive gases (e.g., CHF3, CH3F, CH2F2, and CF4) and sputtering gases (e.g., Ar and O2 / Ar). In this case, an inductively coupled plasma (ICP) source or a capacitively coupled plasma (CCP) source can be used as the plasma source.

[0199] In this process, the portion of the third conductive layer AE33 that does not overlap with the photoresist PR can be removed, thereby exposing the portion of the second conductive layer AE22 located in the portion that does not overlap with the photoresist PR.

[0200] As a result, it can form Figures 6 to 8 The third layer, A33, is explained in the text.

[0201] Figure 13 and Figure 15 To explain in Figure 9 A cross-sectional view of the plasma processing during step S200, and Figures 16 to 18 To explain in Figure 9 A cross-sectional view of the cleaning process during step S200.

[0202] Reference Figure 9 and Figures 13 to 18 Step S200 describes a cleaning process performed after plasma treatment of a portion of the second layer. In this process, the photoresist PR can maintain its state as formed in the previous steps.

[0203] First, method M1 may include performing a plasma processing process on the second conductive layer AE22. This process may use at least one of plasma etching (PE) and reactive ion etching (RIE).

[0204] In this process, the plasma may include fluorine-based gases and oxygen-based gases. As an example, this process can be carried out by mixing fluorine (F)-containing gases (e.g., CHF3, CH3F, CH2F2, and CF4) and oxygen (O2). In this process, the fluorine (F)-containing gas can be used to perform an ionic radical reaction with silver (Ag), and the oxygen (O2) can be used to vaporize carbon (C) into carbon monoxide (CO) and / or carbon dioxide (CO2).

[0205] In this process, the process parameters used to generate plasma may include gas flow rate, pressure, plasma source power, bias power, time, and temperature.

[0206] In this process, the bias power can be set to a value of "0W", and in addition to the bias power, the gas flow rate, pressure, plasma source power, time, and temperature can be set to any suitable range commonly used.

[0207] Generally, in plasma processing, the bias power is provided by a low-frequency power supply that increases the energy of the reactive ions. In this process, in an example where a high bias power is set, the energy of the silver ions included in the anode electrode AE ​​can be increased, which enhances the physical etching properties of the silver ions.

[0208] The manufacturing process of the display device 10 according to the embodiment can minimize the physical etching characteristics of silver (Ag) included in the anode electrode AE ​​by reducing the bias power to zero (bias power = 0W) and improve the chemical reaction characteristics.

[0209] like Figure 15 As explained in the text, through this process, most of the silver (Ag) particles included in the second conductive layer AE22, which does not overlap with the photoresist PR, can be formed as silver fluoride (AgF).

[0210] Figure 14 A cross-sectional view to illustrate the mechanism of silver fluoride formation.

[0211] refer to Figure 14 In this process, method M1 may include forming silver fluoride (AgF) by reacting hydrofluorocarbon gas and oxygen with ionic radicals.

[0212] Specifically, the aforementioned ionic radical reaction can begin on the surface of the second conductive layer AE22, which does not overlap with the photoresist PR, and the ionic radical reaction can penetrate the second conductive layer AE22 as the reaction time Δt elapses. As described herein, maintaining the bias power at zero is a key factor in this process.

[0213] In this process, most of the silver (Ag) particles that do not overlap with the photoresist PR can form silver fluoride (AgF), and some silver peroxide (AgO) can also form between the silver fluoride (AgF). Both silver fluoride (AgF) and silver peroxide (AgO) have high solubility in the cleaning solution of subsequent processes. In some aspects, carbon (C) can react with oxygen (O2) to form carbon monoxide (CO) and / or carbon dioxide (CO2). The reaction rate of this process can be accelerated as the proportion of fluorine in the fluorocarbon gas increases.

[0214] In the intermediate steps of this process, the film density of the second conductive layer AE22 can be temporarily reduced as silver fluoride (AgF) or silver peroxide (AgO) is formed. Therefore, in the intermediate steps of this process, the portion of the second conductive layer AE22 that does not overlap with the photoresist PR can have expansion characteristics.

[0215] The reaction in this process can be represented by the following chemical method.

[0216] Ag + F* → AgF (Solubility of AgF in water at approximately 25°C, 1790 g / L)

[0217] F* can refer to ionized fluorine in the reaction.

[0218] For ease of explanation, this process is described as a single process, but the embodiments of this disclosure are not limited to this. This process can be divided into multiple processes by adjusting process parameter values ​​to form a fine structure. In one example of dividing this process into multiple processes, the second conductive layer AE22 can be finely patterned by dividing it into multiple layers.

[0219] Figures 16 to 18 To explain in Figure 9 A cross-sectional view of the cleaning process during step S200.

[0220] Next, refer to Figures 16 to 18 Method M1 may include a cleaning process. In this process, silver fluoride (AgF) and silver peroxide (AgO) have high solubility in a cleaning solution (e.g., at least one of an organic stripping agent and deionized water (DI)). Therefore, silver fluoride (AgF) and silver peroxide (AgO) can be readily removed by the cleaning solution without any additional process. Accordingly, in this process, silver fluoride (AgF) and some silver peroxide (AgO, not explained) can be completely removed.

[0221] Thus, it can be formed by patterning the second conductive layer AE22 of the anode electrode AE. Figures 6 to 8 The second layer, A22, is explained in the text.

[0222] In some implementations, such as Figure 17 As explained herein, compared to the side surface 2c of the second layer A22, the third layer A33 of the anode electrode AE ​​may have a further protruding tip in the first direction (X-axis direction), and the width of the protruding tip may be 0.1 micrometers or less. Repeated descriptions will be omitted.

[0223] In some implementations, such as Figure 18As explained in the text, the third layer A33 of the anode electrode AE ​​may have a side surface 3c of the third layer A33 located on the same line as the side surface 2c of the second layer A22.

[0224] Step S200 involves a cleaning process following plasma treatment of a portion of the second layer A22 in a micro-step manner. Figure 17 and Figure 18 The anode electrode AE, as explained in the text, can be formed into different shapes. The following will use... Figure 17 The formal description in the text explains the subsequent processes.

[0225] Figure 19 and Figure 20 To explain Figure 9 The cross-sectional view of step S300.

[0226] Reference Figure 9 , Figure 19 and Figure 20 The process S300 describes the removal of a portion of the first layer by performing a dry etching process. In this process, the photoresist PR can maintain its state as formed in the previous steps.

[0227] Next, method M1 may include performing an etching process. As an example, the etching process in this process may be performed as a dry etching process.

[0228] In this process, the portion of the first conductive layer AE11 that does not overlap with the photoresist PR can be removed, thereby forming Figures 6 to 8 The first layer, A11, is explained in the text.

[0229] Refer again Figures 1 to 20 The display device 10 according to the embodiment patterns the anode electrode AE, which includes silver (Ag), by performing a plasma processing process with the bias power reduced to zero (bias power = 0) and then a cleaning process. Accordingly, the display device 10 according to the embodiment can be easily manufactured.

[0230] In some aspects, the display device 10 according to the embodiment may form the width of the protruding tip of the anode electrode AE, which includes silver (Ag), to be 0.1 micrometers or less, thereby forming an element gap Wed between the light-emitting elements ED in the range suitable for high-resolution products.

[0231] Figure 21 This is a block diagram of an electronic device according to an embodiment.

[0232] Apart from Figures 1 to 20 In addition, refer to Figure 21The display device 10 according to the embodiments can be applied to various electronic devices 1. The electronic device 1 according to the embodiments may include the display device 10 described herein, and may further include modules or devices with additional functions in addition to the display device 10.

[0233] The electronic device 1 according to the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0234] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0235] Data information for the operation of processor 12 or display module 11 can be stored in memory 13. In an example where processor 12 executes an application stored in memory 13, image data signals and / or input control signals can be transmitted to display module 11, and display module 11 can process the provided signals and output image information through the display screen.

[0236] The power module 14 may include a power supply module (e.g., a power adapter or battery device) and a power conversion module that converts the power supplied by the power supply module into the power required for the operation of the electronic device 1.

[0237] At least one of the components of the electronic device 1 described herein may be included in the display device according to the embodiments described herein. In some aspects, some of the individual modules that are functionally included in a single module may be included in the display device, while other modules may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided in the form of other devices within the electronic device 1 besides the display device.

[0238] Figure 22 Schematic diagrams illustrating electronic devices according to various embodiments are provided.

[0239] Apart from Figures 1 to 21 In addition, refer to Figure 22The various electronic devices 1 of the display device 10 according to the embodiments may include not only image display electronic devices (e.g., smartphone 1_1a, tablet PC 1_1b, laptop computer 1_1c, TV 1_1d and desktop monitor 1_1e), but also wearable electronic devices (e.g., smart glasses 1_2a, head-mounted display 1_2b and smartwatch 1_2c, etc.) containing display modules, as well as vehicle electronic devices 1_3 containing display modules (e.g., in-vehicle mirror display or central information display (CID) arranged on the dashboard, center console or instrument panel of the vehicle, etc.).

[0240] Those skilled in the art will recognize that this disclosure may be implemented in other specific forms without altering the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described herein are illustrative in all respects and not restrictive. The scope of this specification is indicated by the scope of the claims described herein, and not by the specific embodiments described above, and all changes or modifications arising from the meaning and scope of the claims and their equivalents should be construed as including within the scope of this specification.

[0241] However, the effects of this disclosure are not limited to those stated herein. The foregoing and other effects of this disclosure will become more apparent to those skilled in the art upon reference to the claims.

[0242] This invention should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0243] Although the invention has been specifically illustrated and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: Substrate, including the light-emitting area; An anode electrode is located on the light-emitting region of the substrate and comprises silver; as well as An insulating layer for the component covers the edge of the anode electrode and defines the light-emitting opening. The anode electrode includes: The first layer is located on the substrate; The second layer, located above the first layer; and The third layer, located on top of the second layer, includes a protruding portion that further protrudes compared to the side surface of the second layer, and The width of the protruding portion of the third layer is 0.1 micrometers or less.

2. The display device according to claim 1, wherein: The first layer includes an upper surface. The upper surface of the first layer includes a first portion that does not contact the second layer and a second portion that contacts the second layer, and The width of the first portion is 0.1 micrometers or less.

3. The display device according to claim 2, wherein the thickness of the second layer is greater than the thickness of the first layer and the thickness of the third layer.

4. The display device according to claim 3, wherein the first layer and the third layer each comprise a transparent conductive material.

5. The display device according to claim 1, wherein: The light-emitting area includes a first light-emitting area and a second light-emitting area that are adjacent to each other, and The display device further includes: A first resonant auxiliary layer overlaps with the first light-emitting region and is located between the first layer of the anode electrode and the substrate; and The second resonant auxiliary layer overlaps with the second luminescent region and is spaced apart from the first resonant auxiliary layer. The thicknesses of the first resonant auxiliary layer and the second resonant auxiliary layer are different from each other.

6. The display device according to claim 5, wherein: The display device includes the anode electrode, and the anode electrode is provided in multiple forms to include multiple anode electrodes. The first anode electrode of the plurality of anode electrodes is located on the first resonant auxiliary layer. The second anode electrode of the plurality of anode electrodes is located on the second resonant auxiliary layer, and The first anode electrode and the second anode electrode are located at different heights.

7. The display device according to claim 5, wherein: The display device includes the anode electrode, and the anode electrode is provided in multiple forms to include multiple anode electrodes. The first anode electrode of the plurality of anode electrodes overlaps with the first light-emitting region. The second anode electrode of the plurality of anode electrodes overlaps with the second light-emitting region, and The gap between the second layer of the first anode electrode that overlaps with the first light-emitting region and the second layer of the second anode electrode that overlaps with the second light-emitting region is 1.86 micrometers or less.

8. The display device of claim 1, further comprising a residual pattern positioned to contact the third layer of the anode electrode and positioned such that the residual pattern surrounds the light-emitting opening. The residual pattern thereunder overlaps with the protruding portion included in the third layer of the anode electrode.

9. A method for manufacturing a display device, the method comprising: The first, second, and third layers of the anode electrode are formed on the surface of the resonant auxiliary layer; A portion of the third layer is removed by a dry etching process; A portion of the second layer is subjected to plasma treatment; A cleaning process is performed after the plasma treatment. as well as A portion of the first layer is removed by performing a dry etching process.

10. The method according to claim 9, wherein: The first layer and the third layer each comprise a transparent conductive material, and The second layer includes silver.

11. The method of claim 10, wherein: The plasma treatment is performed using plasma, and The plasma treatment uses a 0W bias power in the process parameter values ​​of the plasma treatment. The plasma daughter product mentioned above includes a fluorine-containing gas.

12. The method according to claim 11, wherein: The plasma further includes oxygen, and The portion of the plasma-treated second layer includes silver fluoride.

13. The method of claim 12, wherein the cleaning process comprises dissolving the silver fluoride using at least one of an organic stripping agent and deionized water.

14. The method according to claim 9, wherein: The third layer includes a protruding portion that further protrudes compared to the side surface of the second layer, and The width of the protruding portion is 0.1 micrometers or less.

15. The method of claim 9, wherein the side surfaces of the first layer, the second layer, and the third layer are located on the same line.

16. An electronic device comprising: The display device according to any one of claims 1 to 8 or the display device manufactured by the method according to any one of claims 9 to 15; as well as The device comprises a display module, a processor, a memory, and a power module, wherein at least one of the display module, the processor, the memory, and the power module is connected to the display device.

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