Package with spacing of less than 50 [mu] m between epitaxial layer and positive side connection body of electronic component

Abstract

A package (100) comprising: an at least partially electrically conductive front-side connection body (102); and an electronic component (104) having an epitaxial layer (118) and assembled with the front-side connection body (102), in which a distance (d) between the epitaxial layer (118) and the front-side connection body (102) is less than 50 [mu] m.

Description

Technical Field

[0001] The various embodiments generally relate to methods of packaging and manufacturing the package. Background Technology

[0002] A package can be represented as an electronic component, in which electrical connections extend out of the package and can be mounted on an electronic periphery, such as on a printed circuit board.

[0003] Packaging cost is a significant driver in the industry. Related to this are performance, size, and reliability. A wide variety of packaging solutions exist, and each must meet the specific application requirements.

[0004] In packaged transistor-type electronic components, Rdson is a quality parameter representing the "drain-source on-resistance". For example, Rdson can indicate the total resistance between the drain and source in a field-effect transistor (FET) when it is in the "on" state. FETs include metal-oxide-semiconductor field-effect transistors (MOSFETs) or junction field-effect transistors (JFETs, i.e., FETs that can be exclusively voltage-controlled and can be used, for example, as electronically controlled switches or resistors). Specifically, Rdson can be used as a basis for the maximum rated current of the electronic component and is also associated with current dissipation. In short, the lower the Rdson, the better.

[0005] However, Rdson in a standard package may be high. Summary of the Invention

[0006] A package with high electrical performance may be required. In particular, a package with low drain-source on-resistance may be required.

[0007] According to an exemplary embodiment, a package is provided, the package including: a front-side connection body, the front-side connection body being at least partially conductive; and an electronic component having an epitaxial layer and assembled with the front-side connection body, wherein the distance between the epitaxial layer and the front-side connection body is less than 50 μm.

[0008] According to another exemplary embodiment, a method for manufacturing a package is provided, wherein the method includes: assembling a positive-side connection body that is at least partially conductive with an electronic component having an epitaxial layer; and arranging the positive-side connection body relative to the electronic component such that the distance between the epitaxial layer and the positive-side connection body is less than 50 μm.

[0009] According to an exemplary embodiment, the package (which may be a semiconductor power package) may be equipped with a partially or fully conductive front-side connection body (such as a clamp, lead frame structure, or another more general substrate) that establishes a connection with the front side of an electronic component (where an active region may be formed). The electronic component may include an epitaxial layer or an active region facing the front-side connection body. The connection between the front-side connection body and the electronic component may be established, for example, by soldering or sintering. Advantageously, the distance between the epitaxial layer and the front-side connection body may be less than 50 μm. It has been found that such a small distance between the active region and the connection body on the front side of the electronic component (e.g., using common interconnect techniques such as soldering, sintering, or (more specifically) diffusion soldering) can generate a considerable amount of mechanical strain on the front side of the electronic component, which may result in a significant reduction in drain-source on-resistance. Therefore, a package with a low Rdson value and thus excellent maximum rated current and low current loss can be obtained. Similarly, in embodiments where the electronic components do not include transistors, the strain applied to the positive side of the electronic components may also have a positive impact on the electrical performance of the package. In particular, semiconductor materials may be included in electronic components that function to modulate current flow. Specifically, structures with such semiconductor content can benefit from the proposed strain engineering concept. Description of further exemplary embodiments

[0010] Further exemplary embodiments of encapsulation and methods will be explained below.

[0011] In the context of this application, the term "package" may specifically refer to an electronic device that may include one or more electronic components mounted on a carrier or having another front and / or back connection body. The components of the package may optionally be at least partially encapsulated by an encapsulating material. Further optionally, one or more conductive interconnect bodies (such as bonding wires) may be implemented in the package, for example for electrically coupling electronic components to the carrier and / or to leads.

[0012] In the context of this application, the term "electronic component" may specifically encompass semiconductor chips (particularly power semiconductor chips), active electronic devices (such as transistors), passive electronic devices (such as capacitors or inductors or ohmic resistors), sensors (such as microphones, light sensors, or gas sensors), light-emitting semiconductor-based devices (such as light-emitting diodes (LEDs) or lasers), actuators (e.g., speakers), and microelectromechanical systems (MEMS). In particular, an electronic component may be a semiconductor chip having at least one integrated circuit element (such as a diode or transistor) in its surface portion. The electronic component may be a bare die or may have been packaged or encapsulated. The semiconductor chip implemented according to exemplary embodiments may be formed using silicon technology, gallium nitride technology, silicon carbide technology, etc. Preferably, at least one electronic component includes a semiconductor chip, more specifically including a metal-oxide-semiconductor field-effect transistor (MOSFET) chip.

[0013] In the context of this application, the term "front-side connection body" may specifically refer to a connection body that is at least partially made of a conductive material such as metal and configured to be attached to the front side of an electronic component. For example, such a front-side connection body may be a clamp (such as a metal plate structure), a carrier (such as a lead frame structure of an electronic component with a flip-chip configuration), or a substrate-type carrier (such as a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal braze (AMB) substrate).

[0014] In the context of this application, the term "epitaxy layer" can refer to a layer, layer sequence, or other structure located on and / or in a surface region of a semiconductor body of an electronic component processed by semiconductor technology for forming at least one integrated circuit element at the epitaxial layer. Specifically, the epitaxial layer can form an active region of the electronic component or a portion thereof. In the context of this application, the term "active region" can specifically refer to a surface region of a semiconductor substrate of an electronic component, on which at least one monolithic integrated circuit element (such as a transistor, diode, capacitor, resistor, etc.) is formed. Specifically, such an active region can form the surface region of the electronic component on its positive side. In a substrate-free chip, the epitaxial structure can be directly connected to the back-side metallization.

[0015] In the context of this application, the term "distance between the epitaxial layer and the positive-side connector" can specifically refer to the spacing between the epitaxial layer and the positive-side connector. This distance can be a constant distance, a minimum distance, or an average distance between the epitaxial layer and the positive-side connector. This distance between the epitaxial layer and the positive-side connector can be bridged by a conductive bonding medium (such as a welding material or a sintering material). Preferably, a diffusion welding material appropriately compatible with such a small distance is preferred.

[0016] In this embodiment, the surface of the main body facing the electronic component is curved, particularly curved in a convex manner. For example, such an embodiment... Figure 3 As shown in the figure. However, it can also be bent in a concave manner or in a complex arrangement of at least one concave and at least one convex segment. Bending the connection surface of the front-side connection body can allow bending of the electronic components during assembly, which can increase stress on the front side of the electronic components and thus improve electrical performance (especially by reducing Rdson).

[0017] In an embodiment, the package includes a conductive connection medium connecting the electronic component to the front-side connection body, wherein, in particular, the connection medium is made of a material having a Young's modulus value of at least 60 GPa at 20°C, and more particularly at least 100 GPa at 20°C. Therefore, the connection between the front-side connection body and the front side of the electronic component can be rigid or brittle to enhance the stress applied to the front side of the electronic component. This can further improve electrical performance (particularly by reducing Rdson).

[0018] In this embodiment, the main connecting body is a clamp. For example, this clamp can be a bent metal plate structure. Such an embodiment is... Figure 2 and Figure 3 As shown in the diagram. The fixture can be a bent or three-dimensional bent metal plate that connects electronic components to the carrier and / or the periphery of another electronic component and / or package. By assembling with a fixture, positive and negative stresses or strains can be applied or enhanced to improve electrical performance.

[0019] In this embodiment, the lateral surface of the fixture is configured to enhance the stress applied to the electronic component. Adjusting the shape and / or size of the side surfaces of the fixture is another design parameter that allows adjustment of the positive lateral stress applied to the electronic component to reduce on-resistance.

[0020] In this embodiment, the front-side connection body is a carrier, and electronic components are mounted on the carrier, for example, in a flip-chip configuration. A corresponding embodiment is, for example, in... Figure 5 As shown in the image.

[0021] In the context of this application, the term "carrier" may specifically refer to a support structure (which may be at least partially conductive) that serves as a mechanical support for one or more electronic components to be mounted thereon, and may also facilitate electrical interconnection between the packaged electronic components (single or multiple) and their surroundings. In other words, a carrier can perform both mechanical support and electrical connection functions. A carrier may comprise a single portion, multiple portions connected via an encapsulation or other packaging component, or a sub-component of a carrier, or may consist of a single portion, multiple portions connected via an encapsulation or other packaging component, or a sub-component of a carrier. When a carrier forms part of a leadframe, it may include die pads. In particular, a carrier may include at least a component assembly section and a lead section. However, a carrier may also be a substrate-type carrier (such as a direct copper bond (DCB) substrate, a direct aluminum bond (DAB) substrate, or an active metal brazing (AMB) substrate).

[0022] In the context of this application, the term "flip-chip configuration of electronic components" may specifically mean that electronic components are inverted such that their front side (rather than their back side) or active regions face or contact the carrier.

[0023] When electronic components are in a flip-chip configuration relative to a carrier, the carrier can act as a positive-side connection body that applies stress or strain to the positive side of the electronic components.

[0024] In another embodiment, in addition to including the front-side connection body, the package also includes a carrier (e.g., a lead frame structure or a substrate structure containing a metal layer), on which electronic components are mounted. This embodiment is exemplified by... Figure 6 As shown in the diagram. For example, it is possible that the back side of the electronic component is mounted on a bottom-side carrier (such as a lead frame structure or substrate), and the top-side front-side connection body (such as a substrate) is mounted on the front side of the electronic component. For example, the carrier can be a substrate structure containing a copper layer, such as a DCB or AMB substrate. For example, an isolation ceramic substrate or lead frame structure can be implemented. The carrier can also be any conductive carrier including copper as a core material and can be plated with layers that may include, for example, Ni, NiP, NiPd, and / or Ag. The carrier can also include a ceramic core layer with copper (or aluminum) plating on both sides of the ceramic core layer (such as a DAB substrate, DCB substrate, or AMB substrate).

[0025] In this embodiment, the surface of the carrier facing the electronic component is curved, particularly in a concave manner. However, it may also be curved in a convex manner or in a complex arrangement of at least one concave and at least one convex segment. Curving the connecting surface of the back carrier allows bending of the electronic component during assembly, which can increase stress on the back side of the electronic component and thus improve electrical performance (particularly by reducing Rdson).

[0026] In an embodiment, the package includes an additional conductive connection medium connecting the electronic component to the carrier, wherein, in particular, the Young's modulus of the additional conductive connection medium is at least 60 GPa at 20°C, and more particularly at least 100 GPa at 20°C. Therefore, the connection between the carrier and the back side of the electronic component can be rigid or brittle to enhance the stress applied to the back side of the electronic component. This can further improve electrical performance (particularly by reducing Rdson). In particular, a double-sided stress-enhanced configuration can be obtained by combining a rigid conductive connection medium between the front-side connection body and the front side of the electronic component.

[0027] In embodiments, the front-side interconnect is: an intermediary, such as a structured intermediary; or a substrate, said substrate comprising, for example, ceramic. In particular, any type of isolation substrate is possible for top-side or front-side interconnects. For example, ceramic material can be provided (directly or indirectly) as a bottom-side or back-side interconnect.

[0028] In an embodiment, the electronic component includes a bulk layer and a metallization layer, wherein an epitaxial layer is located between the bulk layer and the metallization layer, and wherein the epitaxial layer is located closer to the front-side connection body than the bulk layer. For example, the bulk layer can be a semiconductor substrate, particularly a crystalline semiconductor substrate. For example, the bulk layer can include or be composed of silicon. The bulk layer can constitute a majority of the volume of the electronic component, for example, greater than 50% or at least 90% of the volume of the electronic component. The epitaxial layer can be formed in the surface portion of the bulk layer and / or the bulk layer. The epitaxial layer covered by the front-side metallization can form the front side of the electronic component, while the bulk layer covered by the back-side metallization can form the back side of the electronic component. When stress is applied to both sides of the electronic component, a particularly significant improvement in electrical performance and a reduction in on-resistance can be achieved.

[0029] In this embodiment, the thickness of the connection medium between the epitaxial layer, the metallization layer, the electronic component, and the front-side connection body, as well as the thickness of the front-side connection body, has a ratio of 1:at least 2:at least 1:at least 20. Using this ratio, superior properties regarding Rdson can be obtained.

[0030] In embodiments, the thickness of the epitaxial layer ranges from 5 μm to 70 μm, particularly from 5 μm to 30 μm. In embodiments, the thickness of the metallization layer ranges from 1 μm to 20 μm, particularly from 2 μm to 10 μm. In embodiments, the thickness of the interconnect medium ranges from 0.5 μm to 50 μm, particularly from 1.5 μm to 10 μm, and even more particularly from 2 μm to 5 μm. Specifically, a range from 0.5 μm (for ultrathin diffusion bonding) to 50 μm (including some thicker solder or silver sintered layers) is possible. More specifically, this range can be from 1.5 μm to 10 μm (covering the typical diffusion solder range). In embodiments, the thickness of the positive-side interconnect body ranges from 100 μm to 3000 μm. In an embodiment, the thickness of the bulk layer of the electronic component may be less than the thickness of the front-side connecting body, but greater than any of the thicknesses of the epitaxial layer, metallization layer, and connecting medium.

[0031] In this embodiment, the distance between the epitaxial layer and the front-side interconnect is less than 20 μm, and particularly less than 10 μm. Specifically, when a package with a high voltage rating, such as 1200 V, is desired, a very small distance of less than 10 μm may be desirable to meet stringent requirements regarding electrical performance at that voltage level.

[0032] In embodiments, the electronic component is at least one of the following: a semiconductor chip (having a semiconductor bulk body), a transistor chip (particularly a field-effect transistor chip such as a MOSFET or JFET, for which Rdson is an important performance parameter), a power chip (with optimal electronic performance), a vertical chip (experiencing vertical current flow during operation), a silicon carbide chip (particularly advantageous for increasing stress or strain through a corresponding positive-side configuration), a chip with a superjunction (with an inherent configuration that reduces additional on-resistance), a unipolar chip, a bipolar chip, and a chip employing a flip-chip configuration (which can be mounted on only one side, simultaneously achieving positive-side enhancement of strain or stress). However, other configurations of the electronic component are also possible.

[0033] In embodiments, the bonding medium and / or additional bonding media comprise diffusion bonding materials, such as AuSn, NiSn, CuSn, and / or AgSn. Advantageously, diffusion bonding can be performed with very low amounts of solder material, allowing for very small thicknesses of the corresponding bonding medium. Further advantageously, diffusion bonding or diffusion welding can result in very rigid, stiff, or brittle connections, which can further enhance the stress applied to the electronic component, and preferably to its positive side. Therefore, excellent on-resistance behavior can be obtained.

[0034] In embodiments, the connection medium and / or additional connection mediums include sintered materials. Furthermore, sintered materials, such as Ag sintering paste, can be used to establish connections between the front side of the bonding body and the front side of the electronic component, and / or between the back side of the electronic component and the carrier.

[0035] In this embodiment, the thickness of the interconnect medium and / or other interconnect medium is no greater than 20 μm, particularly no greater than 10 μm, and more particularly no greater than 5 μm. This low thickness contribution of the interconnect medium can facilitate a small distance between the epitaxial layer and the positive-side interconnect body, which can lead to excellent electrical performance of the package.

[0036] In the embodiments, the front-side connection body and electronic components are designed such that the stress applied to the electronic components is at least 200 MPa, particularly at least 700 MPa, and more particularly at least 1500 MPa. Such a large stress or strain (especially tensile or compressive strain), particularly when applied to the front side of the electronic components, can result in a very low Rdson value.

[0037] In this embodiment, the front-side connecting body, the electronic component, and the additional carrier on the back side where the electronic component is mounted are designed to apply stress to the electronic component at two opposing main surfaces. This results in a double-sided stress-enhanced configuration, which in turn may lead to excellent electrical properties of the package.

[0038] In an embodiment, the method includes heating the electronic components before and / or during assembly, and allowing the electronic components to be cooled after the assembly. When the electronic components are heated before and / or during assembly and cooled to a lower temperature after assembly, the electronic components can be rigidly connected to the front-side connection body under stress conditions by utilizing the thermal stress generated during the temperature cycle.

[0039] In one embodiment, the method includes bending the electronic components through the assembly. A corresponding embodiment is described in... Figure 3 and Figure 5 As shown in the diagram, bending stress can be applied to the electronic component from the bottom side and / or from the top side, and particularly to the positive side where the active region or epitaxial layer of the electronic component is arranged. This can increase the further stress contribution and thus reduce the on-resistance.

[0040] In an embodiment, the method includes enhancing the stress permanently applied to the electronic components through the assembly. Therefore, the stress is not only applied during the manufacturing process but also preserved within the easily manufactured package. In other words, due to the various measures described herein, the assembled electronic components can still withstand stress, particularly on their front side (and optionally also on their back side). This can allow good electrical performance to be maintained during the long-term use of the package.

[0041] In an embodiment, the method includes adjusting the strain pattern of an electronic component to expose different regions of the electronic component to different strain levels, thereby adjusting the on-resistance characteristics of the electronic component. Specifically, a defined two-dimensional strain or stress pattern can be applied to the front side of the electronic component, and optionally also to its back side. By taking this measure, stress can be specifically applied to various surface portions of the electronic component, wherein the stress has a desired or significant effect on package performance, particularly on the on-resistance of a field-effect transistor type package.

[0042] For example, a desired stress mode can be defined. Subsequently, measures to achieve the desired stress mode can be defined (specifically, adjusting the distance between the epitaxial layer and the front-side interconnect, defining a sufficiently rigid front-side and / or back-side interconnect dielectric, adjusting the semiconductor type of electronic components such as silicon carbide, adjusting the type of electronic components such as superjunctions, etc.). Following the typical co-design procedure, simulations can be performed using the defined measures (one or more), and the simulation results can be compared with the desired stress mode. The measures (one or more) can then be adjusted as needed to achieve better compatibility with the desired stress mode. This process can be iteratively repeated a desired number of times. When a sufficient match has been achieved, a package can be fabricated accordingly.

[0043] In embodiments, encapsulation includes an encapsulant that encapsulates at least a portion of the front-side connection body and at least a portion of the electronic component. In the context of this application, the term "encapsulant" may specifically refer to a substantially electrically insulating material surrounding at least a portion of the electronic component and a portion of the connection body to provide mechanical protection, electrical insulation, and optionally a contribution to heat removal during operation. In particular, the encapsulant may be a molding compound. A molding compound may comprise a matrix of a flowable and hardenable material and filler particles embedded therein. For example, filler particles may be used to modulate the properties of the molded component, particularly to enhance thermal conductivity.

[0044] In embodiments, the package is configured as a power module, such as a molded power module, or a semiconductor power package. For example, an exemplary embodiment of the package may be an intelligent power module (IPM). Another exemplary embodiment of the package is a dual in-line package (DIP).

[0045] In embodiments, the package is configured as one of the following groups: a power module connected by a leadframe, a TransistorOutline (TO) package, a Quad Flat No Leads Package (QFN) package, a Small Outline (SO) package, a Small Outline Transistor (SOT) package, and a Thin Small Outline Package (TSOP) package. Packages for sensors and / or electromechanical devices are also possible embodiments. Furthermore, exemplary embodiments may also relate to packages used as nanobatteries or nanofuel cells, or other devices having chemical, mechanical, optical, and / or magnetic actuators. Therefore, the package according to the exemplary embodiments is fully compatible with standard package concepts (particularly with the standard TO package concept) and externally appears as a conventional package, which is highly user-friendly.

[0046] In this embodiment, the electronic component is a semiconductor power chip. Therefore, the semiconductor component (such as a semiconductor chip) can be used for power applications, for example, in the automotive field, and can, for example, have at least one integrated insulated-gate bipolar transistor (IGBT) and / or at least one other type of transistor (such as a MOSFET, JFET, etc.) and / or at least one integrated diode. Such integrated circuit elements can be fabricated, for example, using silicon technology or based on wide-bandgap semiconductors (such as silicon carbide). In particular, exemplary embodiments can be advantageously implemented for electronic components with vertical current flow. Strain engineering according to exemplary embodiments can be particularly advantageous when the current flow is vertical and is passing through a relatively doped epitaxial layer. In this case, the advantageous nature of the exemplary embodiments is particularly evident. The semiconductor power chip may include one or more field-effect transistors, diodes, inverter circuits, half-bridges, full-bridges, drivers, logic circuits, other devices, etc.

[0047] In this embodiment, the package includes multiple electronic components, particularly semiconductor components, preferably encapsulated by an encapsulant. Therefore, the package may include one or more semiconductor components (e.g., at least one passive component, such as a capacitor, and at least one active component).

[0048] As the substrate or wafer upon which electronic components (single or multiple) are formed, a semiconductor substrate, particularly a silicon substrate, can be used. Alternatively, silicon oxide or another insulating substrate can be provided. Germanium substrates or III-V semiconductor materials can also be implemented. For example, exemplary embodiments can be implemented using GaN or SiC technology.

[0049] The above and other objects, features and advantages will become apparent from the accompanying drawings, the following description and the appended claims, in which like parts or elements are indicated by like reference numerals. Attached Figure Description

[0050] The accompanying drawings, which are included to provide a further understanding of the exemplary embodiments and form part of the specification, illustrate exemplary embodiments.

[0051] In the attached diagram:

[0052] Figure 1 A cross-sectional view of a portion of the package according to an exemplary embodiment is shown.

[0053] Figure 2 A cross-sectional view of the package according to an exemplary embodiment is shown.

[0054] Figure 3 A cross-sectional view of the package according to another exemplary embodiment is shown.

[0055] Figure 4 A plan view and simulation results of the package according to an exemplary embodiment are shown.

[0056] Figure 5 A cross-sectional view of the package according to another exemplary embodiment is shown.

[0057] Figure 6 A cross-sectional view of the package according to another exemplary embodiment is shown.

[0058] Figures 7 to 10 The following is illustrated in the process of manufacturing according to an exemplary embodiment: Figure 10 A cross-sectional view of the structure obtained during the encapsulation method shown.

[0059] Figure 11 A diagram is shown illustrating simulation results of the encapsulation according to an exemplary embodiment.

[0060] Figure 12 A diagram is shown illustrating simulation results of the encapsulation according to an exemplary embodiment.

[0061] Figure 13 The structure shown illustrates the simulation results of the encapsulation according to an exemplary embodiment.

[0062] Figure 14 The structure shown illustrates the simulation results of the encapsulation according to an exemplary embodiment.

[0063] Figure 15 A cross-sectional view of a portion of the package according to an exemplary embodiment is shown.

[0064] Figure 16A diagram is shown illustrating simulation results of the encapsulation according to an exemplary embodiment.

[0065] Figure 17 A cross-sectional view of an encapsulated electronic component according to an exemplary embodiment is shown. Detailed Implementation

[0066] The illustrations in the attached figures are schematic and not to scale.

[0067] Before describing exemplary embodiments in more detail with reference to the accompanying drawings, some general considerations will be outlined based on which exemplary embodiments have been developed.

[0068] Rdson is a critical quality factor for MOSFET-type electronic components. To reduce the on-resistance of vertical power devices, the following techniques can be considered: superjunction architecture (related to front-end technology) and strain engineering (achievable through front-end and back-end technologies).

[0069] However, especially for silicon carbide electronic components, a superjunction architecture alone may not be sufficient to meet stringent on-resistance targets. Even if such a structure (i.e., a superjunction architecture) meets the on-resistance target, the manufacturing effort for such a device can be extremely high.

[0070] Packages formed using silicon carbide MOSFETs with back-end interconnect technology can potentially improve Rdson behavior to some extent. Therefore, strain engineering can be used to improve on-resistance in power packages. Introducing strain into the chip structure using back-end interconnect technology can have a profound impact on Rdson.

[0071] However, back-side interconnects are considered the only back-end approach to leverage strain engineering effects to improve Rdson. Common front-side interconnects are still dominated by wire bonding techniques, which do not allow for the introduction of significant stress into the chip. If other front-side interconnect technologies (especially fixtures) are deployed, it is difficult to utilize strain engineering effects to reduce Rdson because interconnects (most commonly based on Pb solder) have a low Young's modulus, limiting the application of meaningful levels of mechanical stress to the chip.

[0072] According to exemplary embodiments, a package comprising one or more electronic components (particularly semiconductor power chips) can be provided, exhibiting advantageous electrical performance, particularly in terms of drain-source on-resistance. In such a package, a conductive front-side connection body (e.g., a clamp) can be implemented for forming conductive connections at the front side or active regions of one or more electronic components. An epitaxial layer or active region of at least one electronic component can face the front-side connection body and can be connected to the connection body, for example, by diffusion bonding. Advantageously, the distance between the epitaxial layer and the front-side connection body (which can be a minimum, constant, or average distance) can have a very small value of less than 50 μm. Advantageously, this small spacing of the active regions relative to the front-side connection body can apply a certain amount of strain to the front side of the electronic component, which can significantly reduce the drain-source on-resistance of at least one electronic component and the package as a whole. Therefore, the package may have a small Rdson value, which can have a positive impact on the maximum rated current and current dissipation. In short, exemplary embodiments provide strain-induced front-side components.

[0073] Without being bound by any particular theory, it is currently believed that compressive stress applied parallel to the substrate plane can provide a particularly significant Rdson improvement for currents flowing orthogonally to the applied mechanical stress. Among other reasons, it is now believed that the reduction in band edge achieved through a compressive mechanical stress environment can allow more complete trap states to be incorporated into the conduction band, thereby allowing less trap-assisted current to flow through the semiconductor lattice.

[0074] To utilize the crystal strain effect for on-resistance gain as effectively as possible, it may be advantageous to place the stress element as close as possible to the (particularly lightly doped) epitaxial layer of the electronic component. Advantageously, package interconnect techniques can be implemented to apply stress from the epitaxial layer relatively close to the electronic component, i.e., preferably less than 50 μm. Advantageously, package interconnects can be implemented via diffusion bonding (particularly AuSn diffusion bonding interconnects) instead of soft soldering. Advantageously, strain engineering can be applied particularly to silicon carbide devices, preferably via a bending jig architecture. In short, strain in the active region of the electronic component can be tuned by package interconnect parameters that affect Rdson without changing the basic package type or package coverage area. Further advantageously, exemplary embodiments can increase flexibility to achieve appropriate or even optimal class performance at a given package coverage area.

[0075] In contrast to conventional methods, the inventors have considered the possibility of further increasing chip stress by correspondingly designing the front-side interconnects. For example, this can be achieved by assembling a jig-type front-side interconnect body using a hard interface.

[0076] Exemplary embodiments may implement one or more of the following elements for improving electrical performance by increasing strain or stress: Advantageously, a structured jig architecture may be applied to provide a non-planar surface for the front-side metallization of the chip. Advantageously, precision pressing or bending jigs and / or structured intermediaries may be attached to the front side of the electronic component. Moreover, lateral structuring of the jigs for adjusting the strain pattern on the electronic component may be advantageous. Further advantageously, the interconnect between the front-side connection body and the electronic component may be achieved through a connection medium with a high Young's modulus value, which may advantageously result in the rigid interconnect adding stress to the electronic component. Preferably, the front-side connection body may be attached to the electronic component by diffusion bonding (e.g., using AuSn or NiSn as the diffusion bonding connection medium), sintering, etc. Another preferred option may be thermal die attachment (e.g., on a bent lead frame), resulting in a mechanically definable constrained chip environment. The advantage of applying stress from both sides is that there are fewer options for the chip to relax the applied mechanical stress through chip shape deformation. Due to the corresponding formation of the connection between the front-side connection body and the epitaxial layer of the electronic component with mutually perpendicular spacing of less than 50 μm, the exemplary embodiment can increase compressive mechanical stress parallel to the substrate plane in the active chip region. By taking one, some, or all of the above measures, the chip Rdson can be improved by introducing stress through the front side of the electronic component.

[0077] Specifically, the strain mode applied to the electronic component can be adjusted by changing or adapting the fixture shape. In particular, stress absorption can modulate the bandgap of the semiconductor material of the electronic component, which is especially evident and advantageous for silicon carbide-based electronic components. For silicon carbide, preferably, the connection between the epitaxial layer of the electronic component and the front-side interconnect body can be configured such that stress absorption occurs orthogonally to the c-plane of the crystal. This has proven to result in particularly effective bandgap modulation.

[0078] To avoid being bound by a specific theory, it is currently believed that a large number of interface states (e.g., located at the SiC-polysilicon (poly) interface) are about 0.2 eV lower in energy than the conduction band. The small bandgap reduction caused by stress absorption can bind these states into the conduction band. This can reduce the portion of trap-mediated transport that is detrimental to performance during current conduction. Furthermore, it is currently believed that compressive stress along the c-plane of the crystal may be particularly suitable for improving Rdson in devices that rely on vertical current flow. This compressive stress can allow a larger proportion of trap states to bind into the conduction band, thereby reducing Rdson.

[0079] In one embodiment, strain engineering on the front side of the electronic component can be used to reduce Rdson, particularly for SiC-type MOSFETs. In yet another embodiment, the increased front-side stress due to the spatially tight connection between the front-side connection body and the epitaxial layer of the electronic component can be synergistically combined with carrier compensation concepts such as superjunction architectures of the electronic component. Additionally or alternatively, the increased front-side stress due to the spatially tight connection between the front-side connection body and the epitaxial layer of the electronic component can be synergistically combined with increased back-side stress to reduce or even minimize potential stress relaxation caused by chip deformation (e.g., through rigid or rigid connections between leadframe-type carriers and the back side of the electronic component).

[0080] In particular, small or even minimized distances (e.g., multilateral, horizontal) mechanical stress source elements to the epitaxial layer can be highly advantageous for improving Rdson. For example, for SiC MOSFETs, it is currently believed that 700 MPa multilateral compressive stress applied to an epitaxial layer with a distance of 10 μm can result in a gain of approximately 3.5% in terms of Rdson.

[0081] Exemplary embodiments may achieve this via a jig with rigid clamp attachment and / or a flip-chip configuration with rigid die attachment. Preferred embodiments may involve silicon-based devices (e.g., including silicon carbide) constructed in an epitaxial layer, a body layer, and at least one metallization layer, and interconnected to a conductive carrier substrate (such as a jig or substrate via a flip-chip configuration) using a connecting layer (e.g., a diffusion bonding layer). Advantageously, the epitaxial layer may be located spatially close to the conductive carrier (such as a jig or flip-chip substrate). Advantageously, the appropriate thickness of the height of the structural elements involved may be as follows: epitaxial layer (5 μm to 30 μm); nearest metallization layer (5 μm to 20 μm); connecting layer (2 μm to 5 μm); conductive carrier substrate (200 μm to 3000 μm); the mentioned structural elements (in the described order) may have a ratio of 1: at least 2 (or less): at least 1 (or less): 20 (or greater).

[0082] Preferably, the bonding layer or bonding medium may comprise a brittle solder material, preferably a diffused solder material, and more preferably a diffused solderable material of AuSn, NiSn, CuSn, or AgSn. Highly advantageously, the distance between the epitaxial layer and the carrier substrate may be less than 10 μm.

[0083] In a preferred embodiment, the surface compressive stress in the epitaxial layer parallel to the chip surface can be greater than 200 MPa, preferably 700 MPa or greater, and most preferably 1500 MPa or greater.

[0084] The semiconductor chip can be a power semiconductor chip, preferably a vertical power semiconductor chip.

[0085] The surface compressive stress in the epitaxial layer parallel to the chip surface can be lower before the semiconductor chip is mounted on the conductive substrate than after mounting.

[0086] In the embodiments, the manufacturing method may be applicable to unipolar or bipolar power chip technology, and may optionally include an internal power chip structure, such as a superjunction architecture.

[0087] ANSIS strain simulation and DFT (density functional theory) calculations provide strong indications of improvements in Rdson behavior.

[0088] Exemplary applications of the exemplary embodiments are high-power applications, such as in the industrial and automotive sectors.

[0089] Advantageously, packages with improved Rdson behavior can reduce manufacturing effort and can lead to chip shrinkage. Furthermore, chip and / or device performance can be improved. Cooling requirements can be relaxed.

[0090] Figure 1 A cross-sectional view of a portion of the package 100 according to an exemplary embodiment is shown.

[0091] The portion of the power package 100 shown illustrates the interface region between the metal front-side connection body 102 and the semiconductor-type electronic component 104. For example, the front-side connection body 102 can be embodied as a clamp (see...). Figure 2 (See attached figure 110), lead frame structure type carrier (see attached figure 110). Figure 5 (See Figure 112) or substrate, which has a central electrical insulator and a thermally conductive sheet, the two opposing main surfaces of which are covered with corresponding metal layers (see Figure 112). Figure 6 (Ref. 120 in the accompanying drawings). For example, electronic component 104 may be a semiconductor die. The front side of electronic component 104 may be connected to a conductive dielectric layer (see Appendix). Figure 2 , 3 Reference numeral 106 in figures 5 or 6 is connected to the front and side connecting body 102.

[0092] More specifically, the electronic component 104 may have an epitaxial layer 118 on top of the semiconductor bulk layer 114. The epitaxial layer 118 may correspond to the active region of the semiconductor die-type electronic component 104 and may include at least one monolithic integrated circuit element, particularly a monolithically integrated field-effect transistor. A metallization layer 116 may be formed on top of the epitaxial layer 118. The metallization layer 116 may include a sequence of stacked metal sublayers. Thus, the electronic component 104 includes a bulk layer 114 and a metallization layer 116, wherein the epitaxial layer 118 is located between the bulk layer 114 and the metallization layer 116, such that the epitaxial layer 118 is closer to the positive side connection body 102 than the bulk layer 114. In other words, the positive side of the electronic component 104 can be connected to the positive side connection body 102 through the connection medium 106 therebetween. The metallization layer 116 of the electronic component 104 can be connected to the positive side connection body 102 through a layer of conductive connection medium 106 therebetween. Preferably, the conductive connection medium 106 can be a layer or film of diffused solder.

[0093] Advantageously, the vertical distance d between the epitaxial layer 118 and the front-side connection body 102 is less than 50 μm, preferably less than 20 μm, and more preferably less than 10 μm. Advantageously, such a small vertical distance d between the epitaxial layer 118 and the front-side connection body 102 can increase a considerable amount of stress or strain on the front side of the electronic component 102, which is very close to its active region. This can improve the electrical performance of the package 100 due to the reduction in Rdson caused by d < 50 μm. The vertical distance d is composed of the thickness d2 of the metallization layer 116 and the thickness d3 of the connection dielectric layer 106. The thickness of the epitaxial layer 118 is denoted as d1. Similarly, from Figure 1 It can be seen that the vertical thickness d4 of the main body 102 and the thickness d5 of the bulk layer 114 of the electronic component 104 can be significantly greater than each of d1, d2 and d3.

[0094] For example, the thickness d1 of the epitaxial layer 118 can range from 5 μm to 30 μm, particularly from 10 μm to 20 μm. For example, the thickness d2 of the metallization layer 116 can range from 5 μm to 20 μm, particularly from 8 μm to 15 μm. In an embodiment, the thickness d3 of the connection medium 106 can range from 2 μm to 5 μm, particularly from 2.5 μm to 4.5 μm. For example, the thickness d4 of the front-side connection body 102 can range from 200 μm to 3000 μm, particularly from 500 μm to 1000 μm. For example, the thickness d5 of the bulk layer 114 can range from 30 μm to 500 μm, particularly from 50 μm to 200 μm. Preferably, the thicknesses d1, d2, d3, and d4 of the epitaxial layer 118, the metallization layer 116, the connecting medium 106, and the front-side connecting body 102 can have a relational link ratio of 1: at least 2: at least 1: at least 20.

[0095] Referring now in more detail to the conductive connection medium 106 connecting the electronic component 104 to the front-side connection body 102, the connection medium 106 may be made of a material having a Young's modulus value of at least 60 GPa or even at least 100 GPa at 20°C. Descriptively speaking, this may result in a rigid connection rather than a flexible connection between the electronic component 104 and the front-side connection body 102, thereby adding a significant amount of stress or strain to the front side of the electronic component 104 in a defined manner.

[0096] Figure 2 A cross-sectional view of the package 100 according to an exemplary embodiment is shown. Figure 2 The package 100 can have a reference Figure 1 The configuration shown and described. The package 100 shown may be a power package.

[0097] Package 100 includes a bottom-side carrier 112, such as a patterned metal plate or lead frame structure made of a metallic material such as copper or aluminum, on which the back side of electronic component 104 is mounted via a conductive connection medium 108. Advantageously, the Young's modulus of the conductive connection medium 108 can be at least 60 GPa at 20°C or even at least 100 GPa. By providing this rigid connection between the carrier 112 and the back side of electronic component 104, stress or strain can be applied to the back side of electronic component 104, which can have a positive impact on electrical performance, more specifically, can reduce Rdson. For example, the connection medium 108 comprises a diffusion bonding material, such as AuSn, NiSn, CuSn, and / or AgSn. Preferably, the connection medium 108 has a thickness of no more than 10 μm or even no more than 5 μm.

[0098] Package 100 may include a metal front-side connection body 102, which is implemented herein as a clamp 110. The clamp 110 may be a bent metal plate, for example, made of copper. Electronic component 104, which may be, for example, a semiconductor die manufactured using silicon carbide technology, may have an epitaxial layer 118 or an active region, which may be assembled with the front-side connection body 102, wherein the distance d between the epitaxial layer 118 and the front-side connection body 102 is less than 50 μm, preferably less than 20 μm or even less than 10 μm (see [link to product description]). Figure 1 The front-side connection body 102 can be connected via a connection medium 106, which may be a thin film of diffused solder, through the assembly of the front side of the electronic component 104.

[0099] Advantageously, the Young's modulus of the conductive connecting medium 106 can be at least 60 GPa at 20°C, or even at least 100 GPa at 20°C. By providing this rigid connection between the clamp 110 and the positive side of the electronic component 104, stress or strain can be applied to the positive side of the electronic component 104, which can have a very significant positive impact on electrical performance, more specifically, reducing Rdson. For example, the connecting medium 106 comprises a diffusion bonding material, such as AuSn, NiSn, CuSn, and / or AgSn. Preferably, the connecting medium 106 has a thickness d3 of no more than 10 μm or even no more than 5 μm.

[0100] It may be advantageous that, due to the described and shown configuration, the front-side connecting body 102 and the electronic component 104 apply a stress of at least 200 MPa, and preferably at least 1500 MPa, to the electronic component 104. Due to the described configuration, the front-side connecting body 102, the electronic component 104, the additional carrier 112 on the back side where the electronic component 104 is mounted, and the connecting media 106, 108 are designed to apply stress to the electronic component 104 at two opposing main surfaces. By configuring the electronic component 104 as a superjunction chip (comparative...) Figure 17 This can further improve electronic performance, particularly Rdson behavior. Through... Figure 2 The aforementioned configuration enables the achievement of dual-sided stress.

[0101] according to Figure 2 The surface of the main body 102 facing the electronic component 104 is flat or planar. Correspondingly, the surface of the carrier 112 facing the electronic component 104 is flat or planar.

[0102] like Figure 2As shown in the diagram, the terminals (e.g., gate terminals) of the electronic component 104 can be connected to the electronic periphery (e.g., to the lead structure) via metal bonding wire 152. Figure 2 (Not shown, connected to carrier 112 and / or another element). The bonding wire 150 can be connected to the terminals of electronic component 104 via bonding structure 152 (such as solder bumps).

[0103] Figure 3 A cross-sectional view of package 100 according to another exemplary embodiment is shown. Figure 3 The package 100 can have a reference Figure 1 The configuration shown and described.

[0104] Figure 3 Implementation examples and according to Figure 2 The difference in the embodiments is particularly that, according to Figure 3 The surface of the main body 102 facing the electronic component 104 is curved in a raised manner. Correspondingly, the surface of the carrier 112 facing the electronic component 104 is curved in a recessed manner. Therefore, Figure 3 An embodiment with a clamp 110 is shown, which presents a curved, non-flat surface region (which can be achieved, for example, by imprinting or bending) to the front side of the chip. The chip front side, combined with the relatively curved mounting surface of the carrier 112, introduces lattice strain into the electronic component 104 to adjust the on-resistance, such as Rdson behavior.

[0105] By connecting the electronic component 104 to the carrier 112 and the fixture 110 through sintering or diffusion bonding, curvature can be fixed during the process. In particular, when the electronic component 104 is manufactured using silicon carbide technology, bending can be applied to a defined crystal orientation, resulting in a significant increase in stress or strain.

[0106] Other bending structures, such as more complex structures, can be implemented for the carrier 112 and / or the fixture 110 to expose different chip regions to different stress or strain levels.

[0107] Figure 4 A plan view (left-hand side) and simulation results (right-hand side) of the package 100 according to an exemplary embodiment are shown.

[0108] Figure 4 The clamp 110 is shown on the left side, which can be electrically coupled to the lead 154 of the package 100.

[0109] Simulation results on the right side show that, due to the packaging architecture described in this paper, a large amount of stress or strain can be applied to the electronic component 104.

[0110] Figure 5A cross-sectional view of package 100 according to another exemplary embodiment is shown. Figure 5 The package 100 can have a reference Figure 1 The configuration shown and described.

[0111] Figure 5 Implementation examples and according to Figure 2 The difference in the embodiments is particularly that, according to Figure 5 The front-side connection body 102 is a carrier 112, and the electronic component 104 is mounted on the carrier 112 in a flip-chip configuration. For example, the carrier 112 may be bent at its connection surface (or may be flat, not shown). The electronic component 104, arranged in a flip-chip configuration, may have its epitaxial layer 118 or active region arranged facing the carrier 112. In a configuration according to... Figure 5 In another embodiment of the chip architecture, the front-side connection body 102 may have a planar connection surface (not shown).

[0112] Figure 6 A cross-sectional view of package 100 according to another exemplary embodiment is shown. Figure 6 The package 100 can have a reference Figure 1 The configuration shown and described.

[0113] Figure 6 Implementation examples and according to Figure 2 The difference in the embodiments is particularly that, according to Figure 6 The fixture 110 is replaced by the substrate 120 as the front-side connecting body 102. More specifically, according to Figure 6 The package 100 includes a bottom-side carrier 112, such as a lead frame structure, on which electronic components 104 are mounted. Furthermore, the front-side connection body 102 is embodied as a substrate 120 comprising ceramic and assembled to the front side of the electronic components 104 via a connection medium 106. Figure 6 In this configuration, the epitaxial layer 118 faces the substrate 120 instead of the carrier 112.

[0114] Still referencing Figure 6 The substrate 120 is implemented herein as an electrically insulating and thermally conductive sheet 158, which is covered on its two opposing main surfaces by respective metal layers 160, 162 (which may be continuous or patterned). For example, the electrically insulating and thermally conductive sheet 158 ​​may be made of ceramic. For example, each of the metal layers 160, 162 may be copper foil. For example, the substrate 120 may be a DCB substrate, a DAB substrate, or an AMB substrate.

[0115] Figures 7 to 10 The following is illustrated in the process of manufacturing according to an exemplary embodiment. Figure 10 A cross-sectional view of the structure obtained during the method of encapsulation 100 shown.

[0116] refer to Figure 7 The back-side carrier 112 is provided with a curved mounting surface for receiving the electronic component 104 thereon. For example, the back-side carrier 112 may include a die pad 164 for accommodating the electronic component 104 and a separate lead structure 166 including one or more leads 154. A connection medium 108 may be formed on the connection surface of the carrier 112 for receiving the back side of the electronic component 104. For example, the connection medium 108 may be a thin film of diffused solder.

[0117] via arrow 168, Figure 7 The image shows the die being placed onto a die pad 164 with the desired geometry (the carrier 112 may be, for example, a lead frame or another substrate).

[0118] In the illustrated configuration, electronic component 104 is a field-effect transistor chip having a source terminal 170, a drain terminal 172, and a gate terminal 174. The drain terminal 172 is disposed on the bottom main surface of electronic component 104 and can be connected to a die pad 164. The source terminal 170 and the gate terminal 174 are disposed side-by-side on the top main surface of electronic component 104. Electronic component 104 experiences vertical current flow during operation.

[0119] refer to Figure 8 The electronic component 104 has reached the mounting surface of the carrier 112.

[0120] refer to Figure 9 A clamp 110, having a curved connection surface facing the electronic component 104, is configured to connect the main body 102 to the front side and is attached to the source pad 170 of the electronic component 104, see arrow 178. In other words, Figure 9 The image shows the clamp 110 being placed onto the die-type electronic component 104. Advantageously, the clamp geometry (in particular its curvature) of the clamp 110 is adapted to the carrier geometry (in particular its curvature) of the carrier 112 (in particular the lead frame structure).

[0121] refer to Figure 10 The conductive positive-side connection body 102 is assembled with the positive side of the electronic component 104 at its epitaxial layer 118. More specifically, the positive-side connection body 102 is arranged relative to the electronic component 104 such that the distance d between the epitaxial layer 118 and the positive-side connection body 102 (see...) Figure 1 The thickness is less than 50 μm. Optionally, but advantageously, the electronic component 104 can be heated before and / or during the assembly, and the electronic component 104 can be cooled after the assembly (e.g., by active or passive cooling). Due to the matching bending geometry of the carrier 112 and the clamp 110, the electronic component 104 can be bent by the assembly (see...). Figure 10 This applies additional strain or stress. Therefore, chip bending can be performed during die attachment and jig attachment formation (preferably via diffusion bonding or sintering). The enhanced stress applied during the illustrated assembly process can be permanent, i.e., also applied to the electronic component 104 after the assembly. The additional stress components can originate from the rigid front-side connection via the connecting medium 106, the short-distance (d) connection between the epitaxial layer 118 and the front-side connection body 102, the rigid back-side connection via the connecting medium 108, the curvature of the carrier 112 and / or jig 110, and the configuration of the electronic component 104 as a silicon carbide die and / or superjunction die. By correspondingly adjusting the above phenomena through the selection of the components of the package 100 and / or the manufacturing method, the two-dimensional strain pattern of the electronic component 104 can be adjusted on the upper and / or bottom sides of the electronic component 104 to expose different regions of the electronic component 104 to different strain levels. This allows for selective adjustment of the on-resistance characteristics of the electronic component 104.

[0122] Figure 11 Figure 200 illustrates simulation results of package 100 according to an exemplary embodiment. Figure 200 has an abscissa 202, along which the copper lead frame thickness is plotted in micrometers. Along the ordinate 204 of Figure 200, stresses parallel to the c-plane of the SiC crystal (in MPa) are plotted. Tensile stress regions are indicated by reference numeral 206, while compressive stress regions are indicated by reference numeral 208. Curve 212 relates to a 55 μm silicon carbide chip, while curve 214 relates to a 110 μm silicon carbide chip. According to... Figure 11 The simulation results involve the top side of the chip. Figure 12 Figure 210 shows simulation results of package 100 according to an exemplary embodiment. Figure 12 The simulation results involve the bottom side of the chip.

[0123] according to Figure 11 and Figure 12 The simulation has been performed based on an unstructured chip. A simplified two-material-bundle approximation has also been performed, incorporating an AuSn interlayer between the Cu leadframe and the unstructured SiC chip. The model was verified using CoolMOS simulation.

[0124] Figure 11 and Figure 12 The simulations demonstrate that compressive stress can be introduced into silicon carbide chips, particularly through packaging interconnect engineering.

[0125] Figure 13 The structure illustrating simulation results of package 100 according to an exemplary embodiment is shown. More specifically, Figure 13The left side shows a cross-sectional view of the package 100 design with different clamp thicknesses. Arrow 190 indicates the direction of increasing clamp thickness. Figure 13 The results of the strain simulation are shown on the right side. Figure 13 The lead frame thickness is 1.27mm.

[0126] Figure 14 The structure illustrating the simulation results of package 100 according to an exemplary embodiment is shown. Figure 14 It shows the relationship with Figure 13 The corresponding simulation results, however, are used for another package type (especially one with different lead frame thickness). Figure 14 The lead frame thickness is 0.5mm.

[0127] Descriptively speaking, Figure 13 and Figure 14 This involves simulation results used to determine which stress can be applied by adjusting the clamp thickness and the carrier thickness. For example... Figure 13 and Figure 14 As shown, the stress applied to the epitaxial layer 118 of the electronic component 104 has a very significant effect on the strain. In particular, for the relatively safe crack 110 and the relatively safe carrier 100 stress, a significant reduction in Rdson can be achieved, for example, 6% to 7%.

[0128] Figure 15 A cross-sectional view of a portion of the package 100 according to an exemplary embodiment is shown.

[0129] More specifically, Figure 15 The typical stacked configuration of the components of electronic component 104 is shown. On the top side, a metallization layer 116 is disposed on top of an epitaxial layer 118, which in turn is disposed on a semiconductor bulk layer 114. On the bottom side, a rear-end metallization 192 is shown as a substrate layer.

[0130] On one hand, the distance d from the epitaxial layer 118 to the front-side interconnect 102 is preferably less than 10 μm. On the other hand, the distance D from the epitaxial layer 118 to the back-side interconnect can be greater than 100 μm (preferably for a voltage rating of 1200 V). The voltage that the chip can block to the greatest extent is mainly defined by the thickness of the epitaxial layer 118. The thickness D can range, for example, between 250 μm and 20 μm.

[0131] Figure 16Figure 220 illustrates simulation results of package 100 according to an exemplary embodiment. Figure 220 has an abscissa 222 along which biaxial strain within the crystal c-plane (see reference numeral 230) is plotted as a percentage. Along the ordinate 224 of Figure 220, the effective carrier mass along the crystal c-axis (see reference numeral 232) is plotted. Arrow 194 indicates the current direction. Data element 226 relates to a 1.27 mm lead frame, while data element 228 relates to a 500 μm lead frame. This simulation evaluates the relative effect of biaxial mechanical stress in the c-plane of a perfect SiC unit cell on the effective carrier mass orthogonal to the stress source plane (indicated by arrow 194). In a first approximation (ignoring typical scattering phenomena), the simulated carrier mass can be considered proportional to the resistance through the SiC unit cell in the direction of the arrow.

[0132] In short, Figure 220 indicates a significant decrease in on-resistance by increasing the positive side stress.

[0133] Figure 17 A cross-sectional view of the electronic component 104 of the package 100 according to an exemplary embodiment is shown.

[0134] The electronic component 104 shown is configured with a superjunction architecture as known to those skilled in the art. However, in addition to one or more of the corresponding measures explained herein, according to exemplary embodiments, similar trench structures may be advantageously implemented in the package 100 to further increase the strain or stress applied to the electronic component 104.

[0135] Specifically, this superjunction type electronic component 104 can integrate charge-balancing, deeply p-doped pillars 180 in the active region of the electronic component 104. The superjunction structure can be used for charge balancing, especially using different doped materials of the same kind.

[0136] In particular, the combination of a front-end superjunction and front-end and / or back-end strain engineering techniques can result in a lower Rdson. Preferably, the superjunction architecture can be implemented in a SiC MOSFET. Attention should be paid to channel effects and implantation process stability. Specifically, applying a partial superjunction combined with front-end strain engineering to reduce manufacturing effort may be advantageous.

[0137] It should be noted that the term "comprising" does not exclude other elements or features, and "a" or "an" does not exclude a plurality. Elements described in association with different embodiments may also be combined. It should also be noted that reference numerals should not be construed as limiting the scope of the claims. Furthermore, the scope of this application is not intended to be limited to specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. A package (100) comprising: At least partially conductive positive side connection body (102); as well as An electronic component (104) having an epitaxial layer (118) is assembled together with the front-side connecting body (102); The distance (d) between the epitaxial layer (118) and the front-side connecting body (102) is less than 50 μm.

2. The package (100) according to claim 1, wherein, The surface of the front-side connecting body (102) facing the electronic component (104) is curved, particularly curved in a raised manner.

3. The package (100) according to claim 1 or 2, comprising a conductive connection medium (106) connecting the electronic component (104) to the front-side connection body (102), wherein, Specifically, the connecting medium (106) is made of a material having a Young's modulus of at least 60 GPa at 20°C, and more particularly at least 100 GPa at 20°C.

4. The package (100) according to any one of claims 1 to 3, wherein, The front and side connecting body (102) is a clamp (110).

5. The package (100) according to claim 4, wherein, The transverse surface of the clamp (110) is configured to enhance the stress applied to the electronic component (104).

6. The package (100) according to any one of claims 1 to 3, wherein, The front-side connecting body (102) is a carrier (112), and the electronic component (104) is mounted on the carrier (112), for example, mounted on the carrier (112) in a flip-chip configuration.

7. The package (100) according to any one of claims 1 to 5, in addition to including the front-side connection body (102), also includes a carrier (112), such as a metal layer or lead frame structure containing a substrate structure, wherein the electronic component (104) is mounted on the carrier (112).

8. The package (100) according to claim 6 or 7, wherein, The surface of the carrier (112) facing the electronic component (104) is curved, particularly curved in a concave manner.

9. The package (100) according to claim 7 or 8, comprising an additional conductive connection medium (108) connecting the electronic component (104) to the carrier (112), wherein, In particular, the Young's modulus of the additional conductive connecting medium (108) is at least 60 GPa at 20°C, and more particularly, at least 100 GPa at 20°C.

10. The package (100) according to any one of claims 1 to 3 or 7 to 9, wherein, The front-side connection body (102) is: an intermediary, such as a structured intermediary; or a substrate (120), such as a ceramic substrate.

11. The package (100) according to any one of claims 1 to 10, wherein, The electronic component (104) includes a bulk layer (114) and a metallization layer (116), and the epitaxial layer (118) is located between the bulk layer (114) and the metallization layer (116), wherein the epitaxial layer (118) is closer to the front-side connecting body (102) than the bulk layer (114).

12. The package (100) according to claim 11, wherein, The thicknesses (d1, d2, d3, d4) of the epitaxial layer (118), the metallization layer (116), the electronic component (104) and the front-side connecting body (102) have a ratio of 1: at least 2: at least 1: at least 20.

13. The package (100) according to any one of claims 1 to 12, comprising at least one of the following features: in, The thickness (d1) of the epitaxial layer (118) is in the range of 5 μm to 70 μm, particularly in the range of 5 μm to 30 μm; The thickness (d2) of the metallization layer (116) is in the range of 1 μm to 20 μm, particularly in the range of 2 μm to 10 μm; The thickness (d3) of the connecting medium (106) is in the range of 0.5 μm to 50 μm, particularly in the range of 1.5 μm to 10 μm, and even more particularly in the range of 2 μm to 5 μm; and The thickness (d4) of the front-side connecting body (102) is in the range of 100 μm to 3000 μm.

14. The package (100) according to any one of claims 1 to 13, wherein, The distance (d) between the epitaxial layer (118) and the front-side connecting body (102) is less than 20 μm, and particularly less than 10 μm.

15. The package (100) according to any one of claims 1 to 14, wherein, The electronic component (104) is at least one of a semiconductor chip, a transistor chip, a power chip, a vertical chip, a silicon carbide chip, a chip with a superjunction, a unipolar chip, a bipolar chip, and a chip with a flip-chip configuration.

16. The package (100) according to any one of claims 3 to 15, comprising at least one of the following features: in, The connecting medium (106) and / or the additional connecting medium (108) include diffusion bonding materials, such as AuSn, NiSn, CuSn and / or AgSn; Wherein, the connecting medium (106) and / or the other connecting medium (108) comprises a sintered material; and The connecting medium (106) and / or the other connecting medium (108) have a thickness (d3) of no more than 20 μm, particularly no more than 10 μm, and even more particularly no more than 5 μm.

17. The package (100) according to any one of claims 1 to 16, wherein, The front-side connecting body (102) and the electronic component (104) are designed such that the stress applied to the electronic component (104) is at least 200 MPa, particularly at least 700 MPa, and more particularly at least 1500 MPa.

18. The package (100) according to any one of claims 1 to 17, wherein, The front connecting body (102), the electronic component (104), and the additional carrier (112) are designed to apply stress to the electronic component (104) at two opposing main surfaces, with the back side of the electronic component (104) mounted on the additional carrier (112).

19. A method of manufacturing a package (100), the method comprising: The positive-side connection body (102), which is at least partially conductive, is assembled with an electronic component (104) having an epitaxial layer (118); as well as The front-side connecting body (102) is arranged relative to the electronic component (104) such that the distance (d) between the epitaxial layer (118) and the front-side connecting body (102) is less than 50 μm.

20. The method of claim 19, comprising at least one of the following features: in, The method includes heating the electronic component (104) before and / or during the assembly, and allowing the electronic component (104) to cool after the assembly. The method includes bending the electronic component (104) through the assembly. The method includes enhancing the stress permanently applied to the electronic component (104) through the assembly; and The method includes adjusting the strain mode of the electronic component (104) to expose different regions of the electronic component (104) to different strain levels, thereby adjusting the on-resistance characteristics of the electronic component (104).

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