Display device

Abstract

An embodiment of the present invention provides a display device including: a substrate including a display area and a non-display area surrounding the display area; a peripheral island portion disposed in the non-display area, the peripheral island portion including a driver island portion and a wiring island portion disposed to be spaced apart from each other; a peripheral bridge portion disposed in the non-display area to connect the driver island portion and the wiring island portion; a gate driving circuit disposed in the driver island portion, the gate driving circuit including a plurality of stages; a plurality of input lines provided in the wiring island portion; and a plurality of output wirings connected to the gate driving circuit to extend toward the display area. The number of the plurality of output wirings disposed on the peripheral bridge portion gradually increases as the plurality of output wirings approach the display area.

Description

Technical Field

[0001] One or more embodiments relate to the structure of a display device, and more specifically, to a flexible display device or a stretchable display device. Background Technology

[0002] With the development of display devices that can visually display electrical signals, various display devices with excellent characteristics such as thin design, light weight, and low power consumption have been introduced. For example, flexible display devices that can be folded or rolled up have been introduced. Recently, research and development on stretchable display devices that can be changed into various shapes has been actively carried out. Summary of the Invention

[0003] Technical issues One or more embodiments include a display device that can be stretched while minimizing the load on the output wiring. However, the embodiments are exemplary and do not limit the scope of disclosure.

[0004] Technical solution According to one or more embodiments, a display device includes: a substrate including a display area and a non-display area surrounding the display area; a peripheral island located in the non-display area and including a driver island and a wiring island spaced apart from each other; a peripheral bridge located in the non-display area and connecting the driver island to the wiring island; a gate driving circuit located in the driver island and including multiple stages; a plurality of first input lines located in the wiring island; and a plurality of output wirings connected to the gate driving circuit and extending toward the display area, wherein the number of output wirings located in the peripheral bridge gradually increases as the output wirings of the plurality of output wirings approach the display area.

[0005] The width of each of the multiple output lines can gradually decrease as the output lines approach the display area.

[0006] The width of the peripheral bridging section in the non-display area can be constant, and the output lines in the multiple output lines can be spaced apart from each other and each can have a maximum width in the peripheral bridging section.

[0007] The drive island and the wiring island can be arranged alternately along the same row in the first direction.

[0008] The output wiring located in the peripheral bridging section may include output wiring that is electrically connected to the output wiring of a stage located in the driver island section of a plurality of stages, which is located in the same row as the peripheral bridging section but further away from the display area than the peripheral bridging section.

[0009] The gate driving circuit may include a first gate driving circuit to an nth gate driving circuit arranged sequentially along a first direction (where n is a natural number of 2 or greater), and the first gate driving circuit is the outermost gate driving circuit among the first gate driving circuit to the nth gate driving circuit, and the nth gate driving circuit may be positioned closer to the display area than the (n-1)th gate driving circuit.

[0010] The driver island may include a first driver island in which a first gate drive circuit is positioned to an nth driver island in which an nth gate drive circuit is positioned, and the peripheral bridge includes a first peripheral bridge connected to the first driver island to an nth peripheral bridge connected to the nth driver island, and the first driver island, the first peripheral bridge, the nth driver island and the nth peripheral bridge may be arranged in the same row.

[0011] In the first peripheral bridging section, the same number of output cables as the number of stages located in the first driver island section can be positioned among multiple output cables.

[0012] In the nth peripheral bridging section, the same number of output cables as the number of stages located in the first driver island to the nth driver island can be positioned.

[0013] The width of the output cable located in the nth outermost bridging section of a multi-output cable can be smaller than the width of the output cable located in the (n-1)th outermost bridging section of a multi-output cable.

[0014] In the nth driver island, a pre-output wire can be positioned among multiple output wires, and the pre-output wire is connected to the stage located in the first driver island to the (n-1)th driver island among multiple stages.

[0015] In the nth peripheral bridging section, pre-output wiring and output wiring of multiple output wiring connected to the stage located in the nth driver island section can be positioned.

[0016] The pre-output wiring located in the nth driver island can extend to the periphery of the stage located in the nth driver island in multiple stages.

[0017] The output wiring connected to the stage located in the nth driver island can be located at the center of the nth peripheral bridge, and the pre-output wiring can be located outside the nth peripheral bridge.

[0018] The pre-output wiring located in the nth driver island can extend through the space defined by multiple stages located in the nth driver island and spaced apart from each other.

[0019] The output wiring connected to the stage located in the nth driver island can be located outside the nth peripheral bridge, and the pre-output wiring can be located at the center of the nth peripheral bridge.

[0020] The gate drive circuit may include at least one of the following: an emit control drive circuit, a bypass drive circuit, an initialization drive circuit, and a data write drive circuit.

[0021] The multiple output lines may include at least one of the following: a transmit control output line configured to transmit the output signal of the transmit control drive circuit, a bypass output line configured to transmit the output signal of the bypass drive circuit, an initialization output line configured to transmit the output signal of the initialization drive circuit, and a data write output line configured to transmit the output signal of the data write drive circuit.

[0022] In the gate drive circuit, the emit control drive circuit, bypass drive circuit, initialization drive circuit, and data write drive circuit can be arranged from the outside of the display device toward the display area in the order stated.

[0023] The peripheral bridging section can be configured as multiple, and in the peripheral bridging section that extends toward the display area and connects to the driver island in which the emission control drive circuit is located, the emission control output wiring can be located.

[0024] In the peripheral bridging section that extends toward the display area and connects to the driver island where the bypass drive circuit is located, among the multiple peripheral bridging sections, transmit control output wiring and bypass output wiring can be located.

[0025] In the peripheral bridge section that extends toward the display area and connects to the driver island section where the initialization drive circuit is located, which is one of the multiple peripheral bridge sections, the transmit control output wiring, bypass output wiring and initialization output wiring can be located.

[0026] In the peripheral bridge section that extends toward the display area and connects to the driver island section where the data write drive circuit is located, among the multiple peripheral bridge sections, there may be transmitter control output wiring, bypass output wiring, initialization output wiring and data write output wiring.

[0027] The width of the transmit control output wiring can be gradually reduced in the order of the driver island in which the bypass drive circuit is located, the driver island in which the initialization drive circuit is located, and the driver island in which the data write drive circuit is located.

[0028] The two stages of the initialization drive circuit and the two stages of the data write drive circuit can each be located in a driver island, and the one stage of the transmit control drive circuit and the one stage of the bypass drive circuit can each be located in a driver island.

[0029] An initialization drive circuit stage and a data write drive circuit stage can each be located in a separate driver island, and a transmit control drive circuit stage and a bypass drive circuit stage can each be located in two separate driver islands.

[0030] An initialization stage of the driver circuit and a data writing stage of the driver circuit can be located in a driver island.

[0031] The initialization drive circuit stage and the data write drive circuit stage can be configured as a single stage.

[0032] The display device may further include: a plurality of main islands spaced apart from each other in the display area; and a main bridging portion connecting the adjacent main islands among the plurality of main islands.

[0033] The planar area of ​​the outer island can be greater than the planar area of ​​one of the multiple main islands.

[0034] The outer bridging section can extend from the center of the side of the outer island section.

[0035] At least one of the multiple stages may be located in the drive island section.

[0036] The planar area of ​​the outer island can be the same as that of one of the main islands.

[0037] The outer bridging section can extend from the corner of the outer island section.

[0038] One of the multiple stages can be located in the driver island.

[0039] Beneficial effects of the invention According to embodiments, a display device can be provided that can prevent damage due to stress concentration and can be stretched in all directions. Furthermore, the display device according to embodiments can provide images of excellent quality by minimizing the load on the output wiring. The above effects are merely examples, and the scope of disclosure is not limited by these effects. Attached Figure Description

[0040] Figure 1 This is a perspective view schematically showing a display device according to an embodiment.

[0041] Figure 2a and Figure 2b It is shown Figure 1A perspective view of the display device stretched in a first direction.

[0042] Figure 2c It is shown Figure 1 A perspective view of the display device stretched in the second direction.

[0043] Figure 2d It is shown Figure 1 A perspective view of the display device in a stretched state in the first and second directions.

[0044] Figure 2e It is shown Figure 1 A perspective view of the display device stretched upwards from a third-party perspective.

[0045] Figure 3 This is a schematic plan view of a display device according to an embodiment.

[0046] Figure 4 This illustrates an embodiment. Figure 3 An enlarged plan view of part A of the display device.

[0047] Figure 5 This is a schematic cross-sectional view showing the main island portion and the main bridge portion located in the display area of ​​the display device according to an embodiment.

[0048] Figures 6a to 6c This is an equivalent circuit diagram showing a sub-pixel of a display device according to an embodiment.

[0049] Figure 7a and Figure 7b This is a schematic cross-sectional view of the main island portion of the display device according to an embodiment.

[0050] Figures 8a to 8g This is a perspective view schematically illustrating an embodiment of an electronic device including a display device according to an embodiment.

[0051] Figure 9 This is a schematic diagram illustrating the construction of a display device according to an embodiment.

[0052] Figure 10 This is a schematic diagram illustrating the gate driving circuit of a display device according to an embodiment.

[0053] Figure 11a It is shown that it includes Figure 10 A circuit diagram of an embodiment of the first emit control stage in the gate drive circuit.

[0054] Figure 11b It is shown that it includes Figure 10 A circuit diagram of an embodiment of the first bypass stage in the gate drive circuit.

[0055] Figure 11c It is shown that, according to the embodiments, it includes Figure 10 The circuit diagram of the first initialization stage in the gate drive circuit.

[0056] Figure 12 This illustrates an embodiment. Figure 3 An enlarged schematic plan view of part B of the display device.

[0057] Figure 13 This illustrates an embodiment. Figure 12 An enlarged schematic plan view of part C of the display device.

[0058] Figure 14 This illustrates a section taken along line I-I' according to an embodiment. Figure 13 A cross-sectional view of a portion of the display device.

[0059] Figure 15 This illustrates an embodiment. Figure 12 An enlarged cross-sectional view of part D of the display device.

[0060] Figure 16 This illustrates the section taken along lines II-II' and III-III' according to an embodiment. Figure 15 A cross-sectional view of a portion of the display device.

[0061] Figure 17 This illustrates an embodiment. Figure 12 An enlarged schematic plan view of part E of the display device.

[0062] Figure 18 This illustrates the section taken along lines VI-VI' and V-V' according to an embodiment. Figure 17 A cross-sectional view of a portion of the display device.

[0063] Figure 19 This illustrates an embodiment. Figure 12 An enlarged schematic plan view of part F of the display device.

[0064] Figure 20 This illustrates the section taken along lines VI-VI' and VII-VII' according to an embodiment. Figure 19 A cross-sectional view of a portion of the display device.

[0065] Figure 21a This is an enlarged schematic plan view showing a portion of a display device according to another embodiment.

[0066] Figure 21b This illustrates a different embodiment. Figure 21a An enlarged schematic plan view of part G of the display device.

[0067] Figure 22a This is an enlarged schematic plan view showing a portion of a display device according to another embodiment.

[0068] Figure 22b This illustrates a different embodiment. Figure 22a A magnified schematic plan view of part H of the display device.

[0069] Figure 23 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment.

[0070] Figure 24 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment.

[0071] Figure 25 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment.

[0072] Figure 26 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment. Detailed Implementation

[0073] Referring now to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the presented embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only with reference to the accompanying drawings to explain aspects of this specification.

[0074] Because the disclosure allows for various modifications and numerous embodiments, certain embodiments will be shown in the accompanying drawings and described in the detailed description. The effects and features of the disclosure, as well as methods for implementing them, will be illustrated by referring to the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and can be implemented in various forms.

[0075] In the following description, embodiments will be described in detail with reference to the accompanying drawings, wherein the same or corresponding elements are always represented by the same reference numerals, and repeated descriptions thereof are omitted.

[0076] Although terms such as "first," "second," etc., can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0077] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0078] It will be understood that the terms “comprising” and “having” are intended to indicate the presence of the features or elements described in the specification and are not intended to exclude the possibility that one or more other features or elements may be present or added.

[0079] It will also be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, that layer, region, or component may be directly on the other layer, region, or component, or may be indirectly on the other layer, region, or component with an intermediary layer, region, or component situated therebetween.

[0080] For ease of explanation, the dimensions of components in the accompanying drawings may be exaggerated or reduced. For example, the disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of explanation.

[0081] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0082] "A and / or B" is used here to select only A, select only B, or select both A and B. "At least one of A and B" is used to select only A, select only B, or select both A and B.

[0083] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, that layer, region, or component may be "directly connected" to said other layer, region, or component, or may be "indirectly connected" to said other layer, region, or component with other layers, regions, or components situated therebetween. For example, when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, that layer, region, or component may be directly electrically connected to said other layer, region, or component, or may be indirectly electrically connected to said other layer, region, or component with intervening layers, regions, or components situated therebetween.

[0084] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0085] Figure 1 This is a schematic perspective view of the display device 1 according to an embodiment. Figure 2a and Figure 2b It is shown Figure 1 A perspective view of the display device 1 in a stretched state in a first direction. Figure 2c It is shown Figure 1 A perspective view of the display device 1 in a stretched state in the second direction. Figure 2d It is shown Figure 1A perspective view of the display device in a stretched state in the first and second directions. Figure 2e It is shown Figure 1 The perspective view of the display device 1 in a state where it is stretched upwards from a third-party perspective.

[0086] Reference Figure 1 The display device 1 may include a display area DA and a non-display area NDA. The display area DA may include multiple pixels. The display device 1 can provide a specific image by using light emitted from the multiple pixels. The non-display area NDA may be located outside the display area DA. The non-display area NDA may surround the entire display area DA.

[0087] The display device 1 can be stretched or compressed in various directions. The display device 1 can be stretched in a first direction (e.g., the x-direction and / or the -x-direction) by an external force applied by a user or an external object. In an embodiment, as... Figure 2a and Figure 2b As shown, the display area DA and / or non-display area NDA of the display device 1 can be stretched in a first direction (e.g., the x-direction and / or the -x-direction). For example, the display area DA and / or non-display area NDA of the display device 1 can be stretched as follows: Figure 2a As shown, it is stretched along the x and -x directions, or it can be as follows: Figure 2b The image shows a stretch along the x-direction with one side fixed.

[0088] The display device 1 can be stretched in a second direction (e.g., the y-direction and / or the -y-direction) by an external force applied by a user or an external object. In an embodiment, as... Figure 2c As shown, the display area DA and / or non-display area NDA of the display device 1 can be stretched in the y-direction and the -y-direction. In another embodiment, the display area DA and / or non-display area NDA of the display device 1 can be stretched in the y-direction or the -y-direction while being fixed on one side.

[0089] The display device 1 can be stretched in multiple directions (e.g., in a first direction (e.g., x-direction and / or -x-direction) and a second direction (e.g., y-direction and / or -y-direction)) by an external force applied by a user or an external object. Figure 2d As shown, the display area DA and / or the non-display area NDA of the display device 1 can be stretched in the ±x and ±y directions.

[0090] The display device 1 can be stretched in a third direction (e.g., the z-direction or -z-direction) by an external force applied by a human body part or an external object. In an embodiment, in Figure 2eIn one embodiment, a portion of the display device 1 (e.g., a portion of the display area DA) protrudes in the z-direction. In another embodiment, a portion of the display device 1 (e.g., a portion of the display area DA) may protrude along the -z-direction (or be recessed along the z-direction).

[0091] Despite Figures 2a to 2e The display device 1 is stretched upward in a first direction, a second direction, and / or a third direction, but the disclosure is not limited thereto. In another embodiment, the display device 1 can be deformed (e.g., bent or twisted) into various irregular shapes along two or more axes.

[0092] Figure 3 This is a schematic plan view of the display device 1 according to an embodiment. As used herein, "plan view" is a view in the height direction (e.g., the z-direction) of the base 100.

[0093] Multiple pixels can be arranged in the display area DA of the display device 1. Each pixel may include a sub-pixel that emits light of a different color. A light-emitting element corresponding to each sub-pixel may be located in the display area DA. Circuitry for applying electrical signals to the light-emitting elements located in the display area DA and transistors electrically connected to the light-emitting elements may be located in a non-display area NDA surrounding the display area DA. A gate driving circuit GDC may be located in a first non-display area NDA1 and a second non-display area NDA2 positioned on opposite sides of the display area DA. The gate driving circuit GDC may include a driver for applying electrical signals to the gate electrode of a transistor electrically connected to the light-emitting element. Although in Figure 3 The gate drive circuit GDC is located in each of the first non-display area NDA1 and the second non-display area NDA2, but the disclosure is not limited thereto. In another embodiment, the gate drive circuit GDC may be located in either the first non-display area NDA1 or the second non-display area NDA2.

[0094] The data drive circuit DDC may be located in a third non-display area NDA3 and / or a fourth non-display area NDA4 that connects the first non-display area NDA1 to the second non-display area NDA2. In an embodiment, in Figure 3 In one embodiment, the data driving circuit DDC is located in the fourth non-display area NDA4. In another embodiment, the data driving circuit DDC may be located in each of the third non-display area NDA3 and the fourth non-display area NDA4.

[0095] Despite Figure 3The data driving circuit DDC is located in the fourth non-display area NDA4 of the display device 1, but the disclosure is not limited thereto. In another embodiment, the display device 1 may further include a flexible circuit board (not shown) electrically connected via terminal units (not shown) located in the fourth non-display area NDA4, and the data driving circuit DDC may be located on the flexible circuit board.

[0096] In some embodiments, the elongation rate of the non-display area NDA may be equal to or less than the elongation rate of the display area DA. In embodiments, the elongation rate of the non-display area NDA may be different for each area. For example, the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3 may have substantially the same elongation rate. However, modifications can be made. For example, the elongation rate of the fourth non-display area NDA4 may be less than the elongation rate of each of the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3.

[0097] Figure 4 This illustrates an embodiment. Figure 3 An enlarged plan view of part A of the display device 1.

[0098] Reference Figure 4 The display device 1 may include main island portions 11 spaced apart from each other in a first direction (e.g., x direction or -x direction) and a main bridging portion 12 connecting adjacent main island portions 11 in the display area DA.

[0099] The main bridging portions 12 can be spaced apart from each other through a first opening CS1 located between the main bridging portions 12. The main bridging portions 12 can be serpentine in shape. For example, as Figure 4 As shown, the main bridging portion 12 may have a general "letter S" shape.

[0100] Each main island 11 can be connected to multiple main bridging sections 12. For example, each main island 11 can be connected to four main bridging sections 12. Two main bridging sections 12 can be located on opposite sides of the main island 11 along a first direction (e.g., the x-direction or the -x-direction), and the remaining two main bridging sections 12 can be located on opposite sides of the main island 11 along a second direction (e.g., the y-direction or the -y-direction). The four main bridging sections 12 can be connected to the four sides of the main island 11 respectively. Each of the four main bridging sections 12 can be adjacent to each of the corners of the main island 11.

[0101] exist Figure 4In the first non-display area NDA1, the display device 1 may include peripheral island portions 21 spaced apart from each other in a first direction (e.g., x direction or -x direction) and a peripheral bridging portion 22 connecting adjacent peripheral island portions 21.

[0102] The peripheral bridging portions 22 can be spaced apart from each other through a second opening CS2 located between the peripheral bridging portions 22. The peripheral bridging portions 22 can have a serpentine shape. For example, as Figure 4 As shown, the peripheral bridging portion 22 may have an approximate "S" shape. The size and / or width of the peripheral bridging portion 22 may differ from the size and / or width of the main bridging portion 12. For example, the size and / or width of the peripheral bridging portion 22 may be larger than the size and / or width of the main bridging portion 12. The radius of curvature of the circular portion of the peripheral bridging portion 22 may differ from the radius of curvature of the circular portion of the main bridging portion 12. For example, the radius of curvature of the circular portion of the peripheral bridging portion 22 may be larger than the radius of curvature of the circular portion of the main bridging portion 12.

[0103] Each peripheral island 21 may be connected to multiple peripheral bridging portions 22. The size and / or width of each peripheral island 21 may differ from the size and / or width of the main island 11. For example, the planar area of ​​the peripheral island 21 may be larger than the planar area of ​​the main island 11. As used herein, the “planar area” of a portion refers to the area of ​​that portion in a plan view. Each peripheral island 21 may be connected to four peripheral bridging portions 22. Two peripheral bridging portions 22 may be located on opposite sides of the peripheral island 21 along a first direction (e.g., the x-direction or the -x-direction), and the remaining two peripheral bridging portions 22 may be located on opposite sides of the peripheral island 21 along a second direction (e.g., the y-direction or the -y-direction). In an embodiment, the four peripheral bridging portions 22 may be connected to the four sides of the peripheral island 21 respectively. Each peripheral bridging portion 22 may be connected to the central portion of each side of the peripheral island 21.

[0104] The peripheral island 21 arranged in any row of the first non-display area NDA1 can correspond to the main island 11 arranged in multiple rows of the display area DA. For example, the peripheral island 21 arranged in any row of the first non-display area NDA1 can correspond to the main island 11 arranged in the i-th row of the display area DA and the main island 11 arranged in the (i+1)-th row of the display area DA (where i is a positive number greater than 0). In another embodiment, the peripheral island 21 of any row can correspond to the main island 11 of n rows (where n is a positive number of 3 or greater).

[0105] A non-display area (e.g., a first non-display area NDA1) may include a first sub-non-display area SNDA1 in which a peripheral island portion 21 and a peripheral bridging portion 22 are positioned, and a second sub-non-display area SNDA2 between the first sub-non-display area SNDA1 and the display area DA. In the second sub-non-display area SNDA2, a sub-bridging portion 23 for connecting the display area DA to the first sub-non-display area SNDA1 may be positioned. One end of the sub-bridging portion 23 may be connected to the peripheral island portion 21, and the other end of the sub-bridging portion 23 may be connected to the main island portion 11. For example, one end of the sub-bridging portion 23 may be connected to the center portion of one side of the peripheral island portion 21, and the other end of the sub-bridging portion 23 may be connected to the center portion of one side of the main island portion 11.

[0106] The sub-bridging portion 23 may have a serpentine shape. In an embodiment, the shape of the sub-bridging portion 23 may differ from the shape of each of the main bridging portion 12 and the peripheral bridging portion 22. The width of the sub-bridging portion 23 may differ from the width of the main bridging portion 12 and the width of the peripheral bridging portion 22. The width of the sub-bridging portion 23 may be greater than the width of the main bridging portion 12 and less than the width of the peripheral bridging portion 22. A third opening CS3 and a fourth opening CS4 with different shapes may be alternately located between the sub-bridging portions 23 in a second direction (e.g., the y-direction or the -y-direction).

[0107] Figure 5 This is a schematic cross-sectional view showing the main island portion 11 and the main bridging portion 12 located in the display area DA of the display device 1 according to an embodiment.

[0108] Reference Figure 5 The main island portion 11 and the main bridge portion 12 located in the display area DA can be spaced apart from each other, and the first opening CS1 is located between the main island portion 11 and the main bridge portion 12. The main island portion 11 may include light-emitting elements (LEDs) and circuitry (e.g., a pixel driving circuit unit PC) electrically connected to each of the LEDs to drive each of the LEDs, and the main bridge portion 12 may include wiring WL electrically connected to the pixel driving circuit unit PC located in the adjacent main island portion 11.

[0109] Regarding the main island portion 11, a buffer layer 101 comprising inorganic insulating material may be located on the substrate 100, and a pixel driving circuit unit PC may be located on the buffer layer 101. An insulating layer IL comprising inorganic and / or organic insulating material may be located between the pixel driving circuit unit PC and the light-emitting element LED. The light-emitting element LED may be located on the insulating layer IL and may be electrically connected to the corresponding pixel driving circuit unit PC. The light-emitting element LED may emit light of different colors or light of the same color. In an embodiment, the light-emitting element LED may emit red, green, and blue light. In some embodiments, the light-emitting element LED may emit white light. In another embodiment, the light-emitting element LED emits red, green, blue, and white light, respectively.

[0110] Substrate 100 may include a polymeric resin, such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In one embodiment, substrate 100 may have a single-layer structure comprising the polymeric resin. In another embodiment, substrate 100 may have a multilayer structure comprising a matrix layer and a barrier layer, the matrix layer comprising the polymeric resin and the barrier layer comprising an inorganic insulating material. Substrate 100 comprising the polymeric resin may be flexible, rollable, or bendable.

[0111] In the embodiments, although in Figure 5 Three pixel driving circuit units PC are located in each main island section 11, and three light-emitting elements LED are respectively connected to the pixel driving circuit unit PC, but the disclosure is not limited thereto. In another embodiment, the number of pixel driving circuit units PC and light-emitting elements LED located in the main island section 11 can be one, two, four or more.

[0112] The encapsulation layer 300 may be located on the light-emitting element (LED) and may protect the LED from external forces and / or moisture penetration. The encapsulation layer 300 may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer 300 may have a structure in which an inorganic encapsulation layer comprising an inorganic insulating material, an organic encapsulation layer comprising an organic insulating material, and an inorganic encapsulation layer comprising an inorganic insulating material are stacked. In another embodiment, the encapsulation layer 300 may include an organic material such as a resin. In some embodiments, the encapsulation layer 300 may include urethane epoxy acrylate. The encapsulation layer 300 may include a photosensitive material (such as a photoresist).

[0113] Regarding the main bridging portion 12, an insulating layer IL comprising an organic insulating material may be located on the substrate 100. Unlike the main island portion 11, the main bridging portion 12, which deforms relatively greatly when the display device 1 is stretched, may not include a layer containing an inorganic insulating material that is prone to cracking.

[0114] In one embodiment, the substrate 100 corresponding to the main bridging portion 12 may have the same stacking structure as the substrate 100 corresponding to the main island portion 11. In another embodiment, the substrate 100 corresponding to the main bridging portion 12 and the substrate 100 corresponding to the main island portion 11 may be polymer resin layers formed together in the same process. In yet another embodiment, the substrate 100 corresponding to the main bridging portion 12 may have a different stacking structure than the substrate 100 corresponding to the main island portion 11. In some embodiments, the substrate 100 corresponding to the main island portion 11 may have a multilayer structure including a matrix layer and a barrier layer, the matrix layer comprising a polymer resin, the barrier layer comprising an inorganic insulating material, and the substrate 100 corresponding to the main bridging portion 12 may have a structure including a polymer resin layer but without a layer comprising an inorganic insulating material.

[0115] As described above, the wiring WL of the main bridge portion 12 can be signal lines (e.g., gate lines and data lines) for providing electrical signals to transistors included in the pixel driving circuit unit PC of the main island portion 11, or voltage lines (e.g., drive voltage lines and initialization voltage lines) for providing voltage. The encapsulation layer 300 may also be located in the main bridge portion 12. In another embodiment, the encapsulation layer 300 may not be located in the main bridge portion 12.

[0116] Reference Figure 4 a to Figure 4 c and Figure 5 The base 100 corresponding to the main island portion 11 and the base 100 corresponding to the main bridging portion 12 can be connected to each other. In other words, Figure 4 a to Figure 4 The plan view of c can be compared with Figure 5 The plan view of the base 100 is substantially the same. In other words, the base 100 may include a region corresponding to the main island portion 11, a region corresponding to the main bridging portion 12, and an opening 100OP1 having the same shape as the first opening CS1.

[0117] Similarly, the encapsulation layer 300 corresponding to the main island portion 11 and the encapsulation layer 300 corresponding to the main bridging portion 12 can be connected to each other. For example, Figure 4 a to Figure 4 The plan view of c can be substantially the same as the plan view of the encapsulation layer 300. In other words, the encapsulation layer 300 may include a region corresponding to the main island portion 11, a region corresponding to the main bridging portion 12, and an opening 300OP1 having the same shape as the first opening CS1.

[0118] The circuit light-emitting element layer 200 located between the substrate 100 and the encapsulation layer 300 may include a buffer layer 101, a pixel driving circuit unit PC, wiring WL, an insulating layer IL, and a light-emitting element LED. Similar to the substrate 100, Figure 4 a to Figure 4 The plan view of c can be substantially the same as the plan view of the circuit light-emitting element layer 200. In other words, the circuit light-emitting element layer 200 can define an opening 200OP1 having the same shape as the first opening CS1.

[0119] Figures 6a to 6c This is an equivalent circuit diagram showing a sub-pixel of the display device 1 according to an embodiment.

[0120] Reference Figure 6a The light-emitting element (LED) corresponding to the sub-pixel can be electrically connected to the pixel driving circuit unit PC, and the pixel driving circuit unit PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel driving circuit unit PC can be electrically connected to signal lines and voltage lines. The signal lines can include a gate line such as a scan signal line GWL and a data line DL, and the voltage lines can include a first voltage line VDDL.

[0121] The second transistor T2 can be electrically connected to the scan signal line GWL and the data line DL. The scan signal line GWL can provide the scan signal GW to the gate electrode of the second transistor T2. The second transistor T2 can transmit the data signal Dm input from the data line DL to the first transistor T1 according to the scan signal GW input from the scan signal line GWL.

[0122] The storage capacitor Cst can be electrically connected to the second transistor T2 and the first voltage line VDDL, and can store a voltage corresponding to the difference between the voltage received from the second transistor T2 and the first power supply voltage VDD supplied by the first voltage line VDDL.

[0123] The first transistor T1 is a driving transistor and can control the driving current flowing through the light-emitting element LED. The first transistor T1 can be connected to a first voltage line VDDL and a storage capacitor Cst. The first transistor T1 can control the driving current flowing from the first voltage line VDDL through the light-emitting element LED in response to the voltage value stored in the storage capacitor Cst. The light-emitting element LED can emit light with a specific brightness due to the driving current. The first electrode of the light-emitting element LED can be electrically connected to the first transistor T1, and the second electrode of the light-emitting element LED can be electrically connected to the second voltage line VSSL supplying the second power supply voltage VSS.

[0124] Despite Figure 6aThe pixel driving circuit unit PC includes two transistors and a storage capacitor, but in another embodiment, the pixel driving circuit unit PC may include three or more transistors.

[0125] Reference Figure 6b The pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0126] The pixel driving circuit unit PC is electrically connected to signal lines and voltage lines. Signal lines may include gate lines such as the scan signal line GWL, bypass control line GBL, initialization control line GIL, and emit control line EML, as well as data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a first voltage line VDDL.

[0127] The first voltage line VDDL transmits the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 transmits the first initialization voltage Vint, used to initialize the first transistor T1, to the pixel driving circuit unit PC. The second initialization voltage line VIL2 transmits the second initialization voltage Vaint, used to initialize the first electrode of the light-emitting element LED, to the pixel driving circuit unit PC.

[0128] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 acts as a driving transistor, and receives the data signal Dm according to the switching operation of the second transistor T2 and supplies driving current to the light-emitting element LED.

[0129] The second transistor T2 is a data write transistor and is electrically connected to the scan signal line GWL and the data line DL. The second transistor T2 is electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 is turned on according to the scan signal GW received through the scan signal line GWL to perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the first node N1.

[0130] The third transistor T3 is electrically connected to the scan signal line GWL and is also electrically connected to the light-emitting element LED via the sixth transistor T6. The third transistor T3 is turned on according to the scan signal GW received through the scan signal line GWL and is connected to the first transistor T1 as a diode.

[0131] The fourth transistor T4 is the first initialization transistor and is electrically connected to the initialization control line GIL and the first initialization voltage line VIL1. The fourth transistor T4 is turned on according to the initialization control signal GI received via the initialization control line GIL, so as to initialize the voltage of the gate electrode of the first transistor T1 by transmitting the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1. The initialization control signal GI may correspond to the scan signal of another pixel driving circuit unit located in the preceding row relative to the pixel driving circuit unit PC.

[0132] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emitter control transistor. The fifth transistor T5 and the sixth transistor T6 are electrically connected to the emitter control line EML, and are simultaneously turned on according to the emitter control signal EM received through the emitter control line EML, so as to form a current path through which the drive current can flow from the first voltage line VDDL to the light-emitting element LED.

[0133] The seventh transistor T7 is the second initialization transistor and can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be turned on according to the bypass control signal GB received through the bypass control line GBL to initialize the first electrode of the light-emitting element LED by transmitting the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED.

[0134] The storage capacitor Cst includes a first electrode (or lower electrode) CE1 and a second electrode (or upper electrode) CE2. The first electrode CE1 is electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 is electrically connected to the first voltage line VDDL. The storage capacitor Cst can maintain the voltage applied to the gate electrode of the first transistor T1 by storing and holding a voltage corresponding to the voltage difference between the first voltage line VDDL and the gate electrode of the first transistor T1.

[0135] Reference Figure 6c The pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor Cst, and an auxiliary capacitor Ca.

[0136] The pixel driving circuit unit PC is electrically connected to signal lines and voltage lines. Signal lines may include gate lines such as the scan signal line GWL, bypass control line GBL, initialization control line GIL, and emit control line EML, as well as data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, a sustain voltage line VSL, and a first voltage line VDDL.

[0137] The first voltage line VDDL transmits the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 transmits the first initialization voltage Vint, used to initialize the first transistor T1, to the pixel driving circuit unit PC. The second initialization voltage line VIL2 transmits the second initialization voltage Vaint, used to initialize the first electrode of the light-emitting element LED, to the pixel driving circuit unit PC. The sustaining voltage line VSL provides a sustaining voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) during the initialization and data write periods.

[0138] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and can be electrically connected to the light-emitting element LED via the sixth transistor T6. The first transistor T1 can be used as a driving transistor, and can supply driving current to the light-emitting element LED by receiving the data signal Dm according to the switching operation of the second transistor T2.

[0139] The second transistor T2 is electrically connected to the scan signal line GWL and the data line DL, and is also electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8. The second transistor T2 is turned on according to the scan signal GW received through the scan signal line GWL to perform a switching operation to transmit the data signal Dm received through the data line DL to the first node N1.

[0140] The third transistor T3 is electrically connected to the scan signal line GWL and is also electrically connected to the light-emitting element LED via the sixth transistor T6. The third transistor T3 is turned on according to the scan signal GW received through the scan signal line GWL to compensate the threshold voltage of the first transistor T1 by connecting it to the first transistor T1 via a diode.

[0141] The fourth transistor T4 is electrically connected to the initialization control line GIL and the first initialization voltage line VIL1, and is turned on according to the initialization control signal GI received through the initialization control line GIL, so as to initialize the voltage of the gate electrode of the first transistor T1 by transmitting the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1. The initialization control signal GI may correspond to the scan signal of another pixel driving circuit unit located in the previous row relative to the pixel driving circuit unit PC.

[0142] The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are electrically connected to the emitter control line EML, and are simultaneously turned on according to the emitter control signal EM received through the emitter control line EML, so as to form a current path from the first voltage line VDDL through it to the light-emitting element LED.

[0143] The seventh transistor T7 is the second initialization transistor and can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 is turned on according to the bypass control signal GB received through the bypass control line GBL, so as to initialize the first electrode of the light-emitting element LED by transmitting the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting element LED.

[0144] The ninth transistor T9 can be electrically connected to the bypass control line GBL, the second electrode CE2 of the storage capacitor Cst, and the sustaining voltage line VSL. During the initialization and data write periods, the ninth transistor T9 can be turned on according to the bypass control signal GB received through the bypass control line GBL to transmit the sustaining voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst).

[0145] The eighth transistor T8 and the ninth transistor T9 may be electrically connected to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst). In some embodiments, during the initialization and data write periods, the eighth transistor T8 may be turned off and the ninth transistor T9 may be turned on, and during the transmit period, the eighth transistor T8 may be turned on and the ninth transistor T9 may be turned off. Because the sustaining voltage VSUS is transmitted to the second node N2 during the initialization and data write periods, the brightness uniformity of the display device according to the voltage drop of the first voltage line VDDL (e.g., long-distance uniformity (LRU)) can be improved.

[0146] The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 is electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 is electrically connected to the eighth transistor T8 and the ninth transistor T9.

[0147] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the sustaining voltage line VSL, and the first electrode of the light-emitting element LED. When the seventh transistor T7 and the ninth transistor T9 are turned on, the auxiliary capacitor Ca can store and maintain a voltage corresponding to the voltage difference between the first electrode of the light-emitting element LED and the sustaining voltage line VSL, thereby preventing an increase in black brightness when the sixth transistor T6 is turned off.

[0148] Figure 7a and Figure 7b This is a schematic cross-sectional view of the main island portion of the display device according to an embodiment.

[0149] Reference Figure 7a and Figure 7b The main island portion 11 of the display device according to the embodiment (see Figure 4 It may include pixel driving circuit units and light-emitting elements. Figure 7a and Figure 7b For ease of explanation, only the pixel driving circuit unit PC (see [link]) is shown in the image. Figure 6a The first transistor T1, the second transistor T2, and the storage capacitor Cst are described. Figure 7b The pixel driving circuit unit can have the same as Figure 7a The pixel driving circuit unit in the reference has the same structure, therefore, the structure will be omitted. Figure 7a The description is the same as the description given.

[0150] First, refer to Figure 7a The buffer layer 101 may be located on the top surface of the substrate 100. The buffer layer 101 can prevent impurities from penetrating into the semiconductor layer of the transistor. The buffer layer 101 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide, and may have a single-layer structure or a multi-layer structure including the aforementioned inorganic insulating material.

[0151] Pixel driving circuit unit PC (see Figure 6a The pixel driving circuit unit PC (see [link]) can be located on buffer layer 101. Figure 6a ) can include, for example Figures 6a to 6c The diagram shows multiple transistors and storage capacitors. In an embodiment, Figure 7a The pixel driving circuit unit PC (see) is shown. Figure 6a The first transistor T1, the second transistor T2, and the storage capacitor Cst are described.

[0152] The first transistor T1 may include a first semiconductor layer A1 located on a buffer layer 101 and a first gate electrode G1 superimposed on the channel region of the first semiconductor layer A1 in a plan view. The first semiconductor layer A1 may include a silicon-based semiconductor material (e.g., polysilicon). The first semiconductor layer A1 may include a channel region and a first region and a second region located on opposite sides of the channel region. The first region and the second region are regions containing impurities with a higher impurity concentration than the channel region, and one of the first region and the second region may correspond to a source region and the other may correspond to a drain region.

[0153] The second transistor T2 may include a second semiconductor layer A2 located on the buffer layer 101 and a second gate electrode G2 superimposed on the channel region of the second semiconductor layer A2 in a plan view. The second semiconductor layer A2 may include a silicon-based semiconductor material (e.g., polysilicon). The second semiconductor layer A2 may include a channel region and a first region and a second region located on opposite sides of the channel region. The first region and the second region are regions having an impurity concentration higher than that of the channel region, and one of the first region and the second region may correspond to the source region, while the other may correspond to the drain region.

[0154] Each of the first gate electrode G1 and the second gate electrode G2 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure comprising the aforementioned materials.

[0155] A first gate insulating layer 103, used for electrical insulation from the first semiconductor layer A1 and the second semiconductor layer A2, may be located below the first gate electrode G1 and the second gate electrode G2. The first gate insulating layer 103 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide, and may have a single-layer structure or a multi-layer structure including the aforementioned inorganic insulating material.

[0156] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 stacked on top of each other in a plan view. In an embodiment, the lower electrode CE1 of the storage capacitor Cst may include a first gate electrode G1. In other words, the first gate electrode G1 may include the lower electrode CE1 of the storage capacitor Cst. For example, the first gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst may be integrally formed with each other.

[0157] The first interlayer insulating layer 105 may be located between the lower electrode CE1 and the upper electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer 105 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure or a multi-layer structure including the aforementioned inorganic insulating material.

[0158] The upper electrode CE2 of the storage capacitor Cst may include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure including the above materials.

[0159] The second interlayer insulation layer 107 may be located on the storage capacitor Cst. The second interlayer insulation layer 107 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure or a multi-layer structure including the aforementioned inorganic insulating material.

[0160] The source electrode S1 and / or drain electrode D1, electrically connected to the first semiconductor layer A1 of the first transistor T1, may be located on the second interlayer insulating layer 107. The source electrode S2 and / or drain electrode D2, electrically connected to the second semiconductor layer A2 of the second transistor T2, may be located on the second interlayer insulating layer 107. The source electrodes S1 and S2 and / or drain electrodes D1 and D2 may comprise aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure comprising the aforementioned materials.

[0161] The first organic insulating layer 109 may be located on the pixel driving circuit unit. The first organic insulating layer 109 may include organic insulating materials such as acrylic materials, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0162] The first connecting electrode CL1 may be located on the first organic insulating layer 109. The first connecting electrode CL1 may include aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure including the above materials.

[0163] The second organic insulating layer 111 may be located on the first connecting electrode CL1. The second organic insulating layer 111 may include organic insulating materials such as acrylic materials, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0164] The second connecting electrode CL2 may be located on the second organic insulating layer 111. The second connecting electrode CL2 may include aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure including the above materials.

[0165] The third organic insulating layer 113 may be located on the second connecting electrode CL2. The third organic insulating layer 113 may include organic insulating materials such as acrylic materials, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0166] Although in reference Figure 7a and Figure 7bIn the described embodiment, the pixel driving circuit unit and the light-emitting element are electrically connected via a first connecting electrode CL1 and a second connecting electrode CL2. However, in another embodiment, the first connecting electrode CL1 and / or the second connecting electrode CL2 may be omitted.

[0167] Reference Figure 7a According to the embodiments, the light-emitting element may include an organic light-emitting diode 220 comprising organic materials. The organic light-emitting diode 220 may include a first electrode 221 located on an insulating layer, a second electrode 225 facing the first electrode 221, and an emitting layer 223 located between the first electrode 221 and the second electrode 225. A first functional layer 222 may be located between the first electrode 221 and the emitting layer 223, and a second functional layer 224 may be located between the emitting layer 223 and the second electrode 225.

[0168] The edge of the first electrode 221 may be covered by a dam layer BKL comprising insulating material. The dam layer BKL may be defined as an opening B-OP overlapping the central portion of the first electrode 221 in a plan view.

[0169] The first electrode 221 may include a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO)). In another embodiment, the first electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In another embodiment, the first electrode 221 may also include a layer formed of or comprising ITO, IZO, ZnO, AZO, or In2O3 above / below the reflective layer.

[0170] The emitting layer 223 may include a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a specific color. The first functional layer 222 may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 224 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0171] The second electrode 225 may be formed of or comprise a conductive material with low work function. For example, the second electrode 225 may comprise a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, the second electrode 225 may also comprise a layer formed of or comprising ITO, IZO, ZnO, AZO, or In2O3 on a (semi-)transparent layer comprising the above-described materials.

[0172] Reference Figure 7b According to the embodiments, the light-emitting element may include an inorganic light-emitting diode 230 comprising inorganic materials. The inorganic light-emitting diode 230 may include a first semiconductor layer 231, a second semiconductor layer 232, an intermediate layer 233 between the first semiconductor layer 231 and the second semiconductor layer 232, a first electrode 235 electrically connected to the first semiconductor layer 231, and a second electrode 238 electrically connected to the second semiconductor layer 232. The first electrode 235 and the second electrode 238 of the inorganic light-emitting diode 230 may be electrically connected to a first electrode pad (or solder pad) 241 and a second electrode pad 242 located on the same layer.

[0173] In some embodiments, the first semiconductor layer 231 may include a p-type semiconductor layer. The p-type semiconductor layer may be made of materials selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN, having an In... x Al y Ga 1-x-y A semiconductor material with a composition of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) is formed or includes a semiconductor material selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN, having an In x Al y Ga 1-x-y Semiconductor materials with the composition N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) and may be doped with p-type dopants such as Mg, Zn, Ca, Sr or Ba.

[0174] The second semiconductor layer 232 may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be composed of materials selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN, having an In... x Al y Ga 1-x-yA semiconductor material with a composition of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) is formed or includes a semiconductor material selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN, having an In x Al y Ga 1-x-y Semiconductor materials with the composition N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) and may be doped with n-type dopants such as Si, Ge or Sn.

[0175] The intermediate layer 233 can be a region where electrons and holes recombine to change to a lower energy level and generate light with a corresponding wavelength. x Al y Ga 1-x-y The semiconductor material is composed of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) and can have a single quantum well structure or a multiple quantum well (MQW) structure. Furthermore, the intermediate layer 233 can have a quantum wire structure or a quantum dot structure.

[0176] Despite Figure 7b The first semiconductor layer 231 includes a p-type semiconductor layer and the second semiconductor layer 232 includes an n-type semiconductor layer, but the disclosure is not limited thereto. In another embodiment, the first semiconductor layer 231 may include an n-type semiconductor layer and the second semiconductor layer 232 may include a p-type semiconductor layer.

[0177] The display device 1 according to the above embodiment can be used in various electronic devices capable of providing images. The term "electronic device" refers to a device capable of providing a specific image by using electricity.

[0178] Figures 8a to 8g This is a perspective view schematically illustrating an embodiment of an electronic device including a display device according to an embodiment.

[0179] Reference Figure 8a The display device according to the embodiment can be used in a wearable electronic device 3100 that can be worn on a user's body. The wearable electronic device 3100 may include a main body portion 3110 and a display unit 3120 disposed on the main body portion 3110. The display device according to the embodiment can be used as the display unit 3120 of the wearable electronic device 3100. Figure 8a As shown, the wearable electronic device 3100 can be deformable. In an embodiment, the wearable electronic device 3100 can be used as a smartwatch or a smartphone, depending on the user's choice.

[0180] Figure 8bA medical electronic device 3200 is illustrated. In an embodiment, the medical electronic device 3200 may include a main body portion 3210 and a light-emitting unit 3220. A display device according to an embodiment may be used as the light-emitting unit 3220 of the medical electronic device 3200. The light-emitting unit 3220 may emit light of a specific wavelength (e.g., infrared light or visible light) toward the patient's body. In an embodiment, the main body portion 3210 may include a stretchable fiber material and may have a structure that can be worn on a user's body.

[0181] Figure 8c An educational electronic device 3300 is illustrated. In an embodiment, the educational electronic device may include a display unit 3320 disposed in a frame 3310. The display unit 3320 may use a display device according to an embodiment. Images such as a sea with waves, a snow-covered mountain, or a volcano with lava flow can be provided through the display unit 3320, and in this case, the display unit 3320 may be stretched in the height direction (e.g., the z-direction) to reflect the height of the waves, mountain, or volcano. In some embodiments, a portion of the display unit 3320 may sequentially change height along the direction of lava flow to display the movement of lava in three dimensions. The educational electronic device 3300 may include a plurality of pins (or stroke units) 3330 located on the rear surface of the display unit 3320 such that the display unit 3320 is stretched in the height direction. As the pins 3330 move along a third direction (e.g., the z-direction or the -z-direction), the image displayed on the display unit 3320 can be implemented with three-dimensional height. Although referenced... Figure 8c An educational electronic device 3300 is described, but its use is unrestricted as long as certain image information is provided.

[0182] Despite Figures 8a to 8c The electronic device shown is a variable-shape electronic device, but the disclosure is not limited thereto. As in the embodiments described below, the display device according to the embodiments can be used in electronic devices in which the portion for displaying images (e.g., a screen) is fixed.

[0183] Figure 8d A robot 3400 as an electronic device according to an embodiment is shown. The robot 3400 can identify movement or objects using a camera unit 3440, and can display specific images to a user via display units 3420 and 3430. In some embodiments, because the display device according to the embodiment can be stretched in various directions as described above, the display device can be assembled into a main frame having a hemispherical shape; therefore, the robot 3400 may include display units 3420 and 3430, both having a hemispherical shape.

[0184] Figure 8eA display device 3500 for a vehicle, as an electronic device according to an embodiment, is shown. The display device 3500 for a vehicle may include an instrument cluster 3510, a central information display (CID) 3520, and / or a passenger display (front passenger display). Because the display device according to the embodiment can be stretched in various directions, the display device can be used for the instrument cluster 3510, the CID 3520, and / or the front passenger display, regardless of the shape of the vehicle's internal frame.

[0185] Although the instrument cluster 3510, CID 3520 and / or passenger display are in Figure 8e The components are separate from each other, but the disclosure is not limited thereto. In another embodiment, two or more selected from the instrument cluster 3510, CID 3520, and passenger display can be connected integrally.

[0186] In some embodiments, the display device 3500 for a vehicle may include a button 3540 for displaying a specific image. (See also...) Figure 8e The enlarged view shows that the button 3540, which has a hemispherical shape, may include an object 3542 and a display device located on the object 3542, providing a tactile feedback of using the button while the object 3542 moves in the z-direction or -z-direction. In some embodiments, when the object 3542 has a three-dimensional circular surface, the display device may also have a three-dimensional circular surface.

[0187] Figure 8f An electronic device 3600 for advertising or display, as an electronic device according to an embodiment, is shown. In some embodiments, the electronic device 3600 for advertising or display can be mounted on a fixed structure 3610 such as a wall or column. When the structure 3610 includes, for example, Figure 8f When the surface is uneven as shown, the electronic device 3600 for advertising or display can be positioned along the uneven surface of the structure 3610. In some embodiments, the electronic device 3600 for advertising or display can be mounted on the structure 3610 using a heat-shrink film or the like.

[0188] Figure 8g A controller 3700 as an electronic device according to an embodiment is shown. The controller 3700 may include image-type buttons. For example, the display unit 3710 of the controller 3700 may include a first button area 3720, a second button area 3730, and a third button area 3740 that protrude in the z-direction or protrude in the -z-direction (or are recessed in the z-direction). In some embodiments, the first button area 3720 and the third button area 3740 may protrude in the z-direction, and the second button area 3730 may protrude in the -z-direction (or be recessed in the z-direction).

[0189] Figure 9 This is a schematic diagram illustrating the construction of a display device according to an embodiment.

[0190] Reference Figure 9 In the display area DA, multiple pixels PX and signal lines for applying electrical signals to the multiple pixels PX can be located. The signal lines for applying electrical signals to the pixels PX may include multiple data lines DL, multiple transmit control lines EML, multiple scan signal lines GWL, multiple initialization control lines GIL, and multiple bypass control lines GBL.

[0191] The driving circuit DC, which provides signals for driving pixels PX, can be located outside the display area DA. The driving circuit DC may include a data driving circuit DDC and a gate driving circuit GDC (see...). Figure 3 ), gate drive circuit GDC (see Figure 3 This may include a transmit control drive circuit EMDC, a bypass drive circuit GBDC, an initialization drive circuit GIDC, and a data write drive circuit GWDC. The data drive circuit DDC can be positioned adjacent to the lower surface of the display area DA, can be connected to the data line DL, and can output the data signal Dm to the data line DL.

[0192] The transmit control drive circuit EMDC (or the first gate drive circuit), the bypass drive circuit GBDC (or the second gate drive circuit), the initialization drive circuit GIDC (or the third gate drive circuit), and the data write drive circuit GWDC (or the fourth gate drive circuit) can be positioned adjacent to the left or right surface of the display area DA. The transmit control drive circuit EMDC can be connected to the transmit control line EML and can output the transmit control signal EM to the transmit control line EML. The bypass drive circuit GBDC can be connected to the bypass control line GBL and can output the bypass control signal GB to the bypass control line GBL. The initialization drive circuit GIDC can be connected to the initialization control line GIL and can output the initialization control signal GI to the initialization control line GIL. The data write drive circuit GWDC can be connected to the scan signal line GWL and can output the scan signal GW.

[0193] Figure 10 This is a schematic diagram illustrating a gate drive circuit according to an embodiment. Figure 10 This is a schematic diagram showing the configuration of the transmit control drive circuit EMDC, bypass drive circuit GBDC, initialization drive circuit GIDC, and data write drive circuit GWDC.

[0194] Reference Figure 10The transmit control drive circuit EMDC can be implemented as a shift register comprising multiple transmit control stages (e.g., EMST1, EMST2, EMST3, ...). Each of the transmit control stages (e.g., EMST1, EMST2, EMST3, ...) can be a sub-drive circuit. Each of the transmit control stages (e.g., EMST1, EMST2, EMST3, ...) can be connected to a corresponding transmit control line EML and can output a transmit control signal EM to the corresponding transmit control line EML. The first transmit control stage EMST1 can output the transmit control signal EM in response to an external start signal STV, and each of the other transmit control stages (e.g., EMST2, EMST3, ...) can receive a carry signal CR output from the previous stage as a start signal. The transmit control stages (e.g., EMST1, EMST2, EMST3, ...) can be connected to multiple input lines IL arranged outside the transmit control stages (e.g., EMST1, EMST2, EMST3, ...).

[0195] The bypass drive circuit GBDC can be implemented as a shift register comprising multiple bypass stages (e.g., GBST1, GBST2, GBST3, ...). Each of the bypass stages (e.g., GBST1, GBST2, GBST3, ...) can be a sub-drive circuit. Each of the bypass stages (e.g., GBST1, GBST2, GBST3, ...) can be connected to a corresponding bypass control line GBL and can output a bypass control signal GB to the corresponding bypass control line GBL. The first bypass stage GBST1 can output the bypass control signal GB in response to an external start signal STV, and each of the remaining bypass stages (e.g., GBST2, GBST3, ...) can receive a carry signal CR from the previous stage as a start signal. The bypass stages (e.g., GBST1, GBST2, GBST3, ...) can be connected to multiple input lines IL arranged outside the bypass stages (e.g., GBST1, GBST2, GBST3, ...).

[0196] The initialization driver circuit GIDC can be implemented as a shift register comprising multiple initialization stages (e.g., GIST1, GIST2, GIST3, ...). Each of the initialization stages (e.g., GIST1, GIST2, GIST3, ...) can be a sub-driver circuit. Each of the initialization stages (e.g., GIST1, GIST2, GIST3, ...) can be connected to the initialization control line GIL and can output the corresponding initialization control signal GI to the corresponding initialization control line GIL. The first initialization stage GIST1 can output the initialization control signal GI in response to an external start signal STV, and each of the remaining initialization stages (e.g., GIST2, GIST3, ...) can receive the carry signal CR output from the previous stage as a start signal. The initialization stages (e.g., GIST1, GIST2, GIST3, ...) can be connected to multiple input lines IL arranged outside the initialization stages (e.g., GIST1, GIST2, GIST3, ...).

[0197] The data write driver circuit GWDC can be implemented as a shift register comprising multiple data write stages (e.g., GWST1, GWST2, GWST3, ...). Each of the data write stages (e.g., GWST1, GWST2, GWST3, ...) can be a sub-driver circuit. Each of the data write stages (e.g., GWST1, GWST2, GWST3, ...) can be connected to a corresponding scan signal line GWL and can output a scan signal GW to the corresponding scan signal line GWL. The first data write stage GWST1 can output a scan signal GW in response to an external start signal STV, and each of the remaining data write stages (e.g., GWST2, GWST3, ...) can receive a carry signal CR output from the previous stage as a start signal. The data write stages (e.g., GWST1, GWST2, GWST3, ...) can be connected to multiple input lines IL arranged outside the data write stages (e.g., GWST1, GWST2, GWST3, ...).

[0198] Multiple input lines (IL) can be signal lines comprising multiple voltage lines and multiple clock lines. For ease of explanation, in... Figure 10 Only one input line is shown.

[0199] Figure 11a It is shown that it includes Figure 10 A circuit diagram of an embodiment of the first emit control stage in the gate drive circuit. Figure 11b It is shown that it includes Figure 10 A circuit diagram of an embodiment of the first bypass stage in the gate drive circuit. Figure 11cIt is shown that, according to the embodiments, it includes Figure 10 The circuit diagram of the first initialization stage in the gate drive circuit.

[0200] First, refer to Figure 11a The first transmit control stage EMST1 may include an input terminal IN0, a first power input terminal IN1, a second power input terminal IN2, a first clock input terminal CIN1, a second clock input terminal CIN2, a reset terminal RST, and an output terminal OUT. The internal circuit configuration of the first transmit control stage EMST1 can be substantially the same as the internal circuit configuration of other transmit control stages.

[0201] The first power input terminal IN1 can be connected to the gate high-voltage wiring VGH (see...). Figure 13 The second power input terminal IN2 can be connected to the gate low voltage wiring VGL (see...). Figure 13 The reset terminal RST can be connected to the reset signal wiring ESR (see...). Figure 13 Furthermore, the first clock input terminal CIN1 can be connected to the first clock wiring CLK1, and the second clock input terminal CIN2 can be connected to the second clock wiring CLK2. Input terminal IN0 can be connected to the start signal wiring FLM (see...). Figure 13 Furthermore, the transmit control stages other than the first transmit control stage EMST1 can be connected to the carry wiring CRL (see...). Figure 13 The carry wiring CRL is connected to the output terminal OUT of the previous stage.

[0202] The first launch control stage EMST1 may include a node controller SST1, an output unit SST2 (or a buffer unit), and a node holding unit SST3.

[0203] First, the output unit SST2 can be connected to the first power input terminal IN1 and the second power input terminal IN2, and the output unit SST2 can output the gate power voltage as the first gate signal to the output terminal OUT based on the voltage of the second control node Q_F and the first control node QB.

[0204] The output unit SST2 may include a ninth transistor T9 (or a pull-up transistor) and a tenth transistor T10 (or a pull-down transistor). The ninth transistor T9 may include a first electrode connected to the first power input terminal, a second electrode connected to the output terminal OUT, and a gate electrode connected to the first control node QB.

[0205] The tenth transistor T10 may include a first electrode connected to the output terminal OUT, a second electrode connected to the second power input terminal IN2, and a gate electrode connected to the second control node Q_F.

[0206] The node controller SST1 can be connected to input terminal IN0, first power input terminal IN1, second power input terminal IN2, first clock input terminal CIN1, and second clock input terminal CIN2. The node controller SST1 can control the voltage of the first control node QB and the voltage of the second control node Q_F by using the start signal (or the previous gate signal) provided through input terminal IN0 and the gate high voltage received from the gate high voltage wiring VGH.

[0207] The node controller SST1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13, a second capacitor C2 and a third capacitor C3.

[0208] The first transistor T1 may include a first electrode connected to the input terminal IN0, a second electrode connected to the third control node Q (or the first electrode of the twelfth transistor T12), and a gate electrode connected to the first clock input terminal CIN1. The second transistor T2 may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the first electrode of the third transistor T3, and a gate electrode connected to the first electrode of the eleventh transistor T11.

[0209] The third transistor T3 may include a first electrode connected to the second electrode of the second transistor T2, a second electrode connected to the second clock input terminal CIN2, and a gate electrode connected to the second control node Q_F. The third capacitor C3 may be formed between the second electrode of the second transistor T2 and the second control node Q_F, and may include a first electrode connected to the second electrode of the second transistor T2 and a second electrode connected to the second control node Q_F.

[0210] The fourth transistor T4 may include a pair of transistors connected in series between the gate electrode of the second transistor T2 and the first clock input terminal CIN1, and may include a gate electrode connected to the third control node Q. The fifth transistor T5 may include a first electrode connected to the gate electrode of the second transistor T2, a second electrode connected to the second power input terminal IN2, and a gate electrode connected to the first clock input terminal CIN1.

[0211] The sixth transistor T6 may include a first electrode connected to the first control node QB, a second electrode connected to the first electrode of the seventh transistor T7, and a gate electrode connected to the second clock input terminal CIN2. The seventh transistor T7 may include a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the second clock input terminal CIN2, and a gate electrode connected to the second electrode of the eleventh transistor T11.

[0212] The second capacitor C2 may be formed between the second electrode of the eleventh transistor T11 and the second electrode of the sixth transistor T6, and may include a first electrode connected to the second electrode of the eleventh transistor T11 and a second electrode connected to the second electrode of the sixth transistor T6. The eleventh transistor T11 may include a first electrode connected to the gate electrode of the second transistor T2, a second electrode connected to the first electrode of the second capacitor C2, and a gate electrode connected to the second power input terminal IN2.

[0213] The twelfth transistor T12 may include a first electrode connected to the third control node Q (or the second electrode of the first transistor T1), a second electrode connected to the second control node Q_F, and a gate electrode connected to the second power input terminal IN2. The thirteenth transistor T13 may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the third control node Q (or the second electrode of the first transistor T1), and a gate electrode connected to the reset terminal RST. The reset terminal RST may be connected to the reset signal wiring ESR (see...). Figure 13 When the display device is turned on or off, a low-level reset signal can be applied to the reset terminal RST. The thirteenth transistor T13 can turn on in response to the low-level reset signal and perform a reset operation, so that the voltage at the second electrode (and the third control node Q) of the first transistor T1 is high.

[0214] The node holding unit SST3 can maintain a constant voltage at the first control node QB in response to the voltage at the third control node Q. The node holding unit SST3 may include a first capacitor C1 and an eighth transistor T8.

[0215] A first capacitor C1 may be formed between the first power input terminal IN1 and the first control node QB, and may include a first electrode connected to the first power input terminal IN1 and a second electrode connected to the first control node QB. The first capacitor C1 can keep the voltage difference between the first power input terminal IN1 and the first control node QB constant.

[0216] The eighth transistor T8 may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the first control node QB, and a gate electrode connected to the third control node Q. The eighth transistor T8 can maintain a constant voltage at the first control node QB in response to the voltage at the third control node Q. For example, when the voltage at the third control node Q is low, the eighth transistor T8 can maintain a high voltage at the first control node QB by using a high gate voltage.

[0217] Each of the first transistor T1 to the thirteenth transistor T13 can be a P-type transistor. Although in Figure 11a The first transistor T1 through the twelfth transistor T12 are single-gate transistors, but the disclosure is not limited thereto. For example, to improve reliability, at least one of the first transistor T1 through the twelfth transistor T12 may be implemented as a dual-gate transistor.

[0218] The transmit control signal EM (see above) is output from the first transmit control stage EMST1 with the above configuration. Figure 10 It can be transmitted to the corresponding transmit control line EML (see corresponding transmit output wiring) via the corresponding transmit output wiring. Figure 10 Furthermore, the signal output from the first transmit control stage EMST1 can be routed via carry wiring CRL (see...). Figure 13 The data is transmitted to the second launch control level EMST2, which is located one level below the first launch control level EMST1 (see...). Figure 10 ).

[0219] Next, refer to Figure 11b The first bypass stage GBST1 may include an input terminal IN0, a first power input terminal IN1, a second power input terminal IN2, a first clock input terminal CIN1, a second clock input terminal CIN2, a reset terminal RST, and an output terminal OUT. The internal circuit configuration of the first bypass stage GBST1 can be substantially the same as the internal circuit configuration of other bypass stages.

[0220] The first power input terminal IN1 can be connected to the gate high-voltage wiring VGH (see...). Figure 13 The second power input terminal IN2 can be connected to the gate low voltage wiring VGL (see...). Figure 13 The reset terminal RST can be connected to the reset signal wiring ESR (see...). Figure 13 Furthermore, the first clock input terminal CIN1 can be connected to the first clock wiring CLK1, and the second clock input terminal CIN2 can be connected to the second clock wiring CLK2. Input terminal IN0 can be connected to the start signal wiring FLM (see...). Figure 13 ), and bypass stages other than the first bypass stage GBST1 can be connected to the carry routing CRL (see Figure 13The carry wiring CRL is connected to the output terminal OUT of the previous stage.

[0221] The first bypass stage GBST1 may include a node controller SST1', an output unit SST2' (or a buffer unit), and a node holding unit SST3'. Except for the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16, the first bypass stage GBST1 may be substantially the same as or similar to the first transmit control stage EMST1. Therefore, repeated descriptions will be omitted.

[0222] The first bypass stage GBST1 may also include a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16.

[0223] The fourteenth transistor T14 may include a first electrode connected to the gate electrode of the third transistor T3, a second electrode connected to the second control node Q_F, and a gate electrode connected to the gate electrode of the third transistor T3. That is, the fourteenth transistor T14 can be diode-connected between the gate electrode of the third transistor T3 and the second control node Q_F. After a specific time point, the fourteenth transistor T14 can keep the voltage of the second control node Q_F constant, independent of changes in the voltage of the gate electrode of the third transistor T3.

[0224] The fifteenth transistor T15 may include a first electrode connected to the input terminal IN0, a second electrode connected to the first electrode of the sixteenth transistor T16, and a gate electrode connected to the first clock input terminal CIN1. The fifteenth transistor T15 may initialize the gate electrode of the third transistor T3 in response to a first clock signal provided through the first clock input terminal CIN1 by using a start signal (or a previous compensated gate signal) provided to the input terminal IN0.

[0225] The sixteenth transistor T16 may include a first electrode connected to the second electrode of the fifteenth transistor T15, a second electrode connected to the gate electrode of the third transistor T3, and a gate electrode connected to the second power input terminal IN2. The sixteenth transistor T16 may reduce or distribute the bias voltage applied to the fifteenth transistor T15 between the input terminal IN0 and the gate electrode of the third transistor T3.

[0226] The bypass control signal GB (see above) output from the first bypass stage GBST1 with the above configuration Figure 10 It can be transmitted to the corresponding bypass control line GBL through the corresponding bypass output wiring (see...). Figure 10 Furthermore, the signal output from the first bypass stage GBST1 can be routed via carry routing CRL (see...). Figure 15 Transmitted to the second bypass level GBST2, which is located one level below the first bypass level GBST1 (see...) Figure 10 ).

[0227] Next, refer to Figure 11c The first initialization stage GIST1 may include an input terminal IN0, a first power input terminal IN1, a second power input terminal IN2, a first clock input terminal CIN1, a second clock input terminal CIN2, and an output terminal OUT. The internal circuit configuration of the first initialization stage GIST1 may be the same as that of the first data write stage GWST1. Furthermore, the internal circuit configuration of the first initialization stage GIST1 may be substantially the same as that of other initialization stages, and the internal circuit configuration of the first data write stage GWST1 may be substantially the same as that of other data write stages.

[0228] The first power input terminal IN1 can be connected to the gate high-voltage wiring VGH (see...). Figure 13 The second power input terminal IN2 can be connected to the gate low voltage wiring VGL (see...). Figure 13 Furthermore, the first clock input terminal CIN1 can be connected to the first clock wiring CLK1, and the second clock input terminal CIN2 can be connected to the second clock wiring CLK2. Input terminal IN0 can be connected to the start signal wiring FLM (see...). Figure 13 ), and initialization stages other than the first initialization stage GIST1 can be connected to the carry routing CRL (see Figure 13 The carry wiring CRL is connected to the output terminal OUT of the previous stage.

[0229] The first initialization level GIST1 may include a first node controller SST1'', a second node controller SST2'', and an output unit SST3''.

[0230] Output unit SST3'' can control the voltage supplied to output terminal OUT in response to the voltages of the first node N1 and the second node N2. For this purpose, output unit SST3'' can include a sixth transistor T6 and a seventh transistor T7. Output unit SST3'' can be driven as a buffer unit. The sixth transistor T6 and the seventh transistor T7 included in output unit SST3'' can be... Figure 11c The two structures shown are connected in parallel.

[0231] A sixth transistor T6 may be connected between the output terminal OUT and the first power input terminal IN1, which is connected to the gate high-voltage wiring VGH. The sixth transistor T6 may control the connection between the first power input terminal IN1 and the output terminal OUT in response to a voltage applied to the first node N1. The sixth transistor T6 may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the output terminal OUT, and a gate electrode connected to the first node N1.

[0232] A seventh transistor T7 can be connected between the output terminal OUT and the second clock input terminal CIN2 connected to the second clock wiring CLK2. The seventh transistor T7 can control the connection between the output terminal OUT and the second clock input terminal CIN2 in response to a voltage applied to the second node N2. The seventh transistor T7 may include a first electrode connected to the output terminal OUT, a second electrode connected to the second clock input terminal CIN2, and a gate electrode connected to the second node N2.

[0233] The first node controller SST1'' can control the voltage of the third node N3 in response to signals supplied to input terminal IN0, the first clock input terminal CIN1, and the second clock input terminal CIN2. For this purpose, the first node controller SST1'' may include a first transistor T1, a second transistor T2, and a third transistor T3.

[0234] The first transistor T1 can be connected between the third node N3 and the input terminal IN0 to which the start signal (or the previous gate signal) is applied. The first transistor T1 can control the connection between the third node N3 and the input terminal IN0 via a first clock signal supplied to the first clock input terminal CIN1. The first transistor T1 can have a dual-gate structure to prevent leakage current. The first transistor T1 may include a pair of transistors connected in series between the input terminal IN0 and the third node N3, and may include a gate electrode connected to the first clock input terminal CIN1.

[0235] The second transistor T2 and the third transistor T3 can be connected in series between the third node N3 and the first power input terminal IN1. The third transistor T3 can be connected between the second transistor T2 and the third node N3. The third transistor T3 can control the connection between the second transistor T2 and the third node N3 in response to a second clock signal supplied to the second clock input terminal CIN2. The third transistor T3 may include a first electrode connected to the second electrode of the second transistor T2, a second electrode connected to the third node N3, and a gate electrode connected to the second clock input terminal CIN2.

[0236] The second transistor T2 can be connected between the third transistor T3 and the first power input terminal IN1. The second transistor T2 can control the connection between the third transistor T3 and the first power input terminal IN1 in response to the voltage of the first node N1. The second transistor T2 may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the first electrode of the third transistor T3, and a gate electrode connected to the first node N1.

[0237] The second node controller SST2'' can control the voltage of the first node N1 in response to the voltage of the first clock input terminal CIN1 and the voltage of the third node N3. For this purpose, the second node controller SST2'' may include an eighth transistor T8, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0238] A first capacitor C1 may be connected between the first node N1 and the first power input terminal IN1. The first capacitor C1 may be charged with the voltage applied to the first node N1. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the first power input terminal IN1. The first electrode of the first capacitor C1 may be connected to the gate electrode of the second transistor T2 and the gate electrode of the sixth transistor T6.

[0239] The second capacitor C2 can be connected between the second node N2 and the output terminal OUT. The second capacitor C2 is charged with a voltage corresponding to the on and off states of the seventh transistor T7. The second capacitor C2 may include a first electrode connected to the second node N2 and a second electrode connected to the output terminal OUT. The first electrode of the second capacitor C2 can be electrically connected to the second electrode of the eighth transistor T8.

[0240] A fourth transistor T4 can be connected between the first node N1 and the first clock input terminal CIN1. The fourth transistor T4 can control the connection between the first node N1 and the first clock input terminal CIN1 in response to the voltage of the third node N3. The fourth transistor T4 may include a first electrode connected to the first clock input terminal CIN1, a second electrode connected to the first node N1, and a gate electrode connected to the third node N3.

[0241] A fifth transistor T5 may be located between the first node N1 and the second power input terminal IN2 connected to the gate low-voltage wiring VGL. The fifth transistor T5 may control the connection between the first node N1 and the second power input terminal IN2 in response to a first clock signal at the first clock input terminal CIN1. The fifth transistor T5 may include a first electrode connected to the first node N1, a second electrode connected to the second power input terminal IN2, and a gate electrode connected to the first clock input terminal CIN1.

[0242] The eighth transistor T8 can be located between the third node N3 and the second node N2. The eighth transistor T8 can maintain the electrical connection between the third node N3 and the second node N2 while remaining in a conducting state. Furthermore, the eighth transistor T8 can limit the voltage drop width of the third node N3 in response to the voltage of the second node N2. The eighth transistor T8 may include a first electrode connected to the third node N3, a second electrode connected to the second node N2, and a gate electrode connected to the second power input terminal IN2.

[0243] The initialization control signal GI (see [link to initialization control signal]) outputs from the first initialization stage GIST1 with the above configuration. Figure 10 It can be transmitted to the corresponding initialization control line GIL through the corresponding initialization output wiring (see...). Figure 10 Furthermore, the signal output from the first initialization stage GIST1 can be routed via carry routing CRL (see...). Figure 17 ) is transmitted to the second initialization level GIST2, which is located one level below the first initialization level GIST1 (see Figure 10 ).

[0244] Figure 12 This illustrates an embodiment. Figure 3 An enlarged schematic plan view of part B of the display device.

[0245] Reference Figure 12 In the non-display area NDA (see Figure 3 In this embodiment, multiple peripheral islands 21 and multiple peripheral bridging portions 22 can be positioned. The multiple peripheral islands 21 can be spaced apart from each other, and the peripheral bridging portions 22 can connect adjacent peripheral islands 21 to each other. In this specification, when adjacent peripheral islands 21 are connected to each other by peripheral bridging portions 22, it means that the peripheral bridging portions 22 extend between adjacent peripheral islands 21, and the peripheral islands 21 and the multiple peripheral bridging portions 22 are integrally provided.

[0246] The peripheral island 21 may include a driver island DIP in which a driver stage can be positioned and a wiring island WIP in which input lines can be positioned. Specifically, at least one driver stage may be located in the driver island DIP, and some of the input lines used to apply signals or voltages to the driver stage may be located in the wiring island WIP. However, not all input lines used to apply signals or voltages to the driver stage are located in the wiring island WIP; some input lines may be located in the wiring island WIP, while others may be located in the driver island DIP. In the following text, the input line located in the wiring island WIP among the plurality of input lines may be referred to as the first input line IL1 (see...). Figure 13), and the other input lines located in the driver island DIP among the multiple input lines can be referred to as the second input line IL2 (see Figure 13 ).

[0247] Driver island DIPs and wiring island WIPs can be arranged alternately in a first row along a first direction (e.g., the x-direction), and driver island DIPs and wiring island WIPs can be arranged in a second row parallel to the first row in the same manner. That is, driver island DIPs can be arranged continuously in a first column along a second direction (e.g., the y-direction), and wiring island WIPs can be arranged continuously in a second column parallel to the first column. Because multiple wiring island WIPs are arranged continuously along the second direction, multiple first input lines IL1 (see...) Figure 13 The second input line IL2 can extend along a second direction (e.g., the y-direction). Similarly, since multiple driver island DIPs are arranged continuously along the second direction, multiple second input lines IL2 (see...) Figure 13 It can extend along a second direction (e.g., the y direction).

[0248] For example, a drive island DIP may include island IP11 (1-1), island IP12 (1-2), island IP31 (3-1), island IP32 (3-2), island IP51 (5-1), island IP52 (5-2), island IP71 (7-1), and island IP72 (7-2). A cabling island WIP may include island IP21 (2-1), island IP22 (2-2), island IP41 (4-1), island IP42 (4-2), island IP61 (6-1), island IP62 (6-2), island IP81 (8-1), and island IP82 (8-2).

[0249] The peripheral bridging section 22 may be a portion that connects adjacent peripheral island sections 21 to form a serpentine structure, and may have a serpentine shape. Multiple output wirings for transmitting the driver's output signals and multiple connection wirings connected to the input lines for transmitting input signals may be located in the peripheral bridging section 22.

[0250] The peripheral bridging section 22 may include a vertical bridging section VBP and a horizontal bridging section HBP. Specifically, the vertical bridging section VBP is the peripheral bridging section 22 that connects the driver island DIP to the wiring island WIP, and may have an "S" shape in a first direction (e.g., the x-direction). The horizontal bridging section HBP is the peripheral bridging section 22 that connects adjacent driver island DIPs or adjacent wiring island WIPs, and may have an "S" shape in a second direction (e.g., the y-direction). That is, the horizontal bridging section HBP may have a shape obtained by rotating the shape of the vertical bridging section VBP by 90 degrees.

[0251] The vertical bridging section VBP may include a first vertical bridging section VBP1 and a second vertical bridging section VBP2. The first vertical bridging section VBP1 may be a peripheral bridging section 22 located between a specific driver island DIP and a wiring island WIP, and positioned therein for applying signals to input lines of the specific driver island DIP. The second vertical bridging section VBP2 may be located between a specific driver island DIP and a wiring island WIP, and positioned therein for applying signals to input lines of driver island DIPs other than the specific driver island DIP. In other words, the first vertical bridging section VBP1 may be a peripheral bridging section 22 located between a specific driver island DIP and a wiring island WIP associated with that specific driver island DIP, and the second vertical bridging section VBP2 may be a peripheral bridging section 22 located between a specific driver island DIP and a wiring island WIP not associated with that specific driver island DIP.

[0252] Therefore, both the driver's output wiring and the input wiring can be located in the first vertical bridging section VBP1, and only the driver's output wiring can be located in the second vertical bridging section VBP2. The first vertical bridging section VBP1 and the second vertical bridging section VBP2 can be arranged alternately along a first direction. For example, the first vertical bridging section VBP1 may include bridging section BP11 (1-1), bridging section BP12 (1-2), bridging section BP31 (3-1), bridging section BP32 (3-2), bridging section BP51 (5-1), bridging section BP52 (5-2), bridging section BP71 (7-1), and bridging section BP72 (7-2). The second vertical bridging section VBP2 may include bridging section BP21 (2-1), bridging section BP22 (2-2), bridging section BP41 (4-1), bridging section BP42 (4-2), bridging section BP61 (6-1), bridging section BP62 (6-2), bridging section BP81 (8-1), and bridging section BP82 (8-2).

[0253] The horizontal bridging section HBP may include a first horizontal bridging section HBP1 and a second horizontal bridging section HBP2. The first horizontal bridging section HBP1 may be a peripheral bridging section 22 connecting driver island sections DIPs positioned adjacent to each other. The second horizontal bridging section HBP2 may be a peripheral bridging section 22 connecting wiring island sections WIPs positioned adjacent to each other. Therefore, the first horizontal bridging section HBP1 and the second horizontal bridging section HBP2 may be arranged alternately along a first direction (e.g., the x-direction).

[0254] For example, the first horizontal bridging part HBP1 may include bridging part BP111 (11-1), bridging part BP112 (11-2), bridging part BP113 (11-3), bridging part BP131 (13-1), bridging part BP132 (13-2), bridging part BP133 (13-3), bridging part BP151 (15-1), bridging part BP152 (15-2), bridging part BP153 (15-3), bridging part BP171 (17-1), bridging part BP172 (17-2), and bridging part BP173 (17-3). The second horizontal bridging section HBP2 may include bridging section BP121 (12-1), bridging section BP122 (12-2), bridging section BP123 (12-3), bridging section BP141 (14-1), bridging section BP142 (14-2), bridging section BP143 (14-3), bridging section BP161 (16-1), bridging section BP162 (16-2), bridging section BP163 (16-3), bridging section BP181 (18-1), bridging section BP182 (18-2), and bridging section BP173 (18-3).

[0255] The gate drive circuit GDC (see) located in the driver island DIP is Figure 3 In the EMDC (Emitting Control Drive Circuit) (see...), the transmit control drive circuit... Figure 10 ), bypass drive circuit GBDC (see Figure 10 ), Initialize the drive circuit GIDC (see Figure 10 ) and data write drive circuit GWDC (see Figure 10 ) can be directed from the outside toward the display area DA (see Figure 3 Arrange them in that order. Furthermore, as... Figure 12 As shown, when the size and / or width of the outer island portion 21 is greater than that of the main island portion 11 (see...) Figure 4 When considering the size and / or width of the drive island DIP, two drive stages can be located within the drive island DIP.

[0256] For example, the transmission control level can be located in island 1-1 IP11 and island 1-2 IP12. Specifically, the nth transmission control level EMSTn and the (n+1)th transmission control level EMSTn+1 (where n can be a natural number equal to or greater than 1) can be located in island 1-1 IP11, and the (n+2)th transmission control level EMSTn+2 and the (n+3)th transmission control level EMSTn+3 can be located in island 1-2 IP12.

[0257] Similarly, the bypass level can be located in IP31 of island 3-1 and IP32 of island 3-2. Specifically, the nth bypass level GBSTn and the (n+1)th bypass level GBSTn+1 can be located in IP31 of island 3-1, and the (n+2)th bypass level GBSTn+2 and the (n+3)th bypass level GBSTn+3 can be located in IP32 of island 3-2.

[0258] The initialization level can be located in 5-1 island IP51 and 5-2 island IP52. Specifically, the nth initialization level GISTn and the (n+1)th initialization level GISTn+1 can be located in 5-1 island IP51, and the (n+2)th initialization level GISTn+2 and the (n+3)th initialization level GISTn+3 can be located in 5-2 island IP52.

[0259] The data write stages can be located in island 7-1 IP71 and island 7-2 IP72. Specifically, the nth data write stage GWSTn and the (n+1)th data write stage GWSTn+1 can be located in island 7-1 IP71, and the (n+2)th data write stage GWSTn+2 and the (n+3)th data write stage GWSTn+3 can be located in island 7-2 IP72.

[0260] As described above, the input lines used to apply signals or voltages to each driver stage may include a first input line IL1 located in the wiring island WIP (see...). Figure 13 ) and the second input line IL2 located in the DIP of the driver island (see Figure 13 First input line IL1 (see...) Figure 13 The second input line IL2 can be located in the wiring island WIP and can be extended through the second horizontal bridging section HBP2. Figure 13 It can be located in the driver island section DIP, and can also be extended by being located in the first horizontal bridge section HBP1.

[0261] For example, some of the input lines used to supply signals or voltages to the transmit control stage EMST can extend through bridge sections BP121 (12-1), BP122 (12-2), and BP123 (12-3), and other input lines can extend through bridge sections BP111 (11-1), BP112 (11-2), and BP113 (11-3). Similarly, some of the input lines used to supply signals or voltages to the bypass stage GBST can extend through bridge sections BP141 (14-1), BP142 (14-2), and BP143 (14-3), and other input lines can extend through bridge sections BP131 (13-1), BP132 (13-2), and BP133 (13-3). Some of the input lines used to supply signals or voltages to the initialization stage GIST may extend through bridge sections BP161 (16-1), BP162 (16-2), and BP163 (16-3), and other input lines may extend through bridge sections BP151 (15-1), BP152 (15-2), and BP153 (15-3). Similarly, some of the input lines used to supply signals or voltages to the data write stage GWST may extend through bridge sections BP181 (18-1), BP182 (18-2), and BP183 (18-3), and other input lines may extend through bridge sections BP171 (17-1), BP172 (17-2), and BP173 (17-3).

[0262] The output wiring used to transmit the output signals of each driver stage can be directed towards the display area DA along a first direction (e.g., the x-direction) (see...). Figure 3 The output wiring can be in the same row as the driver island DIP where the connected driver stage is located, but can extend through the display area DA closer to the driver island DIP than the driver island DIP (see [link]). Figure 3 (VBP) consists of multiple vertical bridging sections.

[0263] For example, the transmit control output wiring of the nth transmit control stage EMSTn can be in the same row as the 1-1 island IP11, but can extend closer to the display area DA than the 1-1 island IP11, passing through the 1-1 bridging section BP11, 2-1 bridging section BP21, 3-1 bridging section BP31, 4-1 bridging section BP41, 5-1 bridging section BP51, 6-1 bridging section BP61, 7-1 bridging section BP71, and 8-1 bridging section BP81. Similarly, the bypass output wiring of the nth bypass stage GBSTn can be in the same row as the 3-1 island IP31, but can be closer to the display area DA than the 3-1 island IP31 (see...). Figure 3The initialization output wiring extends through bridging sections BP31 (3-1), BP41 (4-1), BP51 (5-1), BP61 (6-1), BP71 (7-1), and BP81 (8-1). The initialization output wiring of the nth initialization stage GISTn can be in the same row as island IP51 (5-1), but can be closer to the display area DA (see [link]). Figure 3 The data write output cabling extends through bridging sections BP51 (5-1), BP61 (6-1), BP71 (7-1), and BP81 (8-1). The data write output cabling for the nth data write stage GWSTn can be in the same row as island IP71 (7-1), but can be closer to the display area DA (see [link]). Figure 3 It extends through 7-1 bridging section BP71 and 8-1 bridging section BP81.

[0264] Figure 13 This illustrates an embodiment. Figure 12 An enlarged schematic plan view of part C of the display device. Figure 14 This illustrates a section taken along line I-I' according to an embodiment. Figure 13 A cross-sectional view of a portion of the display device.

[0265] First, refer to Figure 13 The nth transmit control level EMSTn and the (n+1)th transmit control level EMSTn+1 can be located in the 1-1 island IP11. Each transmit control level EMST may include a node controller and a buffer transistor. For example, the nth transmit control level EMSTn may include a first transmit node controller EMNC1 and a first transmit buffer transistor EMBF1, and the (n+1)th transmit control level EMSTn+1 may include a second transmit node controller EMNC2 and a second transmit buffer transistor EMBF2. Each of the first transmit node controller EMNC1 and the second transmit node controller EMNC2 may include multiple transistors and capacitors, and the voltage of the node can be controlled by using a start signal provided through an input terminal. Each of the first transmit buffer transistor EMBF1 and the second transmit buffer transistor EMBF2 may be a transistor positioned to isolate the signal source from the circuitry driven by the signal source.

[0266] The output signal of each of the nth transmit control level EMSTn and the (n+1)th transmit control level EMSTn+1 can be used to transmit the transmit control signal EM (see [link]) via transmit control output wiring EMO. Figure 10 ) is applied to the display area DA (see Figure 3 In detail, the transmit control signal EM output from the transmit control stage EMST can first be transmitted to the transmit control output wiring EMO, and then transmitted via the transmit control line EML connected to the transmit control output wiring EMO (see...). Figure 10 Supply to the display area DA (see) Figure 3 (pixels).

[0267] The transmit control output wiring (EMO) may include a first transmit control output wiring (EMO1) connected to the nth transmit control level (EMSTn) and a second transmit control output wiring (EMO2) connected to the (n+1)th transmit control level (EMSTn+1). That is, one output wiring can be located for each level. In another embodiment, when a transmit control level (EMST) is located in the 1-1 island IP11, one transmit control output wiring (EMO) may be located in the 1-1 bridging section (BP11).

[0268] First, the first transmit control output wiring EMO1 may include a first part EMO11 and a second part EMO12 of the first transmit control output wiring.

[0269] The first portion of the first transmit control output wiring, EMO11, can be a portion directly connected to the nth transmit control level, EMSTn. The first portion of the first transmit control output wiring, EMO11, can be located within the first vertical bridging section VBP1 (e.g., 1-1 bridging section BP11). Therefore, the first portion of the first transmit control output wiring, EMO11, can include a portion having a serpentine or "S" shape. As described below, because the connection wiring for the first input line IL1 is also located within the 1-1 bridging section BP11, the first portion of the first transmit control output wiring, EMO11, can overlap with a portion of the connection wiring in a plan view.

[0270] The first portion of the first transmit control output wiring, EMO11, can extend from the 1-1 bridging portion BP11 and can also be partially located within the 2-1 island portion IP21. The first portion of the first transmit control output wiring, EMO11, located on the 2-1 island portion IP21, can extend along a first direction (e.g., the x-direction). However, the first input line IL1 can extend within the 2-1 island portion IP21 along a second direction (e.g., the y-direction). Therefore, the first portion of the first transmit control output wiring, EMO11, can extend only to the area where the first input line IL1 is not located, so as not to overlap with the first input line IL1 in the plan view.

[0271] When the first input line IL1 and the transmit control output wiring EMO are located on the same layer, it can be done through, as follows: Figure 13 The bridging electrode BE shown is used to avoid collisions between the wirings. That is, the bridging electrode BE can be located below the first input line IL1 and the transmit control output wiring EMO, and at least one insulating layer can be located between the transmit control output wiring EMO and the bridging electrode BE. This is because the bridging electrode BE should transmit the transmit control signal EM (see...). Figure 10Therefore, one end can be connected to the first part EMO11 of the first transmit control output line through the contact hole, while the other end can be connected to the second part EMO12 of the first transmit control output line through the contact hole.

[0272] The second portion of the first transmit control output wiring, EMO12, can be located on the 2-1 island IP21 and can extend along the first direction (e.g., the x-direction). One end of the second portion of the first transmit control output wiring, EMO12, can be connected to the bridging electrode BE to receive the transmit control signal EM (see...). Figure 10 The second portion of the first transmit control output wiring, EMO12, can extend from the 2-1 island IP21 and can be located in the 2-1 bridging section BP21. The second portion of the first transmit control output wiring, EMO12, may include a portion with a serpentine or "S" shape. Because the connection wiring for the first input line IL1 does not need to be located in the 2-1 bridging section BP21, the second portion of the first transmit control output wiring, EMO12, may not overlap with the connection wiring in the plan view.

[0273] Similarly, the second transmit control output wiring EMO2 can have the same structure as the first transmit control output wiring EMO1. That is, the second transmit control output wiring EMO2 can include a first portion EMO21 and a second portion EMO22 of the second transmit control output wiring. The first portion EMO21 of the second transmit control output wiring can have a shape similar to the first portion EMO11 of the first transmit control output wiring, and the second portion EMO22 of the second transmit control output wiring can have a shape similar to the second portion EMO12 of the first transmit control output wiring.

[0274] In this configuration, the width of each of the 1-1 bridging section BP11 and the 2-1 bridging section BP21 can be between 35 μm and 40 μm. In this embodiment, because two transmit control output wirings (EMOs) are located in each of the 1-1 bridging section BP11 and the 2-1 bridging section BP21, the width of one transmit control output wiring EMO can be 16 μm, and the width of the separation space between the transmit control output wiring EMOs can be 4 μm. That is, the wiring load can be minimized by maximizing the use of the width of the transmit control output wiring EMOs located in each of the 1-1 bridging section BP11 and the 2-1 bridging section BP21.

[0275] The input lines used to apply signals or voltages to the transmit control stage EMST can be located in the non-display area NDA (see...). Figure 3 The input lines may include those located in the wiring island WIP (see...). Figure 12 The first input line IL1 in the driver island and the DIP located in the driver island (see...) Figure 12 The second input line IL2 is located in the EMST (Emitting Control System) interface. Specifically, among the input lines for the EMST interface, the first input line IL1 can be located in island 2-1 IP21, and the second input line IL2 can be located in island 1-1 IP11. Both the first and second input lines IL1 and IL2 can extend along a second direction (e.g., the y-direction). Therefore, the first input line IL1 can extend through bridging sections 12-1 BP121 and 12-2 BP122, and the second input line IL2 can extend through bridging sections 11-1 BP111 and 11-2 BP112.

[0276] In an embodiment, the first input line IL1 may include a gate high voltage wiring VGH, a gate low voltage wiring VGL, and a start signal wiring FLM. The gate high voltage wiring VGH and the gate low voltage wiring VGL are used to apply a drive voltage to the emitter control stage EMST (see [link to emulation]). Figure 12 The gate high voltage wiring VGH can apply the gate cutoff voltage, and the gate low voltage wiring VGL can apply the gate turn-on voltage. The start signal wiring FLM can be used to apply the start signal to the first emitter control stage EMST1 (see...). Figure 10 ) wiring.

[0277] In an embodiment, the second input line IL2 may include a first clock routing CLK1, a second clock routing CLK2, a carry routing CRL, and a reset signal routing ESR. The first clock routing CLK1 and the second clock routing CLK2 are routings used to transmit a first clock signal and a second clock signal, respectively, and each of the first and second clock signals may be a square wave signal in which logic high and logic low levels repeat. The carry routing CRL is a routing for transmitting a carry signal, and the carry signal may be the start signal for the next stage. For example, besides the first transmit control stage EMST1 (see...),... Figure 10 Each of the remaining transmit control stages (EMST) besides the previous stage can receive a carry signal from the previous stage as a start signal. The reset signal wiring (ESR) is the wiring used to transmit the reset signal, and the reset signal can be when the display device 1 (see...) Figure 12 A signal that is activated at a low level when powered on or reset.

[0278] Because the second input line IL2 can be located adjacent to the transmit control stage EMST in island 1-1 IP11, signal transmission is easy. Conversely, because the first input line IL1 is located in island 2-1 IP21, spaced apart from island 1-1 IP11, additional connection wiring CW may be required. Connection wiring CW may include a high-voltage connection wiring VGHL connected to the gate high-voltage wiring VGH in the first input line IL1 and a low-voltage connection wiring VGLL connected to the gate low-voltage wiring VGL. Because the start signal wiring FLM in the first input line IL1 does not need to transmit signals to the nth transmit control stage EMSTn and the (n+1)th transmit control stage EMSTn+1, the start signal wiring FLM may not be connected to the connection wiring CW.

[0279] The high-voltage connection wiring VGHL may include a first portion VGHL1, a second portion VGHL2, and a third portion VGHL3. The first portion VGHL1 may refer to the part of the high-voltage connection wiring VGHL located in the 2-1 island IP21. The first portion VGHL1 is directly connected to the gate high-voltage wiring VGH and can be connected to the gate high-voltage wiring VGH via a contact hole. Because the gate high-voltage wiring VGH extends along a second direction (e.g., the y-direction), the first portion VGHL1 may extend along a first direction (e.g., the x-direction) that intersects the gate high-voltage wiring VGH.

[0280] The second portion VGHL2 of the high-voltage connection wiring can refer to the part of the high-voltage connection wiring VGHL located within the first vertical bridging portion VBP1 (e.g., 1-1 bridging portion BP11). Therefore, the second portion VGHL2 of the high-voltage connection wiring can have a serpentine shape or an "S" shape. The second portion VGHL2 of the high-voltage connection wiring can be superimposed on the transmit control output wiring EMO in a plan view.

[0281] The third portion VGHL3 of the high-voltage connection wiring can refer to the portion of the high-voltage connection wiring VGHL located in the 1-1 island IP11. The third portion VGHL3 of the high-voltage connection wiring can directly transmit voltage to the nth transmit control level EMSTn and the (n+1)th transmit control level EMSTn+1. Therefore, the third portion VGHL3 of the high-voltage connection wiring can have a branch shape extending along a first direction (e.g., the x-direction) and then along a second direction (e.g., the y-direction).

[0282] Similarly, the low-voltage connection wiring VGLL can have a structure similar to that of the high-voltage connection wiring VGHL. That is, the low-voltage connection wiring VGLL can include a first portion VGLL1 corresponding to the first portion VGHL1 of the high-voltage connection wiring, a second portion VGLL2 corresponding to the second portion VGHL2 of the high-voltage connection wiring, and a third portion VGLL3 corresponding to the third portion VGHL3 of the high-voltage connection wiring. However, the third portion VGLL3 of the low-voltage connection wiring can have a shape extending around the periphery of the 1-1 island IP11 so as not to overlap with the third portion VGHL3 of the high-voltage connection wiring in the plan view, and can transmit voltage to each of the nth transmit control level EMSTn and the (n+1)th transmit control level EMSTn+1.

[0283] To maximize cabling width and minimize cabling load, transmit control output (EMO) cabling and connection cabling (CW) can be located on different layers. (See reference...) Figure 14 The transmit control output wiring (EMO) can be located between the second interlayer insulating layer 107 and the first organic insulating layer 109. That is, the transmit control output wiring (EMO) can be located between the main island portion 11 (see...) Figure 4 The source electrode S1 in ) (see Figure 7a ) are located in essentially the same layer and can be with the source electrode S1 (see Figure 7a The same material is used. The connecting wiring CW can be located between the first organic insulating layer 109 and the second organic insulating layer 111. That is, the connecting wiring CW can be connected to the main island portion 11 (see...). Figure 4 The first connecting electrode CL1 (see) Figure 7a They are located in substantially the same layer and may contain the same material as the first connecting electrode CL1.

[0284] like Figure 14 As shown, when the first input line IL1 and the transmit control output wiring EMO are on the same layer, the first portion EMO11 and the second portion EMO12 of the first transmit control output wiring can be electrically connected via a bridging electrode BE. For example, one end of the bridging electrode BE can be connected to the first portion EMO11 of the first transmit control output wiring via contact hole CNT11, and the other end can be connected to the second portion EMO12 of the first transmit control output wiring via contact hole CNT12. The bridging electrode BE can be located below the transmit control output wiring EMO and / or the first input line IL1. For example, the bridging electrode BE can be as follows: Figure 14 The image shown is located at section 11 of the main island (see...) Figure 4The upper electrode CE2 in the ) is located in substantially the same layer. However, the disclosure is not limited thereto, and the bridging electrode BE may be located in the main island section 11 (see Figure 4 The first gate electrode G1 in the ) is located in essentially the same layer.

[0285] Figure 15 This illustrates an embodiment. Figure 12 An enlarged schematic plan view of part D of the display device. Figure 16 This illustrates the section taken along lines II-II and III-III' according to an embodiment. Figure 15 A cross-sectional view of a portion of the display device.

[0286] First, refer to Figure 15 The nth bypass stage GBSTn and the (n+1)th bypass stage GBSTn+1 can be located in the 3-1 island IP31. Each bypass stage GBST may include a node controller and a buffer transistor. For example, the nth bypass stage GBSTn may include a first bypass node controller GBNC1 and a first bypass buffer transistor GBBF1, and the (n+1)th bypass stage GBSTn+1 may include a second bypass node controller GBNC2 and a second bypass buffer transistor GBBF2.

[0287] The output signal of each of the nth bypass stage GBSTn and the (n+1)th bypass stage GBSTn+1 can be used to pass the bypass control signal GB (see bypass output wiring GBO) via bypass output wiring GBO. Figure 10 ) is applied to the display area DA (see Figure 3 In detail, the bypass control signal GB output from the bypass stage GBST (see...) Figure 10 It can first be transmitted to the bypass output wiring GBO, and then through the bypass control line GBL connected to the bypass output wiring GBO (see...). Figure 10 Supply to the display area DA (see) Figure 3 (pixels).

[0288] The bypass output wiring GBO may include a first bypass output wiring GBO1 connected to the nth bypass level GBSTn and a second bypass output wiring GBO2 connected to the (n+1)th bypass level GBSTn+1. The first bypass output wiring GBO1 may include a first portion GBO11 and a second portion GBO12 of the first bypass output wiring, and the second bypass output wiring GBO2 may include a first portion GBO21 and a second portion GBO22 of the second bypass output wiring.

[0289] Similar to the first portion EMO11 of the first transmit control output wiring, the first portion GBO11 of the first bypass output wiring is directly connected to the nth bypass stage GBSTn and can extend to be located in the 3-1 bridging section BP31 and the 4-1 island section IP41. Similar to the second portion EMO12 of the first transmit control output wiring, the second portion GBO12 of the first bypass output wiring can be located in the 4-1 island section IP41 and can extend to the 4-1 bridging section BP41. The first portion GBO11 and the second portion GBO12 of the first bypass output wiring can be connected to one end and the other end of the bridging electrode BE, respectively, for electrical connection to each other. The first portion GBO21 of the second bypass output wiring can have a similar shape to the first portion GBO11 of the first bypass output wiring, and the second portion GBO22 of the second bypass output wiring can have a similar shape to the second portion GBO12 of the first bypass output wiring.

[0290] Reference Figure 16 The first portion GBO11 of the first bypass output wiring and the first portion GBO21 of the second bypass output wiring can be located between the second interlayer insulation layer 107 and the first organic insulation layer 109, and can be connected to the main island portion 11 (see...). Figure 4 The source electrode S1 (see) Figure 7a ) are located in substantially the same layer and may include the source electrode S1 (see Figure 7a The material is the same as that used for the first bypass output wiring. Similarly, the second part GBO12 of the first bypass output wiring and the second part GBO22 of the second bypass output wiring can also be the same as that used for the source electrode S1 (see...). Figure 7a They are located on essentially the same layer.

[0291] The transmit control output cabling (EMO) extending from 2-1 bridging section BP21 can be located in 3-1 island IP31, 3-1 bridging section BP31, and 4-1 island IP41. This is because the transmit control output cabling (EMO) is used to transmit the transmit control level EMST located outside the bypass level GBST (see...). Figure 13 The transmit control output wiring (EMO) is the wiring for the output signal of the transmit control output wiring, so it can be called the "pre-output wiring". The first transmit control output wiring (EMO1) may include the third part (EMO13), the fourth part (EMO14), and the fifth part (EMO15) of the first transmit control output wiring, and the second transmit control output wiring (EMO2) may include the third part (EMO23), the fourth part (EMO24), and the fifth part (EMO25) of the second transmit control output wiring.

[0292] The second portion EMO12 and the second portion EMO22 of the first transmit control output wiring located in the 2-1 bridging section BP21 can be respectively connected to the third portion EMO13 and the third portion EMO23 of the first transmit control output wiring located in the 3-1 island section IP31. The third portion EMO13 and the third portion EMO23 of the first transmit control output wiring can extend around the outside of the bypass stage GBST. Specifically, the third portion EMO13 of the first transmit control output wiring can extend around the upper side of the nth bypass stage GBSTn, and the third portion EMO23 of the second transmit control output wiring can extend around the lower side of the (n+1)th bypass stage GBSTn+1.

[0293] However, refer to Figure 16 To avoid overlapping with the bypass level GBST circuit unit in the plan view, the third portion EMO13 and the third portion EMO23 of the first transmit control output wiring can be located on different layers from the second portions EMO12 and EMO22 of the first transmit control output wiring. That is, the third portions EMO13 and EMO23 of the first transmit control output wiring can be located between the first organic insulating layer 109 and the second organic insulating layer 111, and can be located with the main island portion 11 (see...). Figure 4 The first connecting electrode CL1 (see) Figure 7a They are located in substantially the same layer and may contain the same material as the first connecting electrode CL1.

[0294] The third portion EMO13 of the first transmit control output wiring and the third portion EMO23 of the second transmit control output wiring can extend around the periphery of the 3-1 island IP31 and can be connected to the fourth portion EMO14 of the first transmit control output wiring and the fourth portion EMO24 of the second transmit control output wiring located in the 3-1 bridging section BP31. (Refer to...) Figure 16 The third part of the first transmit control output wiring, EMO13, can be connected to the fourth part of the first transmit control output wiring, EMO14, through the contact hole CNT21, and the third part of the second transmit control output wiring, EMO23, can be connected to the fourth part of the second transmit control output wiring, EMO24, through the contact hole CNT22.

[0295] The fourth portion EMO14 of the first transmit control output wiring can be located on the same layer as the first portion GBO11 of the first bypass output wiring to have a similar shape, and the fourth portion EMO24 of the second transmit control output wiring can be located on the same layer as the first portion GBO21 of the second bypass output wiring to have a similar shape. That is, the fourth portions EMO14 of the first transmit control output wiring and EMO24 of the second transmit control output wiring can extend to be located in the 3-1 bridging section BP31 and the 4-1 island section IP41.

[0296] Furthermore, the fourth portion EMO14 of the first transmit control output wiring can be connected to the fifth portion EMO15 of the first transmit control output wiring via a bridging electrode BE, and the fourth portion EMO24 of the second transmit control output wiring can be connected to the fifth portion EMO25 of the second transmit control output wiring via a bridging electrode BE. The fifth portion EMO15 of the first transmit control output wiring can be located in the same layer as the second portion GBO12 of the first bypass output wiring and can have a similar shape to the second portion GBO12 of the first bypass output wiring. The fifth portion EMO25 of the second transmit control output wiring can be located in the same layer as the second portion GBO22 of the second bypass output wiring and can have a similar shape to the second portion GBO22 of the second bypass output wiring.

[0297] That is, the first part GBO11 of the first bypass output wiring, the first part GBO21 of the second bypass output wiring, the fourth part EMO14 of the first transmit control output wiring and the fourth part EMO24 of the second transmit control output wiring can be located in the 3-1 bridging section BP31, and the second part GBO12 of the first bypass output wiring, the second part GBO22 of the second bypass output wiring, the fifth part EMO15 of the first transmit control output wiring and the fifth part EMO25 of the second transmit control output wiring can be located in the 4-1 bridging section BP41.

[0298] However, because the first transmit control output wiring EMO1 and the second transmit control output wiring EMO2 extend around the outside of the bypass stage GBST, the fourth portion EMO14 of the first transmit control output wiring located in the 3-1 bridging section BP31 and the fourth portion EMO24 of the second transmit control output wiring located in the 3-1 bridging section BP31 can be located outside the 3-1 bridging section BP31. Therefore, the first portion GBO11 of the first bypass output wiring located in the 3-1 bridging section BP31 and the first portion GBO21 of the second bypass output wiring located in the 3-1 bridging section BP31 can be located at the center of the 3-1 bridging section BP31. In other words, the bypass output wiring GBO connected to the bypass stage GBST located in the 3-1 island IP31 can be located at the center of the 3-1 bridging section BP31, and the pre-output wiring can be located outside the 3-1 bridging section BP31.

[0299] In addition, the outer bridging section 22 (see Figure 12 The width of the output lines can be constant; therefore, similar to 1-1 bridging section BP11, the width of each of 3-1 bridging sections BP31 and 4-1 bridging sections BP41 can be 35 μm to 40 μm. However, unlike the case where only two transmit control output lines (EMO) are located in 1-1 bridging sections BP11 and 2-1 bridging sections BP21, two transmit control output lines (EMO) and two bypass output lines (GBO) can be located in 3-1 bridging sections BP31 and 4-1 bridging sections BP41. The width of the output lines located in 3-1 bridging sections BP31 and 4-1 bridging sections BP41 can be smaller than the width of the output lines located in 1-1 bridging section BP11. In an embodiment, the width of each of the transmit control output lines (EMO) and bypass output lines (GBO) located in 3-1 bridging section BP31 can be 6 μm, and the width of the separation space between the output lines can be 4 μm. In other words, the load on the output wiring can be minimized by maximizing the use of the width of the transmit control output wiring (EMO) and bypass output wiring (GBO) located in the 3-1 bridging section BP31 and the 4-1 bridging section BP41.

[0300] The input lines used to apply signals or voltages to the bypass stage GBST can also be located in island 3-1 IP31 and island 4-1 IP41. The first input line IL1 located in island 4-1 IP41 can have the same characteristics as... Figure 13 The structure is similar to that of the first input line IL1 located in island IP21 of 2-1, and the second input line IL2 located in island IP31 of 3-1 can have the same structure as... Figure 13The structure is similar to that of the second input line IL2 located in IP11 of island 1-1. Similarly, the high-voltage connection wiring VGHL and low-voltage connection wiring VGLL, which are used as connection wiring CW for transmitting the voltage of the first input line IL1, can also have the same structure as... Figure 13 The high-voltage connection wiring VGHL and the low-voltage connection wiring VGLL have similar structures.

[0301] Figure 17 This illustrates an embodiment. Figure 12 An enlarged schematic plan view of part E of the display device. Figure 18 This illustrates the section taken along lines IV-IV' and V-V' according to an embodiment. Figure 17 A cross-sectional view of a portion of the display device.

[0302] First, refer to Figure 17 The nth initialization level GISTn and the (n+1)th initialization level GISTn+1 can be located in the 5-1 island IP51. Each initialization level GIST may include a node controller and a buffer transistor. For example, the nth initialization level GISTn may include a first initialization node controller GINC1 and a first initialization buffer transistor GIBF1, and the (n+1)th initialization level GISTn+1 may include a second initialization node controller GINC2 and a second initialization buffer transistor GIBF2.

[0303] The output signals of each of the nth initialization level GISTn and the (n+1)th initialization level GISTn+1 can be used to initialize the control signal GI (see initialization output wiring GIO) via the initialization output wiring GIO. Figure 10 ) is applied to the display area DA (see Figure 3 In detail, the initialization control signal GI output from the initialization stage GIST (see...) Figure 10 It can first be transmitted to the initialization output routing GIO, and then through the initialization control line GIL connected to the initialization output routing GIO (see Initialization Control Line GIL). Figure 10 Supply to the display area DA (see) Figure 3 (pixels).

[0304] The initialization output routing GIO may include a first initialization output routing GIO1 connected to the nth initialization level GISTn and a second initialization output routing GIO2 connected to the (n+1)th initialization level GISTn+1. The first initialization output routing GIO1 may include a first portion GIO11 and a second portion GIO12 of the first initialization output routing, and the second initialization output routing GIO2 may include a first portion GIO21 and a second portion GIO22 of the second initialization output routing.

[0305] Similar to the first portion EMO11 of the first transmit control output wiring, the first portion GIO11 of the first initialization output wiring can be directly connected to the nth initialization stage GISTn and can extend to be located in the 5-1 bridging section BP51 and the 6-1 island section IP61. Similar to the second portion EMO12 of the first transmit control output wiring, the second portion GIO12 of the first initialization output wiring can be located in the 6-1 island section IP61 and can extend to the 6-1 bridging section BP61. The first portion GIO11 and the second portion GIO12 of the first initialization output wiring can be connected to one end and the other end of the bridging electrode BE, respectively, for electrical connection. The first portion GIO21 of the second initialization output wiring can have a similar shape to the first portion GIO11 of the first initialization output wiring, and the second portion GIO22 of the second initialization output wiring can have a similar shape to the second portion GIO12 of the first initialization output wiring.

[0306] Reference Figure 18 The first portion GIO11 of the first initialization output wiring and the first portion GIO21 of the second initialization output wiring can be located between the second interlayer insulating layer 107 and the first organic insulating layer 109. That is, the first portion GIO11 of the first initialization output wiring and the first portion GIO21 of the second initialization output wiring can be connected to the main island portion 11 (see...). Figure 4 The source electrode S1 (see) Figure 7a The first initialization output wiring (GIO12) and the second initialization output wiring (GIO22) are located in substantially the same layer and can comprise the same material as the source electrode S1. Similarly, the second portion of the first initialization output wiring (GIO12) and the second portion of the second initialization output wiring (GIO22) can be located in substantially the same layer as the source electrode S1 (see [link to source electrode S1]). Figure 7a They are located on essentially the same layer.

[0307] The transmit control output wiring (EMO) and bypass output wiring (GBO) extending from the 4-1 bridging section BP41 can be located in the 5-1 island section IP51, the 5-1 bridging section BP51, and the 6-1 island section IP61. Because the transmit control output wiring (EMO) and bypass output wiring (GBO) are used to transmit output signals from stages located outside the initialization stage GIST, they can be referred to as "pre-output wiring".

[0308] The first transmit control output wiring EMO1 may include the sixth portion EMO16 and the seventh portion EMO17 of the first transmit control output wiring, and the second transmit control output wiring EMO2 may include the sixth portion EMO26 and the seventh portion EMO27 of the second transmit control output wiring. Similarly, the first bypass output wiring GBO1 may include the third portion GBO13 and the fourth portion GBO14 of the first bypass output wiring, and the second bypass output wiring GBO2 may include the third portion GBO23 and the fourth portion GBO24 of the second bypass output wiring.

[0309] The transmit control output cabling (EMO) and bypass output cabling (GBO) located in the 4-1 bridging section BP41 can be connected to the transmit control output cabling (EMO) and bypass output cabling (GBO) located in the 5-1 island section IP51. For example, the fifth part of the first transmit control output cabling, EMO15, can be connected to the sixth part of the first transmit control output cabling, EMO16, and the fifth part of the second transmit control output cabling, EMO25, can be connected to the sixth part of the second transmit control output cabling, EMO26. The second part of the first bypass output cabling, GBO12, can be connected to the third part of the first bypass output cabling, GBO13, and the second part of the second bypass output cabling, GBO22, can be connected to the third part of the second bypass output cabling, GBO23.

[0310] The pre-output wiring located in the 5-1 island IP51 may not extend around the outside of the initialization stage GIST, but may extend through the space between the nth initialization stage GISTn and the (n+1)th initialization stage GISTn+1. That is, the pre-output wiring located in the 5-1 island IP51 may extend through the center of the 5-1 island IP51 in a first direction (e.g., the x direction). However, since the pre-output wiring extends in the first direction (e.g., the x direction) and the second input line IL2 extends in the second direction (e.g., the y direction), there may be areas where the pre-output wiring and the second input line IL2 overlap in the plan view. Therefore, in order to avoid collisions between the pre-output wiring and the second input line IL2, the pre-output wiring may be connected to each other in the intersection area via bridging electrodes BE'. For example, the fifth part EMO15 of the first transmit control output wiring located in the 4-1 bridging section BP41 may be connected to the sixth part EMO16 of the first transmit control output wiring located in the 5-1 island IP51 via bridging electrodes BE'.

[0311] Reference Figure 18 The transmit control output wiring EMO and the second input line IL2 can be connected to the source electrode S1 (see...). Figure 7aLocated in essentially the same layer, the bridging electrode BE' can be connected to the upper electrode CE2 (see...). Figure 7a The bridging electrode BE' is located on essentially the same layer. In this case, one end of the bridging electrode BE' can be connected via a contact hole to the fifth portion EMO15 of the first transmit control output wiring, and the other end can be connected to the sixth portion EMO16 of the first transmit control output wiring to transmit the transmit control signal EM (see...). Figure 10 ).

[0312] The sixth portion EMO16 of the first transmit control output wiring and the third portion GBO13 of the first bypass output wiring can be located in the same layer as the first portion GIO11 of the first initialization output wiring to have a similar shape, and the sixth portion EMO26 of the second transmit control output wiring and the third portion GBO23 of the second bypass output wiring can be located in the same layer as the first portion GIO21 of the second initialization output wiring to have a similar shape. That is, the sixth portion EMO16 of the first transmit control output wiring, the sixth portion EMO26 of the second transmit control output wiring, the third portion GBO13 of the first bypass output wiring, and the third portion GBO23 of the second bypass output wiring can extend to be located in the 5-1 bridging section BP51 and the 6-1 island section IP61.

[0313] Furthermore, the sixth portion EMO16 of the first transmit control output wiring can be connected to the seventh portion EMO17 of the first transmit control output wiring via a bridging electrode BE, and the sixth portion EMO26 of the second transmit control output wiring can be connected to the seventh portion EMO27 of the second transmit control output wiring via a bridging electrode BE. Similarly, the bypass output wiring GBO and the initialization output wiring GIO can extend in the 6-1 island IP61 via a bridging electrode BE. The seventh portion EMO17 of the first transmit control output wiring and the fourth portion GBO14 of the first bypass output wiring can be located in the same layer as the second portion GIO12 of the first initialization output wiring, and can have a shape similar to that of the second portion GIO12 of the first initialization output wiring. The seventh portion EMO27 of the second transmit control output wiring and the fourth portion GBO24 of the second bypass output wiring can be located in the same layer as the second portion GIO22 of the second initialization output wiring, and can have a shape similar to that of the second portion GIO22 of the second initialization output wiring.

[0314] In other words, the first part GIO11 of the first initialization output wiring, the first part GIO21 of the second initialization output wiring, the third part GBO13 of the first bypass output wiring, the third part GBO23 of the second bypass output wiring, the sixth part EMO16 of the first transmit control output wiring, and the sixth part EMO26 of the second transmit control output wiring can be located in the 5-1 bridging section BP51. The second part GIO12 of the first initialization output wiring, the second part GIO22 of the second initialization output wiring, the fourth part GBO14 of the first bypass output wiring, the fourth part GBO24 of the second bypass output wiring, the seventh part EMO17 of the first transmit control output wiring, and the seventh part EMO27 of the second transmit control output wiring can be located in the 6-1 bridging section BP61.

[0315] However, because the first transmit control output wiring EMO1, the second transmit control output wiring EMO2, the first bypass output wiring GBO1, and the second bypass output wiring GBO2 extend through the separation space between the initialization stage GIST, the sixth portion EMO16 of the first transmit control output wiring, the third portion GBO13 of the first bypass output wiring, the third portion GBO23 of the second bypass output wiring, and the sixth portion EMO26 of the second transmit control output wiring can be located at the center of the 5-1 bridging section BP51. Therefore, the first portion GIO11 of the first initialization output wiring located in the 5-1 bridging section BP51 and the first portion GIO21 of the second initialization output wiring located in the 5-1 bridging section BP51 can be located outside the 5-1 bridging section BP51. In other words, the initialization output wiring GIO connected to the initialization stage GIST located in the 5-1 island IP51 can be located outside the 5-1 bridging section BP51, and the pre-output wiring can be located at the center of the 5-1 bridging section BP51.

[0316] In addition, the outer bridging section 22 (see Figure 12The width of the output lines can be constant; therefore, similar to 1-1 bridging section BP11, the width of each of 5-1 bridging sections BP51 and 6-1 bridging sections BP11 can be 35μm to 40μm. However, unlike the case where only two transmit control output lines EMO and two bypass output lines GBO are located in 3-1 bridging sections BP31 and 4-1 bridging sections BP41, the two transmit control output lines EMO, two bypass output lines GBO, and two initialization output lines GIO can be located in 5-1 bridging sections BP51 and 6-1 bridging sections BP61. Therefore, the width of the output lines located in 5-1 bridging sections BP51 and 6-1 bridging sections BP61 can be smaller than the width of the output lines located in 1-1 bridging sections BP11 to 4-1 bridging sections BP41. In this embodiment, the width of each of the transmit control output wiring EMO, bypass output wiring GBO, and initialization output wiring GIO located in the 5-1 bridging section BP51 can be 4 μm, and the width of the separation space between the output wirings can be 3 μm. That is, the load on the output wiring can be minimized by maximizing the use of the width of the transmit control output wiring EMO, bypass output wiring GBO, and initialization output wiring GIO located in the 5-1 bridging section BP51 and the 6-1 bridging section BP61.

[0317] The input lines used to apply signals or voltages to the initialization stage GIST can also be located in island 5-1 IP51 and island 6-1 IP61. The first input line IL1 located in island 6-1 IP61 can have the same characteristics as... Figure 13 The structure is similar to that of the first input line IL1 located in island IP21 of 2-1, and the second input line IL2 located in island IP51 of 5-1 can have the same structure as... Figure 13 The structure is similar to that of the second input line IL2 located in IP11 of island 1-1. Similarly, the high-voltage connection wiring VGHL and low-voltage connection wiring VGLL, which are used as connection wiring CW for transmitting the voltage of the first input line IL1, can have the same structure as... Figure 13 The high-voltage connection wiring VGHL and the low-voltage connection wiring VGLL have similar structures.

[0318] Figure 19 This illustrates an embodiment. Figure 12 An enlarged schematic plan view of part F of the display device. Figure 20 This illustrates the section taken along lines VI-VI' and VII-VII' according to an embodiment. Figure 19 A cross-sectional view of a portion of the display device.

[0319] First, refer to Figure 19The nth data write stage GWSTn and the (n+1)th data write stage GWSTn+1 can be located in the 7-1 island IP71. Each data write stage GWST may include a node controller and a buffer transistor. For example, the nth data write stage GWSTn may include a first scan node controller GWNC1 and a first scan buffer transistor GWBF1, and the (n+1)th data write stage GWSTn+1 may include a second scan node controller GWNC2 and a second scan buffer transistor GWBF2.

[0320] The output signal of each of the nth data write stage GWSTn and the (n+1)th data write stage GWSTn+1 can be used to scan the signal GW via the data write output wiring GWO (see...). Figure 10 ) is applied to the display area DA (see Figure 3 In detail, the scan signal GW output from the data write stage GWST (see...) Figure 10 It can first be transmitted to the data write output cabling GWO, and then through the scan signal line GWL connected to the data write output cabling GWO (see...). Figure 10 Supply to the display area DA (see) Figure 3 (pixels).

[0321] The data write output routing GWO may include a first data write output routing GWO1 connected to the nth data write stage GWSTn and a second data write output routing GWO2 connected to the (n+1)th data write stage GWSTn+1. The first data write output routing GWO1 may include a first portion GWO11 and a second portion GWO12 of the first data write output routing, and the second data write output routing GWO2 may include a first portion GWO21 and a second portion GWO22 of the second data write output routing.

[0322] Similar to the first portion EMO11 of the first transmit control output wiring, the first portion GWO11 of the first data write output wiring can be directly connected to the nth data write stage GWSTn and can extend to be located in the 7-1 bridging section BP71 and the 8-1 island section IP81. Similar to the second portion EMO12 of the first transmit control output wiring, the second portion GWO12 of the first data write output wiring can be located in the 8-1 island section IP81 and can extend to the 8-1 bridging section BP81. The first portion GWO11 and the second portion GWO12 of the first data write output wiring can be connected to one end and the other end of the bridging electrode BE, respectively, for electrical connection. The first portion GWO21 of the second data write output wiring can have a similar shape to the first portion GWO11 of the first data write output wiring, and the second portion GWO22 of the second data write output wiring can have a similar shape to the second portion GWO12 of the first data write output wiring.

[0323] Reference Figure 20 The first portion GWO11 and the second portion GWO21 of the first data write output wiring can be located between the second interlayer insulating layer 107 and the first organic insulating layer 109. That is, the first portion GWO11 and the second portion GWO21 of the first data write output wiring can be connected to the main island portion 11 (see...). Figure 4 The source electrode S1 (see) Figure 7a The first data write output wiring (GWO12) and the second data write output wiring (GWO22) are located on substantially the same layer and may contain the same material as the source electrode S1. Similarly, the second portion of the first data write output wiring (GWO12) and the second portion of the second data write output wiring (GWO22) may be located on the same layer as the source electrode S1 (see [link to source electrode S1]). Figure 7a They are located in the same layer.

[0324] The transmit control output wiring (EMO), bypass output wiring (GBO), and initialization output wiring (GIO) extending from the 6-1 bridging section BP61 can be located in the 7-1 island IP71, 7-1 bridging section BP71, and 8-1 island IP81. Because the transmit control output wiring (EMO), bypass output wiring (GBO), and initialization output wiring (GIO) are wirings used to transmit output signals of stages located outside the data write stage GWST, they can be referred to as "pre-output wiring."

[0325] The first transmit control output wiring EMO1 may include the eighth portion EMO18 and the ninth portion EMO19 of the first transmit control output wiring, and the second transmit control output wiring EMO2 may include the eighth portion EMO28 and the ninth portion EMO29 of the second transmit control output wiring. Similarly, the first bypass output wiring GBO1 may include the fifth portion GBO15 and the sixth portion GBO16 of the first bypass output wiring, and the second bypass output wiring GBO2 may include the fifth portion GBO25 and the sixth portion GBO26 of the second bypass output wiring. The first initialization output wiring GIO1 may include the third portion GIO13 and the fourth portion GIO14 of the first initialization output wiring, and the second initialization output wiring GIO2 may include the third portion GIO23 and the fourth portion GIO24 of the second initialization output wiring.

[0326] The transmit control output wiring EMO, bypass output wiring GBO, and initialization output wiring GIO located in the 6-1 bridging section BP61 can be connected to the transmit control output wiring EMO, bypass output wiring GBO, and initialization output wiring GIO located in the 7-1 island section IP71. For example, the seventh part EMO17 of the first transmit control output wiring can be connected to the eighth part EMO18 of the first transmit control output wiring, and the seventh part EMO27 of the second transmit control output wiring can be connected to the eighth part EMO28 of the second transmit control output wiring. The fourth part GBO14 of the first bypass output wiring can be connected to the fifth part GBO15 of the first bypass output wiring, and the fourth part GBO24 of the second bypass output wiring can be connected to the fifth part GBO25 of the second bypass output wiring. The second part GIO12 of the first initialization output wiring can be connected to the third part GIO13 of the first initialization output wiring, and the second part GIO22 of the second initialization output wiring can be connected to the third part GIO23 of the second initialization output wiring.

[0327] The pre-output wiring located in the 7-1 island IP71 may not extend around the outside of the data write stage GWST, but may extend through the space between the nth data write stage GWSTn and the (n+1)th data write stage GWSTn. That is, the pre-output wiring located in the 7-1 island IP71 may extend through the center of the 7-1 island IP71 in a first direction (e.g., the x-direction). However, since the pre-output wiring extends in the first direction (e.g., the x-direction) and the second input line IL2 extends in the second direction (e.g., the y-direction), there may be areas where the pre-output wiring and the second input line IL2 overlap in the plan view. Therefore, to avoid collisions between the pre-output wiring and the second input line IL2, the pre-output wiring may be connected via a bridging electrode BE' in the areas where the pre-output wiring and the second input line IL2 intersect. For example, the seventh portion EMO17 of the first transmit control output wiring located in the 6-1 bridging section BP61 can be connected via the bridging electrode BE' to the eighth portion EMO18 of the first transmit control output wiring located in the 7-1 island IP71.

[0328] Reference Figure 20 The initialization output wiring GIO and the second input line IL2 can be connected to the source electrode S1 (see...). Figure 7a Located in essentially the same layer, the bridging electrode BE' can be connected to the upper electrode CE2 (see...). Figure 7a The two are located on essentially the same layer. In this case, one end of the bridging electrode BE' can be connected via a contact hole to the second part GIO12 of the first initialization output wiring, and the other end of the bridging electrode BE' can be connected via a contact hole to the third part GIO13 of the first initialization output wiring to transmit the initialization control signal GI (see...). Figure 10 ).

[0329] The eighth portion EMO18 of the first transmit control output wiring, the fifth portion GBO15 of the first bypass output wiring, and the third portion GIO13 of the first initialization output wiring can be located in the same layer as the first portion GWO11 of the first data write output wiring to have a similar shape, and the eighth portion EMO28 of the second transmit control output wiring, the fifth portion GBO25 of the second bypass output wiring, and the third portion GIO23 of the second initialization output wiring can be located in the same layer as the first portion GWO21 of the second data write output wiring to have a similar shape. That is, the eighth portion EMO18 of the first transmit control output wiring, the eighth portion EMO28 of the second transmit control output wiring, the fifth portion GBO15 of the first bypass output wiring, the fifth portion GBO25 of the second bypass output wiring, the third portion GIO13 of the first initialization output wiring, and the third portion GIO23 of the second initialization output wiring can be extended to be located in the 7-1 bridging section BP71 and the 8-1 island section IP81.

[0330] Furthermore, the eighth portion EMO18 of the first transmit control output wiring can be connected to the ninth portion EMO19 of the first transmit control output wiring via a bridging electrode BE, and the eighth portion EMO28 of the second transmit control output wiring can be connected to the ninth portion EMO29 of the second transmit control output wiring via a bridging electrode BE. Similarly, the bypass output wiring GBO, the initialization output wiring GIO, and the data write output wiring GWO can be extended in the 8-1 island IP81 via bridging electrodes BE. The ninth portion EMO19 of the first transmit control output wiring, the sixth portion GBO16 of the first bypass output wiring, and the fourth portion GIO14 of the first initialization output wiring can be located in the same layer as the second portion GWO12 of the first data write output wiring, and can have a shape similar to that of the second portion GWO12 of the first data write output wiring. The ninth part EMO29 of the second transmit control output wiring, the sixth part GBO26 of the second bypass output wiring, and the fourth part GIO24 of the second initialization output wiring can be located in the same layer as the second part GWO22 of the second data write output wiring, and can have a shape similar to that of the second part GWO22 of the second data write output wiring.

[0331] In other words, the first part GWO11 of the first data write output wiring, the first part GWO21 of the second data write output wiring, the third part GIO13 of the first initialization output wiring, the third part GIO23 of the second initialization output wiring, the fifth part GBO15 of the first bypass output wiring, the fifth part GBO25 of the second bypass output wiring, the eighth part EMO18 of the first transmit control output wiring, and the eighth part EMO28 of the second transmit control output wiring can be located in the 7-1 bridging section BP71. The second part GWO12 of the first data write output wiring, the second part GWO22 of the second data write output wiring, the fourth part GIO14 of the first initialization output wiring, the fourth part GIO24 of the second initialization output wiring, the sixth part GBO16 of the first bypass output wiring, the sixth part GBO26 of the second bypass output wiring, the ninth part EMO19 of the first transmit control output wiring, and the ninth part EMO29 of the second transmit control output wiring can be located in the 8-1 bridging section BP81.

[0332] However, because the first transmit control output wiring EMO1, the second transmit control output wiring EMO2, the first bypass output wiring GBO1, the second bypass output wiring GBO2, the first initialization output wiring GIO1, and the second initialization output wiring GIO2 extend through the separation space between the data write stage GWST, the third portion GIO13 of the first initialization output wiring, the eighth portion EMO18 of the first transmit control output wiring, the fifth portion GBO15 of the first bypass output wiring, the fifth portion GBO25 of the second bypass output wiring, the eighth portion EMO28 of the second transmit control output wiring, and the third portion GIO23 of the second initialization output wiring can be located at the center of the 7-1 bridging section BP71. Therefore, the first portion GWO11 of the first data write output wiring located in the 7-1 bridging section BP71 and the first portion GWO21 of the second data write output wiring located in the 7-1 bridging section BP71 can be located outside the 7-1 bridging section BP71. In other words, the data write output cabling GWO connected to the data write stage GWST located in the 7-1 island IP71 can be located outside the 7-1 bridging section BP71, and the pre-output cabling can be located at the center of the 7-1 bridging section BP71.

[0333] In addition, the outer bridging section 22 (see Figure 12The width of the output lines can be constant; therefore, similar to 1-1 bridging section BP11, the width of each of 7-1 bridging section BP71 and 8-1 bridging section BP81 can be 35μm to 40μm. However, unlike the cases where only two transmit control output lines EMO, two bypass output lines GBO, and two initialization output lines GIO are located in 5-1 bridging section BP51 and 6-1 bridging section BP61, the two transmit control output lines EMO, two bypass output lines GBO, two initialization output lines GIO, and two data write output lines GWO can be located in 7-1 bridging section BP71 and 8-1 bridging section BP81. Therefore, the width of the output lines located in 7-1 bridging section BP71 and 8-1 bridging section BP81 can be smaller than the width of the output lines located in 1-1 bridging section BP11 to 6-1 bridging section BP61. In this embodiment, the width of each of the transmit control output wire EMO, bypass output wire GBO, initialization output wire GIO, and data write output wire GWO located in the 7-1 bridging section BP71 can be 2.5 μm, and the width of the separation space between the output wires can also be 2.5 μm. That is, the load on the output wires can be minimized by maximizing the use of the widths of the transmit control output wire EMO, bypass output wire GBO, initialization output wire GIO, and data write output wire GWO located in the 7-1 bridging section BP71 and the 8-1 bridging section BP81.

[0334] In other words, the display device 1 with the above-described structure according to the embodiment can improve tensile strength and minimize the load on the wiring. In a typical display device, in the non-display area NDA (see...) Figure 3 There is sufficient space in the display device 1 to arrange the drive circuit, so the output wiring or input lines of the drive circuit can be easily arranged. On the other hand, in the display device 1, since the output wiring or input lines should be located in the bridging section, the length of the wiring can be increased according to the "S" shape, and since multiple wirings should be arranged in a limited space, the width of each wiring may be reduced, thereby increasing the load on the wiring. However, in the display device 1 according to the embodiment, since the gate drive circuit GDC (see Figure 3 The output cabling is effectively arranged in the peripheral bridging section 22 (see...). Figure 12 In, and to the greatest extent possible ensure the peripheral bridging part 22 (see) Figure 12 The width of the output wiring in the image can be reduced, thus effectively reducing the load on the output wiring and providing a high-quality image.

[0335] Input lines used to apply signals or voltages to the data write stage GWST can also be located in island 7-1 IP71 and island 8-1 IP81. The first input line IL1 located in island 8-1 IP81 can have the same characteristics as... Figure 13The first input line IL1 located in island IP21 of 2-1 has a similar structure, and the second input line IL2 located in island IP71 of 7-1 can have the same structure as the first input line IL1 located in island IP21 of 2-1. Figure 13 The structure is similar to that of the second input line IL2 located in IP11 on island 1-1. Similarly, the high-voltage connection line VGHL and the low-voltage connection line VGLL, which are connection lines CW used to transmit the voltage of the first input line IL1, can have the same structure as... Figure 13 The high-voltage connection wiring VGHL and the low-voltage connection wiring VGLL have similar structures.

[0336] Figure 21a This is an enlarged schematic plan view showing a portion of a display device according to another embodiment. Figure 21b This illustrates a different embodiment. Figure 21a A magnified schematic plan view of part G of the display device. (Refer to...) Figure 21a and Figure 21b Features and references other than the characteristics of the transmit control level EMST, bypass level GBST, and output wiring. Figures 12 to 20 The described features are the same. Figure 21a and Figure 21b In, with Figures 12 to 20 The same elements are represented by the same reference numerals; therefore, the differences will be described primarily. For ease of explanation, Figure 21b Only the island section and output wiring are shown.

[0337] First, refer to Figure 21a The transmit control stage EMST can be located in island 1-1 IP11 and island 1-2 IP12, which serve as driver island DIPs, and the bypass stage GBST can be located in island 3-1 IP31 and island 3-2 IP32. However, with Figure 12 The situation differs when the two stages are located in a single drive island DIP, as in... Figure 21a In another embodiment shown, only one stage can reside in a single driver island DIP. For example, the m-th transmit control stage EMSTm (where m is a positive integer) can reside in island IP11 (1-1), and the (m+1)-th transmit control stage EMSTm+1 can reside in island IP12 (1-2). Similarly, the m-th bypass stage GBSTm can reside in island IP31 (3-1), and the (m+1)-th bypass stage can reside in island IP32 (3-2). On the other hand, two initialization stages GIST can reside in island IP51 (5-1) and island IP52 (5-2), and two data write stages GWST can reside in island IP71 (7-1) and island IP72 (7-2).

[0338] Because a driver island DIP can correspond to the display area DA (see...) Figure 3The pixels that make up two rows in the ) can be supplied with signals by the initialization level GIST and the data write level GWST, but the transmit control level EMST and the bypass level GBST can supply signals to the pixels that make up two rows.

[0339] Reference Figure 21b Since only the m-th transmit control stage EMSTm is located in island IP11 (1-1), only the first transmit control output wiring EMO1 can be located in bridge section BP11 (1-1) and bridge section BP21 (2-1). Furthermore, since only the m-th bypass stage GBSTm is located in island IP31 (3-1), only the first bypass output wiring GBO1 can be located in bridge section BP31 (3-1) and bridge section BP41 (4-1). Therefore, the first transmit control output wiring EMO1, the first bypass output wiring GBO1, the first initialization output wiring GIO1, and the second initialization output wiring GIO2 can be located in bridge section BP51 (5-1) and bridge section BP61 (6-1), and the first transmit control output wiring EMO1, the first bypass output wiring GBO1, the first initialization output wiring GIO1, the second initialization output wiring GIO2, the first data write output wiring GWO1, and the second data write output wiring GWO2 can be located in bridge section BP71 (7-1) and bridge section BP81 (8-1).

[0340] In other words, one output cable can be located in bridge section 1-1 BP11 and bridge section 2-1 BP21, two output cables can be located in bridge section 3-1 BP31 and bridge section 4-1 BP41, four output cables can be located in bridge section 5-1 BP51 and bridge section 6-1 BP61, and six output cables can be located in bridge section 7-1 BP71 and bridge section 8-1 BP81. In other words, because each driver island DIP only houses one transmit control stage (EMST) and one bypass stage (GBST), and the number of transmit control output cables (EMO) and bypass output cables (GOB) can be reduced by one, the number of cables located in each peripheral bridge section 22 (see...) can be reduced. Figure 12 The number of output wires in ).

[0341] Because the output wiring can be installed at each peripheral bridging section 22 (see...) Figure 12 Since the output wiring has a limited width, the width of each output wiring can be increased when the number of output wirings is reduced. As a result, because the display device 1 according to another embodiment can ensure a wider width of the output wiring, the load on the output wiring can be further reduced.

[0342] Figure 22a This is an enlarged schematic plan view showing a portion of a display device according to another embodiment. Figure 22b This illustrates a different embodiment. Figure 22a A magnified schematic plan view of part H of the display device. (Refer to...) Figure 22a and Figure 22b Features and references other than the characteristics of the initialization level GIST and the data writing level GWST Figure 21a and Figure 21b The described features are the same. Figure 22a and Figure 22b In, with Figure 21a and Figure 21b The same elements are represented by the same reference numerals, and the differences will be mainly described. For ease of explanation, Figure 22b Only the island section and output wiring are shown.

[0343] First, refer to Figure 22a The initialization level GIST and the data writing level GWST can be located in island 5-1 IP51 and island 5-2 IP52. That is, in Figure 22a In the display device 1, the initialization level GIST can also be used as the data writing level GWST. In other words, the initialization level GIST and the data writing level GWST can be configured as one level. The initialization level GIST can output the initialization control signal GI (see... Figure 10 It can also output a scanning signal GW (see...) Figure 10 Therefore, each of the 7-1 island IP71 and 7-2 island IP72, where the data write stage GWST was previously located, may include a dummy region. For example, 7-1 island IP71 may include a first dummy region DMA1 in which a dummy transistor can be located. Similarly, 7-2 island IP71 may include a second dummy region DMA2 in which a dummy transistor can be located.

[0344] Reference Figure 22b As described above, since the nth initialization level GISTn and the (n+1)th initialization level GISTn+1 can be located in the 5-1 island IP51, and the initialization level GIST can be used as the data write level GWST, the level does not need to be located in the 7-1 island IP71. Therefore, it is not necessary to separately configure the output wiring for transmitting the output signal of the data write level GWST. The first transmit control output wiring EMO1, the first bypass output wiring GBO1, the first initialization output wiring GIO1, and the second initialization output wiring GIO2 can be located in each of the 5-1 bridging section BP51 and the 6-1 bridging section BP61, and the first transmit control output wiring EMO1, the first bypass output wiring GBO1, the first initialization output wiring GIO1, and the second initialization output wiring GIO2 can be located in each of the 7-1 bridging section BP71 and the 8-1 bridging section BP81.

[0345] In other words, one output cable can be located in bridging sections 1-1 (BP11) and 2-1 (BP21), two output cables can be located in bridging sections 3-1 (BP31) and 4-1 (BP41), four output cables can be located in bridging sections 5-1 (BP51) and 6-1 (BP61), and four output cables can be located in bridging sections 7-1 (BP71) and 8-1 (BP81). In other words, when the initialization level (GIST) and the data write level (GWST) are configured as one level, the number of output cables located in bridging sections 7-1 (BP71) and 8-1 (BP81) can be reduced because the data write output cable (GWO) can be omitted.

[0346] Because the output wiring can be installed at each peripheral bridging section 22 (see...) Figure 12 Since the output wiring has a limited width, the width of each output wiring can be increased when the number of output wirings is reduced. As a result, because the display device 1 according to another embodiment can ensure a wider width of the output wiring, the load on the output wiring can be further reduced.

[0347] Figure 23 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment. Figure 24 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment. Figure 25 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment. Figure 26 This is an enlarged schematic plan view showing a portion of a display device according to another embodiment. (Refer to...) Figures 23 to 26 Features other than the features of the outer island portion 21' and the outer bridging portion 22' are the same as those of the reference. Figures 12 to 20 The described features are the same. Figures 23 to 26 In, with Figures 12 to 20 The same elements are represented by the same reference numerals, and the differences will be described in detail.

[0348] First, refer to Figure 23 The display device 1 may include peripheral island portions 21' spaced apart from each other in a first direction (e.g., the x-direction) and a peripheral bridging portion 22' connecting adjacent peripheral island portions 21' within a first non-display area NDA1. In this case, the size and / or width of the peripheral island portions 21' may be the same as the size and / or width of the main island portion 11. For example, the planar area of ​​the peripheral island portions 21' may be the same as the planar area of ​​the main island portion 11. Similarly, the size and / or width of the peripheral bridging portion 22' may be the same as the size and / or width of the main bridging portion 12. For example, the planar area of ​​the peripheral bridging portion 22' may be the same as the planar area of ​​the main bridging portion 12'.

[0349] Therefore, the outer island portion 21' can have the same shape as the main island portion 11, and the outer bridging portion 22 can have the same shape as the main bridging portion 12. That is, the outer bridging portion 22' can be connected to the four sides of the outer island portion 21', and each of the four outer bridging portions 22' can extend from each corner of the outer island portion 21'.

[0350] Furthermore, the peripheral island portion 21' located in any row of the first non-display area NDA1 can correspond to the main island portion 11 arranged in any row of the display area DA. For example, the peripheral island portion 21' located in any row of the first non-display area NDA1 can correspond to the main island portion 11 arranged in the i-th row of the display area DA, and the peripheral island portion 21' of another row can correspond to the main island portion 11 arranged in the (i+1)-th row of the display area DA.

[0351] Reference Figure 24 Only one stage can be located in the outer island 21' with the above structure. For example, the nth transmit control stage EMSTn can be located in island 1-1 IP11', and the (n+1)th transmit control stage EMSTn+1 can be located in island 1-2 IP12'. Similarly, the nth bypass stage GBSTn can be located in island 3-1 IP31', and the (n+1)th bypass stage GBSTn+1 can be located in island 3-2 IP32'. The nth initialization stage GISTn can be located in island 5-1 IP51', and the (n+1)th initialization stage GISTn+1 can be located in island 5-2 IP52'. The nth data write stage GWSTn can be located in island 7-1 IP71', and the (n+1)th data write stage GWSTn+1 can be located in island 7-2 IP72'.

[0352] Therefore, only the first transmit control output wiring EMO1 can be located in 1-1 bridging section BP11' and 2-1 bridging section BP21', and only the first transmit control output wiring EMO1 and the first bypass output wiring GBO1 can be located in 3-1 bridging section BP31' and 4-1 bridging section BP41'. Similarly, only the first transmit control output wiring EMO1, the first bypass output wiring GBO1, and the first initialization output wiring GIO1 can be located in 5-1 bridging section BP51' and 6-1 bridging section BP61', and only the first transmit control output wiring EMO1, the first bypass output wiring GBO1, the first initialization output wiring GIO1, and the first data write output wiring GWO1 can be located in 7-1 bridging section BP71' and 8-1 bridging section BP81'.

[0353] In other words, one output cable can be located in bridging sections 1-1 (BP11) and 2-1 (BP21), two output cables can be located in bridging sections 3-1 (BP31) and 4-1 (BP41), three output cables can be located in bridging sections 5-1 (BP51) and 6-1 (BP61), and four output cables can be located in bridging sections 7-1 (BP71) and 8-1 (BP81). In other words, even when the structure of the peripheral island 21' is the same as that of the main island 11, the above structure can maximize the width of the output cables and reduce the cable load.

[0354] Next, refer to Figure 25 The transmit control stage (EMST) can be located in island 1-1 (IP11') and island 1-2 (IP12'), and the bypass stage (GBST) can be located in island 3-1 (IP31') and island 3-2 (IP32'). However, with Figure 24 Unlike the case where one stage is located in a drive island DIP, in the case of... Figure 25 In the illustrated embodiment, only one stage can reside in both driver island DIPs. In this embodiment, the nth transmit control stage EMSTn can be located in island 1-1 IP11', and the transmit control stage EMST can be located outside island 1-2 IP12'. In another embodiment, a portion of the nth transmit control stage EMSTn can be located in island 1-1 IP11', and another portion of the nth transmit control stage EMSTn' can be located in island 1-2 IP12'. That is, the nth transmit control stage EMST can be divided and located in both island 1-1 IP11' and island 1-2 IP12'.

[0355] Similarly, the nth bypass level GBSTn can be located in the 3-1 island IP31', and the bypass level GBST may not be located in the 3-2 island IP32'. In another embodiment, a portion of the nth bypass level GBSTn can be located in the 3-1 island IP31', and another portion of the nth bypass level GBSTn' can be located in the 3-2 island IP32'. That is, the nth bypass level GBST can be divided and located in both the 3-1 island IP31' and the 3-2 island IP32'.

[0356] According to the embodiment, only the first transmit control output wiring EMO1 can be located in bridging sections 1-1 BP11', 2-1 bridging section BP21', 3-1 bridging section BP31', and 4-1 bridging section BP41', and only the first bypass output wiring GBO1 can be located in bridging sections 3-2 BP32' and 4-2 bridging section BP42'. Therefore, the first transmit control output wiring EMO1 and the first initialization output wiring GIO1 can be located in bridging sections 5-1 BP51' and 6-1 bridging section BP61', and the first bypass output wiring GBO1 and the second initialization output wiring GIO2 can be located in bridging sections 5-2 BP52' and 6-2 bridging section BP62'. Similarly, the first transmit control output wiring EMO1, the first initialization output wiring GIO1, and the first data write output wiring GWO1 can be located in the 7-1 bridging section BP71' and the 8-1 bridging section BP81', and the first bypass output wiring GBO1, the second initialization output wiring GIO2, and the second data write output wiring GWO2 can be located in the 7-2 bridging section BP72' and the 8-2 bridging section BP82'.

[0357] In other words, one output cable can be located in bridge sections 1-1 (BP11'), 2-1 (BP21'), 3-1 (BP31'), and 4-1 (BP41'); two output cables can be located in bridge sections 5-1 (BP51') and 6-1 (BP61'); and three output cables can be located in bridge sections 7-1 (BP71') and 8-1 (BP81'). In other words, because one transmit control stage (EMST) and one bypass stage (GBST) are positioned for each of the two driver island DIPs, and the number of transmit control output cables (EMO) and bypass output cables (GBO) can be reduced by one, the number of output cables located in each peripheral bridge section 22' can be reduced.

[0358] Because the output wiring can have a limited width in each peripheral bridging section 22', the width of each output wiring can be increased when the number of output wirings is reduced. As a result, since the display device 1 according to another embodiment can ensure a wider width of the output wiring, the load on the output wiring can be further reduced.

[0359] Next, refer to Figure 26 The initialization level GIST and the data writing level GWST can be located in island 5-1 IP51' and island 5-2 IP52'. That is to say, in Figure 26 In the display device 1, the initialization level GIST can be used as the data write level GWST. In other words, the initialization level GIST and the data write drive level GWST can be configured as one level. The initialization level GIST can output the initialization control signal GI (see... Figure 10It can also output a scanning signal GW (see...) Figure 10 Therefore, each of the 7-1 island IP71' and 7-2 island IP72', where the data write stage GWST was previously located, may include a dummy region. For example, 7-1 island IP71' may include a first dummy region DMA1 in which a dummy transistor can be located. Similarly, 7-2 island IP71 may include a second dummy region DMA2 in which a dummy transistor can be located.

[0360] In other words, since the nth initialization stage GISTn and the (n+1)th initialization stage GISTn+1 can be located in the 5-1 island IP51', and the initialization stage GIST can be used as the data write stage GWST, the stage does not need to be located in the 7-1 island IP71'. Therefore, it is not necessary to separately configure the output wiring for transmitting the output signal of the data write stage GWST. The first transmit control output wiring EMO1 and the first initialization output wiring GIO1 can be located in the 5-1 bridging section BP51' and the 6-1 bridging section BP61', and the first bypass output wiring GBO1 and the second initialization output wiring GIO2 can be located in the 5-2 bridging section BP52' and the 6-2 bridging section BP62'. Only the first transmit control output wiring EMO1 and the first initialization output wiring GIO1 can be located in the 7-1 bridging section BP71' and the 8-1 bridging section BP81', and the first bypass output wiring GBO1 and the second initialization output wiring GIO2 can be located in the 7-2 bridging section BP72' and the 8-2 bridging section BP82'.

[0361] In other words, one output cable can be located in bridging sections 1-1 (BP11'), 2-1 (BP21'), 3-1 (BP31'), and 4-1 (BP41'), and two output cables can be located in bridging sections 5-1 (BP51'), 6-1 (BP61'), 7-1 (BP71'), and 8-1 (BP81'). In other words, when the initialization level (GIST) and the data write level (GWST) are configured as one level, the number of output cables located in bridging sections 7-1 (BP71') and 8-1 (BP81') can be reduced because the data write output cable (GWO) can be omitted.

[0362] Because the output wiring can have a limited width in each peripheral bridging section 22', the width of each output wiring can be increased when the number of output wirings is reduced. As a result, since the display device 1 according to another embodiment can ensure a wider width of the output wiring, the load on the output wiring can be further reduced.

[0363] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, the display device comprising: The substrate includes a display area and a non-display area surrounding the display area; The peripheral island is located in the non-display area and includes driver islands and wiring islands spaced apart from each other. A peripheral bridging section is located in the non-display area and connects the driver island to the wiring island. A gate drive circuit is located in the driver island and includes multiple stages; Multiple input lines are located in the wiring island section; as well as Multiple output wirings are connected to the gate drive circuit and extend toward the display area. The number of output cables located in the peripheral bridging section gradually increases as the output cables move closer to the display area.

2. The display device according to claim 1, wherein, The width of each of the plurality of output lines gradually decreases as the output line approaches the display area.

3. The display device according to claim 2, wherein, The width of the peripheral bridging portion in the non-display area is constant. The output wirings are spaced apart from each other and each has the maximum width in the peripheral bridging portion.

4. The display device according to claim 1, wherein, The drive island and the wiring island are arranged alternately along the same row extending in a specific direction.

5. The display device according to claim 4, wherein, The output wiring located in the peripheral bridging section includes output wiring electrically connected to the output wiring of the stage located in the driver island section, which is positioned in the same row as the peripheral bridging section but further away from the display area than the peripheral bridging section.

6. The display device according to claim 4, wherein, The gate driving circuit includes a first gate driving circuit to an nth gate driving circuit arranged sequentially along the said direction, where n is a natural number of 2 or greater. Wherein, the first gate driving circuit is the outermost gate driving circuit among the first gate driving circuit to the nth gate driving circuit, and The nth gate driving circuit is positioned closer to the display area than the (n-1)th gate driving circuit.

7. The display device according to claim 6, wherein, The driver island includes a first driver island in which the first gate drive circuit is positioned, to an nth driver island in which the nth gate drive circuit is positioned, and The peripheral bridging portion includes a first peripheral bridging portion connected to the first driver island portion to an nth peripheral bridging portion connected to the nth driver island portion. The first driver island, the first peripheral bridge, the nth driver island, and the nth peripheral bridge are arranged in the same row.

8. The display device according to claim 7, wherein, In the first peripheral bridging section, there is a number of output cables that are the same as the total number of stages located in the first driver island section among the plurality of output cables.

9. The display device according to claim 7, wherein, In the nth peripheral bridging section, the same number of output wires as the total number of stages located in the first driver island to the nth driver island are positioned.

10. The display device according to claim 7, wherein, The width of the output cable located in the nth peripheral bridging section is smaller than the width of the output cable located in the (n-1)th peripheral bridging section.

11. The display device according to claim 7, wherein, In the nth driver island, a pre-output wire is positioned among the plurality of output wires, and the pre-output wire is connected to the stage located in the first driver island to the (n-1)th driver island among the plurality of stages.

12. The display device according to claim 11, wherein, In the nth peripheral bridging section, the pre-output wiring and the output wiring of the plurality of output wirings connected to the stage located in the nth driver island section are positioned.

13. The display device according to claim 11, wherein, The pre-output wiring located in the nth driver island extends outward from the periphery of the stage located in the nth driver island among the plurality of stages.

14. The display device according to claim 13, wherein, The output wiring of the plurality of output wirings connected to the stage located in the nth driver island is located at the center of the nth peripheral bridging section, and The pre-output wiring is located outside the nth peripheral bridging section.

15. The display device according to claim 11, wherein, The pre-output wiring located in the nth driver island extends through the space defined by the stages located in the nth driver island and spaced apart from each other.

16. The display device according to claim 15, wherein, The output wiring of the plurality of output wirings connected to the stage located in the nth driver island is located outside the nth peripheral bridge, and The pre-output wiring is located at the center of the nth peripheral bridging section.

17. The display device according to claim 1, wherein, The gate drive circuit includes at least one of the following: a transmit control drive circuit, a bypass drive circuit, an initialization drive circuit, and a data write drive circuit.

18. The display device according to claim 17, wherein, The plurality of output lines includes at least one of the following: a transmit control output line configured to transmit the output signal of the transmit control drive circuit; a bypass output line configured to transmit the output signal of the bypass drive circuit; an initialization output line configured to transmit the output signal of the initialization drive circuit; and a data write output line configured to transmit the output signal of the data write drive circuit.

19. The display device according to claim 18, wherein, In the gate driving circuit, the emission control driving circuit, the bypass driving circuit, the initialization driving circuit, and the data writing driving circuit are arranged sequentially from the outside of the display device toward the display area in the order stated above.

20. The display device according to claim 18, wherein, The peripheral bridging portion is configured as a plurality of peripheral bridging portions, and the emission control output wiring is located in the peripheral bridging portion that extends toward the display area and connects to the driver island portion in which the emission control drive circuit is located.

21. The display device according to claim 18, wherein, The peripheral bridging portion is configured as a plurality of peripheral bridging portions, and in the peripheral bridging portion that extends toward the display area and connects to the driver island portion in which the bypass drive circuit is located, the transmit control output wiring and the bypass output wiring are located.

22. The display device according to claim 18, wherein, The peripheral bridging section is configured as a plurality of peripheral bridging sections, and in the peripheral bridging section that extends toward the display area and connects to the driver island in which the initialization drive circuit is located, the transmit control output wiring, the bypass output wiring and the initialization output wiring are located.

23. The display device according to claim 18, wherein, The peripheral bridging portion is configured as a plurality of peripheral bridging portions, and in the peripheral bridging portion that extends toward the display area and connects to the driver island in which the data write drive circuit is located, the transmit control output wiring, the bypass output wiring, the initialization output wiring and the data write output wiring are located.

24. The display device according to claim 18, wherein, The width of the transmit control output wiring gradually decreases in the order of the driver island in which the bypass drive circuit is located, the driver island in which the initialization drive circuit is located, and the driver island in which the data write drive circuit is located.

25. The display device according to claim 17, wherein, The two stages of the initialization drive circuit and the two stages of the data write drive circuit are each located in a driver island, and One stage of the launch control drive circuit and one stage of the bypass drive circuit are each located in a driver island.

26. The display device according to claim 17, wherein, One stage of the initialization drive circuit and one stage of the data write drive circuit are each located in a driver island, and One stage of the launch control drive circuit and one stage of the bypass drive circuit are each located in two driver islands.

27. The display device according to claim 17, wherein, One stage of the initialization drive circuit and one stage of the data write drive circuit are located in a driver island.

28. The display device according to claim 27, wherein, The initialization driver circuit stage and the data write driver circuit stage are configured as one stage.

29. The display device according to claim 1, further comprising: Multiple main island sections are spaced apart from each other in the display area; as well as The main bridging section connects the main island sections arranged adjacent to each other among the plurality of main island sections.

30. The display device according to claim 29, wherein, The planar area of ​​the outer island is greater than the planar area of ​​one of the multiple main islands.

31. The display device according to claim 30, wherein, The peripheral bridging portion extends from the center of the side of the peripheral island portion.

32. The display device according to claim 30, wherein, At least one of the plurality of stages is located in the drive island.

33. The display device according to claim 29, wherein, The planar area of ​​the outer island is the same as the planar area of ​​one of the multiple main islands.

34. The display device according to claim 33, wherein, The peripheral bridging portion extends from the corner of the peripheral island portion.

35. The display device according to claim 33, wherein, One of the multiple stages is located in the driver island.

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