Electrolytic cell chamber voltage monitoring system and method

Abstract

The invention discloses an electrolytic cell chamber voltage monitoring system and method, relates to the technical field of monitoring of water electrolysis hydrogen production equipment, and solves the technical problems of low chamber voltage measurement precision, weak anti-interference capability, poor expansibility and insufficient reliability in a high common mode voltage and strong electromagnetic interference environment in the prior art. The system comprises an upper computer, a communication board and an acquisition group, a hierarchical distributed communication topology of a first-level star and a second-level daisy chain is adopted, the acquisition group realizes high-voltage optoelectronic isolation acquisition through optocoupler switching, differential conditioning and an independent ADC architecture, and the communication board integrates isolation protection and a DMA scheduling mechanism; the method comprises the four steps of system initialization, hierarchical polling collection, data aggregation and uploading and exception handling, and high-precision and high-reliability monitoring is achieved through hardware isolation and software cooperative scheduling. According to the invention, high-precision in-situ automatic measurement of multi-channel cell voltage under high common-mode voltage is realized.

Description

Technical Field

[0001] This invention relates to the field of monitoring technology for water electrolysis hydrogen production equipment, and specifically to a voltage monitoring system and method for monitoring the voltage of an electrolyzer chamber. Background Technology

[0002] The cell voltage is a core operating parameter of water electrolysis hydrogen production equipment, directly related to the health status, hydrogen production efficiency, and operational safety of the electrolyzer. It has irreplaceable monitoring value in industries such as chemical engineering, new energy, and hydrogen energy storage. To increase hydrogen production and reduce the unit cost of hydrogen production, large alkaline electrolyzers (ALK) and proton exchange membrane electrolyzers (PEM) generally adopt designs that increase current density and the number of cells connected in series. This results in a high common-mode background voltage of hundreds of volts during electrolyzer operation, and the strong electromagnetic interference in industrial environments further amplifies the noise, severely submerging the weak differential-mode voltage signal (millivolt level) of a single cell, posing a significant challenge to accurate measurement.

[0003] Existing electrolytic cell voltage monitoring technology has the following key drawbacks:

[0004] Insufficient anti-interference capability: Existing systems mostly use a single isolation method (such as power isolation or communication isolation) and have not formed a full-link high-voltage opto-isolation system. High common-mode voltage and electromagnetic interference can easily invade the measurement circuit through the power supply, signal or communication link, resulting in signal distortion. The crosstalk suppression ratio is generally lower than 40dB.

[0005] Limited measurement accuracy: The use of 8-12 bit ADC chips lacks targeted signal conditioning and temperature drift compensation mechanisms, and the measurement error is usually above ±1%, which cannot meet the high-precision monitoring requirements of 0.5% level, and makes it difficult to identify potential faults such as diaphragm breakdown and reverse polarity at an early stage.

[0006] Poor architectural scalability: It mostly adopts a centralized acquisition architecture, with all acquisition channels concentrated on a single device. When adding a new monitoring point, it is necessary to re-lay out high-voltage cabling, resulting in large hardware modifications, high maintenance costs, and the failure of a single device can paralyze the entire monitoring system.

[0007] Imbalance between real-time performance and reliability: The communication adopts a single polling mechanism without a priority scheduling strategy, resulting in delayed response to host computer commands; the lack of a sound fault isolation and automatic recovery mechanism makes it easy for channel failures to spread globally, making it unable to meet the unattended operation requirements of industrial sites.

[0008] Although some existing technologies attempt to employ distributed architectures or opto-isolation techniques, none have achieved deep integration of hierarchical distributed architectures and high-voltage opto-isolation: distributed architectures fail to optimize communication topologies for high common-mode environments, leading to signal reflection and interference superposition; opto-isolation is only applied to local modules, failing to form end-to-end isolation and thus unable to fundamentally solve the interference problem. Therefore, developing a monitoring system and method that combines high anti-interference capability, high precision, high scalability, and high reliability has become crucial to overcoming the bottlenecks of existing technologies. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a voltage monitoring system and method for electrolytic cell chambers based on a hierarchical distributed architecture and high-voltage opto-isolation. Through hardware architecture innovation and software collaborative scheduling, it solves the problem of accurate monitoring under high common-mode voltage and strong electromagnetic interference environments, while taking into account scalability, real-time performance and reliability.

[0010] The technical problem solved by this invention is achieved through the following technical solution:

[0011] An electrolytic cell voltage monitoring system, characterized in that it includes a host computer, a communication board, and a data acquisition group, wherein the communication board is connected to the host computer upwards and to the data acquisition group downwards via an RS-485 bus;

[0012] The host computer is used for parameter configuration, command issuance, and data visualization monitoring.

[0013] The communication board, serving as the central host and Modbus gateway, integrates RS-485 isolation circuit, TVS surge protection, and magnetically isolated transceiver. Its internal main control chip achieves real-time data relay and protocol conversion by executing the "upward response to host computer" task and the "downward polling of acquisition group" task in parallel.

[0014] The acquisition group is physically divided into multiple acquisition boards. Each acquisition board acquires the voltage signal of the electrolytic cell in real time through optocoupler switching, differential conditioning and independent ADC architecture.

[0015] The communication board and the acquisition groups adopt a hierarchical communication topology. The first-level network is a star architecture centered on the communication board, connecting each acquisition group; the second-level network is a daisy-chain cascade architecture between acquisition boards within each group.

[0016] Furthermore, the communication board adopts a DMA scheduling mechanism, which performs active polling of the lower-level machine when there are no instructions from the upper-level machine, and prioritizes responding to the upper-level machine's request when an interrupt instruction from the upper-level machine is detected.

[0017] Furthermore, the acquisition group includes a main acquisition board and multiple slave acquisition boards. The main acquisition board and slave acquisition boards in the acquisition group together constitute a distributed acquisition system. The main acquisition board and each slave acquisition board are responsible for acquiring the voltage of the electrolysis chamber and setting a unique device address through a DIP switch assembly. The main acquisition board is used to summarize the data of each slave acquisition board and package the summarized group data into a unified package.

[0018] Furthermore, both the acquisition motherboard and the acquisition slave board include an isolated power management module, an address detection module, a multiplexing switching module, a signal conditioning module, an ADC analog-to-digital converter module, a main control module, and a communication interface module. The output of the isolated power management module is connected to the address detection module, the multiplexing switching module, the signal conditioning module, the ADC analog-to-digital converter module, the main control module, and the communication interface module, respectively. The main control module is bidirectionally connected to the address detection module, the multiplexing switching module, the signal conditioning module, the ADC analog-to-digital converter module, and the communication interface module, respectively. The output of the main control module is connected to the input of the isolated power management module. The address detection module is equipped with a DIP switch assembly. By manually configuring the positions of the DIP switch assembly, flexible setting and accurate detection of the address within the acquisition group and the system address can be achieved, so as to meet the address differentiation and communication addressing requirements of multiple devices in the distributed acquisition system.

[0019] The multiplexing switching module is equipped with several potential acquisition nodes connected to the electrolytic cell group to cover multiple series electrolytic cells; the multiplexing switching module integrates an isolation optocoupler switching circuit, and the main control module is configured to select the voltage signal at both ends of the target electrolytic cell to the signal conditioning module by controlling the on / off state of the isolation optocoupler switching circuit.

[0020] The signal conditioning module employs a differential amplifier circuit with a high common-mode rejection ratio to separate and amplify the differential-mode voltage signal of the individual cell from the high common-mode background voltage, thereby obtaining a conditioned analog signal, and then transmitting the conditioned analog signal to the next stage circuit.

[0021] The ADC analog-to-digital conversion module uses a 16-bit resolution independent ADC chip to convert the conditioned analog signal into a digital signal.

[0022] The isolated power management module adopts a multi-level isolation design, which converts the external input power into multiple independent power supply branches through DC-DC and the isolated power management module, providing independent power to the main control module, signal conditioning module, ADC analog-to-digital conversion module and communication interface module respectively.

[0023] The main control module uses an STM32 series microcontroller chip. Each main control chip integrates an independent watchdog module to monitor the running status in real time and prevent the program from freezing and causing the system to crash. The main control chip controls the switching of optocoupler relays according to the timing sequence of "selection-stabilization-sampling-disconnection" to ensure physical isolation between channels and high signal-to-noise ratio of sampling.

[0024] The communication interface module uses an isolated transceiver chip paired with a multi-level surge protection network containing a gas discharge tube, a varistor, and a TVS transient suppression diode array, which takes into account miniaturization, high-speed transmission, and anti-static discharge, electrical fast transient pulse group, and lightning surge interference capabilities.

[0025] The acquisition motherboard also includes a data aggregation module, which is integrated into the main control circuit of the acquisition motherboard. The input terminal of the data aggregation module is connected to the acquisition slave board through the inter-board communication interface and is used to receive the voltage digital signals transmitted by each acquisition slave board. The module splices and temporarily stores the data received from the acquisition slave board and the data of the acquisition motherboard itself according to a preset physical address order.

[0026] A method for monitoring the voltage of an electrolytic cell chamber, characterized by comprising the following steps:

[0027] S1: System initialization. After the communication board and acquisition board are powered on, the underlying hardware abstraction layer initialization, clock configuration, peripheral initialization and Modbus protocol stack parameter configuration are executed, and the watchdog mechanism and core task thread are started.

[0028] S2: Hierarchical polling acquisition. The communication board, as the host, periodically polls each acquisition group and the acquisition boards within the group via the RS-485 bus. The acquisition board controls the optocoupler relay according to the "selection-stabilization-sampling-disconnection" timing sequence, and reads and temporarily stores the voltage data of each cell through the ADC chip.

[0029] S3: Data aggregation and uploading. The acquisition board aggregates the processed voltage data to the acquisition motherboard at the head of the group via a daisy chain architecture, and then transmits it to the communication board via a star architecture.

[0030] The communication board stores the data from each acquisition board into a shared buffer, captures the query command from the host computer, performs CRC16 verification, encapsulates it into a Modbus-RTU protocol frame, and uploads it to the host computer.

[0031] S4: Exception handling. The system captures variable-length data frames through serial port idle interrupt and uses a watchdog to monitor the operating status in real time. When communication is interrupted or data exceeds the range, the module is automatically restarted.

[0032] Furthermore, in step S1, the peripheral initialization includes GPIO, UART, SPI, TIM and IWDG initialization, and the core task thread includes a status indication task and a Modbus-RTU communication task; the Modbus protocol stack supports Master mode and Slave mode, the Master mode is used for the communication board to poll the acquisition board, and the Slave mode is used for the acquisition board to respond to the communication board's commands.

[0033] Furthermore, the specific implementation method of the hierarchical polling collection in step S2 is as follows:

[0034] The communication board polls each acquisition group sequentially according to a preset cycle. The acquisition motherboard in each acquisition group acts as the Modbus master station within the group, polling 1-3 acquisition slave boards within the group. The ADC data of the acquisition board is processed by a combination algorithm of dual-window trimming mean filtering and median filtering.

[0035] Furthermore, in step S3, the acquisition time for a single channel is ≤1s, and the acquisition cycle for all 374 channels is ≤36s; the data encapsulation process includes the assembly of address code, function code, data area and CRC16 check field to ensure data transmission integrity.

[0036] Furthermore, in step S4, the anomaly handling also includes a remote fault recovery mechanism: it supports remote OTA upgrades and parameter configurations via 03H register read and 06H parameter write instructions, without any manual intervention throughout the process.

[0037] The advantages and positive effects of this invention are:

[0038] 1. This electrolytic cell small cell voltage monitoring system and method, through a full-link high-voltage opto-isolation design including multi-level power supply isolation, optocoupler channel isolation, differential amplification isolation, and communication isolation, achieves a crosstalk suppression ratio of ≥60dB. It effectively eliminates electromagnetic interference from hundreds of volts of high common-mode voltage and ≤12kV high-voltage environments, solving the core technical pain point of weak signals being submerged by noise, and laying the foundation for high-precision measurement.

[0039] 2. This invention employs a 16-bit lossless ADC chip (sampling rate 1MSPS), a low-noise differential amplifier, and a low-drift reference voltage source. Combined with dual-window trimmed mean filtering and median filtering algorithms and a dynamic temperature drift compensation model, the acquisition error is strictly controlled within ±0.001, achieving high-precision measurement at the 0.5% level. Compared with existing technologies (measurement error of ±1% or more), the accuracy is improved by more than double, and minor faults such as diaphragm breakdown and reverse polarity can be identified at an early stage.

[0040] 3. The layered distributed architecture of this invention achieves high scalability and fault isolation. The first-level star topology ensures that each acquisition group operates independently, and a failure in one group does not affect the whole system; the second-level daisy-chain architecture optimizes signal transmission within the group and reduces reflections; the modular design enables a single device to integrate 374 channels, reducing deployment nodes by 80% compared to traditional multi-device stacking solutions. When adding monitoring points, only the acquisition group or acquisition board needs to be expanded, without the need to reconstruct the system, reducing hardware costs by 35% and maintenance investment by 50%.

[0041] 4. The collaborative scheduling mechanism of this invention balances real-time performance and reliability. The DMA scheduling and parallel execution of dual tasks on the communication board enable the coordination of priority response to upper-level computer instructions and active polling by lower-level computer, solving the problem of insufficient real-time performance of traditional polling mechanisms. Full-link isolation protection, watchdog monitoring, automatic anomaly recovery, and remote OTA upgrade functions ensure continuous and fault-free operation of the system in a wide temperature range of -40℃ to 85℃ and in unattended industrial environments, with reliability significantly superior to existing systems.

[0042] 5. This invention has a wide range of applications and strong compatibility, supporting various hydrogen production equipment such as large alkaline electrolyzers (ALK) and proton exchange membrane electrolyzers (PEM). It is compatible with the Modbus TCP / RTU protocol and can be seamlessly integrated into existing industrial control systems without requiring large-scale modifications to existing equipment, thus possessing extremely strong engineering application value. Attached Figure Description

[0043] Figure 1 This is a block diagram illustrating the principle of the present invention;

[0044] Figure 2 This is a schematic block diagram of the acquisition board of the present invention;

[0045] Figure 3 This is a schematic block diagram of the communication board of the present invention;

[0046] Figure 4 This is a flowchart illustrating the workflow of the data acquisition board of this invention.

[0047] Figure 5 This is a flowchart illustrating the operation of the communication board of the present invention. Detailed Implementation

[0048] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings:

[0049] This invention discloses a voltage monitoring system for use in an electrolytic water tank, comprising: a host computer, a communication board, and a data acquisition group. Wherein:

[0050] The host computer uses the standard Modbus TCP or RTU protocol to achieve bidirectional communication with the communication board. On the one hand, it can configure system parameters (such as alarm thresholds and polling cycles) and issue commands; on the other hand, it can obtain multi-channel small cell voltage data from the communication board to obtain the health status of the electrolytic water tank, and can realize functions such as storage, trend curve display, fault query and historical playback.

[0051] The communication board, acting as the central host of the system, schedules and controls the lower-level acquisition groups and serves as a Modbus gateway. It performs two core tasks in parallel: responding to query commands from the host computer and periodically polling the acquisition board groups via the RS-485 bus network. The core controller of the communication board is an STM32 series microcontroller, and its interface is equipped with TVS surge protection and magnetically isolated transceivers to adapt to the strong electromagnetic environment of industrial sites.

[0052] The data acquisition group is physically divided into multiple data acquisition boards. To adapt to the layout of the hydrogen production site and optimize high-voltage wiring, the multiple boards are divided into three groups: Group A, Group B, and Group C. Each group includes 2-4 data acquisition boards, which are packaged in an independent industrial-grade data acquisition box and are responsible for high-voltage side protection.

[0053] The data acquisition board is the core measurement unit of this system. Each board is responsible for acquiring voltage data from 36 electrolysis cells. The onboard circuitry adopts an architecture of "optical coupler switching + differential conditioning + independent ADC". The primary network (star topology) uses the communication board as the physical center. It connects radially to the main acquisition boards of Group A, Group B, and Group C via multiple independent RS-485 interfaces (or via RS-485 hubs). This design ensures electrical isolation and fault isolation between groups; a bus short circuit in Group A will not affect normal communication in Group B and Group C. The secondary network (daisy-chain topology) cascades the acquisition boards within each acquisition group using an RS-485 daisy-chain configuration. That is, the data output of one board is connected to the input of the next board, up to the end acquisition slave board of the group. This design ensures high-frequency signal integrity within the group and reduces signal reflection.

[0054] Based on the above overall architecture, this invention further describes the circuit structure of the acquisition board that undertakes the core function of data acquisition in the system. This circuit structure, as the hardware support for the underlying data acquisition, is a key technical feature ensuring the stable and reliable operation of the entire system.

[0055] The acquisition board includes a main acquisition board and a slave acquisition board. Both the main acquisition board and the slave acquisition board include an isolated power management module, an address detection module, a multiplexing switching module, a signal conditioning module, an ADC analog-to-digital converter module, a main control module, and a communication interface module. The output of the isolated power management module is connected to the address detection module, the multiplexing switching module, the signal conditioning module, the ADC analog-to-digital converter module, the main control module, and the communication interface module, respectively. The main control module is bidirectionally connected to the address detection module, the multiplexing switching module, the signal conditioning module, the ADC analog-to-digital converter module, and the communication interface module, respectively. The output of the main control module is connected to the input of the isolated power management module. The main acquisition board also includes a data aggregation module.

[0056] The isolated power management module adopts a multi-level power tree architecture of "bus power (24V) -> main step-down (5V) -> distributed isolation (multi-channel DC-DC)", constructing four electrically isolated independent power supply domains to completely block ground loop interference.

[0057] The first isolated DC-DC power supply powers the digital part of the main control chip, related logic circuits, and ADC analog-to-digital conversion module, effectively preventing high-frequency switching noise of the digital circuits from coupling to the analog side.

[0058] A second isolated DC-DC power supply provides clean voltage to the circuitry of the signal conditioning module and the analog section of the ADC analog-to-digital conversion module, minimizing the impact of power supply ripple on the ADC sampling signal-to-noise ratio.

[0059] A bipolar voltage is generated through a third isolated power supply to drive the signal conditioning module, ensuring the large dynamic range requirement for signal processing.

[0060] A fourth isolated power supply provides a separate power supply to the communication interface module, preventing damage to the core control circuitry from surges, static electricity, or ground potential differences on the external bus. This quadruple isolation domain design significantly improves the system's electromagnetic compatibility (EMC) performance, ensuring measurement stability in complex industrial electromagnetic environments.

[0061] The address detection module includes a multi-bit DIP switch assembly. The signal output terminals of the multi-bit DIP switch assembly are electrically connected to the general purpose input / output (GPIO) ports of the main control module, and the common terminal is connected to ground. The main control module is configured to determine the unique physical address of the current circuit board in the bus network by collecting the high and low level state combinations of the GPIO ports and decoding them.

[0062] The communication interface module employs a highly robust design combining integrated isolation and multi-level protection. At the isolation level, this embodiment abandons the traditional discrete optocoupler isolation scheme and adopts a transceiver chip with isolation technology, significantly improving data transmission rate and signal integrity while reducing PCB footprint. At the physical interface protection level, a multi-level surge protection network is designed. This network includes gas discharge tubes, varistors, and a TVS transient suppression diode array, coupled with adaptive pull-up and pull-down resistor biasing circuits, ensuring the deterministic level of the bus in idle states. This design enables the communication interface to effectively resist common industrial field interferences such as electrostatic discharge (ESD), electrical fast transient bursts (EFT), and lightning surges, ensuring the reliability of remote data transmission.

[0063] The signal conditioning module is the front-end unit of the ADC analog-to-digital conversion, employing a hierarchical processing architecture of "optical coupling matrix → differential amplification → filtering". The differential amplification unit uses a high common-mode rejection ratio (CMRR) operational amplifier, relying on its internal precisely matched resistor network to achieve both high input impedance and high attenuation ratio. This allows for precise amplification of small differential voltage signals and protection of subsequent low-voltage circuits from breakdown damage in high-voltage misconnection scenarios. A second-order RC anti-aliasing filter is configured after the differential amplification to effectively filter out high-frequency noise interference, providing a clean signal with a high signal-to-noise ratio for subsequent analog-to-digital conversion.

[0064] The ADC analog-to-digital conversion module, as the core conversion unit of the acquisition link, adopts a high sampling rate ADC chip to receive the clean signal processed by the front-end signal conditioning module and complete the analog-to-digital conversion. At the same time, in conjunction with the software oversampling and averaging filtering algorithm of the main control unit, random noise is further suppressed, significantly improving the effective resolution (ENOB) and final measurement accuracy of the system, ensuring the accuracy and reliability of the acquired data.

[0065] The multiplexing switching module employs a high-voltage optocoupler relay array as the core component for channel switching. Specifically, the circuit integrates several optocoupler relays to form a high-density switching matrix. Compared with traditional mechanical relays, this optocoupler relay array has significant technical advantages, including no mechanical contacts, long operating life, no switching noise, and nanosecond-level response speed. Furthermore, the module adopts a differential multiplexing topology. During the acquisition process, the main control module controls the on / off combinations of corresponding switching channels in the optocoupler switching matrix, selecting the voltage of the current test cell in a time-division manner and connecting it to the subsequent differential signal link. This architecture can withstand extremely high common-mode voltages, enabling the system to be directly connected to battery strings of hundreds of volts or high-voltage industrial equipment, safely performing low-voltage differential measurements on any single node (such as a single battery cell) without requiring an expensive independent isolation amplifier for each sampling channel, thereby significantly reducing the hardware cost and size of the multi-channel high-voltage acquisition system.

[0066] The main control module uses an STM32 series microcontroller main control chip, and each main control chip integrates an independent watchdog module; the microcontroller unit is configured to interact with other modules and perform logic control through general purpose input / output interface (GPIO), direct memory access controller (DMA) and serial communication interface (UART / SPI).

[0067] The data aggregation module is integrated into the main control circuit of the acquisition motherboard. The input terminal of this module is electrically connected to the acquisition slave boards via an inter-board communication interface, and is used to receive voltage digital signals transmitted from each acquisition slave board. The data aggregation module internally includes a data mapping storage unit, used to concatenate and temporarily store the received voltage digital signals from the acquisition slave boards and the voltage digital signals acquired by the acquisition motherboard itself according to a preset physical address order. The output terminal of this module is electrically connected to the uplink communication interface, and is used to output the concatenated group total data frame.

[0068] The specific implementation steps of the acquisition board are as follows: First, control the optocoupler relay to switch the access voltage.

[0069] The main control chip of the STM32 series microcontroller sends a gating signal to the high-voltage optocoupler switching matrix according to the preset inspection sequence. Specifically, it controls the optical solid-state relay corresponding to the currently tested channel to close and conduct, while keeping the optical solid-state relays of other channels in the open state. Through this operation, the battery cell under test or the high-voltage differential signal is connected to the multiplexing switching module, realizing multi-channel time-division multiplexing access in a high common-mode voltage environment.

[0070] The high-voltage differential signal is fed into the signal conditioning module. The high common-mode rejection ratio (CMRR) operational amplifier circuit in the signal conditioning module performs precise attenuation and differential amplification on the input high-voltage differential signal. This step aims to filter out high common-mode voltage interference superimposed on the differential signal and adjust the signal amplitude to the linear input range allowed by the subsequent ADC analog-to-digital conversion module, outputting a conditioned analog signal.

[0071] The conditioned signal is acquired. The ADC analog-to-digital converter receives the output analog signal, performs sample-and-hold and quantization processing, and converts the analog signal into a high-resolution digital signal. In a preferred embodiment, this step may include multiple consecutive samples for subsequent oversampling averaging.

[0072] The digital signal is transmitted to the main control module. After conversion by the ADC analog-to-digital converter module, the digital signal is transmitted to the main control module via the board-level communication bus (SPI bus). After receiving the raw data, the main control module performs digital filtering (moving average filtering), calibration calculation, and data packaging to generate a data frame that conforms to the communication protocol.

[0073] The main control module communicates with the communication board or motherboard. Based on the current hardware address configuration or role setting of the circuit board, the main control module selects the appropriate data upload path. This step specifically includes the following decision logic:

[0074] If this acquisition board is configured in motherboard mode, the master control module interacts directly with the system's communication gateway board (communication board) via an isolated communication interface (such as RS485), uploading the acquired data frames to the communication gateway. Simultaneously, the motherboard polls and reads data from each slave board. The motherboard's master control module operates in master mode. Using a time base generated by an internal timer, the master control module periodically sends data query commands (e.g., Modbus function code 03 read holding register command) to each lower-level slave board connected to the bus via the downlink communication interface (isolated RS485 bus).

[0075] If this acquisition board is configured as a slave board, the master control module transmits data to the next higher-level motherboard or the previous node in the cascade link via the cascade interface. The data is then collected and uploaded by the next higher-level device.

[0076] Through the above steps, this embodiment can flexibly adapt to different battery pack sizes and system topologies, supporting both independent operation of a single board and cascading expansion of multiple boards.

[0077] The specific implementation steps of the communication board involve the main control module polling and reading data from each motherboard. The main control module of the communication board operates in Master mode. Using a time base generated by an internal timer, the main control module periodically sends data query commands (e.g., Modbus function code 03 read holding register command) to each lower-level motherboard connected to the bus via the downlink communication interface (isolated RS485 bus). This step achieves polling acquisition of distributed multi-node data.

[0078] After reading the data, the main control module integrates and stores the data in the memory area. When the main control module receives a data packet returned by the lower-level motherboard, it first performs a CRC check to ensure data integrity. After the check passes, the main control module moves the parsed payload data to a contiguous memory mirror area (Shadow Memory) or a global array allocated in the local SRAM, according to a predefined address mapping table. Through this step, the scattered data on various motherboards is logically concatenated and integrated into a complete system status data table.

[0079] The main control module responds to requests from the host computer for data transmission. When the host computer (PC or server) sends a query command via the uplink communication interface, the main control module does not need to initiate a real-time query to the lower-level motherboard again. Instead, it directly indexes the already updated memory image area. The main control module quickly sends the integrated data in the memory area to the host computer via the uplink interface through direct memory access (DMA) or interrupt methods.

[0080] Through the above steps, this embodiment implements a "proactive aggregation, passive uploading" mechanism for data. Compared to the traditional transparent transmission mode, this mechanism significantly reduces the communication waiting time of the host computer, solves the system response delay problem caused by the increase in the number of lower-level nodes, and also reduces the polling burden on the host computer.

[0081] Although embodiments and drawings of the present invention have been disclosed for illustrative purposes, those skilled in the art will understand that various substitutions, variations and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the scope of the present invention is not limited to the contents disclosed in the embodiments and drawings.

Claims

1. A voltage monitoring system for an electrolytic cell chamber, characterized in that: It includes a host computer, a communication board, and a data acquisition group. The communication board is connected to the host computer at the top and to the data acquisition group at the bottom via an RS-485 bus. The host computer is used for parameter configuration, command issuance, and data visualization monitoring. The communication board, serving as the central host and Modbus gateway, integrates RS-485 isolation circuit, TVS surge protection, and magnetically isolated transceiver. Its internal main control chip achieves real-time data relay and protocol conversion by executing the "upward response to host computer" task and the "downward polling of acquisition group" task in parallel. The acquisition group is physically divided into multiple acquisition boards. Each acquisition board acquires the voltage signal of the electrolytic cell in real time through optocoupler switching, differential conditioning, and an independent ADC architecture. The communication board and the acquisition groups adopt a hierarchical communication topology. The first-level network is a star architecture centered on the communication board, connecting each acquisition group; the second-level network is a daisy-chain cascade architecture between acquisition boards within each group.

2. The electrolytic cell chamber voltage monitoring system according to claim 1, characterized in that: The communication board adopts a DMA scheduling mechanism, which performs active polling of the lower-level machine when there is no instruction from the host computer, and prioritizes responding to the host computer's request when an interrupt instruction from the host computer is detected.

3. The electrolytic cell chamber voltage monitoring system according to claim 1, characterized in that: The acquisition group includes a main acquisition board and multiple slave acquisition boards. The main acquisition board and slave acquisition boards in the acquisition group together constitute a distributed acquisition system. The main acquisition board and each slave acquisition board are responsible for acquiring the voltage of the electrolysis chamber and setting a unique device address through a DIP switch assembly. The main acquisition board is used to summarize the data of each slave acquisition board and package the summarized group data into a unified package.

4. The electrolytic cell chamber voltage monitoring system according to claim 3, characterized in that: Both the acquisition motherboard and the acquisition slave board include an isolated power management module, an address detection module, a multiplexing switching module, a signal conditioning module, an ADC analog-to-digital converter module, a main control module, and a communication interface module. The output of the isolated power management module is connected to the address detection module, the multiplexing switching module, the signal conditioning module, the ADC analog-to-digital converter module, the main control module, and the communication interface module, respectively. The main control module is bidirectionally connected to the address detection module, the multiplexing switching module, the signal conditioning module, the ADC analog-to-digital converter module, and the communication interface module, respectively. The output of the main control module is connected to the input of the isolated power management module. The address detection module is equipped with a DIP switch component. By manually configuring the positions of the DIP switch component, the address within the acquisition group and the system address can be flexibly set and accurately detected, so as to meet the address differentiation and communication addressing requirements of multiple devices in the distributed acquisition system. The multiplexing switching module is configured with several potential acquisition nodes connected to the electrolytic cell group to cover multiple series electrolytic cells; the multiplexing switching module integrates an isolation optocoupler switching circuit, and the main control module is configured to select the voltage at both ends of the target electrolytic cell to the signal conditioning module by controlling the on / off state of the isolation optocoupler switching circuit. The signal conditioning module employs a differential amplifier circuit with a high common-mode rejection ratio to separate and amplify the differential-mode voltage signal of the individual cell from the high common-mode background voltage, thereby obtaining a conditioned analog signal, and then transmitting the conditioned analog signal to the next stage circuit. The ADC analog-to-digital conversion module uses a 16-bit resolution independent ADC chip to convert the conditioned analog signal into a digital signal. The isolated power management module adopts a multi-level isolation design, which converts the external input power into multiple independent power supply branches through DC-DC and the isolated power management module, providing independent power to the main control module, signal conditioning module, ADC analog-to-digital conversion module and communication interface module respectively. The main control module uses an STM32 series microcontroller chip. Each main control chip integrates an independent watchdog module to monitor the running status in real time and prevent the program from freezing and causing the system to crash. The main control chip controls the switching of optocoupler relays according to the timing sequence of "selection-stabilization-sampling-disconnection" to ensure physical isolation between channels and high signal-to-noise ratio of sampling. The communication interface module uses an isolated transceiver chip paired with a multi-level surge protection network containing a gas discharge tube, a varistor, and a TVS transient suppression diode array, which takes into account miniaturization, high-speed transmission, and anti-static discharge, electrical fast transient pulse group, and lightning surge interference capabilities. The acquisition motherboard also includes a data aggregation module, which is integrated into the main control circuit of the acquisition motherboard. The input terminal of the data aggregation module is connected to the acquisition slave board through the inter-board communication interface and is used to receive the voltage digital signals transmitted by each acquisition slave board. The module splices and temporarily stores the data received from the acquisition slave board and the data of the acquisition motherboard itself according to a preset physical address order.

5. The voltage monitoring system for an electrolytic cell chamber according to claim 1, characterized in that: The main control module of the acquisition board controls the switching of optocoupler relays according to the timing sequence of "selection-stabilization-sampling-disconnection" to ensure physical isolation between channels and high signal-to-noise ratio of sampling.

6. A method for monitoring the voltage of an electrolytic cell chamber, characterized in that: This monitoring method is implemented based on the electrolytic cell voltage monitoring system according to any one of claims 1-5, and the monitoring method includes the following steps: S1: System initialization. After the communication board and acquisition board are powered on, the underlying hardware abstraction layer initialization, clock configuration, peripheral initialization and Modbus protocol stack parameter configuration are executed, and the watchdog mechanism and core task thread are started. S2: Hierarchical polling acquisition. The communication board, as the host, periodically polls each acquisition group and the acquisition boards within the group via the RS-485 bus. The acquisition board controls the optocoupler relay according to the "gating-stabilizing-sampling-disconnecting" sequence, and reads and temporarily stores the voltage data of each cell through the ADC chip. S3: Data aggregation and uploading. The acquisition board aggregates the processed voltage data to the acquisition motherboard at the head of the group via a daisy chain architecture, and then transmits it to the communication board via a star architecture. The communication board stores the data from each acquisition board into a shared buffer, captures the query command from the host computer, performs CRC16 verification, encapsulates it into a Modbus-RTU protocol frame, and uploads it to the host computer to complete the current cell voltage monitoring process.

7. The electrolytic cell chamber voltage monitoring system according to claim 6, characterized in that: In step S1, the peripheral initialization includes GPIO, UART, SPI, TIM and IWDG initialization, and the core task thread includes the status indication task and the Modbus-RTU communication task; the Modbus protocol stack supports Master mode and Slave mode. In Master mode, the communication board polls the acquisition board, and in Slave mode, the acquisition board responds to the communication board's commands.

8. The method for monitoring voltage in an electrolytic cell according to claim 6, characterized in that: In step S2, the specific implementation method of the hierarchical polling data collection is as follows: The communication board polls each acquisition group sequentially according to a preset cycle. The acquisition motherboard in each acquisition group acts as the Modbus master station within the group, polling 2-3 acquisition slave boards within the group. The ADC data of the acquisition board is processed by a combination algorithm of dual-window trimming mean filtering and median filtering, and then calibrated in real time through compensation coefficients.

9. The method for monitoring the voltage of an electrolytic cell chamber according to claim 6, characterized in that: It also includes exception handling. The system captures variable-length data frames through serial port idle interrupts, uses a watchdog to monitor the operating status in real time, and automatically restarts the module when communication is interrupted or data exceeds the range.

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