Perovskite X-ray image acquisition system and method based on time domain signal processing

Abstract

The invention relates to the technical field of signal processing, and particularly provides a perovskite X-ray image acquisition system and method based on time domain signal processing, and the system comprises a radiation source module, a detector module, an analog front end module, an ADC module, an FPGA module, a high-speed interface module and an upper computer module. The detector module is used for carrying out charge collection and integration on photons to obtain integral node voltage in pixels, the analog front-end module is used for sampling the integral node voltage in the pixels to obtain multi-channel analog differential voltage, and the ADC module is used for carrying out synchronous sampling quantization on the multi-channel analog differential voltage to obtain a pixel value sequence and a synchronous marking signal. The FPGA module is used for carrying out time domain signal processing to obtain image frames and metadata, the high-speed interface module is used for carrying out packaging to obtain an Ethernet frame packet, and the upper computer module is used for carrying out unpacking display on the Ethernet frame packet to obtain a control signal. According to the invention, the imaging quality and precision are improved by adding the FPGA module.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a perovskite X-ray image acquisition system and method based on time-domain signal processing. Background Technology

[0002] Perovskite direct conversion X-ray detectors are becoming potential core devices for medical imaging and industrial non-destructive testing due to their high X-ray absorption efficiency and integration with large-area readout arrays. The true usability of an imaging system depends not only on the device materials and pixel structure but also significantly on the temporal processing in the signal chain. Key metrics for evaluating the overall imaging capability of a detector are the detection quantum efficiency (DQE) and the modulation transfer function (MTF) that describes detail fidelity.

[0003] Existing direct conversion arrays typically consist of: detector pixel array → analog readout (integration / sample-and-hold / CDS) → ADC → digital processing / host architecture. To improve image quality, common methods include, but are not limited to: static dark field / gain correction (based on offline or periodic calibration frames); spatial domain denoising (median / mean / bilateral filtering, non-local averaging, etc.); row and column fringe correction (row-by-row / column-by-column bias reduction, frequency domain fringe suppression); and inter-frame averaging (trading time for signal-to-noise ratio, sacrificing temporal resolution).

[0004] While existing technologies have improved image quality to some extent, they often suffer from the following problems: temporal statistics are not coupled with the DQE target, and filtering parameters are mostly selected empirically, making it difficult to optimize the system around maximizing DQE and maintaining MTF at the target spatial frequency; the response to dynamic distortion is insufficient, and dark current drift, gain nonlinearity / saturation, etc., change with dose, temperature, and time, making it difficult for static compensation to track them in a timely manner; real-time implementation is difficult, and complex spatial domain algorithms put a lot of pressure on resources, bandwidth, and timing on FPGAs, making it difficult to run stably at high frame rates. Summary of the Invention

[0005] In view of this, this invention proposes a perovskite X-ray image acquisition system and method based on time-domain signal processing. By adding an FPGA module, it achieves real-time intra-frame processing across the entire link. Hardware implementation of the algorithm reduces the load on the host computer, achieving a latency of less than one frame period. Parameters can be switched online to adapt to rapid changes in operating conditions. By employing fixed-point mapping and DSP parallelism, the computational load and resource consumption for filtering / compensation are controlled, enhancing the deployability of the project. Higher image quality can be obtained without increasing the dose, and the radiation dose can be equivalently reduced to achieve the same diagnostic goals, helping to reduce patient / sample exposure. It also reduces reliance on expensive, extremely low-noise, and extremely uniform components; the system image quality target can be achieved by relaxing the specifications of the front-end components, saving costs at the system level.

[0006] In a first aspect, the present invention provides a perovskite X-ray image acquisition system based on time-domain signal processing, comprising a radiation source module, a detector module, an analog front-end module, an ADC module, an FPGA module, a high-speed interface module, and a host computer module, wherein... The X-ray source module is used to emit photons, which pass through the object to be imaged, are attenuated by the object, and are then sent to the detector module. The detector module is used to collect and integrate photons to obtain the integration node voltage within the pixel and send it to the analog front-end module. The analog front-end module is used to sample and hold, reset, and correlate double sampling the voltage of the integration node within the pixel to obtain multi-channel analog differential voltage and send it to the ADC module. The ADC module is used to synchronously sample and quantize multi-channel analog differential voltages to obtain pixel value sequences and synchronization marker signals, which are then sent to the FPGA module. The FPGA module is used to perform time-domain signal processing on pixel value sequences and synchronization marker signals to obtain image frames and metadata, which are then sent to the high-speed interface module. The high-speed interface module is used to package image frames and metadata to obtain Ethernet frame packets and send them to the host computer module. The host computer module is used to unpack and display Ethernet frame packets to obtain control signals.

[0007] Based on the above technical solutions, preferably, the FPGA module includes a data decoding module, a dynamic compensation module, a row and column readout noise correction module, a pixel-level temporal filtering module, an inter-frame fusion module, and an output packaging module.

[0008] Based on the above technical solutions, preferably, the data decoding module is used to perform channel alignment, row and column addressing, and bad pixel replacement on the pixel value sequence and synchronization marker signal to obtain a pixel value matrix.

[0009] Based on the above technical solutions, preferably, the dynamic compensation module is used to map the pixel value matrix from the original ADC code value to the linear luminance code value, while maintaining a slow variable baseline for each pixel and dynamically updating it to obtain the dynamically compensated pixel value.

[0010] Based on the above technical solutions, preferably, the row and column readout noise correction module is used to eliminate the fixed row and column bias introduced by the readout link on a frame-by-frame basis for the dynamically compensated pixel value, and restore the global brightness baseline after deducting the row bias and column bias to obtain the corrected pixel value.

[0011] Based on the above technical solutions, preferably, the pixel-level temporal filtering module is used to perform high-pass filtering to remove slow drift and low-pass filtering to suppress high frequencies for each pixel of the corrected pixel value, so as to obtain the filtered real-time pixel stream.

[0012] Based on the above technical solutions, preferably, the inter-frame fusion module is used to improve the signal-to-noise ratio of the filtered real-time pixel stream through adaptive exponential sliding time fusion and motion gating, thereby obtaining an enhanced view pixel stream.

[0013] Based on the above technical solutions, preferably, the output encapsulation module is used to statistically analyze the saturation count, mean, variance, and row and column residuals of the enhanced view pixel stream and record key parameters to obtain image frames and metadata.

[0014] Based on the above technical solutions, preferably, the control signal includes tube voltage, tube current, integration time, analog gain, filter parameters and baseline step size, and the control signal acts on the FPGA module, analog front-end module and X-ray source module through the control bus.

[0015] Secondly, the present invention also provides a method for acquiring perovskite X-ray images based on time-domain signal processing, the method comprising: Photons are emitted by the X-ray source module, pass through the object to be imaged, and are attenuated by the object to be imaged to obtain the attenuated photons; The attenuated photons are sent to the detector module for charge collection and integration to obtain the integration node voltage within the pixel. The voltage of the integral node within the pixel is sent to the analog front-end module for sample-and-hold, reset, and correlation double sampling to obtain multi-channel analog differential voltage. The multi-channel analog differential voltage is sent to the ADC module for synchronous sampling and quantization to obtain the pixel value sequence and the synchronization marker signal; The pixel value sequence and synchronization marker signal are sent to the FPGA module for time-domain signal processing to obtain image frames and metadata. The image frame and metadata are sent to the high-speed interface module for packaging, resulting in an Ethernet frame packet. The Ethernet frame packets are sent to the host computer module for unpacking and display to obtain control signals.

[0016] The perovskite X-ray image acquisition system based on time-domain signal processing provided by this invention has the following advantages over existing technologies: (1) This invention introduces an FPGA digital signal processing unit to achieve pixel-level filtering, dynamic compensation and type-based noise suppression based on time DQE optimization, which improves the real-time performance and reliability of the whole machine. It can achieve detail reproduction under the same dose, improve contrast visibility, reduce row and column stripes, make the background more uniform, reduce high-frequency noise, reduce the probability of repeated exposure, and improve imaging quality and accuracy.

[0017] (2) The present invention allows the host computer to switch between register addresses and adaptive gears with one click; the metadata output (saturated pixel count, noise estimation, gear marking) facilitates process monitoring and traceability, improves the ease of processing, operation and control, can run stably for a long time, and has no algorithm divergence and cumulative drift; it can meet the image quality requirements at low doses, and indirectly reduces the risk of environmental and human exposure.

[0018] (3) This invention enables real-time operation of the entire link within a frame by adding an FPGA module, reduces the load on the host computer by hardware-based algorithm implementation, achieves a latency of less than one frame period, and allows parameters to be switched online to adapt to rapid changes in operating conditions. By adopting fixed-point and DSP parallel processing, the computational load and resource consumption of filtering / compensation are controlled, enhancing the deployability of the project. Higher image quality can be obtained without increasing the dose, and the radiation dose can be reduced to achieve the same diagnostic goals, which helps to reduce the radiation exposure of patients / samples. It also reduces the dependence on expensive devices with extremely low noise and extremely uniformity, and the system image quality goals can be achieved by relaxing the front-end device specifications, thus saving costs at the system level. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the perovskite X-ray image acquisition system based on time-domain signal processing provided by the present invention; Figure 2 This is a schematic diagram of the FPGA module provided by the present invention; Figure 3 This is a schematic flowchart of the perovskite X-ray image acquisition method based on time-domain signal processing provided by the present invention.

[0021] Explanation of reference numerals in the attached diagram: 1. X-ray source module; 2. Detector module; 3. Analog front-end module; 4. ADC module; 5. FPGA module; 6. High-speed interface module; 7. Host computer module; 51. Data decoding module; 52. Dynamic compensation module; 53. Row and column readout noise correction module; 54. Pixel-level temporal filtering module; 55. Inter-frame fusion module; 56. Output packaging module. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0023] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0024] like Figure 1 As shown, this invention provides a perovskite X-ray image acquisition system based on time-domain signal processing, including a radiation source module 1, a detector module 2, an analog front-end module 3, an ADC module 4, an FPGA module 5, a high-speed interface module 6, and a host computer module 7, wherein... The X-ray source module 1 is used to emit photons, which pass through the object to be imaged and are attenuated by the object to be imaged to obtain attenuated photons, which are then sent to the detector module 2. The detector module 2 is used to collect and integrate photons to obtain the integration node voltage within the pixel and send it to the analog front-end module 3; The analog front-end module 3 is used to sample and hold, reset, and correlate double sampling the voltage of the integration node within the pixel to obtain multi-channel analog differential voltage and send it to the ADC module 4; The ADC module 4 is used to synchronously sample and quantize the multi-channel analog differential voltage to obtain a pixel value sequence and a synchronization marker signal, which are then sent to the FPGA module 5. The FPGA module 5 is used to perform time-domain signal processing on the pixel value sequence and synchronization marker signal to obtain image frames and metadata, and send them to the high-speed interface module 6. The 6 is used to package image frames and metadata to obtain Ethernet frame packets and send them to the host computer module 7; The host computer module 7 is used to unpack and display Ethernet frame packets to obtain control signals.

[0025] In some embodiments, the X-ray source module 1 is an X-ray source, the detector module 2 is a perovskite detector pixel array, the analog front-end module 3 is an analog readout or front-end, the ADC module 4 is a multi-channel ADC, the FPGA module 5 is an FPGA digital signal processing unit, the high-speed interface module 6 is a high-speed interface PCIe / Gigabit Ethernet / USB3, and the host computer module 7 is a host computer.

[0026] The FPGA digital signal processing unit is used to implement pixel-level filtering, dynamic compensation and type-specific noise suppression based on time-based DQE optimization, and to ensure the real-time performance and reliability of the whole machine.

[0027] The perovskite X-ray image acquisition system based on time-domain signal processing operates in the following order: X-ray source → detector → analog front-end → ADC → FPGA → high-speed interface → host computer. The specific process is as follows: The X-ray source receives the tube voltage and tube current, outputs a controlled X-ray photon stream, and sends it to irradiate the perovskite array detector. The perovskite array detector performs charge collection and integration, and outputs the integration node voltage within the pixel.

[0028] The analog front-end integrates the node voltage within the pixel. It performs sample-and-hold, reset, and correlation double sampling to remove kT / C noise and 1 / f noise. The signal is amplified with a certain gain and bandwidth, and multiplexed according to row and column timing to output multi-channel analog differential voltage.

[0029] The ADC receives multi-channel analog differential voltage, synchronously samples and quantizes each channel, performs 16-bit binary quantization on the data and adds frame, line and pixel synchronization markers, and outputs a sequence of pixel values ​​in the scanning order and synchronization marker signals.

[0030] The pixel value sequence and synchronization marker signal enter the FPGA, and are sequentially processed by the data decoding module for channel alignment, row and column addressing, and bad pixel replacement. After outputting the pixel value matrix, it is sent to the dynamic compensation module to track the pixel-by-pixel slow variable baseline μᵢ[t] and subtract dark current. Piecewise linear and logarithmic inversion is performed on near-saturated pixels to linearize the gain. The dynamically compensated pixel values ​​are then sent to the row and column readout noise correction module to estimate and subtract pixel value bias values ​​row by row and column by column, retaining the global mean. The corrected pixel values ​​are then sent to the pixel-level time-domain filtering module, which uses an IIR filter to filter the time series of each pixel to suppress high-frequency noise and 1 / f noise, achieving MTF≥0.2 and DQE≥0.6 at 2lp / mm. The filtered real-time pixel stream is then sent to the inter-frame fusion module, which uses adaptive exponential sliding time fusion and motion gating to improve the signal-to-noise ratio. The enhanced view pixel stream is then sent to the output encapsulation module for statistical saturation count, mean, variance, row and column residuals, simplified NPS, and recording key parameters. Finally, the image frame and metadata are output.

[0031] The high-speed Ethernet interface packages image frames and metadata into Ethernet frame packets and sends them to the host computer.

[0032] The host computer unpacks and displays Ethernet frames, archives and stores them, performs online MTF-NPS-DQE verification and threshold strategy judgment, and generates control signals. It outputs control signals to the FPGA and front-end circuit, including transistor voltage, transistor current, integration time, analog gain, filter parameters and baseline step size β. The host computer's control signals are applied to the FPGA, analog front-end and X-ray source via the control bus, thus forming a closed loop to ensure that the system operates stably near the target point with high DQE and usable MTF.

[0033] For example, the host computer processing flow is as follows: The host computer receives Ethernet frame packets: real-time / enhanced images and metadata from the FPGA, including fields such as frame_id, timestamp_us, payload_type, width / height, bitdepth, profile_id, param_version, param_hash, pipeline_flags, mean, variance, min_val, max_val, median, sat_count, softsat_count, sat_ratio, row_residual, col_residual, gate_rate, alpha_eff, trig_cnt, nps_bins_count, NPS_f[], NPS_v[], and frame_crc32. The output control signals are V_tube / I_tube ray source, T_int integration time, G_ana analog gain, beta_hp, b0,b1,b2,a1,a2 time-domain filter coefficients, beta_dc baseline step size, and alpha_min / alpha_max / kappa fusion parameters. The control message metadata includes cmd_version, apply_at_frame_id, checksum, profile_id, and param_version / param_hash. The runtime side includes events / alarms such as OVER_SAT, UNDER_EXPOSED, ROW_STRIPE, NPS_ANOMALY, historical archive index, and configuration snapshots.

[0034] The host computer follows a four-step process: receiving, checking, judging, and issuing commands. First, it receives and unpacks the data. For each frame, it performs a frame_crc32 checksum. If successful, it parses the Header / Image / Meta / NPS, sends the image to the GUI for real-time frame / enhanced frame switching, and imports the Meta and NPS_f / NPS_v data into the quality panel. Simultaneously, the entire packet is written to the archive. Next, it performs online quality verification: calculating or reading key points of MTF / NPS / DQE, such as MTF and DQE at 2lp / mm, and using a threshold strategy to check for overexposure in sat_ratio, underexposure in mean, stripe residue in row_residual / col_residual, and abnormal high / low frequency energy band noise in NPS. It also confirms consistency with the previous frame / previous group of profile_id / param_version / param_hash. Finally, it proceeds to decision-making and control.

[0035] Exposure control: The brightness target is denoted as mean*, and the error e_m = (mean* - mean) / mean*; the integral time T_int is updated in the logarithmic domain according to the constraint PI to avoid negative values ​​and large dynamic range problems; if sat_ratio exceeds the threshold, a rapid down-adjustment is immediately triggered; the output V_tube / I_tube of the X-ray source is fine-tuned using a slow channel to maintain stable dose.

[0036] Analog gain and filter settings: Combine the high / low frequency energy of NPS and gate_rate to determine noise and motion state, and select / fine adjust G_ana, beta_hp, and second-order IIR coefficients b0, b1, b2, a1, a2; Baseline and fusion parameters: Adjust the beta_dc baseline step size based on temperature drift / slow drift estimation, and adjust alpha_min / alpha_max and kappa fusion threshold sensitivity according to the degree of motion.

[0037] The activation time is uniformly aligned to the frame boundary: apply_at_frame_id = frame_id + 1, to avoid inconsistencies within frames. Finally, these instructions are encapsulated into control messages containing cmd_version, apply_at_frame_id, and checksum, and sent to the FPGA (CTRL_FPGA), the analog front-end (CTRL_AFE), and the X-ray source (CTRL_XSRC) respectively via the control bus.

[0038] In some embodiments, the FPGA module 5 includes a data decoding module 51, a dynamic compensation module 52, a row and column readout noise correction module 53, a pixel-level temporal filtering module 54, an inter-frame fusion module 55, and an output packaging module 56.

[0039] Figure 2 This is a schematic diagram of the FPGA module provided by the present invention, as shown below. Figure 2As shown, FPGA module 5 starts from the multi-channel pixel stream from the ADC, and through data decoding module 51, performs channel alignment and row / column addressing to assemble the original code values ​​into a frame-by-frame matrix. Dynamic compensation module 52 uses LUT_raw2lin to pull the nonlinear code values ​​back to the linear domain, and maintains the slow variable baseline BaseBuf and variance per pixel. After gating and updating, dark current and gain distortion are subtracted to obtain the net signal. Row / column correction module 53 statistically calculates the row mean, column mean, and global mean for the entire frame, and removes row / column stripes in one step using p−R−C+2G while maintaining overall brightness. Pixel-level temporal filtering module 54 performs first-order high-pass suppression of slow drift and second-order high-pass filtering on the time series of each pixel. The IIRDF-II-T low-pass filter suppresses high-frequency random noise, only affecting the time axis without altering spatial sharpness. Through an inter-frame fusion module 55, gated adaptive EMA is used, employing strong fusion with small alpha_min for static scenes and weak fusion with large alpha_max for motion scenes to further improve low-dose SNR. Simultaneously, gate_rate / alpha_eff is statistically analyzed. Finally, the "output encapsulation module" encapsulates the real-time frame FiltBuf / enhanced frame FusBuf along with quality metadata, parameter fingerprints, and optional NPS curves into a unified frame packet. This packet is then sent to a host computer via AXI-Stream through high-speed links such as PCIe / Ethernet for display, archiving, and closed-loop parameter tuning. The overall system operates at a depth pipeline of 1 pixel / frame, with low intra-frame latency and sufficient throughput. While maintaining the required MTF at 2 lp / mm, it significantly suppresses 1 / f and high-frequency noise, reduces row and column fringes and saturation tails, supporting stable system operation at target points with high DQE, usable MTF, and frame-level real-time performance.

[0040] In some embodiments, the data decoding module 51 is used to perform channel alignment, row and column addressing, and bad pixel replacement on the pixel value sequence and the synchronization marker signal to obtain a pixel value matrix.

[0041] For example, the data decoding module 51 receives a pixel-by-pixel value sequence and synchronization flag signals from multiple ADC channels, including frame synchronization (frame_sync), line synchronization (line_sync), and pixel valid (pix_valid). It outputs a pixel value matrix FrameBuf[H][W] of size H×W, and a matrix ready flag (frame_ready). The specific processing flow includes the following steps: Channel Alignment: Each channel input first enters an asynchronous FIFO with a fixed depth of 64 words to eliminate channel phase differences and jitter. The rising edge of the line_sync signal is used as the row alignment boundary. After detecting the first pixel_valid in its row, all channels initiate alignment waiting for a maximum of 32 pixels until the first pixel value of all channels is ready. Information from the channel mapping table is read, and the pixel stream of each channel is concatenated into a row pixel sequence by column segments, ensuring that the output order strictly follows the row and column order to form a one-dimensional row vector.

[0042] Row and column addressing: The row counter y increments on the rising edge of line_sync and is cleared on the rising edge of frame_sync; the column counter x increments on each pixel beat and is cleared on the rising edge of line_sync. Each beat generates a pixel-wise write address addr = y * W + x based on (x, y), and writes the currently stitched pixel value to FrameBuf[addr]. If a channel is not ready within the alignment window, the entire row is marked as incorrect and discarded in parallel; this continues until the next rising edge of line_sync is used for realignment, ensuring the integrity of rows within the frame and matrix consistency.

[0043] Bad Pixel Replacement: The bad pixel matrix `bad_mask` generated during calibration is pre-written into the on-chip BRAM. Each pixel occupies 1 bit, indicating whether the pixel needs to be replaced. If a pixel is bad, the average of its left, right, top, and bottom adjacent pixels is used as the new value. If there are no adjacent pixels, they are ignored, and only the remaining pixels are used for averaging. If all adjacent pixels are unusable, the pixel value at the same position in the previous frame is used as the replacement. The obtained new value is written back to the current frame matrix `FrameBuf`, and the corresponding address is updated in the buffer `PrevFrameBuf` to ensure that a reliable replacement value is immediately obtained when a bad pixel is encountered in the next frame. After the last pixel (x=W-1, y=H-1) is detected as written, a single-shot `frame_ready` pulse is generated; at this time, `FrameBuf` is the complete pixel value matrix, which is available for subsequent modules to read.

[0044] In some embodiments, the dynamic compensation module 52 is used to map the pixel value matrix from the original ADC code value to the linear luminance code value, while maintaining a slow variable baseline for each pixel and dynamically updating it to obtain the dynamically compensated pixel value.

[0045] It is easy to understand that the dynamic compensation module 52 maps the upstream frame data from the original ADC code value to the linear luminance code value, while maintaining and dynamically updating the slow variable baseline for each pixel; the output is a linear pixel matrix with the baseline subtracted, avoiding large dark current and slow drift from consuming the dynamic range; and it statistically calculates the relevant quality indicators for subsequent closed-loop and monitoring.

[0046] The dynamic compensation module 52 receives the frame_ready start signal, the original frame (FrameBuf), the LUT_raw2lin linearization table, the pixel-wise baseline (mu) (BaseBuf), the pixel-wise variance (VarBuf), and the register parameters SAT_SOFT, beta_dc, beta_v, TAU0, and KAPPA. It outputs the linearized pixel matrix (CompBuf) with the baseline subtracted, the comp_ready frame completion pulse, and the softsat_count total number of soft-saturated pixels in the current frame. At the same time, the updated BaseBuf and VarBuf are retained for use in the next frame.

[0047] In some embodiments, after the data decoding module 51 has written the entire frame and raised frame_ready, the dynamic compensation module 52 begins to read FrameBuf[y][x] row by row. The same set of steps is performed for each pixel: first, the original ADC code value r is transformed into a linear value l using the lookup table LUT_raw2lin[r]; if r>=SAT_SOFT, softsat_count is incremented by one. Then, the slow variables left from the previous frame are retrieved: baseline mu=BaseBuf[y][x] and variance v=VarBuf[y][x]. The difference d=l-mu between this frame and the baseline is calculated, and then the threshold tau2=TAU0+KAPPA*v is used to determine whether this change is a "normal fluctuation" (the condition is d*d<=tau2). If it is a normal fluctuation, the baseline and variance are updated: mu'=mu+beta_dc*(l-mu), v'=v+beta_v*(d*dv); then this frame is not updated, keeping mu'=mu and v'=v. Then, the actual compensation is performed: the updated baseline is used for subtraction, c = l - mu'. Negative values ​​are set to 0, and values ​​that are too large are truncated to U16_MAX, resulting in the output pixel c_out. Finally, the state is written back: BaseBuf[y][x] = mu', VarBuf[y][x] = v', and the compensated pixel is written to CompBuf[y][x] = c_out. After the last pixel of a frame is processed, a single-shot comp_ready signal is generated, indicating that the compensation is complete.

[0048] In some embodiments, the row and column readout noise correction module 53 is used to eliminate the row and column fixed bias introduced by the readout link on a frame-by-frame basis for the dynamically compensated pixel value, and restore the global brightness baseline after deducting the row bias and column bias to obtain the corrected pixel value.

[0049] The row and column correction module 53 eliminates fixed offset stripes and banded artifacts introduced by the readout link on a frame-by-frame basis, and restores the global brightness baseline after subtracting the row and column offsets, resulting in a uniform image. Formally, the row mean R[y], column mean C[x], and global mean G are calculated for the compensated pixels, and the output UniBuf[y][x]=clip[0,65535](p(y,x)−R[y]−C[x]+2G), where clip is a saturation cutoff function from 0 to u16. This formula removes the row and column offsets under the ideal model while keeping the global average brightness unchanged.

[0050] For example, the row and column correction module 53 receives the comp_ready start signal, the CompBuf frame to be corrected, u16, and the frame size W / H register, and outputs the UniBuf frame after row and column correction, u16, and the rc_ready frame completion pulse; at the same time, it retains RowMean[], ColMean[], and Gmean for quality inspection / parameter adjustment reading.

[0051] When the dynamic compensation module 52 raises comp_ready, the row and column correction module 53 reads the entire frame CompBuf[y][x] row by row to perform statistics, and then reads it again to perform correction. Specifically, it includes the following steps: Calculate row / column / global averages: Read p=CompBuf[y][x] sequentially from y=0..H-1, x=0..W-1: While accumulating the current row into RowAcc+=p using a register, accumulate the corresponding column into the vector ColSum[x]+=p, and simultaneously accumulate GlobSum+=p globally. When reaching the end of a row x=W-1, write the sum of this row into RowSum[y]=RowAcc and clear RowAcc to zero, then continue to the next row. After scanning the entire frame, calculate the averages: RowMean[y]=RowSum[y] / W, ColMean[x]=ColSum[x] / H, Gmean=GlobSum / (H*W), then clear RowSum[] / ColSum[] / GlobSum to zero, and prepare for the next frame.

[0052] Pixel-by-pixel correction is performed, and p=CompBuf[y][x] is read sequentially again. At the same time, the average values ​​r=RowMean[y], c=ColMean[x], and global average g=Gmean for this row and column are extracted. q=int32(p)-int32(r)-int32(c)+(int32(g)<<1) are calculated. After saturating and cropping q to 0 to 65535, it is written as UniBuf[y][x]=uint16(q). When the last pixel (y=H-1, x=W-1) is written, rc_ready is generated, notifying the downstream that the "uniformed image" is ready.

[0053] In some embodiments, the pixel-level temporal filtering module 54 is used to perform high-pass filtering to remove slow drift and low-pass filtering to suppress high frequencies for each pixel of the corrected pixel value, so as to obtain a filtered real-time pixel stream.

[0054] When the row and column readout noise correction module 53 pulls rc_ready high, the pixel-level temporal filtering module 54 reads UniBuf[y][x] row by row, performs fixed two-stage IIR processing on each pixel independently ("high-pass to remove slow drift + low-pass to suppress high frequency"), and writes the result to FiltBuf[y][x].

[0055] The pixel-level temporal filtering module 54 receives the rc_ready start signal, the UniBuf frame to be filtered, u16, and the filtering parameters beta_hp, b0, b1, b2, a1, a2 registers. It also receives the frame boundary activation, frame size W / H, and pixel-wise state RAMs hp_x1, hp_y1, s1, s2. It outputs the pixel-level temporal filtered frame from the FiltBuf, and u16 and tf_ready are the frame completion pulses. Simultaneously, the updated hp_x1 / hp_y1 / s1 / s2 are retained for recursive use in the next frame. Specifically, it includes the following steps: Read in u=UniBuf[y][x] and convert it to the signed computation format int32.

[0056] The recursive formula y_hp=beta_hp*(hp_y1+u-hp_x1) is used, where beta_hp is a register parameter 0…1, a fixed decimal, and hp_x1 and hp_y1 are the previous state of the pixel: hp_x1←u, hp_y1←y_hp.

[0057] The pixel y_hp is processed through a second-order filter, with coefficients derived from register set b0, b1, b2, a1, a2. Updated using DF-II-T: y0 = b0 * y_hp + s1; s1' = b1 * y_hp - a1 * y0 + s2; s2' = b2 * y_hp - a2 * y0. Then, the pixel state is written back: s1 ← s1', s2 ← s2'.

[0058] Perform a saturation clipping of y0 from 0..65535 to obtain p_out=uint16(saturate(y0)), and write it to FiltBuf[y][x]=p_out. After another stage, when the last pixel (y=H-1, x=W-1) is written, tf_ready is generated to notify the downstream temporal filtering frame that it is ready.

[0059] In some embodiments, the inter-frame fusion module 55 is used to improve the signal-to-noise ratio of the filtered real-time pixel stream through adaptive exponential sliding time fusion and motion gating to obtain an enhanced view pixel stream.

[0060] The inter-frame fusion module 55 performs adaptive exponential sliding fusion along the time axis on the frame FiltBuf[y][x] output by the pixel-level temporal filtering module 54 without changing the spatial sharpness: strong fusion is used during static or low-speed motion to improve low-dose SNR; fusion is automatically weakened when motion or abrupt changes occur to avoid motion blur. The module maintains two states, the time mean m and the variance estimate v, pixel by pixel, and outputs the enhanced view FusBuf[y][x] and fusion statistics for quality assessment and closed-loop use.

[0061] The inter-frame fusion module 55 receives the tf_ready start signal, the FiltBuf temporal filtered frame, u16, the pixel-wise state MeanBuf / VarFus, register parameters alpha_min, alpha_max, beta_var, kappa, sigma_read2, TAU0, and the frame size W / H. It outputs the FusBuf-fused and enhanced frame, u16, the fus_ready frame completion pulse, the statistics gate_rate, alpha_eff, and trig_cnt; simultaneously, the updated MeanBuf / VarFus is retained for recursion in the next frame.

[0062] In some implementations, after the pixel-level temporal filtering module 54 raises tf_ready, the inter-frame fusion module 55 reads FiltBuf[y][x] row by row and performs a unified process for each pixel: dynamic averaging is used in time, with more averaging when stationary and less averaging when moving, and finally the result is written back. Specifically for pixel (y,x): first, the input y_in=FiltBuf[y][x] is taken, and its historical state m=MeanBuf[y][x] and v=VarFus[y][x] are read. The difference between the current frame and the history is calculated as d=int32(y_in)-int32(m), and then tau2=TAU0+kappa*(v+sigma_read2) is used as a threshold to determine gate=(d*d<=tau2): if the difference is small, gate=1, indicating that the scene is stable; if the difference is large, gate=0, indicating that there is motion or abrupt change. Then, select the fusion coefficient alpha = gatealpha_min: alpha_max is used for strong fusion when it is stable; alpha_max is used for weak fusion during motion, updated according to the exponential formula: m' = (1-alpha)*m + alpha*y_in, and the variance is also dynamically updated: v' = (1-beta_var)*v + beta_var*(d*d). Write the new state back to MeanBuf[y][x] = m', VarFus[y][x] = v', and set the output pixel to FusBuf[y][x] = saturate_u16(m'). Simultaneously count the number of gate triggers triggered within the frame, triggered_cnt, to calculate gate_rate = triggered_cnt / (W*H) and alpha_eff = gate_rate*alpha_max + (1-gate_rate)*alpha_min; when the last pixel is processed, generate fus_ready to tell the downstream enhancement frame is ready. If input saturation is detected, directly set alpha = 1 for that pixel to pass through, avoiding the spread of saturation pollution into the historical state.

[0063] In some embodiments, the output encapsulation module 56 is used to statistically analyze the saturation count, mean, variance, and row and column residuals of the enhanced view pixel stream and record key parameters to obtain image frames and metadata.

[0064] The output encapsulation module 56 is used to package the image data and quality metadata of the current frame into a unified frame packet and send it to the host computer through a high-speed interface. It supports packaging real-time frames FiltBuf and enhanced frames FusBuf separately or consecutively; the frame packet includes a header, an image pixel area, a metadata area containing statistics and parameter fingerprints, an optional NPS area, and a CRC tail, with a format consistent with the host computer's parsing.

[0065] The inter-frame fusion module 55 receives the qe_ready start packetization signal; image read ports FiltBuf, FusBufu16, and line priority; statistics / parameter register snapshots such as frame_id, timestamp_us, W / H, bitdepth, profile_id, param_version, param_hash, pipeline_flags, mean, variance, ..., nps_bins_count, NPS_f[], NPS_v[]; control registers payload_enable_mask and payload_order; output AXI4-Stream send ports m_axis_tx_tdata[127:0], tkeep[15:0], tvalid / tready, tuser.start, and tlast; status tx_done (complete pulse for each plane), tx_abort (timeout abort), and tx_drop_count (packet drop count); debug read-only last_frame_crc32 and last_packet_bytes.

[0066] After the inter-frame fusion module 55 outputs qe_ready, the output encapsulation module 56 checks the payload_enable_mask and payload_order in the control register, and decides whether to send real-time frames (FiltBuf) or enhanced frames (FusBuf), and the order thereof, according to the settings. For each matrix to be sent, a whole frame is packaged into a packet according to a fixed procedure: first, the frame header, magic='PXRI', version, frame_id, timestamp_us, width(W), height(H), bitdepth, pix_pitch_um, pipeline_flags, profile_id, param_version, param_hash, and payload_type from the snapshot in the register are used and output; then, the image area is read from FiltBuf or FusBuf line by line, aggregated into a 128-bit width and continuously sent out; after the image is the metadata area, which contains mean, variance, The fields min_val, max_val, median, sat_count, softsat_count, sat_ratio, row_residual, col_residual, gate_rate, alpha_eff, trig_cnt, nps_mode, nps_bins_count, nps_unit_code, and freq_unit_code are written out in order. If nps_bins_count > 0, the NPS_f[] and NPS_v[] curve data are appended. Finally, the CRC of the entire data stream is calculated online, and frame_crc32 is appended as the tail. The entire data is read and sent simultaneously via AXI4-Stream, following the tvalid / tready handshake. The packet begins with a tuser.start and ends with a tlast. After each plane is sent, a tx_done is triggered. If the next plane is also selected by payload_enable_mask, the above process is repeated.

[0067] In some embodiments, the control signal includes tube voltage, tube current, integration time, analog gain, filter parameters and baseline step size, and the control signal acts on FPGA module 5, analog front-end module 3 and X-ray source module 1 through a control bus.

[0068] Figure 3 This is a flowchart illustrating the perovskite X-ray image acquisition method based on time-domain signal processing provided by the present invention, as shown below. Figure 3As shown, the perovskite X-ray image acquisition method based on time-domain signal processing includes steps 310, 320, 330, 340, 350, 360 and 370.

[0069] Step 310: Photons are emitted through X-ray source module 1, pass through the object to be imaged, and are attenuated by the object to be imaged to obtain attenuated photons; Step 320: Send the attenuated photons to detector module 2 for charge collection and integration to obtain the integration node voltage within the pixel; Step 330: Send the integral node voltage within the pixel to the analog front-end module 3 for sampling and holding, reset, and correlation double sampling to obtain multi-channel analog differential voltage; Step 340: Send the multi-channel analog differential voltage to ADC module 4 for synchronous sampling and quantization to obtain the pixel value sequence and the synchronization marker signal; Step 350: Send the pixel value sequence and synchronization marker signal to FPGA module 5 for time-domain signal processing to obtain image frames and metadata; Step 360: Send the image frame and metadata to the high-speed interface module 6 for packaging to obtain an Ethernet frame packet; Step 370: Send the Ethernet frame packet to the host computer module 7 for unpacking and display to obtain the control signal.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A perovskite X-ray image acquisition system based on time-domain signal processing, characterized in that, It includes a radiation source module (1), a detector module (2), an analog front-end module (3), an ADC module (4), an FPGA module (5), a high-speed interface module (6), and a host computer module (7), among which, The X-ray source module (1) is used to emit photons, which pass through the object to be imaged and are attenuated by the object to be imaged to obtain attenuated photons, which are then sent to the detector module (2). The detector module (2) is used to collect and integrate the charge of photons, obtain the integration node voltage within the pixel, and send it to the analog front-end module (3). The analog front-end module (3) is used to sample and hold, reset, and correlate double sampling of the voltage of the integration node in the pixel to obtain multi-channel analog differential voltage and send it to the ADC module (4). The ADC module (4) is used to synchronously sample and quantize the multi-channel analog differential voltage to obtain the pixel value sequence and the synchronization mark signal and send them to the FPGA module (5). The FPGA module (5) is used to perform time-domain signal processing on the pixel value sequence and synchronization marker signal to obtain image frames and metadata and send them to the high-speed interface module (6). The high-speed interface module (6) is used to package image frames and metadata to obtain Ethernet frame packets and send them to the host computer module (7). The host computer module (7) is used to unpack and display Ethernet frame packets to obtain control signals.

2. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 1, characterized in that, The FPGA module (5) includes a data decoding module (51), a dynamic compensation module (52), a row and column readout noise correction module (53), a pixel-level temporal filtering module (54), an inter-frame fusion module (55), and an output packaging module (56).

3. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 2, characterized in that, The data decoding module (51) is used to perform channel alignment, row and column addressing, and bad pixel replacement on the pixel value sequence and synchronization marker signal to obtain the pixel value matrix.

4. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 3, characterized in that, The dynamic compensation module (52) is used to map the pixel value matrix from the original ADC code value to the linear luminance code value, while maintaining a slow variable baseline for each pixel and updating it dynamically to obtain the dynamically compensated pixel value.

5. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 4, characterized in that, The row and column readout noise correction module (53) is used to eliminate the fixed row and column bias introduced by the readout link on a frame-by-frame basis for the dynamically compensated pixel value, and restore the global brightness baseline after deducting the row bias and column bias to obtain the corrected pixel value.

6. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 5, characterized in that, The pixel-level temporal filtering module (54) is used to perform high-pass filtering to remove slow drift and low-pass filtering to suppress high frequencies for each pixel of the corrected pixel value, so as to obtain the filtered real-time pixel stream.

7. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 6, characterized in that, The inter-frame fusion module (55) is used to improve the signal-to-noise ratio of the filtered real-time pixel stream through adaptive exponential sliding time fusion and motion gating, so as to obtain an enhanced view pixel stream.

8. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 7, characterized in that, The output encapsulation module (56) is used to statistically analyze the saturation count, mean, variance, and row and column residuals of the enhanced view pixel stream and record key parameters to obtain image frames and metadata.

9. The perovskite X-ray image acquisition system based on time-domain signal processing as described in claim 8, characterized in that, The control signals include tube voltage, tube current, integration time, analog gain, filter parameters and baseline step size. The control signals are applied to the FPGA module (5), analog front-end module (3) and X-ray source module (1) through the control bus.

10. A perovskite X-ray image acquisition method based on time-domain signal processing, implemented using the perovskite X-ray image acquisition system based on time-domain signal processing as described in any one of claims 1-9, characterized in that, The method includes: Photons are emitted through the X-ray source module (1), pass through the object to be imaged, and are attenuated by the object to be imaged to obtain attenuated photons; The attenuated photons are sent to the detector module (2) for charge collection and integration to obtain the integration node voltage within the pixel; The voltage of the integral node within the pixel is sent to the analog front-end module (3) for sampling and holding, reset, and correlation double sampling to obtain multi-channel analog differential voltage; The multi-channel analog differential voltage is sent to the ADC module (4) for synchronous sampling and quantization to obtain the pixel value sequence and the synchronous marker signal; The pixel value sequence and synchronization marker signal are sent to the FPGA module (5) for time-domain signal processing to obtain image frames and metadata; The image frame and metadata are sent to the high-speed interface module (6) for packaging to obtain an Ethernet frame packet; The Ethernet frame packets are sent to the host computer module (7) for unpacking and display to obtain control signals.

Images