Analog domain asynchronous frequency detection circuit

Abstract

The invention belongs to the field of digital analog hybrid integrated circuits, and particularly relates to an analog domain asynchronous frequency detection circuit. According to the analog domain asynchronous frequency detection circuit, the zero-crossing events of the input signal are detected through the zero-crossing comparator, the time interval of the adjacent zero-crossing events is measured through the time-to-digital converter, and continuous detection of the frequency of the input signal is achieved. According to the scheme, sampling quantization of an analog-to-digital converter and digital signal processing are not needed, the detection time sequence is completely driven by the characteristics of input signals, and the device has the advantages of being simple in structure, high in response speed and high in detection real-time performance. And a detection empty window of a single TDC in a reset stage can be avoided through a double-TDC structure which works alternately, and a continuous and seamless frequency updating process is realized. According to the invention, real-time frequency identification of broadband signals is realized in a low-delay and low-power-consumption mode in an analog domain, and good integration and expansibility are achieved.

Description

Technical Field

[0001] This invention belongs to the field of digital-analog hybrid integrated circuits, specifically relating to an analog-domain asynchronous frequency detection circuit, which is suitable for front-end signal processing scenarios with extremely high requirements for response speed, power consumption and system latency, such as radar, communication and electronic reconnaissance systems. Background Technology

[0002] In modern radar, communication, and electronic reconnaissance systems, front-end signal processing modules often need to quickly and accurately acquire the frequency information of input signals in order to perform filter selection, frequency band identification, or adaptive tuning. The performance of frequency detection directly affects the system's response speed and signal recognition accuracy; therefore, a detection mechanism with high real-time performance and low power consumption over a wide frequency range is required.

[0003] In existing technologies, frequency detection typically relies on spectral analysis methods after digital sampling. A typical implementation involves sampling the input signal using a high-speed analog-to-digital converter (ADC) and then using a Fast Fourier Transform (FFT) or other spectral estimation algorithms to obtain the signal's frequency components. This method can handle continuously varying broadband signals, is suitable for input signals with unstable duty cycles or wide spectral ranges, and is easy to integrate with subsequent digital signal processing modules. However, this method still has certain limitations. High-speed signals require high-sampling-rate ADCs; otherwise, aliasing or frequency distortion may occur. Simultaneously, Fourier transform processing requires accumulating a certain number of sampling points to ensure frequency resolution, resulting in unavoidable delays in frequency detection, making it difficult to meet the real-time detection requirements of high-speed dynamic signals. Furthermore, high sampling rates and large-scale Fourier transform operations significantly increase system power consumption, which is detrimental to low-power applications. In addition, this scheme relies entirely on sampling and computation in the digital domain, lacking the instantaneous response characteristics of the analog domain, and cannot directly output frequency information at the front end. Therefore, it is unsuitable for applications with extremely high requirements for response speed, power consumption, and system latency.

[0004] In summary, while existing frequency detection schemes based on high-speed analog-to-digital converters and digital signal processing modules offer high detection accuracy, they still have significant shortcomings in terms of power consumption, latency, and real-time performance, making it difficult to meet the front-end real-time frequency detection requirements under high-speed, wide-bandwidth, and low-power conditions. Summary of the Invention

[0005] To address the aforementioned problems and shortcomings, and to overcome the deficiencies of existing technologies in terms of power consumption, latency, and real-time performance, this invention provides an analog-domain asynchronous frequency detection circuit. This circuit directly identifies and measures the frequency of the input signal in the analog domain, without requiring sampling, quantization, and digital signal processing via a high-speed analog-to-digital converter. The detection timing is driven by the dynamic characteristics of the input signal itself, using the signal zero-crossing event as the timing trigger source. A time-to-digital converter measures the interval between zero-crossing events in adjacent half-cycles, achieving continuous and seamless frequency detection. The time interval between adjacent zero-crossing events of the input signal is quantized, and the input signal frequency is calculated based on the measured time length, thereby achieving asynchronous frequency detection in the analog domain.

[0006] An analog-domain asynchronous frequency detection circuit includes a zero-crossing comparator and a time-to-digital converter.

[0007] The zero-crossing comparator compares the input signal with the common-mode level in real time, detects the zero-crossing event of the input signal, and outputs the detection result as two complementary square wave signals φ. P and φ N This is used to divide the input signal into positive and negative half-cycles, and to generate reset and latch control signals at the half-cycle boundaries to trigger the start or reset of the time-to-digital converter.

[0008] The time-to-digital converter measures the time difference between adjacent zero-crossing events, quantizes the zero-crossing event signal output by the zero-crossing comparator into a digital time codeword, and outputs the corresponding time interval data at the end of a half-cycle.

[0009] The above-mentioned analog-domain asynchronous frequency detection circuit operates as follows:

[0010] Zero-crossing detection and signal division: The input signal is first compared with the common-mode level by a zero-crossing comparator to generate two complementary square wave signals φ. P and φ N Among them, φ P This indicates that the input signal is in a state higher than the common-mode level, φ N This indicates a state below the common-mode level. A rising-edge zero-crossing event is generated when the input signal crosses the common-mode level in the positive direction; a falling-edge zero-crossing event is generated when the signal crosses the common-mode level in the reverse direction. This zero-crossing event is used to divide the signal into positive and negative half-cycles, and outputs a reset and latch control signal upon the event's occurrence to trigger the start or reset operation of the time-to-digital converter.

[0011] Time interval measurement: TDC uses the zero-crossing event as a reference, and takes two adjacent zero-crossing events as the start signal and the stop signal. The time interval of the half cycle is measured by quantizing the time between the two events.

[0012] Output and Circuit Reset: At the end of each half-cycle, the TDC that has completed the measurement latches the quantization result of the time interval of the current half-cycle; simultaneously, the TDC begins quantizing the time interval of the next half-cycle, achieving seamless switching and continuous detection. By measuring the interval between two adjacent zero-crossing events, the system can obtain the instantaneous frequency of the input signal in real time, realizing a completely asynchronous frequency detection process in the analog domain.

[0013] Furthermore, the time-to-digital converter is a multi-phase clock (TDC) that uses multiple equal-phase-difference clocks generated by a phase-locked loop as a time reference. It accumulates the clock cycle through a counter to achieve ultra-large range measurement and utilizes the closed-loop feedback characteristic of the phase-locked loop to ensure the consistency of the quantization step size, thereby achieving high linearity time-to-digital conversion.

[0014] Furthermore, the time-to-digital converter consists of two channels, TDC1 and TDC2, which operate alternately, corresponding to two adjacent half-cycles respectively, thus avoiding detection gaps during the single TDC reset phase.

[0015] Furthermore, when the input signal remains at the zero-crossing point without any new zero-crossing events, the circuit automatically enters a static standby state with no dynamic power consumption. It is only reactivated when a new zero-crossing event occurs, thus improving the circuit's energy efficiency and adaptive characteristics.

[0016] The beneficial effects of this invention are:

[0017] High real-time performance and low latency: Frequency identification and quantization are completed directly in the analog domain without the need for ADC sampling quantization and digital signal processing. The detection timing is driven by the zero-crossing event of the input signal itself, which fundamentally eliminates the sampling and operation delays of traditional solutions. Furthermore, a dual TDC alternating working architecture can be adopted to avoid detection gaps.

[0018] Low power consumption and high cost performance: No need for high sampling rate ADC and large-scale digital computing modules, simplifying the circuit structure and reducing hardware area and power consumption; the circuit automatically enters a low-power sleep state when there is no valid input signal, further improving energy efficiency.

[0019] Excellent integration and scalability: The circuit structure is simple, requiring no external clock drive or complex logic scheduling, and is easy to integrate with front-end signal processing modules. It can be adapted to various systems with strict requirements for response speed and energy efficiency, such as radar, communication, and electronic reconnaissance, and is suitable for wideband signal detection scenarios.

[0020] In summary, the analog-domain asynchronous frequency detection circuit of this invention detects zero-crossing events of the input signal using a zero-crossing comparator and measures the time interval between adjacent zero-crossing events using a time-to-digital converter (TDC), thus achieving continuous frequency detection of the input signal. This scheme eliminates the need for analog-to-digital converter sampling and quantization, as well as digital signal processing; the detection timing is entirely driven by the characteristics of the input signal itself, offering advantages such as simple structure, fast response speed, and high real-time detection performance. Furthermore, the alternating dual TDC structure avoids the detection gap during the reset phase of a single TDC, achieving a continuous and seamless frequency update process. This invention achieves real-time frequency identification of wideband signals in the analog domain with low latency and low power consumption, exhibiting excellent integration and scalability. Attached Figure Description

[0021] Figure 1 This is a traditional frequency detection scheme.

[0022] Figure 2 This is a block diagram of the overall structure of the present invention.

[0023] Figure 3 This is an overall structural block diagram of an embodiment.

[0024] Figure 4 This is a detailed structural block diagram of an embodiment.

[0025] Figure 5 for Figure 4 Schematic diagram of the embodiment. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0027] Figure 1 In a traditional frequency detection scheme, the input signal is sampled and quantized by a high-speed analog-to-digital converter 101, and then the quantization result is processed by a digital signal processing module 102 to obtain the frequency components of the signal using a fast Fourier transform (FFT) or other spectrum estimation algorithms.

[0028] Figure 2This is a block diagram of the overall structure of the analog-domain asynchronous frequency detection circuit of the present invention. The core functionality involves capturing the zero-crossing events of the input signal using a zero-crossing comparator. This serves as the timing driver, triggering a time-to-digital converter (TD-SCDMA) to quantize the time interval between zero-crossing events in adjacent half-cycles. The real-time frequency of the input signal is then calculated from the quantization result. Compared to traditional solutions, this invention eliminates the need for a high-speed analog-to-digital converter and complex digital signal processing modules. Instead, it directly performs time quantization in the analog domain to detect frequency. The zero-crossing comparator 201 detects the zero-crossing events of the input signal and uses this as the timing driver to trigger the time-to-digital converter 202 to measure the time difference between adjacent zero-crossing events, thus achieving frequency identification without the need for sampling quantization and digital signal processing.

[0029] An example of an analog-domain asynchronous frequency detection circuit employing a multi-phase clock-time digital converter will be described.

[0030] The overall structural block diagram of this embodiment is as follows: Figure 3 As shown, the specific structural block diagram is as follows: Figure 4 As shown, it includes a zero-crossing comparator 401, a 16-phase lock-in loop 402, and a time-to-digital converter 405 (multi-phase clock TDC) composed of 16 3-bit counters 403 and a 16-input adder tree 404. Where φ P and φ N The complementary square wave output represents the detection result of the zero-crossing event of the input signal; Latch represents the latch signal triggered by the zero-crossing event; Reset represents the reset signal triggered by the zero-crossing event; and Time represents φ. P or φ N After multiple delays, the half-cycle time signal CLK<0:15> represents the 16-channel clock signal with uniform phase distribution generated by the phase-locked loop.

[0031] The zero-crossing comparator 401 is used to compare the input signal with the common-mode level in real time, detect the zero-crossing event of the input signal, and output the detection result as two complementary square wave signals φ. P and φ N This is used to divide the input signal into positive and negative half-cycles, and to generate reset and latch control signals at the half-cycle boundaries.

[0032] The 16-phase phase-locked loop 402 internally generates 16 clock signals with uniformly distributed phases. The frequency of these signals is equal to the reference clock frequency, and the phase difference between adjacent phases is 1 / 16 of the reference clock period. These clock signals together form a multi-phase clock network, providing a time reference for frequency detection.

[0033] This phase-locked loop (PLL) consists of a frequency divider (DIV), a phase / frequency detector (PFD), a charge pump (CP), a loop filter (LPF), and a voltage-controlled eight-stage differential loop oscillator, forming a typical delay-locked loop structure. The PLL achieves loop locking through phase detection and voltage-controlled delay lines, thereby obtaining a 16-phase uniformly distributed clock signal CLK<0:15> at a fixed frequency.

[0034] The 3-bit counter 403 is used to count the number of toggles of the 16-phase clock signal in real time during each half-cycle of the input signal. The reset and latch control signals of the counter are provided by the φ output from the zero-crossing comparator. P and φ N Control measures are implemented to ensure that counting occurs independently for each half-cycle.

[0035] This 3-bit counter consists of three D flip-flops. The start and stop of the counter, as well as the switching between low and high levels at the input of the first D flip-flop, are controlled by the half-cycle time signal Time. Within a half-cycle, each time the clock signal CLK... When a rising edge occurs, i.e., when the signal transitions from low to high, the binary output value of the counter increments by one. After the next zero-crossing event of the input signal, counting stops, and a unified latch and reset are performed, thus obtaining the clock signal CLK within half a cycle. The number of flips Ci<0:2> is determined, and preparation is made for the counting of the next half cycle.

[0036] The 16-input adder tree 404 is used to sum the counting results from 16 3-bit counters to obtain the total number of clock toggles within the current half-cycle. The correspondence between this value and the PLL master clock cycle is known, allowing the calculation of the half-cycle length of the input signal and further, the calculation of the signal frequency.

[0037] The time-to-digital converter 405 is used to measure the time interval of the zero-crossing event signal output by the zero-crossing comparator. The time-to-digital converter uses the time difference between adjacent zero-crossing events as the measurement object, obtains the total number of clock flips within the time difference using a counter and an adder tree, converts it into a digital time codeword, thereby obtaining the magnitude of half a cycle of the input signal, and outputs the corresponding time interval data at the end of the half cycle.

[0038] In this embodiment, the time interval measurement circuit includes two alternating time-to-digital converters, TDC1 and TDC2, corresponding to two adjacent half-cycles respectively. When the input signal is within the first half-cycle, TDC1 uses the rising edge zero-crossing event of the current half-cycle as the start signal and the falling edge zero-crossing event as the stop signal to complete the time interval measurement for that half-cycle. Simultaneously, TDC2 is in a reset or standby state, preparing for the measurement of the next half-cycle. When the signal enters the next half-cycle, TDC2 begins measurement, while TDC1 is reset or in standby mode. The two TDCs work alternately, thereby achieving real-time measurement of the half-cycles of a continuous input signal.

[0039] Output and Circuit Reset: At the end of each half-cycle, the TDC that has completed the measurement latches the quantization result of the time interval of the current half-cycle; simultaneously, another TDC automatically starts the measurement at the beginning of the next half-cycle, achieving seamless switching and continuous detection. By measuring the time interval between two adjacent zero-crossing events, the system can obtain the instantaneous frequency of the input signal in real time, realizing a completely asynchronous frequency detection process in the analog domain.

[0040] The principle of this embodiment is as follows: Figure 5 As shown:

[0041] When the analog input Vin remains near the zero-crossing point, the output of the zero-crossing comparator remains stationary, and no new zero-crossing events are generated. Since the timing of this invention is entirely determined by the zero-crossing events of the input signal, when Vin remains at the zero-crossing point, the time-to-digital converter remains latched and does not initiate a new counting process. The entire detection circuit is in a static standby state, with no internal switching or dynamic power consumption. Only when the input signal undergoes a polarity reversal, generating a new zero-crossing event, is the system reactivated and enters the next frequency detection cycle. This working mechanism allows the invention to automatically enter a low-power sleep state when there is no valid input signal, thereby further improving the circuit's energy efficiency and adaptive characteristics.

[0042] When the frequency detection circuit detects the zero-crossing analog input Vin, the signal is compared with the common-mode level by a zero-crossing comparator to detect its zero-crossing switching event, generating two complementary square wave signals φ. P and φ N These control the time-to-digital converters TDC1 and TDC2 respectively. P or φ N The rising edge of the clock first triggers the latch signal, which latches the counting results Q0<0:2> to Q15<0:2> of the 16 3-bit counters in the previous half-cycle, resulting in 16 sets of 3-bit codewords C0<0:2> to C15<0:2>. Then, all codewords are added together through a 16-input adder tree to obtain the total number of toggle cycles of the 16-phase clock within the half-cycle, and this is converted into a digital time codeword T1<0:6> or T2<0:6>. This codeword is added to the result of the previous half-cycle to obtain a digital time codeword T<0:7> representing the size of the complete cycle. After a delay longer than the latching time, the latch signal triggers the reset signal, which resets the D flip-flops in the 16 3-bit counters to prepare for the frequency counting of the next half-cycle. After latching and resetting, the reset signal triggers the half-cycle time signal Time to start the time-domain quantization of this half-cycle.

[0043] After the half-cycle time signal Time is triggered, the counting phase begins. At this time, the 16-phase phase-locked loop outputs 16 clock signals CLK<0:15> with uniformly distributed phases, and the phase difference between adjacent clocks is 1 / 16 of the reference clock period. These 16 multi-phase clocks are input to their corresponding 3-bit counters, and the counter output value is incremented by one each time a clock flip is detected. Within one half-cycle of the input signal, each counter independently counts the number of clock flips for its corresponding phase, ultimately forming 16 sets of 3-bit codewords Q0<0:2> to Q15<0:2>, which reflect the number of clock flips for each phase within that half-cycle. Since the multi-phase clock period output by the phase-locked loop is stable and the phase interval is fixed, the counting result corresponds linearly to the actual time interval. Therefore, the precise time length of the half-cycle can be obtained by accumulating the outputs of the 16 counters. During this phase, the time-to-digital converter TDC1 or TDC2 remains operational until the next zero-crossing event arrives, marking the end of the current half-cycle counting. After counting is completed, the system immediately performs latching and reset processes, enabling the two TDCs to work alternately and realize real-time frequency detection of continuous input signals.

[0044] The final frequency data T<0:7> is the sum of the digital time codewords T1<0:6> and T2<0:6> of the two preceding and following half-cycles, multiplied by the reference clock period T. ref 1 / 16 of this is the period of the input signal, and its reciprocal is the real-time frequency of the input signal, that is:

[0045]

[0046] Where T 10 It is the decimal form of the binary frequency data T<0:7>.

[0047] As can be seen from the above embodiments, this invention does not require external clock driving or complex logic scheduling, relying solely on the zero-crossing events of the input signal for timing control, significantly simplifying the circuit structure and reducing power consumption and area. Compared with traditional frequency detection schemes based on high-speed analog-to-digital converters and digital signal processing modules, this invention directly completes frequency identification and quantization in the analog domain, fundamentally reducing system latency and power consumption. Simultaneously, the architecture employing alternating operation of dual-time digital converters enables parallel execution of the detection and reset processes, avoiding the window period inherent in single-time digital converter structures and improving the continuity and real-time performance of frequency detection. In summary, this invention can achieve high-speed, real-time analog domain frequency detection under low power consumption conditions, making it suitable for front-end signal processing systems with stringent requirements for response speed and energy efficiency.

Claims

1. An analog-domain asynchronous frequency detection circuit, characterized in that: Includes zero-crossing comparators and time-to-digital converters; The zero-crossing comparator compares the input signal with the common-mode level in real time, detects the zero-crossing event of the input signal, and outputs the detection result as two complementary square wave signals φ. P and φ N This is used to divide the input signal into positive and negative half-cycles, and generate reset and latch control signals at the half-cycle boundaries to trigger the start or reset of the time-to-digital converter. The time-to-digital converter measures the time difference between adjacent zero-crossing events, quantizes the zero-crossing event signal output by the zero-crossing comparator into a digital time codeword, and outputs the corresponding time interval data at the end of a half-cycle.

2. The analog domain asynchronous frequency detection circuit as described in claim 1, characterized in that, The specific workflow is as follows: Zero-crossing detection and signal division: The input signal is first compared with the common-mode level by a zero-crossing comparator to generate two complementary square wave signals φ. P and φ N ; where φ P This indicates that the input signal is in a state higher than the common-mode level, φ N This indicates a state below the common-mode level; when the input signal crosses the common-mode level in the positive direction, a rising edge zero-crossing event is generated; when the signal crosses the common-mode level in the reverse direction, a falling edge zero-crossing event is generated; this zero-crossing event is used to divide the positive and negative half-cycles of the signal, and outputs a reset and latch control signal when the event occurs, which is used to trigger the start or reset operation of the time-to-digital converter; Time interval measurement: TDC uses the zero-crossing event as a reference, takes two consecutive zero-crossing events as the start signal and the stop signal, and measures the time interval of the half cycle by quantizing the time between the two. Output and circuit reset: At the end of each half-cycle, the time-to-digital converter (TDC) that has completed the measurement latches the quantization result of the time interval of the current half-cycle; at the same time, the TDC starts quantizing the time interval of the next half-cycle, realizing seamless switching and continuous detection; by measuring the time interval between two adjacent zero-crossing events, the instantaneous frequency of the input signal is obtained in real time, realizing a completely asynchronous frequency detection process in the analog domain.

3. The analog domain asynchronous frequency detection circuit as described in claim 1, characterized in that: The time-to-digital converter consists of two channels, TDC1 and TDC2, which operate alternately, each corresponding to an adjacent half-cycle.

4. The analog domain asynchronous frequency detection circuit as described in claim 3, characterized in that, The specific workflow is as follows: Zero-crossing detection and signal division: The input signal is first compared with the common-mode level by a zero-crossing comparator to generate two complementary square wave signals φ. P and φ N ; where φ P This indicates that the input signal is in a state higher than the common-mode level, φ N This indicates a state below the common-mode level; when the input signal crosses the common-mode level in the positive direction, a rising edge zero-crossing event is generated; when the signal crosses the common-mode level in the reverse direction, a falling edge zero-crossing event is generated; this zero-crossing event is used to divide the positive and negative half-cycles of the signal, and outputs a reset and latch control signal when the event occurs, which is used to trigger the start or reset operation of the time-to-digital converter; Time interval measurement: The circuit includes two alternating time-to-digital converters, TDC1 and TDC2, corresponding to two adjacent half-cycles respectively. When the input signal is in the first half-cycle, TDC1 uses the rising edge zero-crossing event of the current half-cycle as the start signal and the falling edge zero-crossing event as the stop signal to complete the time interval measurement of that half-cycle. At the same time, TDC2 is in a reset or standby state to prepare for the measurement of the next half-cycle. When the signal enters the next half-cycle, TDC2 starts measuring, while TDC1 is reset or in standby. The two TDCs work alternately, thereby realizing real-time measurement of the input signal for consecutive half-cycles. Output and circuit reset: At the end of each half-cycle, the time-to-digital converter (TDC) that has completed the measurement latches the quantization result of the time interval of the current half-cycle; at the same time, another TDC automatically starts the measurement at the beginning of the next half-cycle, realizing seamless switching and continuous detection; by measuring the time interval between two adjacent zero-crossing events, the instantaneous frequency of the input signal is obtained in real time, realizing a completely asynchronous frequency detection process in the analog domain.

5. The analog domain asynchronous frequency detection circuit as described in claim 1, characterized in that: The time-to-digital converter is a multi-phase clock (TDC) that uses multiple equal-phase-difference clocks generated by a phase-locked loop as a time reference. It accumulates the clock cycle through a counter to achieve ultra-large range measurement and utilizes the closed-loop feedback characteristic of the phase-locked loop to ensure the consistency of the quantization step size.

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