Electronic board card test sequence generation method and system

Abstract

The invention discloses an electronic board card test sequence generation method and system, and belongs to the technical field of electronic product automatic testing (ATE). According to the method, features of nodes are extracted through multi-modal engineering data access and map initialization, semantic inference and conflict arbitration based on weighted feature fusion, a connection relation of a map is updated through weighted inference and conflict detection, and dynamic limit value calculation based on physical routing parameters is carried out in sequence. And based on test sequence sorting optimization of a minimum spanning tree (MST) and platform adaptation code generation and verification, a Switch file and an Action file which are separated from each other are generated. According to the method, the problem that the long wiring is misjudged as an open circuit in a high-precision test is solved, and the false test rate is reduced to 0.1% or below; meanwhile, the identification problem of non-standard named pins is solved, and more than 95% of test point attributes can be identified without manual intervention; and the service life of the expensive ATE switch matrix is obviously prolonged.

Description

Technical Field

[0001] This invention belongs to the field of automated testing (ATE) technology for electronic products, and particularly relates to a method and system for generating test sequences for electronic circuit boards. Background Technology

[0002] In the PCBA (Printed Circuit Board Assembly) manufacturing process, continuity testing is a core step in verifying physical manufacturing quality. With the increasing integration of automotive electronics (such as ADAS controllers) and communication equipment, the number of test nodes on a single board often exceeds 2000, resulting in extremely complex network relationships. Existing technologies suffer from the following significant drawbacks: 1. False Failure of Static Limits: Traditional methods typically set uniform static limits (e.g., 10Ω) for all connectivity tests. However, in actual high-density circuit boards, the physical resistance of long traces can reach hundreds of milliohms. When combined with the line resistance of the test fixture, this can easily exceed the stringent static limits, leading to false failures of good products.

[0003] 2. Data source fragmentation and conflicts: Engineering data is scattered across schematics (PDF), BOMs (Excel), and PCB layouts (Gerber / ODB++). Situations frequently arise where "the schematic shows connections, but the BOM shows no components (DNI / NC)," making manual verification highly prone to errors.

[0004] 3. Lack of switch life optimization: Existing automated generation tools typically generate test sequences randomly or in alphabetical order. In large matrix switch systems, frequent and disordered relay operations significantly shorten instrument life and increase test time.

[0005] 4. Shallow semantic understanding: Existing technologies mostly rely on simple string matching (Regex). They cannot handle non-standard naming (such as naming "GND" as "RTN" or "VSS"), nor can they infer the electrical properties of unnamed test points (TestPad) based on the physical layout. Summary of the Invention

[0006] To address the above problems, this invention discloses a method and system for generating test sequences for electronic circuit boards.

[0007] The present invention adopts the following technical solution: A method for generating test sequences for electronic circuit boards, the method being based on EDA graph reconstruction and multimodal semantic fusion, the method comprising the following steps: S1: Multimodal engineering data access and graph initialization, constructing a heterogeneous data access layer, parsing the data source and establishing an initial graph of the device under test; in the graph, nodes represent pins and edges represent electrical connections; S2: Based on weighted feature fusion semantic inference and conflict arbitration, feature extraction is performed on the nodes, and the connection relationship of the graph is updated by weighted inference and conflict arbitration to obtain the updated graph; S3: Calculate dynamic limits based on physical trace parameters. Based on the connection relationship of the updated graph, calculate dynamic limits for test groups determined to be connected; for open-circuit test groups, set static general limits; bind the dynamic limits and static general limits to the graph to obtain a secondary updated graph; determine whether the theoretical value of network impedance is lower than a preset threshold (e.g., 1Ω); if so, trigger the four-wire (Kelvin) test generation strategy, and search for the nearest node at both ends of the device under test as the sensing end (Sense) and the farther node as the forcing end (Force) based on the graph topology. S4: Based on the minimum spanning tree (MST) or specific network priority (such as the DaisyChain strategy used in the common ground GND network), optimize the test sequence sorting, and construct a weighted complete graph based on the secondary update graph, with the weight being the "switch state switching cost"; S5: Platform adaptation code generation and verification, loading the target platform's syntax template, and generating separate Switching and Action files. Performing design rule checks, especially isolation testing steps between high-voltage and sensitive networks.

[0008] Furthermore, the data source mentioned in step S1 includes: document-type data, logical-type data, or physical-type data.

[0009] Further, the analysis in step S1 includes: using OCR and NLP to extract pin definition tables from PDF datasheets and Excel files; parsing netlist files to extract electrical connection logic relationships; and parsing intelligent EDA data to extract PCB stack-up information, trace width, trace length, and number of vias.

[0010] Further, the feature extraction in step S2 includes: extracting a three-dimensional feature vector for each node: ,in For name text features, This refers to the physical adjacency topology feature. These are characteristics of the associated devices.

[0011] Furthermore, the weighted inference in step S2 includes: inferring pin attributes using a weighted scoring mechanism.

[0012] Furthermore, the conflict arbitration in step S2 includes: when the schematic diagram conflicts with the BOM, based on the preset "manufacturability data priority" principle, automatically cutting off the path in the schematic diagram to avoid generating incorrect short-circuit tests.

[0013] Furthermore, step S3, calculating the dynamic limit, includes: calculating the dynamic limit using physical modeling. , In the formula To test the resistance of the fixture and interface path, in the formula To test the relay on-resistance of the system switch matrix, the formula is: The trace resistance is given by the formula. This is the preset engineering safety tolerance.

[0014] Furthermore, the trace resistance The calculations include: In the formula, The resistivity of copper, The first The length, width, and copper foil thickness of the trace segment.

[0015] Furthermore, step S3 also includes incremental updates based on graph differences: reading in the old version of the project file and the new version of the EDA data, calculating the graph difference set; generating test steps for newly added networks in the difference set and inserting the optimal group; annotating or marking deleted networks; automatically annotating or marking deleted networks as deactivated, and retaining the debugging parameters of the unchanged parts; Step S4, which involves constructing a weighted complete graph, includes applying a minimum spanning tree or a traveling salesman problem approximation algorithm and planning the test execution order.

[0016] An electronic board test sequence generation system employing the above method, the system comprising: EDA parsing engine: used to extract physical routing parameters (L / W / T) and topology from ODB++ / IPC-2581; Semantic arbitration module: used to handle multi-source data conflicts and infer pin electrical properties; Dynamic Limit Calculator: Used to calculate the individual resistance limit for each network based on physical parameters; Sequence optimizer: Used to optimize the execution order of test steps based on graph algorithms; Code generator: Used to output project files adapted to specific ATE software.

[0017] The beneficial effects of this invention are: 1. Eliminate false failures: By introducing dynamic limit calculation based on physical trace parameters and dynamically setting limits, the problem of long traces being misjudged as open circuits in high-precision testing is solved, reducing the false failure rate to below 0.1%.

[0018] 2. Deep semantic understanding: Combining semantic inference with physical topology features, it solves the problem of identifying non-standard named pins and can identify more than 95% of test point attributes without manual intervention.

[0019] 3. Extended equipment lifespan: Graph theory-based sequence optimization reduces relay switching actions by approximately 30%-40% compared to traditional random sequences, significantly extending the lifespan of expensive ATE switch matrices.

[0020] 4. Rapid iteration: For complex boards with 2000 nodes, the generation time has been reduced from approximately 50 hours (including debugging) manually to 15 minutes for the entire process (including data import and generation), improving efficiency by more than 99%. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the overall system architecture of the present invention; Figure 2 This is a schematic diagram of the method flow of the present invention; Figure 3 This is a schematic diagram illustrating the dynamic limit calculation principle of the present invention; Figure 4 This is a schematic diagram comparing the test sequence sorting before and after optimization according to the present invention. Detailed Implementation

[0023] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] Example 1 A method for generating test sequences for electronic circuit boards, the method being based on EDA graph reconstruction and multimodal semantic fusion, the method comprising the following steps: S1: Multimodal engineering data access and graph initialization, constructing a heterogeneous data access layer, parsing the data source and establishing an initial graph of the device under test; in the graph, nodes represent pins and edges represent electrical connections; S2: Based on weighted feature fusion semantic inference and conflict arbitration, feature extraction is performed on the nodes, and the connection relationship of the graph is updated by weighted inference and conflict arbitration to obtain the updated graph; S3: Calculate dynamic limits based on physical trace parameters. Based on the connection relationships of the updated graph, calculate dynamic limits for test groups determined to be connected (Short); for open-circuit test groups, set static general limits; bind the dynamic limits and static general limits to the graph to obtain a secondary updated graph; determine whether the theoretical network impedance is lower than a preset threshold (e.g., 1Ω); if so, trigger the four-wire (Kelvin) test generation strategy, and search for the nearest node at both ends of the device under test as the sensing end (Sense) and the farther node as the forcing end (Force) based on the graph topology; if... Figure 3 As shown, Figure 3 The schematic diagram illustrating the principle of dynamic limit calculation shows how to calculate using physical dimensions from EDA data. And the model is superimposed on the final test limit; S4: Based on the minimum spanning tree (MST) or specific network priority (such as the DaisyChain strategy used in the common ground GND network), optimize the test sequence sorting, and construct a weighted complete graph based on the secondary update graph, with the weight being the "switch state switching cost"; S5: Platform adaptation code generation and verification, loading the target platform's syntax template, and generating separate Switching and Action files. Performing design rule checks, especially isolation testing steps between high-voltage and sensitive networks.

[0026] like Figure 2 As shown, Figure 2 This is a flowchart illustrating the method. Figure 2 The logical judgment process of steps S1 to S5 is described, especially the closed-loop logic of conflict arbitration and dynamic limit calculation.

[0027] Furthermore, the data source mentioned in step S1 includes: document-type data, logical-type data, or physical-type data.

[0028] Further, the analysis in step S1 includes: using OCR and NLP to extract pin definition tables from PDF datasheets and Excel files; parsing netlist files to extract electrical connection logic relationships; and parsing intelligent EDA data to extract PCB stack-up information, trace width, trace length, and number of vias.

[0029] Further, the feature extraction in step S2 includes: extracting a three-dimensional feature vector for each node: ,in For name text features, This refers to the physical adjacency topology feature. These are characteristics of the associated devices.

[0030] Furthermore, the weighted inference in step S2 includes: inferring pin attributes using a weighted scoring mechanism.

[0031] Furthermore, the conflict arbitration in step S2 includes: when the schematic diagram conflicts with the BOM, based on the preset "manufacturability data priority" principle, automatically cutting off the path in the schematic diagram to avoid generating incorrect short-circuit tests.

[0032] Furthermore, step S3, calculating the dynamic limit, includes: calculating the dynamic limit using physical modeling. , In the formula To test the resistance of the fixture and interface path, in the formula To test the relay on-resistance of the system switch matrix, the formula is: The trace resistance is given by the formula. This is the preset engineering safety tolerance.

[0033] Furthermore, the trace resistance The calculations include: In the formula, The resistivity of copper, The first The length, width, and copper foil thickness of the trace segment.

[0034] Furthermore, step S3 also includes incremental updates based on graph differences: reading in the old version of the project file and the new version of the EDA data, calculating the graph difference set; generating test steps for newly added networks in the difference set and inserting the optimal group; annotating or marking deleted networks; automatically annotating or marking deleted networks as deactivated, and retaining the debugging parameters of the unchanged parts; Step S4, which involves constructing a weighted complete graph, includes applying a minimum spanning tree or a traveling salesman problem approximation algorithm and planning the test execution order.

[0035] Figure 4 is a schematic diagram comparing the test sequence sorting before and after optimization according to the present invention. Figure 4 The differences in the number of switching actions between "random order" and "topology-optimized order" were compared.

[0036] An electronic board test sequence generation system employing the above method, such as Figure 1 As shown, Figure 1 This demonstrates the data flow from multi-source input (PDF / Excel / ODB++) to the final test code (TestExec SL Files). The core of the system includes an EDA parsing engine, a semantic fusion layer, and a policy generation layer. The system comprises: EDA parsing engine: used to extract physical routing parameters (L / W / T) and topology from ODB++ / IPC-2581; Semantic arbitration module: used to handle multi-source data conflicts and infer pin electrical properties; Dynamic Limit Calculator: Used to calculate the individual resistance limit for each network based on physical parameters; Sequence optimizer: Used to optimize the execution order of test steps based on graph algorithms; Code generator: Used to output project files adapted to specific ATE software.

[0037] Example 2 Test generation of a certain vehicle gateway controller (2500 nodes) Scenario: This board contains a complex CAN FD bus, Ethernet, and high-current power supply network. Data sources include schematic PDF, BOM Excel, and ODB++ files.

[0038] Step 1: Physical Data Analysis The system reads the ODB++ file and identifies that the network GND_ISO spans the entire board on the PCB. The trace length between the farthest test point TP_GND_1 and the connector J1_GND is 250mm, the trace width is 0.2mm (in some areas), and the copper thickness is 35um.

[0039] Step 2: Dynamic Limit Calculation The system calculates the theoretical resistance of this section of the trace according to the formula: If a traditional uniform limit (such as 0.5Ω) is used, this point will inevitably lead to test failure. This system automatically generates the limit: The generated TestExec code automatically applies this specific limit: 1.7.

[0040] Step 3: Conflict Arbitration The schematic shows that Net_A and Net_B are connected via R101 (0Ω). The BOM shows R101 as "DNI" (Do Not Install). Based on the "BOM priority" rule, the system determines that Net_A and Net_B are physically disconnected and automatically divides them into two independent networks for isolation testing, rather than short-circuit testing.

[0041] Step 4: Sequence Optimization For a GND network with 50 pins, the system identifies its physical topology as "star", but in terms of test resources, it rearranges it into a subsequence based on switch matrix Bank grouping to reduce switching actions across Banks.

[0042] Step 5: Output Results The generated TestExec SL code snippet: Verification results: The generated code can be run directly on the machine, and the first pass yield has increased from 85% in traditional manual development to 98%, without the need for manual adjustment of limits.

[0043] Example 3 Automatic generation of four-wire (Kelvin) test results for high-current power boards. Application Scenario: In the testing of battery management systems (BMS) or power distribution units (PDUs) for new energy vehicles, there are numerous low-impedance current sampling resistors (Shunt Resistor, resistance typically <10mΩ) or high-current buses. Traditional two-wire testing is completely unsuitable for measuring such networks due to the influence of relay contact resistance (approximately 0.5Ω). This embodiment demonstrates how the system utilizes EDA topology to automatically identify and generate a four-wire test sequence.

[0044] Step 1: Sensitive Network Identification and Policy Triggering Semantic trigger: The system scans the BOM and identifies the device with bit number R_SENSE1, which has a resistance of 0.005Ω.

[0045] Rule matching: The system's built-in rule base is set as follows: "When the target resistance value..." "At that time, the four-wire (Kelvin) measurement mode will be forcibly enabled."

[0046] Step 2: Four-line topology search based on graph theory The system locates the two end networks Net_Input and Net_Output of R_SENSE1 in the EDA graph.

[0047] Node search: The system traverses all available test points (TestPoints) on Net_Input and Net_Output.

[0048] For Net_Input, the system uses a physical distance algorithm to find the point closest to the resistor pad as Sense_Hi and the point farther away as Force_Hi.

[0049] For Net_Output, the same logic applies to selecting Sense_Lo and Force_Lo.

[0050] Reachability verification: If a network has only one test point, the system will automatically report an error and downgrade to a two-wire test with "offset compensation", and mark a warning in the generated log.

[0051] Step 3: Generate complex switching actions using TestExec SL Unlike ordinary connectivity tests, the system generates a complex sequence of four-way switch actions.

[0052] Switching file generation: Switching Path: Action code generation: Call the dmmMeasureOhms4Wire function of TestExec SL instead of the regular dmmMeasureOhms.

[0053] Implementation results: It achieves automated testing and generation of milliohm-level resistances, with measurement accuracy reaching [value missing]. .

[0054] This eliminates the tedious process of manually finding and matching four test points, reducing the development time for a single Kelvin test item from 15 minutes to 5 seconds.

[0055] Example 4 Incremental generation of map differentiation for responding to Engineering Changes (ECOs) Application Scenario: During product development, hardware versions iterate frequently (e.g., from Rev A to Rev B). Rev B only modifies a portion of the circuitry (e.g., removing a USB interface and adding a set of CAN terminating resistors), while the remaining 90% of the circuitry remains unchanged. If a full rebuild is performed, comments and debugging parameters manually added by engineers in the old version of the code will be lost.

[0056] Step 1: Construction and Comparison of Dual-Version Atlases The system simultaneously loads Rev A's saved state file (JSON Graph) and Rev B's new EDA data (ODB++).

[0057] Graph Diff algorithm: The system compares the nodes and edges of two graphs.

[0058] New episodes ( ): Networks that exist in Rev B but not in Rev A (such as Net_CAN3_H).

[0059] Deleted set ( ): A network that exists in Rev A but not in Rev B.

[0060] Change set ( Networks with the same network name but whose physical properties have changed drastically (e.g., the trace length has changed by more than 20%), requiring dynamic limits to be updated.

[0061] Step 2: Intelligent Incremental Repair Retention logic: For those not in and The system retains the original test code for the test items (including delay Wait() or comments manually modified by engineers).

[0062] Insertion logic: for The network generates new test blocks and inserts them into the optimal Switching Bank group based on their physical location, rather than simply appending them to the end of the file.

[0063] Cleanup logic: Automatically comment out (Comment Out) The code was edited and marked with / / REMOVED INREV B, instead of being directly deleted, so that it could be traced back.

[0064] Step 3: Output Change Report The system generates an "ECO Impact Analysis Report," which lists: "The capacitance of C102 has changed from 10uF to 22uF. The charge and discharge test parameters have been updated." “J4 connector removal detected; 12 related connectivity tests have been disabled.” Implementation results: Data security: Ensures that human assets (experience values ​​from manual debugging) are not lost due to automated regeneration.

[0065] Maintenance efficiency: Version changeover time has been reduced from the original redevelopment (about 2 days) to only needing to check the changes (about 10 minutes).

[0066] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for generating test sequences for electronic circuit boards, characterized in that, The method is based on EDA graph reconstruction and multimodal semantic fusion, and includes the following steps: S1. Multimodal engineering data access and graph initialization: Construct a heterogeneous data access layer, parse the data source, and establish an initial graph of the device under test; in the graph, nodes represent pins, and edges represent electrical connections; S2. Based on weighted feature fusion, semantic inference and conflict arbitration are used to extract features from the nodes, and the connection relationships of the graph are updated by weighted inference and conflict arbitration to obtain the updated graph. S3. Calculate dynamic limits based on physical routing parameters. Based on the connection relationship of the updated map, calculate dynamic limits for test groups that are determined to be connected; for open-circuit test groups, set static general limits; bind the dynamic limits and static general limits to the map to obtain a secondary updated map. S4. Optimize the test sequence sorting based on the minimum spanning tree or a specific network priority, and construct a weighted complete graph based on the secondary update graph, with the weight being the "switch cost". S5. Platform adaptation code generation and verification: Based on the weighted complete graph, load the target platform's syntax template and generate separate Switching and Action files.

2. The method according to claim 1, characterized in that, The data source mentioned in step S1 includes: document-type data, logical-type data, or physical-type data.

3. The method according to claim 2, characterized in that, The analysis in step S1 includes: using OCR and NLP to extract pin definition tables from PDF datasheets and Excel files; parsing netlist files to extract electrical connection logic relationships; and parsing intelligent EDA data to extract PCB stack-up information, trace width, trace length, and number of vias.

4. The method according to claim 1, characterized in that, The feature extraction in step S2 includes: extracting a three-dimensional feature vector for each node: ,in For name text features, This refers to the physical adjacency topology feature. These are characteristics of the associated devices.

5. The method according to claim 4, characterized in that, The weighted inference in step S2 includes: inferring pin attributes using a weighted scoring mechanism.

6. The method according to claim 5, characterized in that, The conflict arbitration in step S2 includes: when the schematic diagram conflicts with the BOM, the path is automatically cut off in the schematic diagram based on the preset "manufacturability data priority" principle.

7. The method according to claim 1, characterized in that, Step S3, calculating the dynamic limit, includes: calculating the dynamic limit using physical modeling. , In the formula To test the resistance of the fixture and interface path, in the formula To test the relay on-resistance of the system switch matrix, the formula is: The trace resistance is given by the formula. This is the preset engineering safety tolerance.

8. The method according to claim 7, characterized in that, The wiring resistor The calculations include: In the formula, The resistivity of copper, The order is number 1 The length, width, and copper foil thickness of the trace segment.

9. The method according to claim 1, characterized in that, Step S4, which involves constructing a weighted complete graph, includes applying a minimum spanning tree or a traveling salesman problem approximation algorithm and planning the test execution order.

10. An electronic board test sequence generation system employing the method described in any one of claims 1-9, characterized in that, The system includes: EDA parsing engine: used to extract physical routing parameters and topology relationships; Semantic arbitration module: used to handle multi-source data conflicts and infer pin electrical properties; Dynamic Limit Calculator: Used to calculate personalized resistance limits for a network based on physical parameters; Sequence optimizer: Used to optimize the execution order of test steps based on graph algorithms; Code generator: Used to output project files adapted to specific ATE software.

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