Display panel and display device

Abstract

The invention discloses a display panel and a display device. A cofferdam is arranged between an array substrate and an opposite substrate, and the cofferdam is provided with a plurality of openings; the array substrate and the opposite substrate extrude the cofferdam, the cofferdam has elastic restoring force, and the opening, the array substrate and the opposite substrate form a sealing cavity. Electrophoretic particles are arranged in the sealing cavity. According to the display panel and the display device, the elastic cofferdam is arranged between the array substrate and the opposite substrate, the elastic cofferdam is extruded through the action of the array substrate and the opposite substrate in the box forming process, and the elastic restoring force is achieved based on the fact that the cofferdam is compressed; the cofferdam is further in sealed contact with the array substrate and the opposite substrate, a gap between the array substrate or the opposite substrate and the cofferdam in the prior art is eliminated, the risk that electrophoretic particles flow through the gap is avoided, and pressing uniformity and display uniformity are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In existing electrophoretic electronic paper, the dam is generally made of a highly rigid material. Because of this rigidity, the dam is prone to breakage under pressure, allowing electronic ink to flow through the gap between the dam and the opposing substrate, resulting in uneven pressure distribution. Secondly, process instability can lead to inconsistent dam heights, and the high rigidity of the dam can also result in gaps between the lower dam and the opposing substrate. During pressing, electronic ink can flow through these gaps, again causing uneven pressure distribution. Summary of the Invention

[0003] This application provides a display panel and a display device to at least partially solve the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising: Array substrate; The opposing substrate is disposed opposite to the array substrate; A dike is disposed between the array substrate and the opposing substrate, and the dike has multiple openings; the array substrate and the opposing substrate compress the dike, the dike has an elastic restoring force, and the openings, the array substrate and the opposing substrate form a sealed cavity; Electrophoretic particles are disposed within the sealed cavity.

[0005] Optionally, in some embodiments of this application, the elastic recovery rate of the cofferdam is between 75% and 80%.

[0006] Optionally, in some embodiments of this application, the compression rate of the cofferdam is between 45% and 50%.

[0007] Optionally, in some embodiments of this application, the elastic modulus of the cofferdam is between 2 GPa and 3 GPa.

[0008] Optionally, in some embodiments of this application, the cofferdam comprises a black material.

[0009] Optionally, in some embodiments of this application, the array substrate includes a plurality of pixel electrodes, with a gap between two adjacent pixel electrodes, the dam being disposed at the gap, and the electrophoretic particles being located within the region of the pixel electrode.

[0010] Optionally, in some embodiments of this application, the array substrate includes a first substrate and a metal electrode, the metal electrode being located on the side of the pixel electrode closer to the first substrate, and the metal electrode and the pixel electrode being disposed in different layers; In the display panel viewed from above, the dam is located outside the metal electrode.

[0011] Optionally, in some embodiments of this application, the array substrate includes a thin-film transistor and a planarization layer, the thin-film transistor is disposed on the first substrate, the planarization layer covers the thin-film transistor, the metal electrode is disposed on the side of the planarization layer away from the first substrate, and the planarization layer includes a black material.

[0012] Optionally, in some embodiments of this application, the array substrate further includes a light-absorbing layer, which is disposed on the side of the first substrate close to the metal electrode or on the side of the first substrate away from the first substrate.

[0013] Optionally, in some embodiments of this application, the array substrate includes a first substrate and a metal electrode, the metal electrode being located on the side of the pixel electrode close to the first substrate, the metal electrode and the pixel electrode being disposed in different layers, and the dam at least partially overlapping the metal electrode in the thickness direction of the display panel; The display panel includes a black matrix layer, which overlaps with the dike in the thickness direction of the display panel. The black matrix layer is formed on the opposing substrate or the array substrate.

[0014] Optionally, in some embodiments of this application, the array substrate includes a first substrate and a metal electrode, the metal electrode being located on the side of the pixel electrode close to the first substrate, the metal electrode and the pixel electrode being disposed in different layers, and the dam at least partially overlapping the metal electrode in the thickness direction of the display panel; The metal electrode is made of ferrous metal.

[0015] Optionally, in some embodiments of this application, the dam is formed on the opposing substrate, a groove is formed on the side of the array substrate facing the opposing substrate, and the side of the dam away from the opposing substrate is disposed in the groove.

[0016] Optionally, in some embodiments of this application, the array substrate includes a first substrate, a thin-film transistor, a planarization layer, and a pixel electrode. The thin-film transistor is disposed on the first substrate, the planarization layer covers the thin-film transistor, and the pixel electrode is disposed on the side of the planarization layer away from the metal electrode. The groove is formed on the planar layer and is spaced apart from the pixel electrode.

[0017] Optionally, in some embodiments of this application, the dam is formed on the array substrate, a groove is formed on the side of the opposing substrate facing the array substrate, and the side of the dam away from the array substrate is disposed in the groove.

[0018] Optionally, in some embodiments of this application, the opposing substrate includes a second substrate, a cover layer, and a common electrode layer. The cover layer is disposed on the side of the second substrate close to the array substrate, and the cover layer has a cutout in the area corresponding to the dam. The common electrode layer is disposed on the side of the cover layer away from the second substrate, and the common electrode layer covers the cutout to form the groove. The cofferdam abuts against the common electrode layer located within the groove.

[0019] According to a second aspect of this application, a display device is provided, which includes a display panel as described in any of the above embodiments.

[0020] In the display panel and display device of this application embodiment, a dam is disposed between the array substrate and the opposing substrate, and the dam has multiple openings; the array substrate and the opposing substrate compress the dam, the dam has elastic restoring force, and the openings, the array substrate, and the opposing substrate form a sealed cavity. Electrophoretic particles are disposed within the sealed cavity.

[0021] It is understood that the display panel and display device of this application embodiment adopt an elastic dam set between the array substrate and the opposing substrate, and the elastic dam is squeezed by the action of the array substrate and the opposing substrate during the cell assembly process. Based on the elastic recovery force of the dam being compressed, the dam is in sealed contact with the array substrate and the opposing substrate respectively, eliminating the gap between the array substrate or the opposing substrate and the dam in the prior art, avoiding the risk of electrophoretic particles flowing through the gap, and improving the uniformity of pressing and display.

[0022] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0025] Figure 1 This is a schematic diagram of a first structure of a display panel provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of a second structure of the display panel provided in an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram of a third structure of the display panel provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of a fourth structure of the display panel provided in an exemplary embodiment of this disclosure; Figure 5 This is a fifth structural schematic diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 6 This is a sixth structural schematic diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 7 This is a seventh structural schematic diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of this disclosure.

[0026] Explanation of reference numerals in the attached figures: Display panel 100; array substrate 10; opposing substrate 20; dike 30; electrophoretic particles 40; opening k1; sealing cavity m1; first substrate 101; thin film transistor 102; planarization layer 103; pixel electrode 104; metal electrode 105; passivation layer 106; light-absorbing layer 107; second substrate 201; common electrode layer 202; black matrix layer 203; cover layer 204; gap jx1; groove a1; cutout c1; display device 1000. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0028] This application provides a display panel 100; please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of a first structure of the display panel 100 provided in an embodiment of this application.

[0029] Optionally, in some embodiments of this application, the display panel 100 includes an array substrate 10, an opposing substrate 20, a dike 30, and electrophoretic particles 40.

[0030] The opposing substrate 20 is disposed opposite to the array substrate 10. A dike 30 is disposed between the array substrate 10 and the opposing substrate 20. The dike 30 has multiple openings k1. The array substrate 10 and the opposing substrate 20 compress the dike 30, and the dike 30 has an elastic restoring force. The openings k1, the array substrate 10, and the opposing substrate 20 form a sealed cavity m1. Electrophoretic particles 40 are disposed within the sealed cavity m1.

[0031] It is understood that the display panel 100 of this application embodiment uses an elastic dam 30 disposed between the array substrate 10 and the opposing substrate 20. During the cell assembly process, the elastic dam 30 is squeezed by the action of the array substrate 10 and the opposing substrate 20. Based on the elastic recovery force of the dam 30 after being compressed, the dam 30 is in sealed contact with the array substrate 10 and the opposing substrate 20 respectively, eliminating the gap between the array substrate 10 or the opposing substrate 20 and the dam 30 in the prior art, avoiding the risk of electrophoretic particles 40 flowing through the gap, and improving the uniformity of pressing and display.

[0032] It should be noted that the dike 30 can be formed on the array substrate 10 or the opposing substrate 20.

[0033] exist Figure 1 In this embodiment, the cofferdam 30 is formed on the array substrate 10 as an example, but the application is not limited thereto. Figure 1 In the corresponding embodiment, during the cell assembly stage, the opposing substrate 20 is used to compress the cofferdam 30, so that the cofferdam 30 with a larger height is compressed more and the cofferdam 30 with a smaller height is compressed less, so that there is no gap between the opposing substrate 20 and the cofferdam 30. This solves the risk that the cofferdam 30 has a uniform height due to process instability, resulting in gaps and causing electrophoretic particles 40 to crosstalk through the gaps. In other words, it avoids the risk of crosstalk flow of electrophoretic particles 40.

[0034] Secondly, the cofferdam 30 is elastic, which allows it to buffer the external force when the display panel 100 is pressed, reducing the risk of the cofferdam 30 breaking.

[0035] Optionally, the array substrate 10 includes a first substrate 101, a thin film transistor 102, a planarization layer 103, and a pixel electrode 104. The thin film transistor 102 is disposed on the first substrate 101, the planarization layer 103 covers the thin film transistor 102, and the pixel electrode 104 is disposed on the side of the planarization layer 103 away from the first substrate 101.

[0036] Optionally, the opposing substrate 20 includes a second substrate 201 and a common electrode layer 202, wherein the common electrode layer 202 is disposed on the side of the second substrate 201 near the array substrate 10.

[0037] It should be noted that the structure of the array substrate 10 is not limited to... Figure 1 The implementation method shown.

[0038] Optionally, the material of the cofferdam 30 may include at least one of acrylic resins, polystyrene resins, and mixtures thereof.

[0039] Optionally, compared to setting elastic support members on a rigid cofferdam, the cofferdam 30 in this embodiment of the application is an integrally connected structure to improve the elastic recovery rate and compression rate of the cofferdam 30, thereby improving the sealing performance between the cofferdam 30, the array substrate 10 and the opposing substrate 20; secondly, the integrally connected structure of the cofferdam 30 has better stability and a simpler manufacturing process.

[0040] Optionally, in some embodiments of this application, the elastic recovery rate of the cofferdam 30 is between 75% and 80%.

[0041] It is understandable that the elastic recovery rate = (elastic recovery deformation / total applied deformation) × 100%. The smaller the elastic recovery rate of the cofferdam 30, the more difficult it is for the cofferdam 30 to return to the same height as its surroundings after deformation, and the easier it is for gaps to appear between the cofferdam 30 and the opposing substrate 20 when localized stress occurs. On the other hand, if the elastic recovery rate of the cofferdam 30 is too large, it is difficult to ensure that all cofferdams 30 are pressed to the same height during casing. Therefore, the elastic recovery rate of the cofferdam 30 is selected to be between 75% and 80%, so that the cofferdam 30 and the opposing substrate 20 are in sealed contact during casing, eliminating gaps; at the same time, it can improve the uniformity of all cofferdams 30 being pressed to the same height.

[0042] Optionally, the elastic recovery rate of the cofferdam 30 can be 75%, 76%, 77%, 78%, 79%, and 80%.

[0043] Optionally, in some embodiments of this application, the compression ratio of the cofferdam 30 is between 45% and 50%.

[0044] It is understandable that the compression ratio = (thickness after compression / thickness before compression) × 100%.

[0045] The smaller the compression ratio of the cofferdam 30, the better its compression effect, but the more difficult it is to recover to the same height as its surroundings after compression. This makes it easier for gaps to appear between the cofferdam 30 and the opposing substrate 20 under localized stress. Conversely, if the compression ratio of the cofferdam 30 is too large, it is difficult to ensure that all cofferdams 30 are compressed to the same height during cell assembly. Therefore, a compression ratio of 45% to 50% is selected for the cofferdam 30 to ensure a sealed contact between the cofferdam 30 and the opposing substrate 20 during cell assembly, eliminating gaps. Simultaneously, this improves the uniformity of all cofferdams 30 being compressed to the same height.

[0046] Optionally, the compression rate of the cofferdam 30 can be 45%, 46%, 47%, 48%, 49% and 50%.

[0047] Optionally, in some embodiments of this application, the elastic modulus of the cofferdam 30 is between 2 GPa and 3 GPa.

[0048] It is understandable that the elastic modulus is Young's modulus. The larger the elastic modulus of the cofferdam 30, the weaker its deformation capacity and the less compressible it is; that is, the more difficult the cofferdam 30 is to be compressed, and the more difficult it is to ensure that all cofferdams 30 are compressed to the same height during casing. Conversely, the smaller the elastic modulus of the cofferdam 30, the stronger its deformation capacity and the greater its compressibility, but the weaker its support performance. Therefore, the elastic modulus of the cofferdam 30 is selected to be between 2 GPa and 3 GPa to ensure that the cofferdam 30 and the opposing substrate 20 are in sealed contact during casing, eliminating gaps; at the same time, it meets the support requirements of the cofferdam 30.

[0049] Optionally, the elastic modulus of the cofferdam 30 can be 2 GPa, 2.1 GPa, 2.2 GPa, 2.3 GPa, 2.4 GPa, 2.5 GPa, 2.6 GPa, 2.7 GPa, 2.8 GPa, 2.9 GPa and 3 GPa.

[0050] Optionally, in some embodiments of this application, the cofferdam 30 comprises a black material.

[0051] For example, the material of the cofferdam 30 can be a black, opaque material. For instance, a black medium (carbon black particles, black pigment, or black dye, etc.) can be filled into transparent resin, making the transparent resin a black, opaque mixture. However, it is not limited to this; for example, the cofferdam 30 can also be made directly from a black material.

[0052] Understandably, the cofferdam 30 includes black material to improve the contrast of the display.

[0053] Optionally, in some embodiments of this application, the array substrate 10 includes a plurality of pixel electrodes 104, with a gap jx1 between adjacent pixel electrodes 104. A dike 30 is disposed at the gap jx1. Electrophoretic particles 40 are located within the region of the pixel electrode 104.

[0054] It is important to understand that in traditional electronic paper, a significant number of electrophoretic particles fall into the gaps between pixel electrodes. This area cannot be effectively controlled, resulting in numerous "dead zones" in the display area. This leads to lower white reflectivity and increased black reflectivity, thus affecting display contrast.

[0055] Based on this, the cofferdam 30 is set at the gap jx1 so that the electrophoretic particles 40 fall within the area of ​​the pixel electrode 104, thereby improving the effectiveness of controlling the electrophoretic particles 40 and thus improving the display contrast.

[0056] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a second structure of the display panel 100 provided in an embodiment of this application. Figure 2 In this application, the embodiments will be described in the parts that differ from the above embodiments to avoid redundancy.

[0057] Optionally, in some embodiments of this application, the array substrate 10 includes a first substrate 101 and a metal electrode 105. The metal electrode 105 is located on the side of the pixel electrode 104 near the first substrate 101, and the metal electrode 105 and the pixel electrode 104 are disposed in different layers. In the thickness direction of the display panel 100, the dike 30 at least partially overlaps with the metal electrode 105. The metal electrode 105 is made of ferrous metal.

[0058] It is important to understand that in related technologies, transparent dams are usually set on metal electrodes. External light enters from the dam and falls onto the metal electrodes below, and is then reflected from the metal electrodes to the observer's side, resulting in an increase in the black reflectivity of the electronic paper, thereby reducing the display contrast.

[0059] Based on this, in this embodiment of the application, the metal electrode 105 is made of ferrous metal to reduce the reflectivity of the metal electrode 105 and thereby improve the display contrast.

[0060] Optionally, the metal electrode 105 may include, but is not limited to, metal traces, capacitor plates, etc.

[0061] Optionally, the display panel 100 also includes a passivation layer 106 disposed between the metal electrode 105 and the pixel electrode 104.

[0062] Optionally, in some embodiments, the cofferdam 30 is black.

[0063] Understandably, the black dam 30 has light-absorbing properties, which can absorb external light and thus reduce the reflectivity of external light, thereby improving the display contrast.

[0064] The cofferdam 30 comprises a black material. For example, the material of the cofferdam 30 can be a black, opaque material, such as filling a transparent resin with a black medium (carbon black particles, black pigment, or black dye, etc.), thus transforming the transparent resin into a black, opaque mixture. However, this is not a limitation; for instance, the cofferdam 30 can also be prepared directly using a black material.

[0065] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a third structure of the display panel 100 provided in an embodiment of this application. Figure 3 In this application, the embodiments will be described in the parts that differ from the above embodiments to avoid redundancy.

[0066] Optionally, in some embodiments of this application, the array substrate 10 includes a first substrate 101 and a metal electrode 105, the metal electrode 105 being located on the side of the pixel electrode 104 near the first substrate 101. The metal electrode 105 and the pixel electrode 104 are disposed in different layers. In the thickness direction of the display panel 100, the dike 30 at least partially overlaps with the metal electrode 105.

[0067] The display panel 100 includes a black matrix layer 203. The black matrix layer 203 and the dike 30 are overlapped in the thickness direction of the display panel 100, and the black matrix layer 203 is formed on the opposing substrate 20 or the array substrate 10.

[0068] It is understandable that by setting the black matrix layer 203 and the dike 30 to overlap, the incident light in the area of ​​the dike 30 is absorbed by the black matrix layer 203, reducing the risk of incident light hitting the metal electrode 105, thereby improving the display contrast.

[0069] like Figure 3 As shown, a black matrix layer 203 is formed on the opposing substrate 20. The black matrix layer 203 is disposed on the side of the common electrode layer 202 closer to the array substrate 10, such that the black matrix layer 203 covers the dike 30. It is understood that disposing the black matrix layer 203 on the opposing substrate 20 side reduces the risk of incident light illuminating the dike 30, further improving display contrast. In some embodiments, the black matrix layer 203 may also be formed on the side of the common electrode layer 202 away from the array substrate 10 to further absorb incident light, reduce reflectivity, and improve contrast.

[0070] Optionally, in some embodiments, the black matrix layer 203 may also be formed on the array substrate 10, at any film location between the dam 30 and the metal electrode 105, that is, on the side of the metal electrode 105 closer to the dam 30. For example, the black matrix layer 203 may be formed on the surface of the metal electrode 105, or on the surface of the passivation layer 106 away from the metal electrode 105.

[0071] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a fourth structure of the display panel 100 provided in an embodiment of this application. Figure 4 In this application, the embodiments will be described in the parts that differ from the above embodiments to avoid redundancy.

[0072] Optionally, in some embodiments of this application, the array substrate 10 includes a first substrate 101 and a metal electrode 105, the metal electrode 105 being located on the side of the pixel electrode 104 near the first substrate 101, and the metal electrode 105 and the pixel electrode 104 being disposed in different layers.

[0073] In the top-view display panel 100, the cofferdam 30 is located outside the metal electrode 105.

[0074] It is understandable that placing the dike 30 outside the metal electrode 105 allows the light incident on the transparent dike 30 to avoid the metal electrode 105, reducing the risk of light being reflected by the metal electrode 105 and thus improving the display contrast.

[0075] Optionally, in some embodiments of this application, the array substrate 10 includes a thin-film transistor 102 and a planarization layer 103. The thin-film transistor 102 is disposed on a first substrate 101, and the planarization layer 103 covers the thin-film transistor 102. A metal electrode 105 is disposed on the side of the planarization layer 103 away from the first substrate 101. The planarization layer 103 comprises a black material.

[0076] Understandably, the planarization layer 103 includes a black material, which allows the planarization layer 103 to absorb external incident light. When external light passes through the dike 30 and enters the planarization layer 103, it will be absorbed by the planarization layer 103, thereby reducing the reflectivity of the display panel 100 and improving the display contrast.

[0077] The planarization layer 103 includes a black material. For example, the material of the planarization layer 103 can be a black, opaque material, such as filling a transparent resin with a black medium (carbon black particles, black pigment, or black dye, etc.), thus transforming the transparent resin into a black, opaque mixture. However, this is not a limitation; for instance, the planarization layer 103 can also be prepared directly using a black material.

[0078] Please refer to Figure 5 , Figure 5 This is a fifth structural schematic diagram of the display panel 100 provided in an embodiment of this application. Figure 5 In this application, the embodiments will be described in the parts that differ from the above embodiments to avoid redundancy.

[0079] Optionally, in some embodiments of this application, the array substrate 10 further includes a light-absorbing layer 107, which is disposed on the side of the first substrate 101 close to the metal electrode 105 or on the side of the first substrate 101 away from the metal electrode 105.

[0080] It is understood that the embodiments of this application provide a light-absorbing layer 107 to absorb external incident light. When external light passing through the dike 30 enters the light-absorbing layer 107, it will be absorbed by the light-absorbing layer 107, thereby reducing the reflectivity of the display panel 100 and improving the display contrast.

[0081] like Figure 5 As shown, the light-absorbing layer 107 is disposed on the side of the first substrate 101 away from the metal electrode 105. However, it is not limited to this; for example, the light-absorbing layer 107 may be formed on the surface of the first substrate 101 on the side closer to the metal electrode 105.

[0082] Please refer to Figure 6 , Figure 6 This is a sixth structural schematic diagram of the display panel 100 provided in an embodiment of this application. Figure 6 In this application, the embodiments will be described in the parts that differ from the above embodiments to avoid redundancy.

[0083] Optionally, in some embodiments of this application, a dike 30 is formed on the opposing substrate 20. A groove a1 is formed on the side of the array substrate 10 facing the opposing substrate 20, and the side of the dike 30 away from the opposing substrate 20 is disposed in the groove a1.

[0084] Understandably, placing the cofferdam 30 within the groove a1 restricts its displacement, thereby reducing the risk that the cofferdam 30 may not be able to recover after displacement. Secondly, since the cofferdam 30 is in a compressed state, its elastic restoring force acts on the groove a1, increasing the friction between the cofferdam 30 and the groove a1, further restricting the movement of the cofferdam 30.

[0085] Optionally, in some embodiments of this application, the array substrate 10 includes a first substrate 101, a thin film transistor 102, a planarization layer 103, and a pixel electrode 104. The thin film transistor 102 is disposed on the first substrate 101, the planarization layer 103 covers the thin film transistor 102, and the pixel electrode 104 is disposed on the side of the planarization layer 103 away from the first substrate 101.

[0086] The groove a1 is formed on the planarization layer 103, and the groove a1 is disposed at a distance from the pixel electrode 104.

[0087] It is understandable that, given that the planarization layer 103 needs to plan the terrain of the thin-film transistor 102, the planarization layer 103 has a relatively thick thickness. Therefore, the depth of the groove a1 formed in the planarization layer 103 can be flexibly selected according to requirements.

[0088] Optionally, the depth of the groove a1 is less than or equal to the thickness of the planarization layer 103.

[0089] Optionally, the depth of groove a1 is between 0.1 micrometers and 10 micrometers. It is understood that the greater the depth of groove a1, the more of the cofferdam 30 can extend into groove a1, and the stronger the ability of groove a1 to restrict the movement of cofferdam 30. However, the planarization layer 103 is more easily peeled off. Therefore, the depth of groove a1 is set between 0.1 micrometers and 10 micrometers to improve the ability to restrict the movement of cofferdam 30 while maintaining the stability of planarization layer 103.

[0090] Optionally, the depth of groove a1 can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm, or 10 μm.

[0091] Please refer to Figure 7 , Figure 7 This is a seventh structural schematic diagram of the display panel 100 provided in an embodiment of this application. Figure 7 In this application, the embodiments will be described in the parts that differ from the above embodiments to avoid redundancy.

[0092] Optionally, in some embodiments of this application, a dike 30 is formed on the array substrate 10. A groove a1 is formed on the side of the opposing substrate 20 facing the array substrate 10. The side of the dike 30 away from the array substrate 10 is disposed in the groove a1.

[0093] Understandably, placing the cofferdam 30 within the groove a1 restricts its displacement, thereby reducing the risk that the cofferdam 30 may not be able to recover after displacement. Secondly, since the cofferdam 30 is in a compressed state, its elastic restoring force acts on the groove a1, increasing the friction between the cofferdam 30 and the groove a1, further restricting the movement of the cofferdam 30.

[0094] Optionally, in some embodiments of this application, the opposing substrate 20 includes a second substrate 201, a cover layer 204, and a common electrode layer 202. The cover layer 204 is disposed on the side of the second substrate 201 close to the array substrate 10. The cover layer 204 has a cutout c1 corresponding to the area of ​​the dike 30. The common electrode layer 202 is disposed on the side of the cover layer 204 away from the second substrate 201. The common electrode layer 202 covers the cutout c1 to form a groove a1.

[0095] The cofferdam 30 abuts against the common electrode layer 202 located in the groove a1.

[0096] Optionally, the depth of the groove a1 is between 0.1 micrometers and 10 micrometers. It is understood that the greater the depth of the groove a1, the more of the cofferdam 30 can extend into the groove a1, and the stronger the ability of the groove a1 to restrict the movement of the cofferdam 30. However, the cover layer 204 is more easily peeled off. Therefore, the depth of the groove a1 is set between 0.1 micrometers and 10 micrometers to improve the ability to restrict the movement of the cofferdam 30 while maintaining the stability of the cover layer 204.

[0097] Optionally, the material of the cover layer 204 is a material with leveling properties.

[0098] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of a display device 1000 provided in an embodiment of this application. The display device 1000 of this application includes a display panel 100 as described in any of the above embodiments.

[0099] It should be noted that the structure of the display panel 100 of the display device 1000 in this application embodiment is similar to or the same as the structure of the display panel 100 of any of the above embodiments. For details, please refer to... Figures 1 to 7 Therefore, the relevant explanations will not be repeated here.

[0100] Alternatively, the display device 1000 may be a tablet computer, an e-book reader, or the like.

[0101] In the display device 1000 of this application embodiment, a dam 30 is disposed between the array substrate 10 and the opposing substrate 20, and the dam 30 is provided with a plurality of openings k1; the array substrate 10 and the opposing substrate 20 compress the dam 30, the dam 30 has an elastic restoring force, and the openings k1, the array substrate 10 and the opposing substrate 20 form a sealed cavity m1. Electrophoretic particles 40 are disposed within the sealed cavity m1.

[0102] It is understood that the display device 1000 of this application embodiment uses an elastic dam 30 disposed between the array substrate 10 and the opposing substrate 20. During the cell assembly process, the elastic dam 30 is squeezed by the action of the array substrate 10 and the opposing substrate 20. Based on the elastic recovery force of the dam 30 after being compressed, the dam 30 makes sealed contact with the array substrate 10 and the opposing substrate 20 respectively, eliminating the gap between the array substrate 10 or the opposing substrate 20 and the dam 30 in the prior art, avoiding the risk of electrophoretic particles 40 flowing through the gap, and improving the uniformity of pressing and display.

[0103] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0105] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0106] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Array substrate; The opposing substrate is disposed opposite to the array substrate; A dike is disposed between the array substrate and the opposing substrate, and the dike has multiple openings; the array substrate and the opposing substrate compress the dike, the dike has an elastic restoring force, and the openings, the array substrate and the opposing substrate form a sealed cavity; Electrophoretic particles are disposed within the sealed cavity.

2. The display panel according to claim 1, characterized in that, The elastic recovery rate of the cofferdam is between 75% and 80%.

3. The display panel according to claim 2, characterized in that, The compression rate of the cofferdam is between 45% and 50%.

4. The display panel according to claim 2, characterized in that, The elastic modulus of the cofferdam is between 2 GPa and 3 GPa.

5. The display panel according to claim 1, characterized in that, The cofferdam is made of black material.

6. The display panel according to claim 1, characterized in that, The array substrate includes multiple pixel electrodes, with a gap between two adjacent pixel electrodes, a dam is disposed at the gap, and the electrophoretic particles are located within the region of the pixel electrode.

7. The display panel according to claim 6, characterized in that, The array substrate includes a first substrate and a metal electrode, the metal electrode being located on the side of the pixel electrode closer to the first substrate, and the metal electrode and the pixel electrode being disposed in different layers; In the display panel viewed from above, the dam is located outside the metal electrode.

8. The display panel according to claim 7, characterized in that, The array substrate includes thin-film transistors and a planarization layer. The thin-film transistors are disposed on the first substrate, and the planarization layer covers the thin-film transistors. The metal electrodes are disposed on the side of the planarization layer away from the first substrate, and the planarization layer includes a black material.

9. The display panel according to claim 7, characterized in that, The array substrate further includes a light-absorbing layer, which is disposed on the side of the first substrate close to the metal electrode or on the side of the first substrate away from the metal electrode.

10. The display panel according to claim 6, characterized in that, The array substrate includes a first substrate and a metal electrode. The metal electrode is located on the side of the pixel electrode close to the first substrate. The metal electrode and the pixel electrode are disposed in different layers. In the thickness direction of the display panel, the dam at least partially overlaps with the metal electrode. The display panel includes a black matrix layer, which overlaps with the dike in the thickness direction of the display panel. The black matrix layer is formed on the opposing substrate or the array substrate.

11. The display panel according to claim 6, characterized in that, The array substrate includes a first substrate and a metal electrode. The metal electrode is located on the side of the pixel electrode close to the first substrate. The metal electrode and the pixel electrode are disposed in different layers. In the thickness direction of the display panel, the dam at least partially overlaps with the metal electrode. The metal electrode is made of ferrous metal.

12. The display panel according to claim 1, characterized in that, The dam is formed on the opposing substrate, and a groove is formed on the side of the array substrate facing the opposing substrate. The side of the dam away from the opposing substrate is disposed in the groove.

13. The display panel according to claim 12, characterized in that, The array substrate includes a first substrate, thin-film transistors, a planarization layer, and pixel electrodes. The thin-film transistors are disposed on the first substrate, the planarization layer covers the thin-film transistors, and the pixel electrodes are disposed on the side of the planarization layer away from the first substrate. The groove is formed on the planar layer and is spaced apart from the pixel electrode.

14. The display panel according to claim 1, characterized in that, The dam is formed on the array substrate, and a groove is formed on the side of the opposing substrate facing the array substrate. The side of the dam away from the array substrate is disposed in the groove.

15. The display panel according to claim 14, characterized in that, The opposing substrate includes a second substrate, a cover layer, and a common electrode layer. The cover layer is disposed on the side of the second substrate close to the array substrate. The cover layer has a cutout in the area corresponding to the dam. The common electrode layer is disposed on the side of the cover layer away from the second substrate. The common electrode layer covers the cutout to form the groove. The cofferdam abuts against the common electrode layer located within the groove.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1-15.

Images