Low dropout linear regulator circuit with high power supply rejection ratio
By combining an operational amplifier clamping module, a power supply rejection enhancement module, and a frequency compensation module, the problem of poor power supply rejection in low dropout linear regulators is solved, achieving high power supply rejection ratio (PSRR) and low power consumption, making it suitable for powering load-sensitive modules such as digital systems and RF modules.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-02-10
- Publication Date
- 2026-05-12
AI Technical Summary
Existing low-dropout linear regulators have poor power suppression performance in the mid-to-high frequency range, and are complex in design, with high stability and power consumption. Traditional solutions have stability problems or introduce additional noise, making it difficult to balance power suppression and transient response in low-dropout applications.
By combining an operational amplifier clamping module, a power supply suppression enhancement module, and a frequency compensation module, and using cascaded NMOS and PMOS transistors to form a negative feedback loop, combined with a flip-flop voltage follower structure, the power supply suppression effect is enhanced and frequency compensation is performed, simplifying the circuit design.
It achieves a power supply rejection ratio (PSRR) of less than -10dB across the entire frequency range, reducing power consumption and chip area, simplifying circuit design, and improving robustness. It is suitable for powering modules with high PSRR requirements.
Smart Images
Figure CN122018622A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog integrated circuit technology, and specifically to a low dropout linear regulator circuit with high power supply rejection ratio. Background Technology
[0002] Low-dropout linear regulators (LDOs) are the power source of analog and mixed-signal integrated circuits. Their core task is to provide stable and clean power supply voltages for load-sensitive modules such as digital systems, memory, and RF modules. Capless LDOs, with their low cost and ease of integration within the chip, have become a key module in the power networks of portable devices and System-on-a-Chip (SoC). However, they face the serious challenge of poor power rejection in the mid-to-high frequency range. The pursuit of higher power rejection is the core driving force behind the evolution of this technology. Existing technologies have mainly gone through several development stages, each with significant limitations.
[0003] Traditional high-gain operational amplifier regulators represent the simplest and most classic structure. They typically consist of a high-gain operational amplifier connected in series with a power transistor to form a negative feedback loop. The high-gain operational amplifier further enhances the loop gain. The power supply rejection ratio (PSRR) in the low-frequency range is proportional to the loop gain, thus improving the PSRR in the mid-to-low frequency range. Its core advantage lies in achieving excellent PSRR in the low-frequency range through high loop gain, effectively filtering out power supply noise. However, this advantage comes at a significant cost: to ensure loop stability, the dominant pole must be located at an extremely low frequency, severely limiting the system's unity-gain bandwidth and resulting in slow transient response, failing to meet the demands of rapid load switching. More importantly, achieving stability usually relies on large external or on-chip capacitors, which contradicts the high-integration, low-cost capacitive design principle of capless systems.
[0004] To improve the power supply rejection ratio (PSRR) of voltage regulators, mainstream solutions include ripple feedforward technology. The core idea is to detect the input power supply ripple before the main feedback loop reacts to power fluctuations, generate a correction signal with the opposite amplitude, and then directly drive the power transistor to "cancel" the ripple's impact on the output, achieving rapid ripple processing. However, this method has drawbacks: the feedforward path needs to generate a signal with equal amplitude and opposite phase to the noise; any mismatch will weaken the suppression effect, or even amplify the noise. Furthermore, the feedforward path (especially when capacitors are included) introduces new zeros and poles, altering the loop's frequency response. Improper compensation can reduce the phase margin, causing system oscillations. In summary, while ripple feedforward technology can significantly improve the PSRR in the mid-to-high frequency range, improper design may introduce stability issues or poor suppression performance, ultimately resulting in less than expected performance.
[0005] To simplify circuit design, some studies have explored changing the type of power transistor, using other types of power transistors with better power supply noise suppression, such as NMOS power transistors, or even employing two or more cascaded stages to achieve step-by-step suppression of power supply noise. Using NMOS power transistors or cascaded structures can fundamentally improve the power supply rejection capability in the low-frequency range. Theoretically, cascaded structures can make the total PSRR the sum of the PSRR of each stage, but they also have some problems. When using NMOS as a power transistor or a cascaded structure, the input-output voltage drop will increase significantly, leading to a decrease in efficiency. In applications with low voltage drop requirements, the circuit must add an additional charge pump circuit, which will significantly increase the complexity of the circuit design, introduce additional noise, and increase chip area and static power consumption.
[0006] In summary, existing technologies have the following problems: If a traditional high-gain operational amplifier type regulator is used, a high power supply rejection ratio (PSRR) can be obtained, but this introduces problems such as slower transient response, circuit stability, high circuit design complexity, large area, and high power consumption; if an NMOS transistor is used as a power transistor, it has a better power supply rejection effect than a PMOS transistor, but for low dropout applications, the need to add an additional charge pump undoubtedly sacrifices more area and power consumption for the power supply rejection effect, which is too costly; if ripple feedforward technology is used, the circuit design requirements are higher, and improper design can cause circuit system oscillations, resulting in poor robustness. Summary of the Invention
[0007] The purpose of this invention is to provide a low-dropout linear regulator circuit with high power supply rejection ratio (PSRR) for outputting a low-noise, high-PSRR low-dropout linear regulator, suitable for powering modules with high PSRR requirements.
[0008] The technical solution adopted in this invention is as follows: a low dropout linear regulator circuit with high power supply rejection ratio, the circuit specifically includes: an operational amplifier clamping module, a power supply rejection enhancement module and a frequency compensation module; The operational amplifier clamping module includes a first-stage operational amplifier circuit composed of NMOS transistors and POMS transistors and a second-stage VBIAS generation circuit. The two circuits are cascaded to form a negative feedback loop for clamping the operational amplifier input voltage. The operational amplifier clamping module is connected to a flip-flop voltage follower for voltage output. The power supply suppression enhancement module is electrically connected to the operational amplifier clamping module and is used to increase the voltage of the operational amplifier after it is clamped by the operational amplifier clamping module. The frequency compensation module is electrically connected to the power suppression enhancement module and is used to perform stability compensation on the voltage after gain by the power suppression enhancement module and output the compensated voltage.
[0009] Furthermore, the first-stage operational amplifier circuit includes NMOS transistors NM1, NMOS transistor NM2, NMOS transistor NM3, NMOS transistor NM4, NMOS transistor NM5, PMOS transistors PM1, PM2, PM3, and PM4, wherein: The gate of NM1 is connected to the reference voltage VREF. The source of NM1 is connected to the source of NM2 and the drain of NM3. The drain of NM1 is connected to the drain of PM1 and the source of PM3. The gate of NM2 is connected to the second-stage VBIAS generation circuit. The drain of NM2 is connected to the drain of PM2 and the source of PM4. The gate potential of NM3 is the bias voltage VB. The source of NM3 is connected to the power supply ground GND. The gate of NM4 is connected to the gate of NM5 and the gate of NM3 to output the bias voltage VB. The source of NM4 is connected to the power supply ground GND. The drain of NM4 is connected to the gate of PM1, PM2 and the drain of PM3. The source of NM5 is connected to the power supply ground GND. The drain of NM5 is connected to the drain of PM4 and the second-stage VBIAS generation circuit. The sources of PM1 and PM2 are connected to the power supply VDD. The gates of PM3 and PM4 are connected together.
[0010] Furthermore, the second-stage VBIAS generation circuit includes PMOS transistor PM5, PMOS transistor PM6, and NMOS transistor NM6; Wherein: the gate of PM5 is connected to the drain of NM5, the drain of PM5 and the source of PM6 are connected to the gate of NM2; the drain of PM5 is connected to the power supply VDD, and the source of PM5 is connected to the power supply VDD. The gate of NM6 is connected to the bias voltage VBN and the flip voltage follower. The source of NM6 is connected to the power ground GND. The drain of NM6 is connected to the gate and drain of PM6 and the flip voltage follower via the VBIAS signal.
[0011] Furthermore, the operational amplifier clamping module also includes a Miller compensation capacitor C1, the gate terminal of NM2 is connected to the right side of capacitor C1, and the drain terminal of NM5 is connected to the left side of capacitor C1, with the signal at that point being EA_OUT.
[0012] Furthermore, the power supply suppression enhancement module includes NMOS transistor NM8, NMOS transistor NM9, NMOS transistor NM10, PMOS transistor PM8, PMOS transistor PM9, switch TG1, switch TG2, switch TG3, and module logic control signals; The input signal for the module logic control is PSR_ON. This signal is output as PSR_EN after passing through the first-stage inverter, and as PSR_ENB after passing through the second-stage inverter. The gate of NM8 is connected to the left side of the flip voltage follower and switch TG3. The drain of NM8 is connected to the gate of NM9, the drain of NM9, the gate of NM10, and the drain of PM8. The source of NM8 is connected to the source of NM9 and the source of NM10, and both are connected to the power supply ground GND. The source of PM8 and the source of PM9 are connected to the power supply VDD. The drain of NM10 is connected to the drain of PM9, the flip voltage follower, and the right side of TG3. The left side of TG1 and TG2 is the bias voltage VBP. The right side of TG1 is connected to the gate of PM8, and the right side of TG2 is connected to the gate of PM9. The upper and lower control signals of switches TG1, TG2, and TG3 are PSR_EN and PSR_ENB, respectively.
[0013] Furthermore, the frequency compensation module includes switch TG4, switch TG5, capacitor Cc, and resistor Rc; Specifically: the control signals on the right and left sides of TG4 and TG5 are PSR_EN and PSR_ENB, respectively; the upper side of TG4, the upper plate of capacitor Cc, and the flip voltage follower are connected and form the output voltage LDO_OUT; the lower side of TG4 is connected to the lower plate of capacitor Cc, the upper side of TG5, and the upper side of resistor Rc; the lower side of TG5 and the lower side of resistor Rc are connected to the power ground GND.
[0014] Furthermore, the flip voltage follower includes PMOS transistor PM7, PMOS transistor PM10, PMOS transistor PM11, NMOS transistor NM7, and NMOS transistor NM11; Wherein: the gate of NM11 is connected to the gate of NM6, the gate of PM11 is connected to the drain of NM6, the drain of NM7 and the drain of PM7 are connected to the gate of NM8, the source of PM10 and the source of PM7 are connected to the power supply VDD, and the gate of PM10 is connected to the drain of NM10. The gate of NM7 is the bias voltage VSET. The source of NM7 is connected to the drain of NM11 and the drain of PM11. The source of NM11 is connected to the power ground GND. The drain of PM10, the source of PM11, the upper side of switch TG4, and the upper plate of capacitor Cc are connected to form the output voltage LDO_OUT.
[0015] In summary, due to the adoption of the above technical solution, the beneficial effects of this application are: (1) Good power suppression effect: The core objective of this invention is to obtain a high power suppression effect, which can achieve a power suppression ratio (PSRR) of less than -10dB across the entire frequency range. After adding the power suppression enhancement module, the power suppression ratio effect at low and medium frequencies is significant.
[0016] (2) Significantly reduced power consumption and chip area: The ripple feedforward technology requires an additional auxiliary operational amplifier, which is the main contributor to static power consumption and chip area. This invention does not require an additional auxiliary operational amplifier, resulting in smaller overall static power consumption and chip area, making it more suitable for applications such as IoT, wearable devices, and implantable medical devices that have extremely high requirements for energy consumption and integration.
[0017] (3) Simple circuit design and strong robustness: This invention does not introduce too many auxiliary modules to achieve the effect of improving power supply suppression. It adheres to the principle of simplification from the beginning of the design, which reduces the workload of back-end simulation, shortens the R&D cycle, and has strong robustness to process, voltage, temperature PVT changes, thus improving the success rate of tape-out. Attached Figure Description
[0018] Figure 1 This is a circuit diagram of a low dropout linear regulator with high power supply rejection ratio according to the present invention; Figure 2 The power supply rejection ratio (PSRR) curve of the output of a low dropout linear regulator circuit with high power supply rejection ratio according to the present invention is shown. Figure 3 This is a comparison diagram showing the power suppression enhancement module before and after being turned on and off according to the present invention. Detailed Implementation
[0019] The present invention will now be described in detail with reference to the accompanying drawings.
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0021] Example This embodiment provides a low dropout linear regulator circuit with high power supply rejection ratio (PSRR). It proposes an LDO circuit based on a flip-flop voltage follower (PSRR) structure to obtain a high PSRR output voltage without sacrificing transient response.
[0022] like Figure 1 As shown, the overall circuit is divided into three parts, including an operational amplifier clamping module, a power supply suppression enhancement module, and a frequency compensation module.
[0023] The operational amplifier clamping module includes NM1, NM2, NM3, NM4, NM5, NM6, PM1, PM2, PM3, PM4, PM5, PM6, and C1. The gate voltage of NMOS transistor NM1 here is the reference signal VREF. Its source is connected to the source of NMOS transistor NM2 and the drain of NMOS transistor NM3. Its drain is connected to the drain of PMOS transistor PM1 and the source of PM3. The gate of NMOS transistor NM2 is connected to the source of PMOS transistor PM6, the drain of PM5, and the right side of capacitor C1. Its drain is connected to the drain of PMOS transistor PM2 and the source of PM4. The gate potential of NMOS transistor NM3 here is the bias voltage VB. Its source is connected to power ground GND. The gates of NMOS transistor NM4, NM5, and NM3 are connected to the bias voltage VB. Its source is connected to power ground GND. Its drain is connected to the gates of PMOS transistors PM1 and PM2 and the drain of PM3. The source of NMOS transistor NM5 is connected to power ground GND. Its drain is connected to the drain of PMOS transistor PM4, the gate of PM5, and the left side of capacitor C1, and the signal here is EA_OUT. The gate of NMOS transistor NM6 is connected to the gate of NM11 via the bias voltage VBN, and its source is connected to the power supply ground GND. Its drain is connected to the gate and drain of PMOS transistor PM6 and the gate of PM11 via the VBIAS signal. The sources of PMOS transistors PM1, PM2, and PM5 are connected to the power supply VDD, and the gates of PMOS transistors PM3 and PM4 are connected via the bias voltage VB1.
[0024] The power suppression enhancement module includes NM8, NM9, NM10, PM8, PM9, TG1, TG2, TG3, and module logic control signals. The input signal for module logic control is PSR_ON. This signal outputs PSR_EN after passing through the first-stage inverter, and PSR_ENB after passing through the second-stage inverter. The gate of NMOS transistor NM8 is connected to the drain of NM7, the drain of PM7, and the left side of switch TG3. Its drain is connected to the gate of NM9, the drain of NM9, the gate of NM10, and the drain of PM8. Its source is connected to the power ground GND along with the sources of NM9 and NM10. The sources of PMOS transistors PM8, PM9, PM10, and PM7 are connected to the power supply VDD. The drain of NMOS transistor NM10 is connected to the drain of PMOS transistor PM9, the gate of PM10, and the right side of switch TG3. The left side of switches TG1 and TG2 and the gate terminal of PMOS transistor PM7 are both biased by voltage VBP. The right side of TG1 is connected to the gate terminal of PMOS transistor PM8, and the right side of TG2 is connected to the gate terminal of PMOS transistor PM9. The control signals on the upper and lower sides of switches TG1, TG2, and TG3 are PSR_EN and PSR_ENB, respectively.
[0025] The frequency compensation module includes TG4, TG5, Cc, and Rc. The control signals on the right and left sides of switches TG4 and TG5 are PSR_EN and PSR_ENB, respectively. The upper side of switch TG4, the upper plate of capacitor Cc, the drain of PMOS transistor PM10, and the source of PM11 are connected to form the output voltage LDO_OUT. The lower side of switch TG4 is connected to the lower plate of capacitor Cc, the upper side of switch TG5, and the upper side of resistor Rc. The lower side of switch TG5 and the lower side of resistor Rc are connected to power ground GND. The gate of NMOS transistor NM7 is the bias voltage VSET, and its source is connected to the drain of NM11 and the drain of PM11. The source of NM11 is connected to power ground GND.
[0026] The working principle of the circuit in this embodiment is as follows: First, let's explain how to determine the static operating point of the circuit. In the op-amp clamping module, NM1, NM2, NM3, NM4, NM5, PM1, PM2, PM3, and PM4 form the first-stage op-amp circuit, while PM5, PM6, and NM6 form the second-stage VBIAS generation circuit. NM6 acts as a current source to keep the current flowing through the branches of PM5, PM6, and NM6 constant. The two cascaded stages form a negative feedback loop. C1 is a Miller compensation capacitor used to stabilize the negative feedback. The input of the op-amp circuit is the gate voltage of NM1 and NM2. The op-amp's function is to clamp the voltage at its input, i.e., clamp the reference voltage VREF and the gate voltage of NM2 (the source voltage of PM6). Since NM6 in the second-stage circuit fixes the current flowing through the second-stage branch, the gate-source voltage VGS for PM6 is fixed. The presence of the first and second stages in the negative feedback loop ensures... The magnitude of the VBIAS voltage is determined by the current flowing through NM6 in the second-stage circuit. The size of NM6 determines the current flow; PM7 is a current source transistor, its function is to fix the current flowing through the branch containing NM7, and the current flowing through this branch is defined as... NM11 is a current source transistor whose function is to fix the total current flowing through the NM7 / PM7 branch and the PM10 / PM11 branch, defined as follows: Therefore, the current flowing through the PM10 and PM11 branches If the PM11 and PM6 parameters are matched and and If the two currents are also matched, then the gate-source voltages VGS of PM11 and PM6 are almost equal. Therefore, the output voltage LDO_OUT of the circuit can be expressed as: (1) (2) Combining equations (1) and (2), we can obtain that LDO_OUT≈VREF. The core of this is to determine the static operating point of the circuit by matching the current flowing through PM6 and PM11 with their dimensions. Secondly, we can explain the fast response of the circuit. PM7, PM10, PM11, NM7, and NM11 form a flipped voltage follower (FVF) structure, which constitutes the negative feedback output stage circuit of the LDO. It has a small output resistance and a good transient response speed. Among them, PM10 is a power MOS transistor responsible for providing the output current required by the load, and NM11 and PM7 are current sources. If the load of the regulator changes, causing the LDO_OUT voltage to drop, the VGS of PM11 decreases, and the current IPM11 decreases, while the total current INM11 flowing through NM11 remains unchanged. The current INM7 flowing through the NM7 branch increases, which enhances the pull-down capability of PM10. The gate voltage of PM10 decreases, and its VGS increases. PM10 provides a larger output current to the load to ensure that the LDO_OUT voltage rises quickly. This process is the process of fast transient response. The Filpped Voltage Follower (FVF) circuit structure is simple, requiring only PM10, PM11, and NM7 to form a fast negative feedback loop without the need for traditional operational amplifiers. The FVF fast negative feedback loop can achieve a faster transient response, but the loop gain of the formed fast negative feedback loop is lower than that of the operational amplifier-based loop. Since the loop gain is proportional to the power supply rejection ratio (PSRR), the power supply rejection ratio (PSRR) of the LDO circuit in the mid-to-low frequency range is relatively low. When powering power-sensitive modules, this can result in large output voltage ripple, affecting the normal operation of the circuit. This embodiment adds a power suppression enhancement module and a frequency compensation module to improve the above situation, so as to achieve better power suppression effect of LDO circuit. Finally, the power suppression enhancement module is described. PM8 is a current source with a total current of IPM8. PM8 provides current to NM8 and NM9 respectively, with the current ratio of 1:K. The first stage composed of NM8, NM9, and PM8 generates a gain of K through current multiplication. NM10 and PM9 form a common source to provide gain. The two stages are cascaded to provide higher gain, and the total gain provided is... As can be seen, the power supply suppression enhancement module can significantly increase the loop gain, inevitably leading to stability issues. A suitable stability compensation scheme is needed to meet the design requirements. Therefore, a frequency compensation module is introduced. Its core is that Cc and Rc are connected in series to introduce a zero in the left half-plane of the fast negative feedback loop, improving loop stability and ensuring a phase margin PM greater than 45 degrees, thus guaranteeing circuit stability. Simultaneously, the module logic control signal PSR_ON can control whether the power supply suppression enhancement module and the frequency compensation module are turned on or off. This control signal can be turned on or off according to the load type.
[0027] like Figure 2 As shown in the figure, this embodiment has been verified to achieve a power supply rejection ratio (PSRR) of -70dB in the low-frequency range, -66dB at 1kHz, -29dB at 100kHz, and -30dB at 5MHz, with the PSRR not exceeding -10dB across the entire frequency range, thus achieving excellent power supply rejection performance.
[0028] like Figure 3 As shown, purple represents the power suppression ratio (PSRR) curve without the power suppression enhancement module enabled, and green represents the curve after the improvement based on this invention. The improved curve is significantly lower than the curve without the power suppression enhancement module enabled, indicating better power suppression performance.
[0029] This article uses specific embodiments to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
Claims
1. A low-dropout linear regulator circuit with high power supply rejection ratio, characterized in that, The circuit specifically includes: an operational amplifier clamping module, a power supply rejection enhancement module, and a frequency compensation module; The operational amplifier clamping module includes a first-stage operational amplifier circuit composed of NMOS transistors and POMS transistors and a second-stage VBIAS generation circuit. The two circuits are cascaded to form a negative feedback loop for clamping the operational amplifier input voltage. The operational amplifier clamping module is connected to a flip-flop voltage follower for voltage output. The power supply suppression enhancement module is electrically connected to the operational amplifier clamping module and is used to increase the voltage of the operational amplifier after it is clamped by the operational amplifier clamping module. The frequency compensation module is electrically connected to the power suppression enhancement module and is used to perform stability compensation on the voltage after gain by the power suppression enhancement module and output the compensated voltage.
2. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 1, characterized in that, The first-stage operational amplifier circuit includes NMOS transistors NM1, NMOS transistor NM2, NMOS transistor NM3, NMOS transistor NM4, NMOS transistor NM5, PMOS transistors PM1, PM2, PM3, and PM4, wherein: The gate of NM1 is connected to the reference voltage VREF. The source of NM1 is connected to the source of NM2 and the drain of NM3. The drain of NM1 is connected to the drain of PM1 and the source of PM3. The gate of NM2 is connected to the second-stage VBIAS generation circuit. The drain of NM2 is connected to the drain of PM2 and the source of PM4. The gate potential of NM3 is the bias voltage VB. The source of NM3 is connected to the power supply ground GND. The gate of NM4 is connected to the gate of NM5 and the gate of NM3 to output the bias voltage VB. The source of NM4 is connected to the power supply ground GND. The drain of NM4 is connected to the gate of PM1, PM2 and the drain of PM3. The source of NM5 is connected to the power supply ground GND. The drain of NM5 is connected to the drain of PM4 and the second-stage VBIAS generation circuit. The sources of PM1 and PM2 are connected to the power supply VDD. The gates of PM3 and PM4 are connected together.
3. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 2, characterized in that, The second-stage VBIAS generation circuit includes PMOS transistor PM5, PMOS transistor PM6, and NMOS transistor NM6; Wherein: the gate of PM5 is connected to the drain of NM5, the drain of PM5 and the source of PM6 are connected to the gate of NM2; the drain of PM5 is connected to the power supply VDD, and the source of PM5 is connected to the power supply VDD. The gate of NM6 is connected to the bias voltage VBN and the flip voltage follower. The source of NM6 is connected to the power ground GND. The drain of NM6 is connected to the gate and drain of PM6 and the flip voltage follower via the VBIAS signal.
4. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 3, characterized in that, The operational amplifier clamping module also includes a Miller compensation capacitor C1, the gate terminal of NM2 is connected to the right side of capacitor C1, and the drain terminal of NM5 is connected to the left side of capacitor C1, with the signal at that point being EA_OUT.
5. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 1, characterized in that, The power suppression enhancement module includes NMOS transistors NM8, NMOS transistors NM9, NMOS transistors NM10, PMOS transistors PM8 and PM9, switches TG1, TG2, and TG3, as well as module logic control signals. The input signal for the module logic control is PSR_ON. This signal is output as PSR_EN after passing through the first-stage inverter, and as PSR_ENB after passing through the second-stage inverter. The gate of NM8 is connected to the left side of the flip voltage follower and switch TG3. The drain of NM8 is connected to the gate of NM9, the drain of NM9, the gate of NM10, and the drain of PM8. The source of NM8 is connected to the source of NM9 and the source of NM10, and both are connected to the power supply ground GND. The source of PM8 and the source of PM9 are connected to the power supply VDD. The drain of NM10 is connected to the drain of PM9, the flip voltage follower, and the right side of TG3. The left side of TG1 and TG2 is the bias voltage VBP. The right side of TG1 is connected to the gate of PM8, and the right side of TG2 is connected to the gate of PM9. The upper and lower control signals of switches TG1, TG2, and TG3 are PSR_EN and PSR_ENB, respectively.
6. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 5, characterized in that, The frequency compensation module includes switch TG4, switch TG5, capacitor Cc, and resistor Rc; Specifically: the control signals on the right and left sides of TG4 and TG5 are PSR_EN and PSR_ENB, respectively; the upper side of TG4, the upper plate of capacitor Cc, and the flip voltage follower are connected and form the output voltage LDO_OUT; the lower side of TG4 is connected to the lower plate of capacitor Cc, the upper side of TG5, and the upper side of resistor Rc; the lower side of TG5 and the lower side of resistor Rc are connected to the power ground GND.
7. A low-dropout linear regulator circuit with high power supply rejection ratio according to any one of claims 1 to 6, characterized in that, The flip-flop voltage follower includes PMOS transistor PM7, PMOS transistor PM10, PMOS transistor PM11, NMOS transistor NM7, and NMOS transistor NM11; Wherein: the gate of NM11 is connected to the gate of NM6, the gate of PM11 is connected to the drain of NM6, the drain of NM7 and the drain of PM7 are connected to the gate of NM8, the source of PM10 and the source of PM7 are connected to the power supply VDD, and the gate of PM10 is connected to the drain of NM10. The gate of NM7 is the bias voltage VSET. The source of NM7 is connected to the drain of NM11 and the drain of PM11. The source of NM11 is connected to the power ground GND. The drain of PM10, the source of PM11, the upper side of switch TG4, and the upper plate of capacitor Cc are connected to form the output voltage LDO_OUT.