Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device, the array substrate comprises a substrate, a first signal line, a second signal line, a first touch control wire and a second touch control wire, and the first signal line is located on one side of the substrate and extends in the first direction; the second signal lines are located on the sides, away from the substrate, of the first signal lines and extend in the second direction, and the second direction intersects with the first direction; the first touch wires extend in the first direction, the multiple first touch wires form a set of first touch coils, and the first touch wires and the first signal wires are arranged on the same layer or located on the sides, away from the substrate, of the second signal wires; the second touch wires extend in the second direction, the multiple second touch wires form a set of second touch coils, and the second touch wires and the second signal wires are arranged on the same layer. According to the array substrate, the electromagnetic touch control function is achieved, a product has finer handwriting and higher response speed, meanwhile, the number of mask times of at least one layer can be reduced, and cost can be saved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] EMR (Electro Magnetic Resonance) Incell is a technology that integrates electromagnetic touch technology into the LCD panel. Compared to traditional capacitive touch, it offers advantages such as finer handwriting, faster response speed, and unique hover positioning. In the field of drawing, it allows for more precise and lower-latency writing. At the same time, the application of this technology can make LCD panels thinner and lighter, and lower in cost.

[0003] Current LCD panel designs result in high costs for LCD panels. Summary of the Invention

[0004] This disclosure provides an array substrate, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the present disclosure, an embodiment of the present disclosure provides an array substrate, comprising: Substrate; A first signal line is located on one side of the substrate and extends along a first direction; The second signal line is located on the side of the first signal line away from the substrate, and the second signal line extends along a second direction, which intersects with the first direction; The first touch trace extends along the first direction, and multiple first touch traces form a group of first touch coils. The first touch trace is disposed on the same layer as the first signal line, or the first touch trace is located on the side of the second signal line away from the substrate. The second touch trace extends along the second direction, and multiple second touch traces form a group of second touch coils. The second touch traces are arranged on the same layer as the second signal lines.

[0006] As a second aspect of the present disclosure, the present disclosure provides a display panel including the array substrate disclosed in the present embodiment.

[0007] As a third aspect of the present disclosure, the present disclosure provides a display device, including the display panel described in the present disclosure.

[0008] In the array substrate provided in this application, a first touch trace and a second touch trace constitute an electromagnetic touch module. The array substrate integrates the electromagnetic touch module internally, thereby enabling electromagnetic touch functionality. The electromagnetic touch module can be used with an electromagnetic pen to achieve touch control and display. Specifically, the first touch trace extends in the same direction as the first signal line, allowing them to be placed on the same layer to reduce manufacturing costs. Alternatively, the first touch trace can be a separate layer. The second touch trace extends in the same direction as the second signal line, also allowing them to be placed on the same layer to reduce manufacturing costs. This array substrate not only achieves electromagnetic touch functionality, enabling products to have finer handwriting and faster response speeds, but also reduces the number of mask layers required, simplifying the manufacturing process and saving manufacturing costs.

[0009] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0010] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0011] Figure 1 A schematic diagram of an array substrate provided in this application; Figure 2 for Figure 1 A cross-sectional view along P-P'; Figure 3 for Figure 1 Another sectional view along P-P'; Figure 4 A schematic diagram of the structure of a first touch coil and a second touch coil in an array substrate provided in this application; Figure 5 A schematic diagram of a first structure of a first touch coil in an array substrate provided in this application; Figure 6 This application provides a schematic diagram of a second structure of a first touch coil in an array substrate. Figure 7 A schematic diagram of a first structure of a second touch coil in an array substrate provided in this application; Figure 8 This application provides a schematic diagram of a second structure of a second touch coil in an array substrate. Figure 9 This application provides a schematic diagram of a driving method in an array substrate. Figure 10 A schematic diagram of a third structure of a first touch coil in an array substrate provided in this application; Figure 11 A schematic diagram of a third structure of a second touch coil in an array substrate provided in this application; Figure 12 This application provides a schematic diagram of another driving method in an array substrate. Figure 13 for Figure 1 A sectional view along line B-B'; Figure 14 This application provides a schematic diagram of a fourth structure of a first touch coil in an array substrate. Figure 15 This application provides a schematic diagram of a fourth structure of a second touch coil in an array substrate. Figure 16 This is a schematic diagram of the structure of a display panel provided in this application.

[0012] Explanation of reference numerals in the attached figures: 1. Array substrate; 10. Substrate; 11. First electrode; 111. First electrode row; 112. First electrode column; 12. First conductive layer; 121. First signal line; 122. Gate; 13. Second conductive layer; 131. Second signal line; 132. Source electrode; 14. Third conductive layer; 15. First touch coil; 151. First touch trace; 152. First connecting wire; 16. Second touch coil; 161. Second touch trace; 162. Second connecting wire; 17. Second electrode; 18. Gate insulating layer; 19. First insulating layer; 20. Fourth insulating layer; 21. First common signal line; 22. Second common signal line; 23. Third connecting line; 24. Driver module; 25. Via; AA, Region 1; NA, Region 2; NA1, First Division; NA2, Second Division; NA3, Third Division; NA4, Fourth Division; NA5, Fifth Division; NA6, Sixth Division; 2. Display panel; 3. Color filter substrate; 31. Substrate layer; 32. Color filter part; 33. Light shielding part; 4. Liquid crystal layer; x, first direction; y, second direction. Detailed Implementation

[0013] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0014] Figure 1 This is a schematic diagram of an array substrate.

[0015] like Figures 1 to 4 As shown, this application provides an array substrate 1, which includes a substrate 10, a first signal line 121, a second signal line 131, a first touch trace 151, and a second touch trace 161. The first signal line 121 is located on one side of the substrate 10 and extends along a first direction x. The second signal line 131 is located on the side of the first signal line 121 opposite to the substrate 10 and extends along a second direction y, which intersects with the first direction x. Figure 4 As shown, the first touch trace 151 extends along the first direction x, and multiple first touch traces 151 form a group of first touch coils 15. Figure 2 As shown, the first touch trace 151 and the first signal line 121 are arranged on the same layer, or, as... Figure 3 As shown, the first touch trace 151 is located on the side of the second signal line 131 facing away from the substrate 10. Figure 4 As shown, the second touch trace 161 extends along the second direction y, and multiple second touch traces 161 form a group of second touch coils 16. The second touch trace 161 and the second signal line 131 are arranged on the same layer.

[0016] In the array substrate 1 provided in this application, the first touch trace 151 and the second touch trace 161 form an electromagnetic touch module. The array substrate 1 integrates the electromagnetic touch module internally, thereby realizing electromagnetic touch functionality. The electromagnetic touch module can cooperate with an electromagnetic pen to achieve touch control and display. Specifically, the first touch trace 151 extends in the same direction as the first signal line 121, allowing the first touch trace 151 and the first signal line 121 to be placed on the same layer to reduce manufacturing costs. Alternatively, the first touch trace 151 can be a separate layer. The second touch trace 161 extends in the same direction as the second signal line 131, allowing the second touch trace 161 and the second signal line 131 to be placed on the same layer to reduce manufacturing costs. This array substrate 1 not only realizes the electromagnetic touch function, enabling products to have finer handwriting and faster response speeds, but also reduces the number of mask layers required, helping to simplify the manufacturing process and save manufacturing costs.

[0017] In the above embodiments, the first direction x and the second direction y can be perpendicular to each other.

[0018] In one feasible embodiment, the array substrate 1 includes a first conductive layer 12, a semiconductor layer (not shown), and a second conductive layer 13 sequentially stacked along a direction away from the substrate 10. The array substrate 1 includes a transistor, which includes a gate (not shown), a semiconductor portion (not shown), a source (not shown), and a drain (not shown). Taking a bottom-gate structure transistor as an example, the gate is located in the first conductive layer 12, the semiconductor portion is located in the semiconductor layer, and the source and drain are located in the second conductive layer 13.

[0019] Specifically, the first conductive layer 12 and the second conductive layer 13 may both be made of metal. Metals have low impedance and better conductivity, which helps to improve the performance of the transistor and the overall performance of the array substrate 1. The semiconductor layer may be made of polycrystalline silicon or oxide semiconductor materials.

[0020] Specifically, the transistor adopts a bottom-gate structure, with the gate located below the semiconductor section and the source and drain located above the semiconductor section.

[0021] The array substrate 1 also includes a gate insulating layer 18, which is located between the first conductive layer 12 and the semiconductor layer.

[0022] The first signal line 121 is located in the first conductive layer 12. The first signal line 121 can be a gate line, i.e., a scan line, and the gate line is connected to the gate electrode. The second signal line 131 is located in the second conductive layer 13. The second signal line 131 can be a data line and can be connected to the source electrode. The second touch trace 161 is located in the second conductive layer 13, so the second touch trace 161 and the second signal line 131 can be fabricated simultaneously, saving one mask process.

[0023] In one feasible implementation, such as Figure 2 As shown, the first touch trace 151 is located in the first conductive layer 12. The first touch trace 151 and the first signal line 121 can be fabricated using the same process, saving one mask process. The first touch trace 151 and the first signal line 121 are spaced apart, and the orthographic projection of the first touch trace 151 on the substrate 10 does not overlap with the orthographic projection of the first signal line 121 on the substrate 10.

[0024] Alternatively, in another feasible implementation, such as Figure 3As shown, the array substrate 1 further includes a third conductive layer 14, which is located on the side of the second conductive layer 13 facing away from the substrate 10. The first touch trace 151 is located on the third conductive layer 14. In this embodiment, the first touch trace 151 is located on a separate film layer and is not shared with the film layer of the transistor. Since the first touch trace 151 is disposed on a different film layer from the other film layers, the wiring of the first touch trace 151 is more convenient. The orthographic projection of the first touch trace 151 on the substrate 10 and the orthographic projection of the first signal line 121 on the substrate 10 may or may not overlap.

[0025] Specifically, the material of the third conductive layer 14 includes metal.

[0026] In one feasible implementation, such as Figures 4 to 6 As shown, the array substrate 1 also includes a first connecting line 152, which extends along the second direction y. The first connecting line 152 is disposed on the same layer as the second signal line 131. Multiple first touch traces 151 in the first touch coil 15 are connected through multiple first connecting lines 152.

[0027] In the above embodiments, since the different first touch lines 151 are spaced apart and arranged in parallel, the different first touch lines 151 are not directly connected. The different first touch lines 151 are connected through the first connecting line 152 to form the first touch coil 15.

[0028] Specifically, such as Figure 5 As shown, multiple first touch traces 151 within the first touch coil 15 are connected in parallel via a first connecting line 152. The first ends of the multiple first touch traces 151 within the first touch coil 15 are connected to the same first connecting line 152, and the second ends of the multiple first touch traces 151 are connected to another first connecting line 152. Alternatively, as... Figure 6 As shown, multiple first touch traces 151 within the first touch coil 15 are connected in series via a first connecting line 152.

[0029] When multiple first touch lines 151 are connected in parallel through the first connecting line 152, each group of first touch coils 15 includes multiple first touch lines 151 arranged along the second direction y. Adjacent first touch lines 151 are spaced apart, and the multiple first touch lines 151 in each group are connected in parallel with each other. A closed coil Q can be formed between each two adjacent first touch lines 151. Each group of first touch coils 15 includes multiple coils Q arranged along the second direction y.

[0030] Specifically, such as Figure 5As shown, each group of first touch coils 15 may include two first connecting lines 152. One first connecting line 152 is connected to the first end of each first touch trace 151 within the group of first touch coils 15, and the other first connecting line 152 is connected to the second end of each first touch trace 151 within the group of first touch coils 15. This allows each pair of adjacent first touch traces 151 and the two first connecting lines 152 to form a closed coil Q. When the number of first touch traces 151 in each group of first touch coils 15 is m, the number of closed coils Q formed by each pair of adjacent first touch traces 151 and the two first connecting lines 152 is m-1. These m-1 coils Q are arranged along the second direction y.

[0031] like Figure 6 As shown, when multiple first touch traces 151 within the first touch coil 15 are connected in series via first connecting lines 152, the first touch coil 15 includes a non-closed coil, meaning that multiple first touch traces 151 connected in series via multiple first connecting lines 152 form a wound coil. Two of the multiple first touch traces 151 within the first touch coil 15 have free ends E, meaning that free ends E are not connected to other first touch traces 151 or to the first connecting lines 152, thus preventing the first touch coil 15 from forming a closed structure. The free ends E are subsequently connected to other structures within the array substrate 1.

[0032] Specifically, in the series implementation, the number of first touch traces 151 within the first touch coil 15 is the number of first connecting lines 152 plus 1.

[0033] In the above embodiment, the first connecting line 152 and the first touch trace 151 are disposed on different layers and connected through a via 25. The first connecting line 152 is used to connect multiple first touch traces 151. By setting the first touch coil 15 to include the first connecting line 152 and the first touch trace 151 that are connected across layers, it helps to save a lot of space in the wiring, thereby enabling the first touch coil 15 to be fabricated through existing film layers, reducing the number of masking steps and the number of film layers, thereby helping to reduce the fabrication cost and the thickness of the array substrate 1.

[0034] In the above embodiments, the first touch trace 151 is located in the first conductive layer 12 or the third conductive layer 14, and the first connecting line 152 is located in the second conductive layer 13. Regardless of whether the first touch trace 151 is located in the first conductive layer 12 or the third conductive layer 14, it is connected through the first connecting line 152 located in the second conductive layer 13.

[0035] In one feasible implementation, such as Figure 4 , Figure 7 and Figure 8As shown, the array substrate 1 also includes a second connection line 162. The second connection line 162 extends along the first direction x. The second connection line 162 is disposed in the same layer as the first signal line 121. Alternatively, the second connection line 162 is located on the side of the second signal line 131 away from the substrate 10. Multiple second touch traces 161 in the second touch coil 16 are connected through multiple second connection lines 162.

[0036] In the above embodiments, the second connecting line 162 extends along the first direction x. Since the first signal line 121 extends along the first direction x, the second connecting line 162 and the first signal line 121 can be disposed on the same layer. Alternatively, when the array substrate 1 includes a third conductive layer 14, that is, when the first touch trace 151 is located on the side of the second signal line 131 away from the substrate 10, the second connecting line 162 can be located in the third conductive layer 14.

[0037] In the above embodiments, such as Figure 7 As shown, multiple second touch traces 161 within the second touch coil 16 are connected in parallel via a second connecting line 162. The first ends of the multiple second touch traces 161 within the second touch coil 16 are connected to the same second connecting line 162, and the second ends of the multiple second touch traces 161 are connected to another second connecting line 162. Alternatively, the multiple second touch traces 161 within the second touch coil 16 are connected in series via the second connecting line 162.

[0038] Specifically, such as Figure 7 As shown, when multiple second touch lines 161 are connected in parallel through the second connecting line 162, each group of second touch coils 16 includes multiple second touch lines 161 arranged along the first direction x. Adjacent second touch lines 161 are spaced apart, and the multiple second touch lines 161 in each group are connected in parallel with each other. A closed coil Q can be formed between each two adjacent and connected second touch lines 161. Each group of second touch coils 16 includes multiple coils Q arranged along the first direction x.

[0039] Specifically, each group of second touch coils 16 may include two second connecting lines 162. One second connecting line 162 is connected to the first end of each second touch trace 161 within the group of second touch coils 16, and the other second connecting line 162 is connected to the second end of each second touch trace 161 within the group of second touch coils 16, thereby enabling each pair of adjacent second touch traces 161 and the two second connecting lines 162 to jointly form a closed coil Q. When the number of second touch traces 161 in each group of second touch coils 16 is n, the number of closed coils Q formed by each pair of adjacent second touch traces 161 and the two second connecting lines 162 is n-1, and these n-1 coils are arranged along the first direction x.

[0040] like Figure 8 As shown, when multiple second touch traces 161 within the second touch coil 16 are connected in series via second connecting lines 162, the second touch coil 16 includes a non-closed coil, meaning that multiple second touch traces 161 connected in series via multiple second connecting lines 162 form a wound coil. Two of the multiple second touch traces 161 within the second touch coil 16 have free ends E, meaning that free ends E are not connected to other second touch traces 161 or to the second connecting lines 162, thus preventing the second touch coil 16 from forming a closed structure. The free ends E are subsequently connected to other structures within the array substrate 1.

[0041] Specifically, in the series implementation, the number of second touch traces 161 within the second touch coil 16 is the number of second connecting lines 162 plus one.

[0042] In the above embodiment, the second connecting line 162 and the second touch trace 161 are disposed on different layers and connected through the via 25. The second connecting line 162 is used to connect multiple second touch traces 161.

[0043] By configuring the second touch coil 16 in the form of a second connecting line 162 and a second touch trace 161 that are connected across layers, it helps to save a lot of space in the wiring, thereby enabling the second touch coil 16 to be fabricated through existing film layers, reducing the number of masking steps and film layers, which helps to reduce the fabrication cost and the thickness of the array substrate 1.

[0044] In the above embodiments, the second touch trace 161 is located in the second conductive layer 13, and the first connecting line 152 is located in the first conductive layer 12 or the third conductive layer 14. The second touch trace 161 located in the second conductive layer 13 or the third conductive layer 14 is connected by the second connecting line 162 located in the first conductive layer 12 or the third conductive layer 14. In one feasible embodiment, when multiple first touch traces 151 within the first touch coil 15 are connected in parallel via the first connecting line 152, multiple second touch traces 161 within the second touch coil 16 are connected in parallel or in series via the second connecting line 162; when multiple first touch traces 151 within the first touch coil 15 are connected in series via the first connecting line 152, multiple second touch traces 161 within the second touch coil 16 are connected in parallel or in series via the second connecting line 162. The above can be configured according to actual needs.

[0045] In one feasible implementation, such as Figure 2 , Figure 3 and Figure 9 As shown, the array substrate 1 also includes a plurality of first electrodes 11, which are arranged in an array along a first direction x and a second direction y.

[0046] Specifically, the first electrode 11 can be a pixel electrode, and the first electrode 11 corresponds one-to-one with the sub-pixels in the array substrate 1.

[0047] In one feasible implementation, the orthographic projection of the first touch trace 151 on the substrate 10 does not overlap with the orthographic projection of the first electrode 11 on the substrate 10, and the orthographic projection of the second touch trace 161 on the substrate 10 does not overlap with the orthographic projection of the first electrode 11 on the substrate 10.

[0048] In the above embodiment, a portion of the orthographic projection of the first touch trace 151 and the second touch trace 161 on the substrate 10 is located between adjacent first electrodes 11, and the other portion is located outside all the first electrodes 11. That is, the orthographic projection of the first touch trace 151 and the second touch trace 161 on the substrate 10 does not overlap with the orthographic projection of the first electrode 11 on the substrate 10, so that the arrangement of the first touch trace 151 and the second touch trace 161 will not affect the transmittance of the array substrate 1 and the subsequent display effect.

[0049] In the above embodiments, the first electrode 11 is made of a transparent conductive layer material. Specifically, it may include indium tin oxide or indium zinc oxide, etc.

[0050] In the above embodiments, the first electrode 11 may be located on the side of the second conductive layer 13 away from the substrate 10, that is, the first electrode 11 is prepared after the second conductive layer 13.

[0051] In one feasible implementation, such as Figure 9 As shown, the array substrate 1 includes a first electrode row 111 and a first electrode column 112. The first electrode row 111 includes a plurality of first electrodes 11 arranged along a first direction x, and the first electrode column 112 includes a plurality of first electrodes 11 arranged along a second direction y. In the array substrate 1, the number of first touch traces 151 is a positive integer multiple of the number of first electrode rows 111, and / or, the number of second touch traces 161 is a positive integer multiple of the number of first electrode columns 112.

[0052] In the above embodiment, the orthographic projection of the first touch trace 151 on the substrate 10 lies between the orthographic projections of adjacent first electrode rows 111 on the substrate 10. The region between each pair of adjacent first electrode rows 111 corresponds to one or more sets of first touch coils 15, and one or more first touch traces 151 in each set of first touch coils 15 are located within this region. Therefore, the number of first touch traces 151 can be the same as the number of first electrode rows 111, or the number of first touch traces 151 can be X1 times the number of first electrode rows 111, where X1 is a positive integer greater than or equal to 2. Figure 10 As shown, Figure 10The solid lines represent the first touch traces 151 and the first connecting lines 152 in one set of first touch coils 15, while the dashed lines represent the first touch traces 151 and the first connecting lines 152 in another set of first touch coils 15. The solid and dashed lines are staggered, and the spacing between the solid lines and adjacent dashed lines is smaller than the spacing between adjacent first electrode rows 111. This allows for one solid line and one dashed line to be provided between adjacent first electrode rows 111, meaning that the number of first touch traces 151 is twice the number of first electrode rows 111.

[0053] In the above embodiment, the orthographic projection of the second touch trace 161 on the substrate 10 lies between the orthographic projections of adjacent first electrode columns 112 on the substrate 10. The region between each pair of adjacent first electrode columns 112 corresponds to one or more sets of second touch coils 16, and one or more second touch traces 161 in each set of second touch coils 16 are located within this region. Therefore, the number of second touch traces 161 can be the same as the number of rows of second electrodes 17, or the number of second touch traces 161 can be twice the number of first electrode columns 112, where x2 is a positive integer greater than or equal to 2.

[0054] like Figure 11 As shown, Figure 11 The solid lines represent the second touch traces 161 and second connecting lines 162 in one set of second touch coils 16, while the dashed lines represent the second touch traces 161 and second connecting lines 162 in another set of second touch coils 16. The solid and dashed lines are staggered, and the spacing between the solid lines and adjacent dashed lines is smaller than the spacing between adjacent first electrode columns 112. This allows for one solid line and one dashed line to be provided between adjacent first electrode columns 112, meaning the number of first touch traces 151 is twice the number of first electrode columns 112.

[0055] like Figure 12 As shown, the array substrate 1 provided in this application can adopt a Single Gate design (one first electrode row 111 is driven by one scan line). It uses two data lines (i.e., second signal lines 131) to transmit drive signals to two adjacent first electrode columns 112. That is, by halving the number of scan lines (i.e., first signal lines 121), the number of IC channels can be reduced. When the first touch trace 151 and the first signal line 121 are disposed on the same layer, reducing the number of first signal lines 121 can increase the density and number of the first touch trace 151, thereby reducing the resistance of the first touch trace 151.

[0056] Or, such as Figure 9As shown, the array substrate 1 provided in this application can adopt a Dual Gate design (one first electrode row 111 is driven by two scan lines). A single data line (i.e., the second signal line 131) is used to transmit drive signals to two adjacent first electrode columns 112. This reduces the number of IC channels by halving the number of data lines. Placing the second touch trace 161 and the second signal line 131 on the same layer increases the density and number of the second touch trace 161 and reduces its resistance by reducing the number of second signal lines 131.

[0057] In one feasible implementation, in the array substrate 1, a plurality of first touch coils 15 are arranged sequentially along the second direction y, and / or a plurality of second touch coils 16 are arranged sequentially along the first direction x.

[0058] In the above embodiment, the first touch trace 151 extends from one end of the first electrode row 111 to the other end, so that the plurality of first touch coils 15 are arranged sequentially along the second direction y, thereby ensuring that the distribution range of the first touch trace 151 covers the entire area where the first electrode 11 is located. The second touch trace 161 extends from one end of the first electrode array 112 to the other end, so that the plurality of second touch coils 16 are arranged sequentially along the first direction x, thereby ensuring that the distribution range of the second touch trace covers the entire area where the first electrode 11 is located. This achieves good touch functionality.

[0059] Specifically, the distance D1 between the outer edges of the two parallel first touch traces 151 at both ends of each first touch coil 15 ranges from 5.8 mm to 6.2 mm, and the distance D2 between the outer edges of the two parallel second touch traces 161 at both ends of each second touch coil 16 ranges from 5.8 mm to 6.2 mm. This ensures touch accuracy while reducing wiring complexity.

[0060] In one feasible implementation, such as Figure 13 As shown, the array substrate 1 includes a first region AA and a second region NA. The second region NA includes a first partition NA1, a second partition NA2, a third partition NA3 and a fourth partition NA4 nested sequentially outside the first region AA. The first electrode 11 is located in the first region AA. The first touch trace 151 is located in the first region AA, the first partition NA1 and the second partition NA2. The second touch trace 161 is located in the first region AA, the first partition NA1 and the second partition NA2.

[0061] Specifically, in the second region NA, the first partition NA1 is adjacent to the first region AA, and the first partition NA1 is arranged around at least a portion of the first region AA. The second partition NA2 is adjacent to the first partition NA1, and the second partition NA2 is located on the side of the first partition NA1 away from the first region AA, and the second partition NA2 is arranged around at least a portion of the first partition NA1. The third partition NA3 is adjacent to the second partition NA2, and the third partition NA3 is located on the side of the second partition NA2 away from the first region AA, and the third partition NA3 is arranged around at least a portion of the second partition NA2. The fourth partition NA4 is adjacent to the third partition NA3, and the fourth partition NA4 is located on the side of the third partition NA3 away from the first region AA.

[0062] In the above embodiment, the distribution range of the first touch trace 151 (first region AA, first partition NA1 and second partition NA2) is larger than the distribution range of the first electrode 11 (first region AA) to ensure the touch effect of the peripheral area of ​​the first region AA of the array substrate 1. Specifically, the width L between the edge of the third partition NA3 away from the first region AA and the first region AA ranges from 2.9mm to 3.1mm.

[0063] When the width L between the edge of the third partition NA3 furthest from the first region AA and the first region AA is too small, the touch effect of the peripheral area of ​​the first region AA of the array substrate 1 is easily poor; when the width L between the edge of the third partition NA3 furthest from the first region AA and the first region AA is too large, the peripheral area of ​​the first region AA of the array substrate 1 is easily too wide, which is not conducive to achieving a narrow bezel. Setting the width L between the edge of the third partition NA3 furthest from the first region AA and the first region AA to a range of 2.9mm-3.1mm can ensure the distribution range of the first touch coil 15 and the second touch coil 16, thereby improving the touch effect of the peripheral area of ​​the first region AA of the array substrate 1.

[0064] Specifically, the average value of the width L between the edge of the third partition NA3 away from the first region AA and the first region AA can be 2.9mm-3.1mm, and the width L can be different at different positions.

[0065] like Figure 14 and Figure 15As shown, the array substrate 1 also includes a third connection line 23, a first common signal line 21, a second common signal line 22, and a driving module 24. The third connection line 23 and the driving module 24 are located in the third partition NA3, and the first common signal line 21 and the second common signal line 22 are located in the fourth partition NA4. The third connection line 23 is used to connect the first touch coil 15 and the driving module 24. The first touch trace 151 is connected to the first common signal line 21, and the second touch trace 161 is connected to the second common signal line 22.

[0066] Specifically, the first common signal line 21 and the second common signal line 22 are low-level signal lines, which can realize the grounding of the first electromagnetic coil and the second electromagnetic coil.

[0067] The first touch coil 15 and the second touch coil 16 are respectively connected to the driving module 24 so that the driving module 24 can identify and locate the first touch coil 15 and the second touch coil 16, thereby realizing accurate touch function.

[0068] The first touch coil 15 is connected to the driving module 24 via a third connecting line 23. The third connecting line 23 can be arranged on the same layer as the first touch trace 151, or on the same layer as the first common signal line 21, or on the same layer as both the first touch trace 151 and the first common signal line 21. The first touch coil 15 can be connected to the first common signal line 21 via the third connecting line 23 to achieve grounding.

[0069] The second touch coil 16 can be directly connected to the driving module 24. Alternatively, the third partition NA3 also includes a fourth connecting line (not shown in the figure), which is used to connect the second touch coil 16 to the driving module 24. The fourth connecting line can be arranged on the same layer as the second touch trace 161. Alternatively, the fourth connecting line is also used to connect the second touch trace 161 to the second common signal line 22. The fourth connecting line can be arranged on the same layer as the second common signal line 22. Or, the fourth connecting line can be arranged on the same layer as both the second touch trace 161 and the second common signal line 22.

[0070] In one feasible implementation, the second region NA further includes a fifth region NA5 located on the side of the fourth region NA4 away from the first region AA, and a sixth region NA6 located on the side of the fifth region NA5 away from the first region AA. The fourth region NA4 includes a driving circuit (GOA driving circuit, not shown in the figure), which is connected to the structures (transistor, first signal line 121 and second signal line 131) within the first region AA to drive the first electrode 11. Specifically, the first signal line 121 can extend from the first region AA to the fifth region NA5 and be connected to the driving circuit. The second signal line 131 can be connected to the driving circuit via a connecting line. The connecting line does not interfere with the first touch trace 151, the second touch trace 161, the first connecting line 152, the second connecting line 162, the third connecting line 23, and the fourth connecting line.

[0071] The sixth partition NA6 can be a sealed area to prevent water and oxygen from corroding the internal structure of the array substrate 1.

[0072] In one feasible implementation, such as Figure 2 and Figure 3 As shown, the array substrate 1 also includes a second electrode 17, which is located on the side of the second signal line 131 away from the substrate 10, and is located in the first partition NA1 and the second partition NA2.

[0073] In the above embodiments, the second electrode 17 can be disposed on its entire surface and cover the first partition NA1 and the second partition NA2, and the second electrode 17 can be a common electrode. Alternatively, the second electrode 17 can also be a strip electrode.

[0074] Specifically, the second electrode 17 is made of a transparent conductive material, such as indium tin oxide or indium zinc oxide.

[0075] Specifically, such as Figure 2 and Figure 3 As shown, the array substrate 1 also includes a first insulating layer 19 located between the second conductive layer 13 and the second electrode 17, and the first insulating layer 19 is in contact with the second conductive layer 13.

[0076] In one feasible implementation, such as Figure 3 As shown, when the second touch trace 161 is located on the side of the second signal line 131 away from the substrate 10, the second touch trace 161 is located on the side of the second electrode 17 away from the substrate 10.

[0077] Specifically, when the array substrate 1 includes a third conductive layer 14, the second electrode 17 is located on the side of the third conductive layer 14 facing away from the substrate 10, such as... Figure 3 As shown, a second insulating layer 20 is also provided between the second electrode 17 and the third conductive layer 14, and the second insulating layer 20 is in contact with the third conductive layer 14.

[0078] This application also provides a display panel 2, such as Figure 16 As shown, it includes any one of the array substrates 1 provided in the above embodiments.

[0079] The display panel 2 integrates electromagnetic touch functionality, providing finer handwriting and faster response speed. Additionally, manufacturing costs can be reduced by placing the first touch trace 151 and the first signal line 121 on the same layer, and / or by placing the second touch trace 161 and the second signal line 131 on the same layer.

[0080] Specifically, the display panel 2 may be a liquid crystal display panel 2, and the display panel 2 may also include a liquid crystal layer 4 and a color filter substrate 3. The color filter substrate 3 is disposed opposite to the array substrate 1, and the liquid crystal layer 4 is located between the color filter substrate 3 and the array substrate 1.

[0081] Specifically, the color filter substrate 3 includes a substrate 10 layer and a color filter functional layer located on one side of the substrate 10 layer. The color filter functional layer includes a color filter portion 32 and a light-shielding portion 33 located between the color filter portions 32. The color filter portion 32 corresponds to the first electrode 11, that is, the orthographic projection of the color filter portion 32 on the substrate 10 and the orthographic projection of the first electrode 11 on the substrate 10 overlap at least partially. At least a portion of the orthographic projection of the first touch trace 151 on the substrate 10 is located within the orthographic projection of the light-shielding portion 33 on the substrate 10, and at least a portion of the orthographic projection of the second touch trace 161 on the substrate 10 is located within the orthographic projection of the light-shielding portion 33 on the substrate 10, thereby reducing the impact on the display effect.

[0082] In an exemplary embodiment, the first insulating layer 19, the second insulating layer 20, and the gate insulating layer 18 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The first conductive layer 12, the second conductive layer 13, and the third conductive layer 14 may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The semiconductor layer may be made of amorphous indium gallium zinc oxide (a IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a Si), polycrystalline silicon (p Various materials such as Si, hexathiophene, and polythiophene, that is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0083] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display device, which includes any of the display panels 2 provided in the above embodiments.

[0084] Specifically, the display device can be a drawing tablet, e-book, e-paper, mobile phone, tablet computer, television, monitor, laptop computer, or other products or components with display and touch functions.

[0085] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0086] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0087] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0088] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0089] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0090] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure. Different parts of different embodiments can be combined with each other without conflict, and these should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A first signal line is located on one side of the substrate and extends along a first direction; The second signal line is located on the side of the first signal line away from the substrate, and the second signal line extends along a second direction, which intersects with the first direction; The first touch trace extends along the first direction, and multiple first touch traces form a group of first touch coils. The first touch trace is disposed on the same layer as the first signal line, or the first touch trace is located on the side of the second signal line away from the substrate. The second touch trace extends along the second direction, and multiple second touch traces form a group of second touch coils. The second touch traces are arranged on the same layer as the second signal lines.

2. The array substrate according to claim 1, characterized in that, The array substrate further includes a first connecting line, which extends along the second direction and is disposed on the same layer as the second signal line. Multiple first touch traces within the first touch coil are connected through multiple first connecting lines.

3. The array substrate according to claim 2, characterized in that, Multiple first touch traces within the first touch coil are connected in parallel via the first connecting line. The first ends of these multiple first touch traces are connected to the same first connecting line, and the second ends of these multiple first touch traces are connected to another first connecting line; or... Multiple first touch traces within the first touch coil are connected in series via the first connecting line.

4. The array substrate according to claim 1, characterized in that, The array substrate further includes a second connecting line, which extends along the first direction. The second connecting line is disposed on the same layer as the first signal line, or the second connecting line is located on the side of the second signal line away from the substrate. Multiple second touch traces in the second touch coil are connected through multiple second connecting lines.

5. The array substrate according to claim 4, characterized in that, Multiple second touch traces within the second touch coil are connected in parallel via the second connecting line. The first ends of these multiple second touch traces are connected to the same second connecting line, and the second ends of these multiple second touch traces are connected to another second connecting line; or... Multiple second touch traces within the second touch coil are connected in series via the second connecting line.

6. The array substrate according to claim 1, characterized in that, The array substrate further includes a plurality of first electrodes, which are arranged in an array along the first direction and the second direction; The orthographic projection of the first touch trace on the substrate does not overlap with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second touch trace on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

7. The array substrate according to claim 6, characterized in that, The array substrate includes a first electrode row and a first electrode column, the first electrode row including a plurality of first electrodes arranged along a first direction, and the first electrode column including a plurality of first electrodes arranged along a second direction; The number of the first touch traces is a positive integer multiple of the number of the first electrode rows, and / or the number of the second touch traces is a positive integer multiple of the number of the first electrode columns.

8. The array substrate according to claim 6, characterized in that, In the array substrate, a plurality of first touch coils are arranged sequentially along the second direction, and / or a plurality of second touch coils are arranged sequentially along the first direction.

9. The array substrate according to claim 6, characterized in that, The array substrate includes a first region and a second region. The second region includes a first partition, a second partition, a third partition, and a fourth partition nested sequentially outside the first region. The first electrode is located in the first region. The first touch trace is located in the first region, the first partition, and the second partition. The second touch trace is located in the first region, the first partition, and the second partition. The array substrate further includes a third connecting line, a first common signal line, a second common signal line, and a driving module. The third connecting line and the driving module are located in the third partition, and the first common signal line and the second common signal line are located in the fourth partition. The third connecting line is used to connect the first touch coil and the driving module. The first touch trace is connected to the first common signal line, and the second touch trace is connected to the second common signal line.

10. The array substrate according to claim 9, characterized in that, The array substrate further includes a second electrode located on the side of the second signal line away from the substrate, and the second electrode is located in the first partition and the second partition.

11. The array substrate according to claim 10, characterized in that, When the second touch trace is located on the side of the second signal line away from the substrate, the second touch trace is located on the side of the second electrode away from the substrate.

12. The array substrate according to claim 9, characterized in that, The width between the edge of the third partition away from the first region and the first region ranges from 2.9mm to 3.1mm.

13. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 12.

14. The display panel according to claim 13, characterized in that, It also includes a liquid crystal layer and a color filter substrate, wherein the color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located between the color filter substrate and the array substrate.

15. A display device, characterized in that, Includes the display panel as described in claim 13 or 14.

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