Three-dimensional stacked memory based on storage and calculation integration and distributed interface

Abstract

The invention relates to a three-dimensional stacked memory based on storage and calculation integration and a distributed interface, and the memory comprises a calculation chip which is used for executing a calculation task; the storage chip comprises a plurality of independent addressing storage spaces; the distributed interface is integrated with the computing chip by adopting a three-dimensional stacking packaging technology to form a three-dimensional integrated high-speed channel, and the three-dimensional integrated high-speed channel comprises a plurality of independent distributed interfaces; the computing chip accesses the plurality of independent addressing storage spaces in parallel through the plurality of independent distributed interfaces; a data interaction sampling mechanism of the computing chip and the storage chip comprises at least one of asynchronous data interaction based on delay time sequence information, asynchronous data interaction based on data effective signals and synchronous data interaction based on clocks, and the data interaction sampling mechanism can be used for sampling data according to requirements of application scenes on time sequence allowance, power consumption budget and design complexity. The most suitable communication mode is flexibly selected, or a composite scheme is adopted to optimize the energy efficiency in a distributed interface communication scene.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a three-dimensional stacked memory based on in-memory computing and a distributed interface. Background Technology

[0002] Memory typically consists of multiple storage spaces and interacts with each other through peripheral interface circuits. Traditional memory (such as DDR series) mainly relies on peripheral interface protocols defined by international standards (such as JEDEC) to sequentially access the internal storage space through command addressing (specifying the storage space, row, and column address) by an external controller.

[0003] With the development of semiconductor technology, three-dimensional stacked memory has emerged. This architecture utilizes advanced packaging technology to integrate computing chips and memory chips vertically, enabling computing chips to access multiple internal memory spaces in parallel and distributed ways, thereby significantly improving data transmission bandwidth and alleviating the "memory wall" problem.

[0004] However, existing international or national standard protocols mainly target the peripheral interface circuits of traditional memories and do not specify the interconnect interfaces of the internal storage space of 3D stacked memories. Directly using the existing interfaces within traditional memories, due to their lack of optimization for distributed memory access characteristics (such as high concurrency and short paths), will lead to low memory access efficiency and fail to fully leverage the performance advantages of the 3D stacked architecture. Therefore, a dedicated storage space interface protocol for 3D stacked memories is urgently needed. Summary of the Invention

[0005] To address the above problems, embodiments of this application provide a three-dimensional stacked memory based on in-memory computing and a distributed interface, comprising: Computing chips are used to perform computing tasks; The memory chip contains multiple independently addressable memory spaces; it is integrated with the computing chip using a three-dimensional stacking packaging technology to form a three-dimensional integrated high-speed channel, the three-dimensional integrated high-speed channel including multiple independent distributed interfaces; The computing chip accesses the multiple independently addressed storage spaces in parallel through the multiple independent distributed interfaces, and the data interaction sampling mechanism between the computing chip and the storage chip includes at least one of the following: Asynchronous data interaction based on delay timing information, asynchronous data interaction based on valid data signals, and synchronous data interaction based on clocks.

[0006] This application improves memory access parallelism and overall system bandwidth through a three-dimensional stacking and distributed access architecture. Its data interaction sampling mechanism is flexible and adaptable, and can be flexibly switched between different mechanisms based on the application scenario.

[0007] Optionally, the data interaction between the computing chip and the storage chip includes read operations and write operations, and the data interaction sampling mechanisms of the read operations and the write operations may be the same or different.

[0008] Optionally, the asynchronous data interaction based on delay timing information includes: In a write operation, the computing chip sends data sequentially according to the timing requirements of the storage chip, without transmitting a write clock signal or a write data valid signal; In a read operation, the computing chip samples the read data according to fixed delay timing requirements, without relying on a read clock signal or a read data valid signal.

[0009] This design eliminates the power consumption of clock and handshake signal switching, reduces the occupation of TSV connections in three-dimensional stacked distributed application scenarios, and achieves lower interconnection overhead under the premise of controllable timing.

[0010] Optionally, the asynchronous data interaction based on the data valid signal includes: in a write operation, the computing chip synchronously sends a write data valid signal to the storage chip, and the storage chip performs data sampling in response to the valid level of the signal; in a read operation, the storage chip feeds back a read data valid signal synchronized with the read data to the computing chip, and the computing chip performs data sampling in response to the valid level of the signal.

[0011] This design achieves data synchronization through handshake signals (valid signals), reducing the dependence on the global clock tree and the strict timing alignment requirements, and improving the reliability of data transmission in a distributed architecture.

[0012] Optionally, the clock-based synchronous data interaction includes: in both write and read operations, the sending and receiving of data are synchronized with the edge of the clock signal; the source of the clock signal includes: a new clock generated by the memory chip, a clock fed back by the memory chip that is from the same source as the computing chip, or a synchronous clock forwarded by the memory chip.

[0013] This design, utilizing a synchronous clock mechanism, simplifies data alignment logic, supports higher frequency data transmission, and is suitable for application scenarios with extremely high bandwidth and latency requirements.

[0014] Optionally, the key interface signals of the multiple independent distributed interfaces include: activation, precharge, and request signals for read and write operations, respectively; address signals containing the storage space and its row and column information; data signals containing data content and ECC verification information; and timing control, data validity, or clock signals that match the selected data communication method.

[0015] Optionally, the read address signal and the write address signal share the same set of physical transmission lines; and a single address signal, through encoding or time-division multiplexing, simultaneously contains at least two of the following: storage space address, storage space row address, and storage space column address information.

[0016] This design, through high address signal multiplexing, significantly reduces the number of through-silicon vias (TSVs) required for vertical stacking, thereby reducing chip manufacturing costs and wiring congestion.

[0017] Optionally, the read control interface and the write control interface are configured to share the same set of signal lines or two independent sets of signal lines; the read data interface and the write data interface are configured as two unidirectional transmission interfaces or share a bidirectional transmission port.

[0018] This design balances performance and area, making trade-offs between "high performance (independent interface / concurrent read and write)" and "low area (reused interface / reduced wiring)," thus enhancing the customization capabilities of the solution.

[0019] Optionally, the key interface signals also include auxiliary function signals: the auxiliary function signals include at least one of the following: a refresh signal for maintaining data retention characteristics; a register read / write signal for configuring interface parameters; and an interrupt signal for system reset and exception handling.

[0020] Optionally, it also includes an interface device, which is disposed on the storage chip or the computing chip and is used to interact with an external host device for data exchange.

[0021] Optionally, the three-dimensional stacked packaging technology includes at least one of the following: hybrid bonding, through-silicon vias, flip-chip and microbump connections.

[0022] In summary, the 3D stacked memory provided in this application offers a flexible interaction mechanism, balancing power consumption and performance by defining three optional data interaction sampling mechanisms (delay-based asynchronous, valid signal-based asynchronous, and clock-synchronized). Designers can flexibly choose the most suitable communication method based on the timing margin, power budget, and design complexity requirements of specific application scenarios, or adopt a composite solution (such as using different methods for reading and writing) to optimize system-level energy efficiency. Optimizing interconnect resources and reducing packaging costs: By standardizing the flexible multiplexing strategy of key interface signals (such as read / write address multiplexing, control signal multiplexing, and bidirectional data port configuration), the number of through-silicon vias (TSVs) required for 3D stacking can be effectively reduced while ensuring high performance, thereby reducing inter-chip wiring congestion and manufacturing costs. Attached Figure Description

[0023] Figure 1 According to some embodiments of this application, a schematic diagram of the internal storage space interface of a three-dimensional stacked memory is shown; Figure 2 According to some embodiments of this application, a schematic diagram of an interface protocol is shown; Figure 3 According to some embodiments of this application, a schematic diagram of an asynchronous data interaction method is shown; Figure 4 According to some embodiments of this application, a schematic diagram of an asynchronous data interaction method is shown; Figure 5 According to some embodiments of this application, a schematic diagram of a data synchronization interaction method based on a synchronous clock is shown; Figure 6 According to some embodiments of this application, a schematic diagram of a data synchronization interaction method based on an asynchronous clock is shown; Figure 7 According to some embodiments of this application, a schematic diagram of the implementation of key interface signals of a three-dimensional stacked memory is shown; Figure 8 According to some embodiments of this application, a schematic diagram of the structure of a digital in-memory computing unit of a computing chip is shown. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] As mentioned in the background, for example Figure 1 As shown, three-dimensional stacked memory achieves higher-density integration by vertically stacking memory chips on top of computing / logic chips, enabling the storage of more memory and logic chips within the same volume. The internal circuitry of a three-dimensional stacked memory typically consists of multiple storage spaces (also called memory banks), each of which can contain multiple storage arrays. These storage arrays are composed of arranged smallest storage cells used for actual data storage.

[0026] In some embodiments, the 3D stacked memory can be equipped with peripheral interface circuitry, allowing an external control terminal to precisely locate the storage space and access the data stored therein using command addressing. Command addressing may involve the external control terminal first determining the address of the storage space, then determining the row and column addresses, and finally identifying the storage cell. However, existing interface protocols are not suitable for the peripheral interface circuitry of the 3D stacked memory; that is, there is currently no protocol specification for the internal storage space interface of the 3D stacked memory. This results in low efficiency for data access and storage in the 3D stacked memory.

[0027] This embodiment provides a three-dimensional stacked memory based on in-memory computing and a distributed interface, such as... Figure 2 As shown, it includes: Computing chip 100 is used to perform computing tasks; The memory chip 200 is integrated with the computing chip 100 using three-dimensional stacking packaging technology to form a three-dimensional integrated high-speed channel, which contains multiple independently addressable memory spaces (also called memory blocks or memory banks). The computing chip 100 accesses one or more storage spaces in the storage chip 200 in a parallel manner through multiple independent distributed interfaces; The data interaction sampling mechanism between computing chip 100 and memory chip 200 includes at least one of the following: Asynchronous data interaction based on delay timing information, asynchronous data interaction based on valid data signals, and synchronous data interaction based on clocks.

[0028] This implementation defines the interface protocol for the storage space, including the data communication method specification that defines the data interaction sampling mechanism, and the key interface signal setting specification that defines the interface signal types and their combinations. The data interaction sampling mechanism can be selected from one or more of the following methods based on the application scenario: Asynchronous method based on delay timing information: The read and write process does not depend on the transmission clock signal or data valid signal, but only on the data sampling according to the fixed timing delay requirements; Asynchronous method based on data validity signal: The read / write process triggers data sampling by synchronously sending or receiving a data validity signal; and Clock synchronization method: Data transmission and reception during the read and write process are synchronized with the clock signal.

[0029] This implementation improves memory access parallelism and overall system bandwidth through a three-dimensional stacking and distributed access architecture. Its data interaction sampling mechanism is flexible and adaptable, and can be flexibly switched between different mechanisms based on the application scenario.

[0030] Optionally, the asynchronous mode based on delay timing information is configured as follows: in a write operation, the computing chip 100 sends data sequentially according to the timing requirements of the storage chip 200, and does not transmit a write clock signal or a write data valid signal; in a read operation, the computing chip 100 samples the read data according to fixed delay timing requirements, and does not depend on the read clock signal or the read data valid signal.

[0031] This design eliminates the power consumption of clock and handshake signal switching. In distributed application scenarios with three-dimensional stacking, the elimination of clock and handshake signal lines reduces the occupation of through-silicon via (TSV) interconnects, achieving lower interconnect overhead under the premise of controllable timing.

[0032] Specifically, refer to Figure 3 Taking data that may include data 1, data 2, and data 3 as an example, the asynchronous data interaction method based on delay timing information mentioned in the embodiments of this application will be described as follows: The data to be stored may include data 1, data 2, and data 3. When the computing chip 100 needs to write data to the storage chip 200, the computing chip 100 can send a storage request to the storage chip 200. The computing chip 100 may not need to transmit clock signals and / or data valid signals to the storage chip 200 simultaneously; it can simply output data signals and, according to the storage timing of the storage chip 200, send data 1, data 2, and data 3 sequentially to the write data interface. The storage chip 200 can then store data 1, data 2, and data 3 to the corresponding target storage address.

[0033] When the computing chip 100 needs to read data from the storage chip 200, for example, the data to be read may include data 1, data 2, and data 3, the computing chip 100 can send a read request containing the target read address to the storage chip 200. The computing chip 100 still does not need to simultaneously transmit a clock signal and / or a data valid signal to the storage chip; instead, it can directly sample the data and read the required data after a preset fixed delay sequence.

[0034] With this design, in this embodiment, neither storing nor retrieving data depends on the clock signal and the data validity signal, which can significantly reduce the power consumption of the circuit.

[0035] In certain specific application scenarios, such as when the computing chip 100 has a high clock frequency (e.g., above 1 GHz) and the storage chip 200 cannot provide or use a clock signal (or a signal with a similar clock function), the high-frequency clock signal of the computing chip 100 can be matched with the asynchronous timing requirements of the storage chip 200 through a synchronous timer to achieve data storage and data retrieval.

[0036] Optionally, the asynchronous mode based on the data valid signal is configured as follows: in a write operation, the computing chip 100 synchronously sends a write data valid signal to the storage chip 200, and the storage chip 200 performs data sampling in response to the valid level of the signal; in a read operation, the storage chip 200 feeds back a read data valid signal synchronized with the read data to the computing chip 100, and the computing chip 100 performs data sampling in response to the valid level of the signal.

[0037] This design achieves data synchronization through handshake signals (valid signals), reducing the dependence on the global clock tree and the strict timing alignment requirements, and improving the reliability of data transmission in a distributed architecture.

[0038] like Figure 4 As shown, in some optional embodiments, the data to be stored may include data 1, data 2, and data 3. When the computing chip 100 needs to write the data to be stored to the storage chip 200, the computing chip 100 can simultaneously send a first data valid signal (e.g., the first data valid signal is high when the data to be stored is valid) while sending a storage request to the storage chip 200. The first data valid signal can be transmitted to the controller via an independent control line, and the controller decodes it to generate a storage space-level enable signal. When the controller of the storage chip 200 detects the first data valid signal, it can activate the data latch circuit (not shown) of the corresponding storage space. This allows the storage chip 200 to sample data when the first data valid signal is high, thus completing the storage of the data to be stored.

[0039] When the computing chip 100 needs to read data from the storage chip 200, the data to be read may include data 1, data 2, and data 3. After the data to be read is ready, the controller of the storage chip 200 can send a second data valid signal (e.g., the second data valid signal is low when the data to be read is valid) while simultaneously sending the data to the computing chip 100. Furthermore, when the computing chip 100 detects that the second data valid signal is valid (e.g., the second data valid signal is low), it can activate the receiving circuit, sample the data when the second data valid signal is low, and read the data to be read.

[0040] With this design, in this embodiment, both storing and retrieving data can reduce the dependence of the computing chip 100 and the storage chip 200 on the clock signal, and can reduce the timing requirements of the computing chip 100 and the storage chip 200.

[0041] In some specific application scenarios, such as when the clock frequency of the computing chip 100 is limited and the storage chip 200 cannot provide or use a clock signal (or a signal with a clock function), the low-frequency clock signal of the computing chip 100 cannot properly match the asynchronous timing requirements of the storage chip 200. Therefore, in the above embodiment, asynchronous sampling can be performed using a valid data signal to achieve data storage and data retrieval.

[0042] Optionally, the clock-based synchronization method is configured such that, during read / write operations, both data transmission and reception are synchronized with the edge of the clock signal; the sources of the clock signal include: a new clock generated by the memory chip, a clock fed back by the memory chip that originates from the same source as the computing chip, or a synchronization clock forwarded by the memory chip.

[0043] This design, utilizing a synchronous clock mechanism, simplifies data alignment logic, supports higher frequency data transmission, and is suitable for application scenarios with extremely high bandwidth and latency requirements.

[0044] Figure 5 A schematic diagram of a data synchronization interaction method based on a synchronous clock is shown. In some optional embodiments, the data to be stored may include data 1, data 2, and data 3. When the computing chip 100 needs to write data to the storage chip 200, the computing chip 100 sends a storage request to the storage chip 200 while simultaneously sending the data signal and the rising edge of the computing chip 100's clock signal to the storage chip 200. Then, the storage chip 200 samples the data according to the rising edge of the clock signal and completes the storage of the data to be stored.

[0045] When the computing chip 100 needs to read data from the storage chip 200, the data to be read may include data 1, data 2, and data 3. The storage chip 200 can, according to the read request, synchronously send the data to be read corresponding to the target read address to the computing chip 100 along with its clock signal. Then, the computing chip 100 can use the received clock signal to sample the data on the rising edge of the clock signal and read the data to be read.

[0046] This design effectively reduces the complexity of data interaction in this embodiment.

[0047] Figure 6A schematic diagram of a data synchronization interaction method based on an asynchronous clock is shown. In some optional embodiments, the data to be stored may include data 1, data 2, and data 3. When the computing chip 100 needs to write data to the storage chip 200, the computing chip 100 can send a storage request to the storage chip 200. The controller can decode the target storage address in the storage request, verify the integrity of the data to be stored, and then, under the precise control of the controller, the storage chip 200 can store the data to be stored into the target storage address.

[0048] When the computing chip 100 needs to read data from the storage chip 200, for example, the data to be read may include data 1, data 2, and data 3, the computing chip 100 can send a read request to the storage chip 200. The controller can decode the target read address in the read request, and then, under the precise control of the controller, the storage chip 200 can send the data to be read to the controller. After buffering the data, the controller sends it to the computing chip 100, so that the computing chip 100 can read the data to be read.

[0049] In the above embodiments, various data communication methods between the memory chip 200 and the computing chip 100 are illustrated, and the data interaction sampling mechanism between the computing chip 100 and the memory chip 200 in the three-dimensional stacked memory is clarified.

[0050] Optionally, the storage space interface protocol is configured to allow different one of the three data interaction sampling mechanisms mentioned above to be used in read and write operations respectively; or to use two or more interaction methods simultaneously in a single read or write operation.

[0051] This design allows for separate optimization of the protocol for the different physical characteristics of read and write operations (such as reads being sensitive to latency and writes being sensitive to setup time), thereby achieving optimization of system-level energy efficiency.

[0052] Optionally, key interface signals include: activation, precharge, and request signals for read and write operations, respectively; address signals containing information about memory groups, memory spaces, rows, and columns; data signals containing data content and ECC check information; and timing control, data valid, or clock signals that match the selected data communication method.

[0053] Optionally, the key interface signal setting specification supports an address signal multiplexing strategy: read address signals and write address signals share the same set of physical transmission lines; and a single address signal, through encoding or time-division multiplexing, simultaneously contains at least two of the following: storage space group address, storage space address, row address, and column address information.

[0054] This design, through high address signal multiplexing, significantly reduces the number of through-silicon vias (TSVs) required for vertical stacking, thereby reducing chip manufacturing costs and wiring congestion.

[0055] Optionally, such as Figure 7 As shown, the distributed interface of a memory can be divided into read / write control, address and data, access control, and other signals based on functional dimensions. Specifically, it may include: The read control interface can be used for signals such as communication activation, precharge, read clock, read request, or similar functions.

[0056] The read address interface can be used for communication storage space group read address signal, storage space read address signal, row read address signal, column read address signal, or similar signals.

[0057] The data read interface can be used to read data signals, read ECC (Error Checking and Correcting) data verification signals, or signals with similar functions.

[0058] The write control interface can be used for signals such as communication activation, precharge, write clock, write request, or similar functions.

[0059] The write address interface can be used for communication memory space group write address signals, memory space write address signals, row write address signals, column write address signals, or signals with similar functions.

[0060] The write data interface can be used to write data signals, write ECC data verification signals, or signals with similar functions.

[0061] The clock / sampling interface can be used for communication timing control signals, data valid signals, various forms of clock signals, or clock-like signals or signals with similar functions generated in sync with the data, depending on the data interaction method.

[0062] Other signals include, but are not limited to, refresh signals, register read / write signals, and other functional signals that memory chips need to support, as well as system signals or signals with similar functions that computing chips need to function normally, such as reset signals and interrupt signals.

[0063] Specifically, for the aforementioned signals, the read / write control interface signals can share the same set of signal lines, or consist of two separate sets of signals, or be combined into a composite application scheme according to the read / write format supported by the memory chip. The read / write address signals can share address signals, and can simultaneously contain memory space group address information, memory space address information, row address information, and column address information in a single signal, or a combination of the above. The read / write data interface can be two unidirectional interfaces, or it can share a single bidirectional port. The sampling signals can be one or more combinations, and their consistency with the data interaction method is required.

[0064] Continue to refer to Figure 7 The key interface signal setting specifications support flexible configuration of control and data interfaces: the read control interface and the write control interface can be configured to share the same set of signal lines or two independent sets of signal lines; the read data interface and the write data interface can be configured as two unidirectional transmission interfaces or share a bidirectional transmission port.

[0065] This design balances performance and area, making trade-offs between "high performance (independent interface / concurrent read and write)" and "low area (reused interface / reduced wiring)," thus enhancing the customization capabilities of the solution.

[0066] Optionally, the critical interface signal setting specification also includes auxiliary function signals, which include at least one of the following: a refresh signal for maintaining data retention characteristics; a register read / write signal for configuring interface parameters; and an interrupt signal for system reset and exception handling.

[0067] In summary, the three-dimensional stacked memory provided in this embodiment offers a flexible interaction mechanism, balancing power consumption and performance by defining three optional data interaction sampling mechanisms (latency-based asynchronous, valid signal-based asynchronous, and clock-synchronized). Designers can flexibly choose the most suitable communication method based on the timing margin, power budget, and design complexity requirements of specific application scenarios, or adopt a composite scheme (such as using different methods for reading and writing) to optimize system-level energy efficiency.

[0068] Optimizing interconnect resources and reducing packaging costs: By standardizing the flexible multiplexing strategy of key interface signals (such as read / write address multiplexing, control signal multiplexing, and bidirectional data port configuration), the number of through-silicon vias (TSVs) required for three-dimensional stacking can be effectively reduced while ensuring high performance, thereby reducing wiring congestion and manufacturing costs between chips.

[0069] More specifically, the computing chip 100 integrates at least one digital in-memory computing unit for performing computing tasks, specifically, such as Figure 8As shown, the structure of the digital in-memory computing unit mainly includes a DCIM array based on 6T SRAM, a word line decoder (WL DEC), a word line buffer (WL DRV), read / write circuits, and a controller. The DCIM array consists of C DCIM columns, each containing R subarrays and an adder tree. Each subarray integrates 6T SRAM bit cells and a Local Read-Out and Compute Unit (LRCC), storing N-bit weights per row. Functionally, the DCIM macro can perform matrix-vector multiplication (MVM) multiplication-accumulation (MAC) calculations: the operating mode is switched via the MEM_EN signal. When MEM_EN is low, the N-bit weights in the subarray are multiplied by a 1-bit input, read and latched by the LRCC, accumulated by the adder tree, and then sent to a shift-and-accumulator to extend the input precision in the time dimension, ultimately completing a full MVM operation with K-bit input and N-bit weights, while also supporting the storage and efficient computation of multi-weight matrices.

[0070] Optionally, the three-dimensional stacked memory based on in-memory computing and distributed interfaces provided in this embodiment also includes an interface device (not shown), which is disposed on the memory chip or the computing chip and is used to interact with an external host device.

[0071] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0072] It should be noted that, in the examples and description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0073] Although this application has been illustrated and described with reference to certain embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

[0074] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-dimensional stacked memory based on in-memory computing and a distributed interface, characterized in that, include: Computing chips are used to perform computing tasks; A memory chip contains multiple independently addressable memory spaces; The memory chip and the computing chip are integrated using three-dimensional stacking packaging technology to form a three-dimensional integrated high-speed channel, which includes multiple independent distributed interfaces. The computing chip accesses the multiple independently addressed storage spaces in parallel through the multiple independent distributed interfaces, and the data interaction sampling mechanism between the computing chip and the storage chip includes at least one of the following: Asynchronous data interaction based on delay timing information, asynchronous data interaction based on valid data signals, and synchronous data interaction based on clocks.

2. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to claim 1, characterized in that, The data interaction between the computing chip and the storage chip includes read operations and write operations, and the data interaction sampling mechanisms of the read operations and the write operations may be the same or different.

3. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to claim 2, characterized in that, The asynchronous data interaction based on delay timing information includes: During the write operation, the computing chip sends data sequentially according to the timing requirements of the storage chip, without transmitting a write clock signal or a write data valid signal. In the readout operation, the computing chip samples the readout data according to fixed delay timing requirements, without relying on the read clock signal or the read data valid signal.

4. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to claim 2, characterized in that, The asynchronous data interaction based on the valid data signal includes: During the write operation, the computing chip synchronously sends a write data valid signal to the storage chip, and the storage chip performs data sampling in response to the valid level of the signal; During the read operation, the storage chip feeds back a read data validity signal synchronized with the read data to the computing chip, and the computing chip samples the data in response to the validity level of the signal.

5. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to claim 2, characterized in that, The clock-based synchronous data interaction includes: In both the write and read operations, the transmission and reception of data are synchronized with the edge of the clock signal; The sources of the clock signal include: a new clock generated by the memory chip, a clock fed back by the memory chip that is of the same origin as the computing chip, or a synchronization clock forwarded by the memory chip.

6. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to any one of claims 1-5, characterized in that, The key interface signals of the multiple independent distributed interfaces include one or more of the following: These are respectively used for activation, precharge, and request signals for the read and write operations; An address signal containing the storage space, the row and column information of the storage space; Data signals containing data content and ECC verification information; Timing control, data validity, or clock signals that match the selected data communication method.

7. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to claim 6, characterized in that, The read address signal and the write address signal share the same set of physical transmission lines, and a single address signal contains at least two of the following through encoding or time-division multiplexing: storage space address, storage space row address, and column address information.

8. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to claim 6, characterized in that, The read control interface and the write control interface are configured to share the same set of signal lines or to have two independent sets of signal lines. The read data interface and the write data interface are configured as two unidirectional transmission interfaces or share a bidirectional transmission port.

9. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to claim 7, characterized in that, The key interface signals also include auxiliary function signals, which include at least one of the following: A refresh signal used to maintain data retention characteristics; Register read / write signals used to configure interface parameters; And interrupt signals used for system reset and exception handling.

10. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to any one of claims 1-5, characterized in that, It also includes an interface device, which is disposed on the storage chip or the computing chip, for data interaction with an external host control device.

11. The three-dimensional stacked memory based on in-memory computing and distributed interfaces according to any one of claims 1-5, characterized in that, The three-dimensional stacked packaging technology includes at least one of the following: hybrid bonding, through-silicon vias, flip-chip and microbump connection.

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