Bridging device
By designing a bridging device, high-speed second and third storage modules are used to replace bad pixels in DRAM, solving the problems of capacity reduction and low data read/write efficiency caused by bad pixel repair and replacement in DRAM storage devices, and achieving efficient data read/write and storage performance assurance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHONGSHAN JIANGBOLONG ELECTRONICS CO LTD
- Filing Date
- 2026-04-13
- Publication Date
- 2026-05-12
AI Technical Summary
Repairing and replacing dead pixels in existing DRAM memory devices reduces capacity and affects data read/write efficiency.
A bridging device is adopted, including a first storage module, a second storage module and a control module. After power-on, the remapped address data is loaded into the second storage module, and the high read and write speed of the second storage module is used to realize data read and write operations. The third storage module is used to replace bad pixels.
Without reducing storage capacity, data read and write efficiency was improved, and bad pixels were repaired and replaced, thus ensuring storage performance.
Smart Images
Figure CN122018818A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and more particularly to a bridging device. Background Technology
[0002] Storage devices have an extremely dense structure (billions of storage cells), and defects are inevitable during the manufacturing process. In some application scenarios, redundant storage cells are designed into the original storage device as replacements.
[0003] Taking DRAM (Dynamic Random Access Memory) as an example, DRAM must be a continuous set of usable storage cells in order to read and write data smoothly. Once there are some bad storage cells, the continuous storage cells must be replaced and repaired. This will result in a situation where the DRAM chip exceeds the original reserved redundancy and replacement range, and the DRAM chip can only be regarded as a defective product. Summary of the Invention
[0004] The main technical problem addressed by this application is to provide a bridging device that can repair and replace bad pixels without derating, and improve data read and write efficiency.
[0005] To address the aforementioned technical problems, this application provides a bridging device comprising: a first storage module; a second storage module connected to the first storage module, wherein the read / write speed of the second storage module is greater than that of the first storage module; a third storage module; and a control module connected to the first, second, and third storage modules. The control module is configured to: upon power-on, load remapped address data from the first storage module into the second storage module, wherein the remapped address data includes a mapping relationship between bad address addresses of a fourth storage module externally connected to the bridging device and good address addresses of the third storage module; and during operation, read the remapped address data from the second storage module to perform data read / write operations.
[0006] In one embodiment, the bridging device further includes: a first interface module, connected to the control module and the second storage module, and configured to connect to a host computer; a second interface module, connected to the control module, the second storage module and the first interface module, and configured to connect to a fourth storage module; the control module is configured to: during operation, acquire the target bad address in the read / write instruction received by the first interface module, read the remapped address data in the second storage module to find the target good address corresponding to the target bad address, and perform data read / write operations based on the target good address.
[0007] In one embodiment, the bridging device further includes: a first adapter module connected to a first interface module, the first adapter module storing multiple interface protocols, and the first adapter module being configured to control the first interface module to communicate with a host computer based on a selected interface protocol; and a second adapter module connected to a second interface module, the second adapter module storing multiple interface protocols, and the second adapter module being configured to control the second interface module to communicate with a fourth storage module based on a selected interface protocol.
[0008] In one embodiment, the first adapter module and the second adapter module are connected to the control module, and the first adapter module and the second adapter module are configured to select the corresponding interface protocol based on the configuration instructions of the control module.
[0009] In one embodiment, the bridging device further includes a register module, a first adapter module and a second adapter module are connected to the register module, and the first adapter module and the second adapter module are configured to select the corresponding interface protocol based on the protocol configuration parameters of the register module.
[0010] In one embodiment, the bridging device further includes: a first switching module connected to the first interface module, the first switching module being configured to control the order of pins of the first interface module; and a second switching module connected to the second interface module, the second switching module being configured to control the order of pins of the second interface module.
[0011] In one embodiment, the first switching module includes a first command pin switching module and a first data pin switching module. The first command pin switching module is configured to control the order of command pins of the first interface module, and the first data pin switching module is configured to control the order of data pins of the first interface module. The second switching module includes a second command pin switching module and a second data pin switching module. The second command pin switching module is configured to control the order of command pins of the second interface module, and the second data pin switching module is configured to control the order of data pins of the second interface module.
[0012] In one embodiment, the bridging device further includes a register module. A first command pin exchange module, a first data pin exchange module, a second command pin exchange module, and a second data pin exchange module are connected to the register module. The first command pin exchange module and the second command pin exchange module are configured to control the command pin order based on the command exchange configuration parameters of the register module. The first data pin exchange module and the second data pin exchange module are configured to control the data pin order based on the data exchange configuration parameters of the register module.
[0013] In one embodiment, the bridging device further includes a programming interface module connected to a control module. The control module is configured to: store the remapped address data obtained through the programming interface module into a first storage module; or modify the remapped address data loaded in the second storage module according to the modified mapping data obtained by the programming interface module.
[0014] In one embodiment, the bridging device further includes a programming interface module and a register module, which are connected to a control module. The control module is configured to modify the configuration parameters of the register module based on the configuration parameters obtained by the programming interface module.
[0015] In one embodiment, the bridging device further includes a configuration pin module and a register module, which are connected to a control module. The control module is configured to modify the configuration parameters of the register module based on the configuration parameters obtained by the configuration pin module.
[0016] In one embodiment, when the fourth storage module has bad pixels, the remapping address data includes the mapping relationship between the bad pixel address of the fourth storage module and the good pixel address of the third storage module; when the fourth storage module does not have bad pixels, the remapping address data includes the mapping relationship between the high-order address of the fourth storage module and the good pixel address of the third storage module, wherein the high-order address is an address that is sequentially added in addition to the original address of the fourth storage module.
[0017] In one embodiment, the bridging device includes identity information used to represent bad pixel address data of a fourth storage module bound to the bridging device.
[0018] In one embodiment, the first storage module is one of EFUSE, SPI NOR or EEPROM, and the second and third storage modules are SRAM.
[0019] The beneficial effects of this application are as follows: The bridging device provided by this application includes a control module and a first storage module, a second storage module, and a third storage module connected to it. The control module is configured to: after power-on, load remapped address data from the first storage module into the second storage module. The remapped address data includes a mapping relationship between the bad address of the fourth storage module connected externally to the bridging device and the good address of the third storage module; during operation, read the remapped address data from the second storage module to realize data read / write operations. Through the above method, on the one hand, by pre-loading the remapped address data into the second storage module after power-on, the remapped address data can be read more quickly during subsequent read / write operations, improving data read / write efficiency; on the other hand, by utilizing the third storage module, the bad points of the fourth storage module can be replaced without reducing the storage capacity of the fourth storage module, ensuring the storage performance of the fourth storage module. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the bridging device provided in this application; Figure 2 This is a schematic diagram illustrating the replacement of the fourth storage module and the third storage module in one embodiment; Figure 3 This is a schematic diagram showing the replacement of the fourth storage module and the third storage module in another embodiment; Figure 4 This is a schematic diagram of the structure of the second embodiment of the bridging device provided in this application; Figure 5 This is a schematic diagram of the structure of the third embodiment of the bridging device provided in this application; Figure 6 This is a schematic diagram of the fourth embodiment of the bridging device provided in this application; Figure 7 This is a schematic diagram of the fifth embodiment of the bridging device provided in this application; Figure 8 This is a schematic diagram of the sixth embodiment of the bridging device provided in this application; Figure 9 This is a schematic diagram of the structure of the seventh embodiment of the bridging device provided in this application; Figure 10 This is a schematic diagram of the structure of the eighth embodiment of the bridging device provided in this application; Figure 11 This is a structural schematic diagram of the ninth embodiment of the bridging device provided in this application. Detailed Implementation
[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that any embodiment described herein can be combined with associated technical features in other embodiments.
[0023] DRAM is a semiconductor memory used to store each data bit in an individual memory cell consisting of a capacitor and a transistor. It is a "volatile" memory, meaning that the data stored in it is lost once power is turned off. Because each memory cell of DRAM only requires one transistor and one capacitor, its structure is very simple, allowing for the integration of more storage capacity on the same chip area. This also leads to more faulty memory cells. DRAM requires consecutive usable memory cells for successful data reading and writing. Once some memory cells fail, consecutive memory cells must be replaced or repaired. This can exceed the originally reserved redundancy for replacement, rendering the DRAM chip a defective product.
[0024] See Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the bridging device provided in this application. The bridging device 100 includes a first storage module 10, a second storage module 20, a third storage module 30, and a control module 40. The second storage module 20 is connected to the first storage module 10, and the control module 40 is connected to the first storage module 10, the second storage module 20, and the third storage module 30. In this embodiment, the bridging device 100 serves as a bridge between an external host computer (such as a processor) and an external fourth storage module, enabling the host computer to perform read and write operations on the fourth storage module via the bridging device 100.
[0025] Optionally, the first storage module 10 is a non-volatile memory, such as EFUSE (Electronic Fuse), SPI NOR (NOR FLASH based on SPI bus), or EEPROM (Electrically Erasable Programmable Read-Only Memory). The first storage module 10 is used to store remapped address data. The remapped address data includes the mapping relationship between the bad address of the fourth storage module and the good address of the third storage module 30.
[0026] Understandably, the bad and good addresses mentioned above can be row addresses or block addresses; there are no restrictions here. For example, DRAM memory cells are divided into blocks of 64 rows each. When any memory cell in a block is detected to be bad, the block is considered a bad block.
[0027] In one optional application scenario, the remapped address data is obtained by performing a second bad pixel check on the fourth storage module. Understandably, DRAM undergoes initial bad pixel detection during the original manufacturer's production process, and downstream manufacturers perform a second bad pixel check after purchasing DRAM chips from the original manufacturer, thus forming the aforementioned remapped address data.
[0028] Optionally, the read / write speed of the second storage module 20 is greater than that of the first storage module 10. For example, the second storage module 20 and the third storage module 30 are SRAM (Static Random Access Memory). SRAM is a volatile memory (data is lost after power is off). Its core feature is that it uses bistable flip-flop circuits to store data. As long as power is maintained, the data will remain stable and will not require refresh operations like DRAM. Because SRAM does not require refresh latency and its internal circuitry responds extremely quickly, its read / write speed is very fast.
[0029] Understandably, the second storage module 20 and the third storage module 30 can be implemented by two independent storage modules, or by the same storage module by dividing it into different storage areas; there is no restriction here.
[0030] The control module 40 is configured to: load the remapped address data in the first storage module 10 to the second storage module 20 after power-on; and read the remapped address data in the second storage module 20 during operation to realize data read / write operations.
[0031] In a further embodiment, the bridging device 100 further includes a first interface module 51 and a second interface module 52. The first interface module 51 is connected to the control module 40 and the second storage module 20 and is configured to connect to a host computer; the second interface module 52 is connected to the control module 40, the second storage module 20 and the first interface module 51, and is configured to connect to a fourth storage module.
[0032] The control module 40 is configured to: during operation, obtain the target bad point address from the read / write instruction received by the first interface module 51, read the remapped address data in the second storage module 20, find the target good point address corresponding to the target bad point address, and perform data read / write operations based on the target good point address.
[0033] Specifically, the "host computer - first interface module 51 - second storage module 20 - second interface module 52 - fourth storage module" form a command transmission channel for transmitting signals such as CK (clock) / CS (chip select) / CA (column address), and the "host computer - first interface module 51 - third storage module 30" and "host computer - first interface module 51 - second interface module 52 - fourth storage module" form a data transmission channel for transmitting signals such as DQ (bidirectional data) / DM (data mask) / DQS (data strobe). The bridging device 100 includes the following functions: After power-on, the control module 40 loads the remapped address data in the first storage module 10 into the second storage module 20.
[0034] During a read operation, the control module 40 receives a read command (containing the target bad pixel address) sent by the host computer and received by the first interface module 51. It then reads the remapped address data from the second storage module 20 to locate the target good pixel address corresponding to the target bad pixel address. If this target good pixel address is located in the third storage module 30, the corresponding data is returned via the path "third storage module 30 - first interface module 51 - host computer" to complete the read operation. Alternatively, if the read command does not contain a bad pixel address, the corresponding data is directly returned via the path "fourth storage module - second interface module 52 - first interface module 51 - host computer" to complete the read operation.
[0035] During a write operation, the control module 40 receives the write command (containing the target bad pixel address) sent by the host computer and received by the first interface module 51. It then reads the remapped address data in the second storage module 20 to locate the target good pixel address corresponding to the target bad pixel address. If this target good pixel address is located in the third storage module 30, the write operation is performed via the path "host computer - first interface module 51 - third storage module 30". Alternatively, if the write command does not contain a bad pixel address, the write operation is performed directly via the path "host computer - first interface module 51 - second interface module 52 - fourth storage module".
[0036] The bridging device in this embodiment includes a control module and connected to a first storage module, a second storage module, and a third storage module. The control module is configured to: upon power-on, load remapped address data from the first storage module into the second storage module. This remapped address data includes a mapping relationship between the bad pixel addresses of a fourth storage module externally connected to the bridging device and the good pixel addresses of the third storage module; during operation, read the remapped address data from the second storage module to perform data read / write operations. Through this method, on the one hand, pre-loading the remapped address data into the second storage module after power-on allows for faster reading and writing of the remapped address data during subsequent read / write operations, improving data read / write efficiency; on the other hand, utilizing the third storage module enables the replacement of bad pixels in the fourth storage module without reducing its storage capacity, ensuring the storage performance of the fourth storage module.
[0037] The replacement schemes for the fourth and third storage modules are further described below. For example... Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the replacement of the fourth and third storage modules in one embodiment. When the fourth storage module has bad pixels, the remapping address data includes the mapping relationship between the bad pixel addresses of the fourth storage module and the good pixel addresses of the third storage module.
[0038] Specifically, taking DRAM as an example, DRAM storage cells are divided into blocks of 64 rows each. An 8Gbit DRAM has 65,536 rows, divided into 1024 blocks. In one application scenario, when performing bad pixel detection on the fourth storage module, bad storage cells are detected in blocks 2, 5, and 1019. After remapping, blocks 2, 5, and 1019 of the fourth storage module are replaced with blocks 0, 1, and 2 of the third storage module, respectively.
[0039] By using the replacement method described above, the third storage module of the bridging device 100 replaces the bad pixels in the fourth storage module, thereby achieving the purpose of repairing the bad pixels without reducing the capacity of the fourth storage module.
[0040] In another embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the replacement of the fourth and third storage modules in another embodiment. When the fourth storage module has no bad pixels, the remapping address data includes the mapping relationship between the high-order addresses of the fourth storage module and the good-order addresses of the third storage module. The high-order addresses are addresses sequentially added in addition to the original addresses of the fourth storage module.
[0041] Specifically, taking DRAM as an example, DRAM storage cells are divided into blocks of 64 rows each. An 8Gbit DRAM has 65,536 rows, divided into 1024 blocks. In one application scenario, when performing bad pixel detection on the fourth storage module, no bad storage cells are detected. Therefore, after remapping, the high-order addresses of the fourth storage module (block1024, block1025, block1026, etc.) are mapped to the blocks of the third storage module 30.
[0042] Through the above-mentioned remapping, the expansion of the fourth storage module is achieved through the third storage module of the bridging device 100.
[0043] In an optional embodiment, the bridging device 100 includes identification information, which represents the bad pixel address data of the fourth storage module bound to the bridging device 100. This identification information can be set on the surface of the bridging device 100 in the form of characters (letters / numbers), graphics (barcodes / QR codes), or engravings, or it can be stored in the bridging device 100 as data. An external device can obtain this identification information to query the bad pixel address data of the fourth storage module bound to the bridging device 100, and, when needed, burn the bad pixel address data into the aforementioned first storage module 10.
[0044] See Figure 4 , Figure 4 This is a schematic diagram of the structure of the second embodiment of the bridging device provided in this application. The bridging device 100 includes a first storage module 10, a second storage module 20, a third storage module 30, and a control module 40. The second storage module 20 is connected to the first storage module 10, and the control module 40 is connected to the first storage module 10, the second storage module 20, and the third storage module 30.
[0045] The bridging device 100 further includes a first interface module 51 and a second interface module 52. The first interface module 51 is connected to the control module 40 and the second storage module 20 and is configured to connect to a host computer; the second interface module 52 is connected to the control module 40, the second storage module 20 and the first interface module 51, and is configured to connect to a fourth storage module.
[0046] The bridging device 100 further includes a first adapter module 61 and a second adapter module 62. The first adapter module 61 is connected to the first interface module 51 and stores multiple interface protocols. The first adapter module 61 is configured to control the first interface module 51 to communicate with the host computer based on the selected interface protocol. The second adapter module 62 is connected to the second interface module 52 and stores multiple interface protocols. The second adapter module 62 is configured to control the second interface module 52 to communicate with the fourth storage module based on the selected interface protocol.
[0047] Optionally, the aforementioned interface protocols may include DRAM-compatible interface protocols such as DDR3, DDR4, DDR5, DDR6, GDDR5, GDDR6, GDDR7, LPDDR3, LPDDR4, LPDDR5, and LPDDR6.
[0048] In one embodiment, the first adapter module 61 and the second adapter module 62 are connected to the control module 40, and the first adapter module 61 and the second adapter module 62 are configured to select the corresponding interface protocol based on the configuration instructions of the control module 40.
[0049] In another embodiment, such as Figure 5 As shown, Figure 5 This is a structural schematic diagram of the third embodiment of the bridging device provided in this application. The bridging device 100 also includes a register module 70. The first adapter module 61 and the second adapter module 62 are connected to the register module 70. The first adapter module 61 and the second adapter module 62 are configured to select the corresponding interface protocol based on the protocol configuration parameters of the register module 70.
[0050] Figure 4 and Figure 5 The embodiments are used to implement the adaptation function of the bridging device 100. The first adaptation module 61 controls the communication protocol of the first interface module 51, and the second adaptation module 62 controls the communication protocol of the second interface module 52, so that the bridging device 100 can adapt to various types or models of DRAM.
[0051] See Figure 6 , Figure 6 This is a structural schematic diagram of the fourth embodiment of the bridging device provided in this application. The bridging device 100 includes a first storage module 10, a second storage module 20, a third storage module 30, and a control module 40. The second storage module 20 is connected to the first storage module 10, and the control module 40 is connected to the first storage module 10, the second storage module 20, and the third storage module 30.
[0052] The bridging device 100 further includes a first interface module 51 and a second interface module 52. The first interface module 51 is connected to the control module 40 and the second storage module 20 and is configured to connect to a host computer; the second interface module 52 is connected to the control module 40, the second storage module 20 and the first interface module 51, and is configured to connect to a fourth storage module.
[0053] The bridging device 100 further includes a first switching module 81 and a second switching module 82. The first switching module 81 is connected to the first interface module 51 and is configured to control the pin order of the first interface module 51; the second switching module 82 is connected to the second interface module 52 and is configured to control the pin order of the second interface module 52.
[0054] Understandably, the first switching module 81 and the second switching module 82 are used to define the pin order. For example, DRAM types such as DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5, and LPDDR6 require defining data pins DQ0~DQ31. Taking LPDDR4 / LPDDR5 as an example, it is necessary to interchange the low-order DQ pins and the high-order DQ pins, as shown in Table 1: Table 1
[0055] As can be seen from Table 1, DQ0 and DQ8 are interchanged, DQ1 and DQ9 are interchanged, and so on, DQ7 and DQ15 are interchanged.
[0056] In addition to the interchange of data pins mentioned above, command pins can also be interchanged. For example, DRAM types such as DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5, and LPDDR6 require defining command pins A0~A17. Taking LPDDR4 as an example, the order of CA0~CA5 needs to be reversed; taking LPDDR5 as an example, the order of CA0~CA6 needs to be reversed, as shown in Table 2. Table 2
[0057] As can be seen from Table 2, CA0~CA5 of LPDDR4 are completely reversed, and CA0~CA6 of LPDDR5 are completely reversed.
[0058] In another embodiment, combined Figure 6 and Figure 7 , Figure 7This is a schematic diagram of the fifth embodiment of the bridging device provided in this application. The first switching module includes a first command pin switching module 811 and a first data pin switching module 812. The second switching module 82 includes a second command pin switching module 821 and a second data pin switching module 822.
[0059] The first command pin exchange module 811 is configured to control the order of command pins of the first interface module 51, and the first data pin exchange module 812 is configured to control the order of data pins of the first interface module 51; the second command pin exchange module 821 is configured to control the order of command pins of the second interface module 52, and the second data pin exchange module 822 is configured to control the order of data pins of the second interface module 52.
[0060] Optionally, in this embodiment, the first command pin exchange module 811, the first data pin exchange module 812, the second command pin exchange module 821, and the second data pin exchange module 822 are connected to the control module 40. The first command pin exchange module 811, the first data pin exchange module 812, the second command pin exchange module 821, and the second data pin exchange module 822 control the order of the pins of the corresponding interfaces based on the configuration instructions of the control module 40.
[0061] In another embodiment, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the sixth embodiment of the bridging device provided in this application. The bridging device 100 further includes a register module 70. A first command pin exchange module 811, a first data pin exchange module 812, a second command pin exchange module 821, and a second data pin exchange module 822 are connected to the register module 70. The first command pin exchange module 811 and the second command pin exchange module 821 are configured to control the command pin sequence based on the command exchange configuration parameters of the register module 70. The first data pin exchange module 812 and the second data pin exchange module 822 are configured to control the data pin sequence based on the data exchange configuration parameters of the register module 70.
[0062] Figures 6-8 The embodiments are used to implement the pin swap function of the bridging device, controlling the pin order of the first interface module 51 through the first swap module 81 and controlling the pin order of the second interface module 52 through the second swap module 82, so that the bridging device 100 can adapt to various types or models of DRAM.
[0063] See Figure 9 , Figure 9This is a structural schematic diagram of the seventh embodiment of the bridging device provided in this application. The bridging device 100 includes a first storage module 10, a second storage module 20, a third storage module 30, and a control module 40. The second storage module 20 is connected to the first storage module 10, and the control module 40 is connected to the first storage module 10, the second storage module 20, and the third storage module 30.
[0064] The first storage module 10 stores remapped address data. This remapped address data includes the mapping relationship between the bad address of the fourth storage module and the good address of the third storage module 30. The control module 40 is configured to: load the remapped address data from the first storage module 10 into the second storage module 20 after power-on; and read the remapped address data from the second storage module 20 during operation to perform data read / write operations.
[0065] The bridging device 100 also includes a programming interface module 91, which is connected to the control module 40. Optionally, the programming interface module 91 can use the IIC communication protocol, or embedded communication protocols such as SPI, UART, or USART, or other custom communication protocols; no restrictions are placed here.
[0066] In one embodiment, the control module 40 is configured to store the remapped address data obtained through the programming interface module 91 into the first storage module 10.
[0067] In another embodiment, the control module 40 is configured to modify the remapped address data loaded in the second storage module 20 according to the modified mapping data obtained by the programming interface module 91. Understandably, since the bridging device 100 typically only loads the remapped address data from the first storage module 10 into the second storage module 20 after power-on, if modification of the remapped address data is required after power-on, it is necessary to power off and reprogram the remapped address data back to the first storage module 10 before powering on again, which is cumbersome. This embodiment allows direct modification of the remapped address data loaded in the second storage module 20 without modifying the remapped address data stored in the first storage module 10.
[0068] See Figure 10 , Figure 10 This is a schematic diagram of the structure of the eighth embodiment of the bridging device provided in this application. The bridging device 100 includes a first storage module 10, a second storage module 20, a third storage module 30, and a control module 40. The second storage module 20 is connected to the first storage module 10, and the control module 40 is connected to the first storage module 10, the second storage module 20, and the third storage module 30.
[0069] The first storage module 10 stores remapped address data. This remapped address data includes the mapping relationship between the bad address of the fourth storage module and the good address of the third storage module 30. The control module 40 is configured to: load the remapped address data from the first storage module 10 into the second storage module 20 after power-on; and read the remapped address data from the second storage module 20 during operation to perform data read / write operations.
[0070] The bridging device 100 further includes a programming interface module 91 and a register module 70. The programming interface module 91 is connected to the control module 40, and the register module 70 is also connected to the control module 40. Optionally, the programming interface module 91 can use the IIC communication protocol, or embedded communication protocols such as SPI, UART, or USART, or other custom communication protocols; no restrictions are placed here. The control module 40 is configured to modify the configuration parameters of the register module 70 based on the configuration parameters obtained from the programming interface module 91.
[0071] In one embodiment, in conjunction with the above Figure 5 In one embodiment, the control module 40 is configured to modify the protocol configuration parameters of the register module 70 according to the configuration parameters obtained by the programming interface module 91, so as to control the first interface module 51 to communicate with the host computer based on the selected interface protocol, and to control the second interface module 52 to communicate with the fourth storage module based on the selected interface protocol.
[0072] In another embodiment, in conjunction with the above... Figure 8 In this embodiment, the control module 40 is configured to modify the command exchange configuration parameters and data exchange configuration parameters of the register module 70 according to the configuration parameters obtained by the programming interface module 91. The first command pin exchange module 811 and the second command pin exchange module 821 are configured to control the command pin sequence based on the command exchange configuration parameters of the register module 70. The first data pin exchange module 812 and the second data pin exchange module 822 are configured to control the data pin sequence based on the data exchange configuration parameters of the register module 70.
[0073] See Figure 11 , Figure 11 This is a structural schematic diagram of the ninth embodiment of the bridging device provided in this application. The bridging device 100 includes a first storage module 10, a second storage module 20, a third storage module 30, and a control module 40. The second storage module 20 is connected to the first storage module 10, and the control module 40 is connected to the first storage module 10, the second storage module 20, and the third storage module 30.
[0074] The first storage module 10 stores remapped address data. This remapped address data includes the mapping relationship between the bad address of the fourth storage module and the good address of the third storage module 30. The control module 40 is configured to: load the remapped address data from the first storage module 10 into the second storage module 20 after power-on; and read the remapped address data from the second storage module 20 during operation to perform data read / write operations.
[0075] The bridging device 100 further includes a configuration pin module 92 and a register module 70. The configuration pin module 92 is connected to the control module 40, and the register module 70 is also connected to the control module 40. The control module 40 is configured to modify the configuration parameters of the register module 70 based on the configuration parameters obtained from the configuration pin module 92.
[0076] In one embodiment, in conjunction with the above Figure 5 In one embodiment, the control module 40 is configured to modify the protocol configuration parameters of the register module 70 according to the configuration parameters obtained by the configuration pin module 92, so as to control the first interface module 51 to communicate with the host computer based on the selected interface protocol, and to control the second interface module 52 to communicate with the fourth storage module based on the selected interface protocol.
[0077] In another embodiment, in conjunction with the above... Figure 8 In one embodiment, the control module 40 is configured to modify the command exchange configuration parameters and data exchange configuration parameters of the register module 70 according to the configuration parameters obtained by the configuration pin module 92. The first command pin exchange module 811 and the second command pin exchange module 821 are configured to control the command pin sequence based on the command exchange configuration parameters of the register module 70. The first data pin exchange module 812 and the second data pin exchange module 822 are configured to control the data pin sequence based on the data exchange configuration parameters of the register module 70.
[0078] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.
[0079] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment, depending on actual needs.
[0080] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.
[0081] If the integrated modules in the other embodiments described above are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0082] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The term "and / or" is merely a description of the association of related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this document means two or more. In addition, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of elements, such as including at least one of A, B, and C, and may mean including any one or more elements selected from the set consisting of A, B, and C.
[0083] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A bridging device, characterized in that, The bridging device includes: First storage module; The second storage module is connected to the first storage module, and the read / write speed of the second storage module is greater than that of the first storage module. Third storage module; A control module, connected to the first storage module, the second storage module, and the third storage module, is configured to: After power-on, the remapped address data in the first storage module is loaded into the second storage module. The remapped address data includes the mapping relationship between the bad address of the fourth storage module externally connected to the bridging device and the good address of the third storage module. During operation, the remapped address data in the second storage module is read to perform data read / write operations.
2. The bridging device according to claim 1, characterized in that, The bridging device further includes: The first interface module connects the control module and the second storage module, and is configured to connect to a host computer; The second interface module connects the control module, the second storage module, and the first interface module, and is configured to connect to the fourth storage module; The control module is configured to: during operation, acquire the target bad address in the read / write instruction received by the first interface module, read the remapped address data in the second storage module to find the target good address corresponding to the target bad address, and perform data read / write operations based on the target good address.
3. The bridging device according to claim 2, characterized in that, The bridging device further includes: A first adapter module is connected to the first interface module. The first adapter module stores multiple interface protocols and is configured to control the first interface module to communicate with the host computer based on the selected interface protocol. The second adapter module is connected to the second interface module. The second adapter module stores multiple interface protocols and is configured to control the second interface module to communicate with the fourth storage module based on the selected interface protocol.
4. The bridging device according to claim 3, characterized in that, The first adapter module and the second adapter module are connected to the control module, and the first adapter module and the second adapter module are configured to select the corresponding interface protocol based on the configuration instructions of the control module.
5. The bridging device according to claim 3, characterized in that, The bridging device further includes a register module, and the first adapter module and the second adapter module are connected to the register module. The first adapter module and the second adapter module are configured to select the corresponding interface protocol based on the protocol configuration parameters of the register module.
6. The bridging device according to claim 2, characterized in that, The bridging device further includes: A first switching module is connected to the first interface module, and the first switching module is configured to control the pin order of the first interface module; The second switching module is connected to the second interface module, and the second switching module is configured to control the pin order of the second interface module.
7. The bridging device according to claim 6, characterized in that, The first switching module includes a first command pin switching module and a first data pin switching module. The first command pin switching module is configured to control the order of command pins of the first interface module, and the first data pin switching module is configured to control the order of data pins of the first interface module. The second switching module includes a second command pin switching module and a second data pin switching module. The second command pin switching module is configured to control the order of command pins of the second interface module, and the second data pin switching module is configured to control the order of data pins of the second interface module.
8. The bridging device according to claim 7, characterized in that, The bridging device further includes a register module. The first command pin exchange module, the first data pin exchange module, the second command pin exchange module, and the second data pin exchange module are connected to the register module. The first command pin exchange module and the second command pin exchange module are configured to control the command pin order based on the command exchange configuration parameters of the register module. The first data pin exchange module and the second data pin exchange module are configured to control the data pin order based on the data exchange configuration parameters of the register module.
9. The bridging device according to claim 1, characterized in that, The bridging device further includes a programming interface module connected to the control module, wherein the control module is configured to: The remapped address data obtained through the programming interface module is stored in the first storage module; or Based on the modified mapping data obtained by the programming interface module, the remapped address data loaded by the second storage module is modified.
10. The bridging device according to claim 1, characterized in that, The bridging device further includes a programming interface module and a register module, which are connected to the control module. The control module is configured to modify the configuration parameters of the register module based on the configuration parameters obtained by the programming interface module.
11. The bridging device according to claim 1, characterized in that, The bridging device further includes a configuration pin module and a register module, which are connected to the control module. The control module is configured to modify the configuration parameters of the register module based on the configuration parameters obtained by the configuration pin module.
12. The bridging device according to claim 1, characterized in that, When the fourth storage module has bad pixels, the remapped address data includes the mapping relationship between the bad pixel address of the fourth storage module and the good pixel address of the third storage module; When the fourth storage module has no bad pixels, the remapped address data includes the mapping relationship between the high-order address of the fourth storage module and the good pixel address of the third storage module. The high-order address is an address that is added sequentially in addition to the original address of the fourth storage module.
13. The bridging device according to claim 1, characterized in that, The bridging device includes identity information, which is used to represent the bad pixel address data of the fourth storage module bound to the bridging device.
14. The bridging device according to claim 1, characterized in that, The first storage module is one of EFUSE, SPI NOR or EEPROM, and the second and third storage modules are SRAM.