Universal processor instruction extraction device and method
By combining a two-level branch predictor, a decoupled queue, and an instruction hardware prefetcher, the problems of high processor front-end hardware resource overhead and high power consumption are solved, achieving efficient instruction supply and decoding optimization, reducing ineffective power consumption, and improving processor performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING YINGQI INTELLIGENT TECH CO LTD
- Filing Date
- 2026-01-20
- Publication Date
- 2026-05-12
AI Technical Summary
In existing processor front-end designs, the tight coupling between the branch predictor and the instruction fetching unit leads to high hardware resource overhead and high power consumption. Furthermore, it is difficult to balance prediction latency and accuracy. The instruction prefetching mechanism lacks precision, resulting in low cache efficiency. The bandwidth bottleneck of the decoding unit cannot match the back-end requirements, and repeated decoding causes a waste of computing power.
A two-level branch predictor design is adopted, which combines a decoupled queue with an instruction hardware prefetcher. A micro-operation cache stores decoding results and conflict information, and an asynchronous collaborative mechanism is constructed. Independent branch prediction and accurate prefetching are achieved, the decoupled queue buffers latency fluctuations, and the micro-operation cache reuses decoding logic to realize asynchronous collaboration between modules.
While maintaining processor performance, we reduce hardware resource overhead, improve instruction supply efficiency, reduce unnecessary power consumption, improve branch prediction accuracy, and optimize decoding and conflict detection efficiency.
Smart Images
Figure CN122018983A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to computer processors, and more particularly to a general-purpose processor instruction extraction apparatus and method. Background Technology
[0002] Modern out-of-order superscalar processors typically have pipeline depths exceeding 10 stages. The front-end, as the core component for instruction supply, directly determines the overall processor performance. The front-end primarily handles instruction fetching, branch prediction, decoding, and dispatching, requiring a continuous and sufficient instruction flow to the back-end to maintain high execution unit utilization. Traditional front-end designs often employ a coupled architecture, with the branch predictor and instruction fetch unit operating synchronously, and the prediction result directly driving the instruction fetch process. Furthermore, to improve prediction accuracy, mainstream solutions rely on large-capacity branch target buffers (BTBs) and complex prediction algorithms, supplemented by instruction prefetching mechanisms based on historical access patterns. The decoding stage employs multi-channel parallel decoders, decoding a fixed number of instructions per cycle.
[0003] However, existing technologies suffer from the following structural defects: First, high-precision branch prediction relies on large-scale storage arrays and complex computational logic, leading to a significant increase in area and power consumption. Furthermore, it is difficult to balance prediction latency and accuracy, especially given the persistently high error rates in predicting indirect jumps and branches with long historical patterns. Second, the instruction prefetching mechanism lacks precise coordination with branch prediction, often resulting in cache pollution due to blind prefetching, or failing to cover basic blocks across cache lines in a timely manner due to conservative strategies, leading to reduced cache efficiency. Third, the decoding unit, acting as a front-end bandwidth bottleneck, cannot match the dynamic execution demands of the back-end with its fixed throughput, and repeatedly decoding the same instructions wastes computational power. Fourth, the tightly coupled operation of various front-end submodules forces branch prediction and prefetching logic to pause in long-latency scenarios such as instruction cache misses, resulting in idle speculative execution resources and significant power consumption even under low load conditions.
[0004] These shortcomings are particularly pronounced in RISC architecture processors, where high instruction density and frequent branching make front-end power consumption and area overhead key bottlenecks restricting energy efficiency improvements. How to reduce hardware resource overhead and improve instruction supply efficiency through microarchitecture-level optimization while maintaining performance is a pressing technical problem that the industry needs to solve. Summary of the Invention
[0005] Purpose of the invention: The purpose of this invention is to provide a general-purpose processor instruction extraction device and method that can reduce hardware resource overhead and improve instruction supply efficiency while ensuring performance.
[0006] Technical solution: The general-purpose processor instruction extraction device of the present invention includes an instruction extraction unit, an instruction decoding unit, and an instruction distribution unit, and further includes:
[0007] Branch prediction unit: contains two levels of predictors, each of which can predict the branch jump address and direction;
[0008] Decoupling queue: connects the branch prediction unit and the instruction fetching unit, and is used to cache the predicted branch jump address;
[0009] Instruction hardware prefetcher: Coupled with the branch prediction unit, it is used to retrieve the instruction prefetch table based on the predicted branch jump address and generate a prefetch request, and store the prefetched instructions in the instruction cache prefetch queue for the instruction fetching unit to retrieve;
[0010] Micro-operation cache: Located downstream of the instruction decoding unit, it stores decoded instructions and corresponding resource conflict information. The information stored in the cache can be directly retrieved by the instruction dispatch unit.
[0011] By systematically integrating four modules—branch prediction unit, decoupling queue, instruction hardware prefetcher, and micro-operation cache—an asynchronous collaborative mechanism between front-end subsystems is constructed. The branch prediction unit operates independently and continuously produces predicted addresses. The decoupling queue acts as a buffer layer, absorbing latency fluctuations caused by instruction cache misses, improving the utilization of the branch prediction unit, providing sufficient instructions, and avoiding pipeline stalls. The instruction hardware prefetcher directly couples the branch prediction results, transforming predicted addresses into precise prefetch requests, avoiding the blindness caused by the lack of program flow information in traditional prefetchers. This provides sufficient instructions while avoiding unnecessary power consumption. The micro-operation cache, located downstream of the decoding unit, not only stores decoded micro-operations but also extends storage to include resource conflict information, enabling the reuse of decoding and conflict detection logic. This not only improves decoding and conflict detection efficiency and increases the attack rate of subsequent instructions but also significantly reduces front-end power consumption. In summary, the four modules of this device work together to maintain the original performance of the front-end, significantly reduce unnecessary power consumption (i.e., reduce hardware resource overhead), and improve instruction supply efficiency.
[0012] Preferably, the branch prediction unit includes a first-level predictor and a second-level predictor, wherein the first-level predictor includes a regular branch entry array and an indirect branch entry array; the regular branch entry array stores branch instruction information other than indirect branches, and the branch instruction information includes jump address and branch type attribute; the indirect branch entry array stores only the type identifier and index information of indirect branch instructions.
[0013] By employing a separate design for the first-level predictor (miniature BTB), regular branches and indirect branches are handled differently. The regular branch entry array fully stores jump addresses and type attributes, enabling fast single-cycle hits; the indirect branch entry array only stores type identifiers and index information, forcing complex prediction tasks to be routed to the second-level ITTAGE predictor, thus avoiding indirect branches occupying valuable miniature BTB storage space. This "lightweight and fast + accurate and complex" division of labor mechanism reduces the capacity and power consumption of the first-level predictor, while leveraging the accuracy advantage of the second-level predictor in handling indirect branches to ensure prediction accuracy, achieving an optimal balance between accuracy and overhead in area- and power-sensitive scenarios.
[0014] Preferably, the first-stage predictor also includes a return address stack, which is a circular buffer structure used to store the return address of the function call instruction. When the first-stage predictor predicts a return type branch and the return address stack is not empty, it will select the target address at the top of the stack as the prediction result and update the stack pointer.
[0015] Preferably, the instruction hardware prefetcher includes an instruction prefetch table and an instruction prefetch controller. The prefetch table includes multiple entries, and each entry includes multiple prefetch target addresses and corresponding cache block flag bits.
[0016] By supporting multiple prefetch target addresses and cache block flags through prefetch table entries, it can respond to single-branch prediction trigger conditions and prefetch complete basic blocks across cache lines at once.
[0017] Preferably, the instruction prefetch controller uses the branch prediction address of the branch prediction unit to index the instruction prefetch table to retrieve the address of the prefetch candidate and sends it to the instruction prefetch queue. When the instruction prefetch queue is full, the latest sent candidate address is discarded. The prefetch request is sent to the next level cache only when an instruction cache miss is detected and the miss status holding register is available.
[0018] Preferably, each entry in the prefetch table supports association with multiple prefetch target addresses under the same triggering condition; the cache block flag indicates several cache blocks in the prefetch address space.
[0019] Preferably, the micro-operation cache includes a multi-path tag array and a data array; the tag array stores entry tags and entry information, and the entry information is used to index information in the data array; the data array stores decoded instruction information and corresponding resource conflict information.
[0020] Preferably, each row of the data array includes multiple decoded instruction information and corresponding resource conflict information; the resource conflict information includes data hazards and conflict information of execution unit hardware resources, which is used by the instruction distribution unit to directly read and skip subsequent conflict detection logic.
[0021] The conflict detection logic, which was originally required to be executed repeatedly during the distribution phase, is cached. When the micro-operation cache is hit, the distribution unit does not need to re-analyze the dependencies between instructions. It can directly use the flag bit for arbitration, which greatly shortens the operation cycle, improves operating efficiency and reduces power consumption.
[0022] The general processor instruction extraction method of the present invention includes the following steps:
[0023] S1: The branch prediction unit runs independently based on the current program counter, generates prediction jump addresses and writes them into the decoupling queue;
[0024] S2: The instruction fetching unit reads the instruction fetching target address from the decoupling queue and queries the micro-operation cache and instruction cache in parallel based on the address;
[0025] S3: If the micro-operation cache is hit, the stored decoded instruction information and the corresponding resource conflict information are sent to the instruction dispatch unit; if it is not hit, the instruction cache data is processed by the instruction decoding unit and sent to the instruction dispatch unit, while the decoded instruction information and the corresponding resource conflict information are stored in the micro-operation cache.
[0026] S4: The instruction hardware prefetcher actively queries the prefetch table after the branch prediction address is generated, and initiates a prefetch request when the cache miss is satisfied and the miss status holding register is available.
[0027] Beneficial effects: The decoupled queue and independent branch prediction mechanism eliminate inter-module waiting dependencies, improving instruction supply rate while reducing unnecessary power consumption; the branch prediction unit is divided into two-stage predictors, with each stage improving prediction speed and accuracy respectively; by setting an instruction hardware prefetcher, the branch prediction-driven on-demand prefetch mechanism improves prefetch accuracy, ensuring instruction supply rate while reducing unnecessary power consumption; the micro-operation cache stores decoding results and resource conflict information, enabling multiple uses of a single decoding operation, improving subsequent processing efficiency and significantly reducing redundant power consumption. The overall effect is that, while maintaining the processor's original performance level, both the instruction supply rate and power consumption are improved. Attached Figure Description
[0028] Figure 1 This is the top-level block diagram of the device;
[0029] Figure 2 This is a schematic diagram of the microarchitecture of the branch prediction unit in this device;
[0030] Figure 3 This is a schematic diagram of the microarchitecture of the first-stage predictor in this device;
[0031] Figure 4 This is a schematic diagram of the microarchitecture of the second-stage predictor in this device;
[0032] Figure 5 This is a schematic diagram of the instruction prefetch table in this device;
[0033] Figure 6 This is a schematic diagram of the micro-architecture of the micro-operation cache of this device. Detailed Implementation
[0034] like Figure 1 As shown, the general-purpose processor instruction extraction device of the present invention includes an instruction extraction unit, an instruction decoding unit, and an instruction dispatch unit, and further includes:
[0035] Branch prediction unit: contains two levels of predictors, each of which can predict the branch jump address and direction;
[0036] Decoupling queue: connects the branch prediction unit and the instruction fetching unit, and is used to cache the predicted branch jump address;
[0037] Instruction hardware prefetcher: Coupled with the branch prediction unit, it is used to retrieve the instruction prefetch table based on the predicted branch jump address and generate a prefetch request, and store the prefetched instructions in the instruction cache prefetch queue for the instruction fetching unit to retrieve;
[0038] Micro-operation cache: Located downstream of the instruction decoding unit, it stores decoded instructions and corresponding resource conflict information. The information stored in the cache can be directly retrieved by the instruction dispatch unit.
[0039] The processor front-end is responsible for maintaining the program counters (PCs) of different threads and managing the instruction cache subsystem. Based on the program counters, it retrieves the corresponding instructions from the instruction cache and provides them to the subsequent decoding stage. The program counter is sent as an index to the branch prediction unit and the instruction cache subsystem to access the instruction cache and read instructions. The main sources of program counter updates may include: sequential instruction fetching, branch instruction jump addresses, pipeline flushing and redirection (mainly caused by control instructions), and processor exceptions.
[0040] Instructions are read and stored in the instruction buffer in units of aligned N bytes per clock cycle. In other words, N instructions are typically fetched as a block of instructions (one cache line). This design not only meets the requirement of multiple instruction issuance but also aims to reduce access to the instruction cache and provide a wider time window for filling cache lines.
[0041] In the processor front end, the branch prediction unit and the instruction fetch unit are decoupled. This means the branch prediction unit independently predicts the jump direction and target address of branch instructions, regardless of the instruction fetch pipeline's operation, and places the predicted jump instructions into a decoupled queue. Simultaneously, the instruction fetch unit can use these branch jump addresses as needed in the appropriate pipeline based on the instruction cache behavior. By using a decoupled queue, during instruction cache misses or other long-latency events in the instruction fetch pipeline, the branch jump addresses predicted by the branch prediction unit are arranged into the decoupled queue, thus generating instruction fetch addresses without pausing the instruction fetch pipeline. If the decoupled queue occupancy is high enough, "bubbles" in the branch prediction pipeline can be compressed as much as possible. If enough instruction fetch addresses are supplied to the instruction fetch unit in the pipeline, the latency is hidden.
[0042] In real-world applications, the branch prediction unit almost always maintains higher throughput than the processor execution engine. Therefore, without instruction fetch redirection (pipeline flushing), the decoupled queue is typically full. Consequently, the processor front-end implements a deeply decoupled queue to maximize the benefits of prefetching and tolerate cache miss latency.
[0043] like Figure 2 As shown, the microarchitecture of the branch prediction unit adopts a two-stage predictor design. The main predictor of each stage combines the functions of branch jump address and direction prediction. The microarchitecture of the first predictor is as follows: Figure 3 As shown, the first-stage predictor, also known as the miniature BTB (Branch Target Buffer), is used to predict all types of branch instructions. The tag of each valid entry is compared in parallel with the new instruction fetch start address (PC). Since at most one entry can be hit, if a hit occurs, the jump address and attribute field of that entry are read (the attribute field records the type of the branch instruction, used to distinguish between return, unconditional, indirect, etc., branch instructions). Otherwise, if no branch information is indexed in the miniature BTB, the pipeline continues sequential instruction fetching, and branch prediction is handled by the second-stage predictor. In this invention, the miniature BTB is divided into two parts: a regular branch entry array (i.e., ... Figure 3 The upper half stores branch instruction information other than indirect branch instructions, including tags, jump addresses, branch type attributes, and prediction counter information; there is also a separate array of indirect branch entries (i.e., ...) that stores indirect branch instruction information. Figure 3 (The lower half) This component only stores the indirect branch instruction type and related index information, but does not store the branch jump address. When an indirect branch instruction is indexed, the prediction is completed by accessing the second-level predictor.
[0044] Program (function) return is predicted via the return address stack, which tracks pairs of push and pop instructions. Each time a return instruction is executed, it matches a specific call instruction. Therefore, the push instruction pushes the return target onto the return address stack, and the corresponding return instruction pops its predicted target from the stack. The return address stack is typically implemented as a circular buffer to store the return address and a stack pointer pointing to the current top of the stack. If the resolved instruction is a call, the return address is pushed onto the return address stack; if the predicted instruction is a return, the corresponding address is popped from the return address stack. If the number of nested calls exceeds the depth of the return address stack, the oldest record will be overwritten. This means that if the program keeps calling without returning (e.g., recursion), a pop operation only occurs when a return occurs. If the number of calls exceeds the capacity of the return address stack, the newest record will overwrite the oldest record.
[0045] When making predictions, if a branch instruction with the attribute of function return is predicted in the mini BTB and the return address stack is not empty, the top target field of the return address stack entry will be used as the branch prediction result.
[0046] like Figure 4 As shown, the second-level predictor consists of an ITTAGE (existing technology) and a branch history table. This predictor has a base predictor T0 responsible for providing basic predictions, and four sets of storage blocks 1-4 with (partial) tags. These (partially) tagged components are indexed using the different branch history lengths forming the geometric sequence and a program counter (PC) hash. The base predictor can be designed as a simple predictor based on an n-bit saturated counter with direct program counter (PC) indexing. Entries in the (partially) tagged predictor components contain a prediction counter, a tag, a replacement counter, and a branch jump target address. During prediction, both the base predictor and the global predictor, which indexes the tag components using historical information, are accessed simultaneously. The base predictor provides a default prediction, while the global predictor only provides a prediction when a tag matches. The prediction result is provided by the global predictor component that hits using the longest branch history information. If no matching global predictor component is found, the prediction result from the base predictor is used.
[0047] The branch history table maintains a register of width K, storing the sequence of jumps from the K most recent branches (e.g., 111001001101… where 1 indicates a jump to the corresponding branch, and 0 indicates no jump) or a truncation or hash of the jump target address. The K most recent branches can represent the K most recent branch instructions actually encountered, or the K most recent occurrences of the same branch instruction. A left shift operation is performed when the register is updated.
[0048] See Figure 1A branch instruction pre-decoding module (existing technology) is added after the branch prediction unit. This module's function is to quickly identify unconditional branch jump instructions that the branch predictor fails to recognize, enabling early redirection of the processor's front-end pipeline and thus improving performance. Branch instruction pre-decoding is a simple check performed after instruction fetching, only determining whether the fetched instruction block contains any unpredicted unconditional jump branch instructions.
[0049] To further optimize the performance of the processor front end, this invention incorporates two components: an instruction hardware prefetcher and a micro-operation cache.
[0050] Prefetching is a technique that attempts to write data to a cache before the program accesses it, reducing the time the program waits to fetch data and thus speeding up program execution. When the processor front-end's instruction supply slows down, even the most abundant pipeline issue width and execution resources are wasted. Out-of-order instruction execution usually cannot hide instruction fetch latency, and pauses during instruction fetching typically account for a significant portion of the overall processor pipeline pauses. Therefore, instruction hardware prefetching is necessary in design.
[0051] like Figure 1 As shown, the instruction hardware prefetcher includes an instruction prefetch table and an instruction prefetch controller. When the branch prediction unit provides its prediction result, it provides the branch jump address to the instruction hardware prefetcher. The instruction prefetch controller uses this address to index the instruction prefetch table to retrieve the address of the prefetch candidate and send it to the instruction prefetch queue. If the instruction prefetch queue is full, the address will be discarded. The instruction prefetch queue probes the instruction cache with each entry and only sends a prefetch request to the next level cache if an instruction cache miss is detected. Sufficient Miss Status Holding Registers (MSHRs) must be available; otherwise, the prefetch request will also be discarded.
[0052] like Figure 5 As shown, the instruction prefetch table associates prefetch addresses with branch instructions. When the instruction fetch unit fetches multiple instructions in a single cycle, an instruction block may contain multiple branch instructions. Therefore, each entry in the instruction prefetch table contains multiple prefetch target addresses, such as... Figure 5 As shown. When they share the same triggering condition (the same branch address), each target address can also indicate any one or more of several cache blocks in the address space to be prefetched through the cache block flag. The advantage of this design is that it can handle basic blocks that span multiple cache lines very well.
[0053] The instruction fetching unit normally retrieves instructions from the decoupled queue. The instruction hardware prefetcher is used only when there is a cache miss (i.e., accessing the cache fails to retrieve the desired data), and is used to control the fetching of a certain amount of data from the lower-level cache into the current cache.
[0054] like Figure 6 As shown, the micro-operation cache includes a multi-way tag array and a data array, similar in structure to a conventional cache architecture. It consists of two parts: a tag array and a data array. The tag array can be designed as multiple blocks (multi-way), storing the tag (truncated as needed within the PC address range) and entry information for each entry in the micro-operation cache. Each entry information can point to a corresponding location in the data array. The data array has the same structure as the tag array, designed as multiple blocks (multi-way), and is indexed by the entry information in the tag array. The target address index is extracted by instruction. If the tag field matches a tag in the tag array, the instruction information related to that address exists in the corresponding line of the micro-operation cache, and can be read and sent to the instruction dispatch unit.
[0055] Because instruction fetching can be designed as an instruction block format where multiple instructions are fetched simultaneously, the decoded instruction information in each row of the data array can contain the decoded information of multiple instructions. Since data dependencies between instructions can lead to data hazards and conflicts in execution unit hardware resources, an instruction issue conflict detection module is typically designed in the instruction dispatch unit to avoid these situations. In this case, the resource conflict information of the obtained decoded instruction sequence can be stored in the micro-operation cache along with the corresponding micro-operation information. This effectively saves both decoding logic resources and instruction issue conflict detection logic resources.
[0056] Similar to the instruction cache, the micro-operation cache uses the target address index of the instruction fetch to index the micro-operation cache. If the tag field does not match the tag in the tag array, a new entry can be allocated to the micro-operation cache. When new decoding information is generated, the micro-operation cache write logic stores the decoded micro-operation and the corresponding resource conflict information into the micro-operation cache. When the micro-operation cache is full, cache lines can be prioritized based on recent information, and then the replacement line can be selected. The Least Recently Used (LRU) replacement strategy is the simplest and most widely used of these strategies. When selecting a cache line to be replaced, the LRU strategy simply eliminates the oldest (used) line from a given set of candidate cache lines.
[0057] The general processor instruction extraction method of the present invention includes the following steps:
[0058] S1: The branch prediction unit runs independently based on the current program counter, generates prediction jump addresses and writes them into the decoupling queue;
[0059] S2: The instruction fetching unit reads the instruction fetching target address from the decoupling queue and queries the micro-operation cache and instruction cache in parallel based on the address;
[0060] S3: If the micro-operation cache is hit, the stored decoded instruction information and the corresponding resource conflict information are sent to the instruction dispatch unit; if it is not hit, the instruction cache data is processed by the instruction decoding unit and sent to the instruction dispatch unit, while the decoded instruction information and the corresponding resource conflict information are stored in the micro-operation cache.
[0061] S4: The instruction hardware prefetcher actively queries the prefetch table after the branch prediction address is generated, and initiates a prefetch request when the cache miss is satisfied and the miss status holding register is available.
Claims
1. A general-purpose processor instruction extraction device, comprising an instruction extraction unit, an instruction decoding unit, and an instruction dispatch unit, characterized in that, Also includes: Branch prediction unit: contains two levels of predictors, each of which can predict the branch jump address and direction; Decoupling queue: connects the branch prediction unit and the instruction fetching unit, and is used to cache the predicted branch jump address; Instruction hardware prefetcher: Coupled with the branch prediction unit, it is used to retrieve the instruction prefetch table based on the predicted branch jump address and generate a prefetch request, and store the prefetched instructions in the instruction cache prefetch queue for the instruction fetching unit to retrieve; Micro-operation cache: Located downstream of the instruction decoding unit, it stores decoded instructions and corresponding resource conflict information. The information stored in the cache can be directly retrieved by the instruction dispatch unit.
2. The apparatus according to claim 1, characterized in that: The branch prediction unit includes a first-level predictor and a second-level predictor. The first-level predictor includes a regular branch entry array and an indirect branch entry array. The regular branch entry array stores branch instruction information other than indirect branches. The branch instruction information includes jump address and branch type attribute. The indirect branch entry array only stores the type identifier and index information of indirect branch instructions.
3. The apparatus according to claim 2, characterized in that: The first-stage predictor also includes a return address stack, which is a circular buffer structure used to store the return address of the function call instruction. When the first-stage predictor predicts a return type branch and the return address stack is not empty, it will select the target address at the top of the stack as the prediction result and update the stack pointer.
4. The apparatus according to claim 1, characterized in that: The instruction hardware prefetcher includes an instruction prefetch table and an instruction prefetch controller. The prefetch table includes multiple entries, and each entry includes multiple prefetch target addresses and corresponding cache block flags.
5. The apparatus according to claim 1, characterized in that: The instruction prefetch controller indexes the instruction prefetch table with the branch prediction address of the branch prediction unit to retrieve the address of the prefetch candidate and sends it to the instruction prefetch queue. When the instruction prefetch queue is full, the latest sent candidate address is discarded. The prefetch request is sent to the next level cache only when an instruction cache miss is detected and the miss status holding register is available.
6. The apparatus according to claim 4, characterized in that: Each entry in the prefetch table supports association with multiple prefetch target addresses under the same trigger condition; the cache block flag indicates several cache blocks in the prefetch address space.
7. The apparatus according to claim 1, characterized in that: The micro-operation cache includes a multi-path tag array and a data array; the tag array stores entry tags and entry information, and the entry information is used to index information in the data array. The data array stores the decoded instruction information and the corresponding resource conflict information.
8. The apparatus according to claim 7, characterized in that: Each row of the data array includes multiple decoded instruction information and corresponding resource conflict information; the resource conflict information includes data hazards and conflict information of execution unit hardware resources, which is used by the instruction distribution unit to directly read and skip subsequent conflict detection logic.
9. A general-purpose processor instruction extraction method, characterized in that, Includes the following steps: S1: The branch prediction unit runs independently based on the current program counter, generates prediction jump addresses and writes them into the decoupling queue; S2: The instruction fetching unit reads the instruction fetching target address from the decoupling queue and queries the micro-operation cache and instruction cache in parallel based on the address; S3: If the micro-operation cache is hit, the stored decoded instruction information and the corresponding resource conflict information are sent to the instruction dispatch unit; if it is not hit, the instruction cache data is processed by the instruction decoding unit and sent to the instruction dispatch unit, while the decoded instruction information and the corresponding resource conflict information are stored in the micro-operation cache. S4: The instruction hardware prefetcher actively queries the prefetch table after the branch prediction address is generated, and initiates a prefetch request when the cache miss is satisfied and the miss status holding register is available.