Processor, chip, electronic equipment and instruction processing method

Abstract

The embodiment of the invention provides a processor, a chip, electronic equipment and an instruction processing method, and belongs to the technical field of chips. The processor comprises an instruction processing unit and a stack. The instruction processing unit is used for generating current instruction execution information and storing the current instruction execution information to the stack in the current instruction execution process; the current instruction execution information comprises address information of a next instruction to be executed, address information of a convergent point instruction and recursive depth information; the recursion depth information represents a difference value between the executed times of the function call instruction and the executed times of the return instruction; after the current instruction is executed, instruction execution information is read from the stack; and if it is determined that the next instruction address to be executed is the same as the convergent point instruction address and the difference value is 0, performing a stack-out operation on the stack, and returning to the operation of reading the instruction execution information from the stack until the stack is empty. According to the method and the device, the problem of calculation error of a thread program counter in a recursive function nesting scene can be avoided.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a processor, chip, electronic device, and instruction processing method. Background Technology

[0002] To improve computing performance, a SIMT (Single Instruction Multi Thread) architecture can be adopted in processors that support parallel processing. SIMT refers to binding multiple threads together to execute instruction stream operations in lockstep. During instruction execution, different threads may enter different instruction branches within conditional branches. For example, when encountering a conditional branch instruction, the execution results of some threads in the thread bundle may satisfy the condition indicated by the branch instruction, while the execution results of other threads may not satisfy the condition. The threads that satisfy the condition will perform a branch transfer and execute the first branch, while the other threads will execute a second branch different from the first branch.

[0003] Since different threads may correspond to different branch paths, in order to reduce the communication cost between the compiler and the processor and improve instruction processing efficiency, a stack corresponding to SIMT is usually set in the processor: SIMT_Stack, which is used to store the execution context and temporary data during thread execution to assist the processor in completing the instruction processing process.

[0004] The above instruction processing based on SIMT_Stack, once a thread reaches the convergence point—that is, when the next instruction to be executed by the thread is the same as the instruction at the convergence point (hereinafter referred to as the convergence point instruction)—a pop operation is performed on the thread-related data stored in the stack to allow the threads to converge and execute the instruction at the convergence point in parallel. Using this instruction processing method, in scenarios with nested recursive functions, will cause errors in the calculation of the thread's program counter. Summary of the Invention

[0005] In view of the above, embodiments of this disclosure provide a processor, chip, electronic device, and instruction processing method to at least solve or alleviate the above problems.

[0006] According to a first aspect of the present disclosure, a processor is provided, the processor comprising: an instruction processing unit and a stack;

[0007] The instruction processing unit is configured to: generate current instruction execution information and store the current instruction execution information into the stack during the execution of the current instruction; the current instruction execution information includes: address information of the next instruction to be executed, address information of the convergence instruction, and recursion depth information; the recursion depth information represents the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed; after the current instruction is executed, read instruction execution information from the stack; if it is determined based on the read instruction execution information that the address of the next instruction to be executed is the same as the address of the convergence instruction, and the difference is 0, then perform a pop operation on the stack and return the operation of reading instruction execution information from the stack until the stack is empty.

[0008] According to a second aspect of the present disclosure, a chip is provided, comprising: the processor described in the first aspect above.

[0009] According to a third aspect of the present disclosure, an electronic device is provided, comprising: the processor described in the first aspect above, or the chip described in the second aspect above.

[0010] According to a fourth aspect of the present disclosure, an instruction processing method is provided, applied to a processor including an instruction processing unit and a stack, the method comprising:

[0011] During the execution of the current instruction, the instruction processing unit generates current instruction execution information and stores it in the stack. This current instruction execution information includes: the instruction address information of the next instruction to be executed, the address information of the convergence instruction, and recursion depth information. The recursion depth information represents the difference between the number of times a function call instruction has been executed and the number of times a function return instruction has been executed. After the current instruction is completed, the instruction processing unit reads instruction execution information from the stack. If, based on the read instruction execution information, it is determined that the address of the next instruction to be executed is the same as the address of the convergence instruction, and the difference is 0, a pop operation is performed on the stack, and the operation of reading instruction execution information from the stack is returned until the stack is empty.

[0012] According to the processor provided in this embodiment, during instruction execution, the instruction processing unit adds recursion depth information to the stack storage, representing the difference between the number of times function call instructions have been executed and the number of times function return instructions have been executed. Then, when performing thread pop-and-convergence judgment, two factors are considered simultaneously: whether the next instruction to be executed is a convergence instruction, and whether the number of times function call instructions have been executed equals the number of times function return instructions have been executed, i.e., whether the recursion depths of the threads to be converged are consistent. Only when both factors are met is a pop operation performed. This ensures that the recursion depths of all threads converging at the convergence point are the same, meaning that only threads with the same recursion depth converge to the same convergence instruction. Because the recursion depths of all threads at the convergence point are the same, it ensures that the software stack pointer shared by all threads is the same as the actual stack pointer of each thread, thereby avoiding the problem of thread calculation errors in nested recursive function scenarios. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is a schematic diagram of the instruction flow under the SIMT architecture;

[0015] Figure 2 This is a schematic diagram of the instruction flow in a nested recursive function scenario;

[0016] Figure 3 This is a schematic diagram of the structure of a processor according to an embodiment of the present disclosure;

[0017] Figures 4-7 This is a schematic diagram illustrating the process of processing instruction flow in a nested recursive function scenario using the solution disclosed in this embodiment.

[0018] Figure 8 This is a flowchart of an instruction processing method according to an embodiment of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0020] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0021] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0022] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0023] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0024] General Overview of this Disclosure

[0025] To facilitate understanding, the relevant technologies involved in the embodiments of this disclosure will be explained first:

[0026] I. Instruction Flow under SIMT Architecture:

[0027] See Figure 1 , Figure 1 This is a schematic diagram of the instruction flow under the SIMT architecture. Figure 1 The thread bundle in the SIMT architecture shown contains four threads: thread 1, thread 2, thread 3, and thread 4. The instruction stream consists of seven instructions: A, B, C, D, E, F, and G. Each instruction node has a mask value, which determines which threads execute the instructions at that node and which do not. For example, for instruction node A, the mask value 1111 indicates that all four threads execute the instruction; for instruction node C, the mask value 1110 indicates that threads 1-3 execute the instruction, while thread 4 does not; and for instruction node B, the mask value is the opposite of the instruction node mask, specifically 0001, indicating that thread 4 executes the instruction, while threads 1-3 do not.

[0028] exist Figure 1 In the instruction stream shown, instructions A and C are both branch jump instructions. When the instruction execution reaches point A, each thread will jump to a different instruction branch according to the branch conditions: in the first branch, threads 1, 2, and 3 will jump to instruction C; in the second branch, thread 4 will jump to instruction B. Regarding the first branch, when the execution reaches the branch jump instruction C, threads 1, 2, and 3 will jump to different sub-branches according to the branch conditions: in the first sub-branch, thread 1 will jump to instruction E; in the second sub-branch, threads 2 and 3 will jump to instruction E. Afterward, the first and second sub-branches will converge at convergence point F; finally, the first and second branches will converge at convergence point G.

[0029] II. Instruction stream processing based on SIMT_Stack:

[0030] For processors with a SIMT architecture, in order to reduce the communication cost between the compiler and the processor and improve execution efficiency, a stack can be set up inside the processor to store the execution context and temporary data information during thread execution, thereby assisting the processor in completing the instruction processing. For ease of recording, the stack set up inside the processor in this embodiment is referred to as SIMT_Stack. During instruction execution, the instruction processing unit can calculate instruction execution information in real time and store this information in the SIMT_Stack. In related technologies, the aforementioned instruction execution information typically includes: information about the next instruction to be executed, information about converged instructions, and a mask value at the node where the next instruction to be executed is located. The information about the next instruction to be executed can typically be information representing the storage location of the next instruction to be executed, such as the value of the program counter (NPC) corresponding to the next instruction to be executed. The information about converged instructions can typically be information representing the storage location of converged instructions, such as the value of the program counter (RPC) corresponding to the converged instructions. The mask value at the node where the next instruction to be executed is located can typically correspond to the value of the vector predicate register (VP). The mask value can typically be represented by N binary numbers, each binary number corresponding to a thread. When the binary number is 1, it indicates that the corresponding thread executes the next instruction to be executed; conversely, when the binary number is 0, it indicates that the corresponding thread does not execute the next instruction to be executed.

[0031] The following combination Figure 1 The instruction stream shown explains the instruction stream processing procedure based on SIMT_Stack:

[0032] Assuming that at time T0, instruction execution reaches point A, and since point A is a branch jump instruction, the instruction processing unit will generate instruction execution information for different branches and push this information into the SIMT_Stack respectively. Specifically:

[0033] First stack: G, the convergence point after the branch at point A.

[0034] Second stack: Branch after point A: AC (Since this branch corresponds to a large number of threads, information is pushed onto the stack first, that is: the instruction stream in this branch is executed later).

[0035] Top element of the stack: Another branch of the fork at point A: AB (Since the number of threads corresponding to this branch is small, the information is pushed onto the stack later, that is: the instruction stream in this branch is executed first).

[0036] Ultimately, we can obtain a SIMT_Stack in the following form:

[0037] RPC NPC VP / G 1111 G C 1110 Top element of stack G B 0001

[0038] After instruction A is executed, the execution of subsequent instructions continues according to the top element of the stack, i.e., B is executed. At this time, NPC = RPC = G in the top element of the stack, and a pop operation is performed on the top element of the stack. That is, after instruction B is executed, the execution of the AB branch is paused and the AC branch is executed instead, thus obtaining the updated SIMT_Stack, as shown in the table below:

[0039]

[0040] At time T1: Instruction execution reaches point C, and another branch occurs. The instruction processing unit generates instruction execution information for each branch and pushes this information onto the SIMT_Stack. Specifically:

[0041] First stack: the convergence point F after the branch at point C.

[0042] Second stack: A branch that forks at point C: CD.

[0043] Top element of the stack: another branch from point C: CE.

[0044] Ultimately, we can obtain a SIMT_Stack in the following form:

[0045]

[0046] After instruction C is completed, the execution of subsequent instructions continues according to the top element of the stack, i.e., E is executed. At this time, NPC = RPC = F in the top element of the stack. A pop operation is performed on the top element of the stack. That is, after instruction E is completed, the execution of the CE branch is paused and the CD branch is executed instead, thus obtaining the updated SIMT_Stack, as shown in the table below:

[0047]

[0048] At time T2: Instruction execution reaches point C, at which point NPC = RPC = F, and the stack continues to pop. At this point, all branches that branched off from point C converge at point F.

[0049]

[0050]

[0051] At time T3: Instruction execution reaches point F, at which point NPC = RPC = G, and the stack continues to pop instructions. All branches converge at point G. The information in SIMT_Stack is shown in the table below:

[0052]

[0053] When instruction G finishes execution, SIMT_Stack becomes empty. At this point... Figure 1 The instruction stream shown has been executed.

[0054] As can be seen from the above, in the relevant instruction stream processing based on SIMT_Stack, once a thread reaches the convergence point, that is, when the next instruction to be executed by the thread is the same as the convergence instruction, the relevant data of the thread stored in the stack will be popped to allow the threads to converge, and then the instructions in the convergence point and subsequent paths will be executed in parallel.

[0055] III. Instruction Flow in Nested Recursive Function Scenarios:

[0056] A recursive function is a function that calls itself within its function body. Executing a recursive function will repeatedly call itself, entering a new level each time it is called. For example, the factorial function is a typical recursive function, f(n) = n * f(n-1), where f(n) represents the factorial of n and f(n-1) represents the factorial of n-1.

[0057] The following explanation uses the factorial function as an example to illustrate the instruction flow in a nested recursive function scenario:

[0058] Assume the SIMT architecture has three threads: thread 1, thread 2, and thread 3. Thread 1 calculates 1!, thread 2 calculates 2!, and thread 3 calculates 3!. The pseudocode for this calculation task is as follows:

[0059]

[0060] Compiling the above pseudocode yields the following: Figure 2 The instruction stream shown is specifically:

[0061] Instruction block A: Corresponds to the instruction block in the main program. The specific operations performed include: assigning the thread number value tid.x to the vector register V1, and assigning V1 to the vector register V4; in addition, at instruction block A, the value of the software-maintained stack pointer SP is also initialized. For example, the initial value of SP can be set to 0.

[0062] B instruction block: Factorial function call instruction block. The specific operations performed include: calling the factorial function and assigning the address of the next instruction block C to scalar register x1, so that execution returns to instruction block C after the function call completes.

[0063] The D instruction block performs the following operations: assign SP+1 to SP; store x1 (the storage address of x1 is related to the current SP value); assign the value of V4 to register V3; store V3 (the storage address of V3 is related to the current SP value); compare the values ​​of each thread in register V3 with 1, and if they are the same, set the mask of the corresponding thread in the vector predicate register VP to 1, otherwise set the mask of the corresponding thread to 0.

[0064] Instruction block E: Branch jump instruction block. The specific operations performed include: based on the mask values ​​of each thread in the vector predicate register VP, performing different branch jumps on each thread in the thread bundle: for threads with a mask value of 1, jump to instruction block F; for threads with a mask value of 0, jump to instruction block G. Additionally, the convergence point is recorded as instruction block J.

[0065] F instruction block: if branch instruction block. The specific operations performed include: setting the value of register V2 to 1 and jumping to instruction block J.

[0066] G instruction block: else branch instruction block. The specific operation performed includes: assigning V3-1 to V4.

[0067] H instruction block: Factorial function call instruction. The specific operations performed include: calling the factorial function and assigning the address of instruction block i to register x1, so that the function return instruction can return to the address corresponding to instruction block i after the function call is completed.

[0068] J instruction block: Function return instruction. The specific operations performed include: loading the value of x1 based on the memory address associated with the current SP; assigning SP-1 to SP; calling the function return instruction, with the return address being the value stored in the current x1; specifically, if SP = 0 at this time, the function return instruction will return to the C instruction block.

[0069] Instruction block I: Assign V2 to V5; assign SP+1 to SP; load the value of V3 (the storage address of V3 is related to the current value of SP); assign SP-1 to SP; assign the product of V3 and V5 to V2; jump to instruction block J.

[0070] C instruction block: corresponds to subsequent instructions in the main program.

[0071] against Figure 2The instruction flow in the nested recursive function scenario shown has the following correct instruction execution paths for a single thread: Thread 1: ABDEFJC; Thread 2: ABDEGHDEFJIJC; Thread 3: ABDEGHDEGHDEFJIJIJC. Analysis shows that for correct instruction flow execution, the correct instruction convergence method should be: convergence of the three threads when Thread 1 executes to instruction block J, Thread 2 executes to the second instruction block J, and Thread 3 executes to the third instruction block J.

[0072] If the above instruction stream processing procedure based on SIMT_Stack is adopted... Figure 2 In the nested recursive function scenario shown, instruction stream processing is affected by the fact that in the SIMT_Stack-based instruction stream processing, instruction aggregation occurs when the next instruction to be executed by a thread is the same as the converged instruction. This causes the three threads to perform an incorrect instruction aggregation when they all reach the first instruction block J. After that, the three threads execute J and subsequent instructions in parallel.

[0073] Regarding the J instruction block, it needs to load x1 to return and execute the instruction at x1. As mentioned in the description of the J instruction block above, the storage address of x1 is related to the current SP value. That is, for a single thread, whether the J instruction block can be executed correctly depends on the actual stack pointer of that thread (denoted as C_SP for ease of description). In the SIMT structure, all threads in the thread bundle share a single software stack pointer (denoted as Warp_SP for ease of description). In the scenario of nested recursive functions, the recursion depth (i.e., the number of function calls) of different threads is not the same. The instruction execution process of the thread with a larger recursion depth (i.e., thread 3) will change the value of Warp_SP. This means that at the convergence point J, the value of Warp_SP only represents the actual stack pointer of the thread with a larger recursion depth (i.e., thread 3), and not the actual stack pointers of the other threads. If the threads are converged at this point, and each thread performs the convergence point instruction block calculation based on Warp_SP, the calculation result will be incorrect. Specifically, although the next instruction to be executed for each thread is J, the number of recursive function calls for thread 3 is 3, the number of recursive function calls for thread 2 is 2, and the number of recursive function calls for thread 1 is only 1. That is, the recursion depth of each thread is different, and the actual stack pointers of each thread are different. This will cause thread 1 to return to instruction block I instead of instruction block C when executing the function return instruction, resulting in a program error.

[0074] The processor provided in this embodiment adds recursion depth information, representing the difference between the number of times function call instructions have been executed and the number of times function return instructions have been executed, to the information stored in the stack SIMT_Stack during instruction execution. Then, when determining thread popping and converging, two factors are considered simultaneously: whether the next instruction to be executed is a convergence instruction, and whether the number of times function call instructions have been executed equals the number of times function return instructions have been executed, i.e., whether the recursion depths of the threads to be converged are consistent. Only when both factors are met is a popping operation performed. This ensures that the recursion depths of all threads converging at the convergence point are the same, meaning that threads with the same recursion depth converge to the same convergence instruction. Because the recursion depths of all threads at the convergence point are the same, it ensures that the software stack pointer shared by all threads is the same as the actual stack pointer of each thread, thereby avoiding the problem of thread calculation errors in nested recursive function scenarios.

[0075] Detailed implementation process of the embodiments disclosed herein

[0076] See Figure 2 , Figure 2 This is a schematic diagram of the structure of a processor according to an embodiment of the present disclosure. The processor 100 includes: an instruction processing unit 1002 and a stack 1004;

[0077] Instruction processing unit 1002, used for:

[0078] During the execution of the current instruction, current instruction execution information is generated and stored on the stack. The current instruction execution information includes: the address information of the next instruction to be executed, the address information of the convergence instruction, and the recursion depth information. The recursion depth information represents the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed.

[0079] After the current instruction is executed, read the instruction execution information from the stack. If the address of the next instruction to be executed is the same as the address of the merging instruction based on the read instruction execution information, and the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed is 0, then pop the stack and return the operation of reading instruction execution information from the stack until the stack is empty.

[0080] Specifically, the processor 100 in this embodiment can be a processor supporting the SIMT architecture, and the instruction processing unit 1002 can run multiple threads. To improve processing performance, during instruction execution, the multiple threads are locked together to execute each instruction in the instruction stream in lockstep. In this embodiment, the number of instruction processing units 1002 included in the processor 100, and the number of threads running in parallel in each instruction processing unit 1002, are not limited and can be customized according to actual conditions.

[0081] After obtaining the program code to be executed, the compiler can compile the code to determine the instruction stream corresponding to the code. Then, the instruction processing unit 1002 in the processor 100 can execute each instruction in the instruction stream sequentially until the instruction execution is completed. Specifically, in order to reduce the communication cost between the compiler and the processor and improve instruction execution efficiency, a stack 1004 can be set up in the processor 100 to store instruction execution information during thread execution, so as to assist the instruction execution unit 1002 in completing the instruction processing process.

[0082] The specific process is as follows: After the instruction processing unit 1002 obtains an instruction, it can calculate the address information of the next instruction to be executed, the address information of the convergence instruction corresponding to the current instruction, and the recursion depth information representing the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed during the execution of the current instruction. Then, the calculated information is stored as the current instruction execution information in the stack 1004 of the processor 100. When the obtained current instruction is executed, the instruction execution information can be read from the stack 1004. The instruction is obtained according to the address information of the next instruction to be executed in the instruction execution information. The obtained new instruction is used as the current instruction. The instruction execution process and the current instruction execution information calculation process are repeated until the elements in the stack 1004 are empty. At this time, the instruction processing process ends.

[0083] In this embodiment of the disclosure, when generating the current instruction execution information, the executed instructions are statistically analyzed to determine the recursion depth information, that is, to determine the difference between the number of function calls executed and the number of function return instructions executed during the current instruction execution process. In this embodiment of the disclosure, the specific presentation form of the recursive function information in the stack 1004 is not limited. For example, a single parameter, the recursion depth value, can be used to represent the above-mentioned recursion depth information. In this case, when the recursion depth value is 0, it indicates that the number of recursive function calls executed is the same as the number of function return instructions executed. Alternatively, the function call count value and the return count value can be used together to represent the above-mentioned recursion depth information. In this case, the difference between the function call count value and the return count value represents the difference between the number of times the function call instructions have been executed and the number of times the function return instructions have been executed.

[0084] The method described above, which uses both function call counts and return counts to represent recursion depth, allows the instruction processing unit 1002 to obtain the current instruction execution information through simple statistical operations during instruction execution. This method is characterized by its simplicity and high computational efficiency. In contrast, the method using a single recursion depth value to represent recursion depth requires only one parameter to be stored in the stack 1004. Furthermore, no additional subtraction operation is needed. This parameter directly reflects the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed. Therefore, this representation method effectively saves storage space.

[0085] According to the processor 100 provided in this embodiment, during instruction execution, the instruction processing unit 1002 adds recursion depth information, which characterizes the difference between the number of times a function call instruction has been executed and the number of times a function return instruction has been executed, to the stack storage 1004. Then, when performing thread pop-and-convergence judgment, two factors are considered simultaneously: whether the next instruction to be executed is a convergence instruction, and whether the number of times a function call instruction has been executed equals the number of times a function return instruction has been executed, i.e., whether the recursion depths of the threads to be converged are consistent. Only when both factors are met is a pop operation performed. This ensures that the recursion depths of all threads converging at the convergence point are the same, meaning that threads with the same recursion depth converge to the same convergence instruction. Because the recursion depths of all threads at the convergence point are the same, it ensures that the software stack pointer shared by all threads is the same as the actual stack pointer of each thread, thereby avoiding the problem of thread calculation errors in nested recursive function scenarios.

[0086] Optionally, in some embodiments, if the recursion depth information is presented in the form of a recursion depth value, the process of generating the current instruction execution information described above may include:

[0087] If the current instruction is a function call instruction, then the sum of the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information;

[0088] If the current instruction is a function return instruction, then the difference between the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information;

[0089] Among them, the previous instruction execution information is the instruction execution information generated during the execution of the previous instruction before the current instruction is executed;

[0090] Store the current instruction execution information onto stack 1004, including:

[0091] Update the top element of stack 1004 with the current instruction execution information.

[0092] Specifically, when using the recursion depth value as a parameter to represent recursion depth information, the recursion depth value can be updated according to the meaning of the recursion depth information. The update rule is: when executing a function call instruction, the recursion depth value is increased; conversely, when executing a function return instruction, the recursion depth value is decreased. Further, the update rule can be specifically set as follows: if the current instruction is a function call instruction, a first preset value is added to the previously calculated recursion depth value to obtain the updated recursion depth value; conversely, if the current instruction is a function return instruction, the first preset value is subtracted from the previously calculated recursion depth value to obtain the updated recursion depth value.

[0093] Function call instructions and function return instructions are both non-branch jump instructions, so no new stack element will be generated in stack 1004, which stores instruction execution information. In this case, when storing the generated current instruction execution information into stack 1004, the top element of stack 1004 can be updated using the newly generated current instruction execution information.

[0094] In this embodiment, the specific value of the first preset value is not limited, and any positive value can be selected as the first preset value in this application example according to the actual situation. In order to facilitate calculation and save storage space, in some optional embodiments, the first preset value can be set to 1. That is, if the current instruction is a function call instruction, the recursion depth value obtained by the previous calculation is increased by 1 to obtain the updated recursion depth value; conversely, if the current instruction is a function return instruction, the recursion depth value obtained by the previous calculation is subtracted by 1 to obtain the updated recursion depth value.

[0095] In addition, as described above, in the above embodiments of this disclosure, since only one parameter needs to be stored in the stack 1004, and no additional subtraction operation is required, the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed can be intuitively reflected by this parameter, thus effectively saving storage space.

[0096] Optionally, in some embodiments, if the current instruction is a branch jump instruction, the recursion depth value in the generated current instruction execution information is set to a second preset value;

[0097] Store the current instruction execution information at the top of the stack, including:

[0098] Push the current instruction execution information onto the stack;

[0099] If, based on the read instruction execution information, it is determined that the address of the next instruction to be executed is the same as the address of the convergence instruction, and the difference is 0, then a pop operation is performed on the top element of the stack, including:

[0100] If the address of the next instruction to be executed is the same as the address of the convergence instruction based on the read instruction execution information, and the recursion depth value is equal to the second preset value, then a pop operation is performed on the top element of the stack.

[0101] Specifically, if the current instruction is a branch jump instruction, it means that after the current instruction is executed, the subsequent instruction path will fork, and different threads may enter different branches. At this time, a new stack element will be generated in the stack 1004 that stores instruction execution information. Therefore, when storing the generated current instruction execution information into the stack 1004, a push operation can be performed on the stack 1004 to push the newly generated current instruction execution information onto the stack 1004.

[0102] In the embodiments disclosed above, for cases where different instruction branches will subsequently appear, the recursion depth value in the generated current instruction execution information is set to a second preset value. That is, at the instruction fork position, the initial recursion depth value of each branch is unified. Subsequently, when performing stack pop and convergence judgment on the threads of each branch, in addition to considering whether the next instruction to be executed is a convergence point instruction, the recursion depth value is also considered to be equal to the aforementioned second preset value. Through the above processing method, for different branches, when the next instruction to be executed is a convergence instruction and the recursion depth value is equal to the aforementioned second preset value, it indicates that the difference between the number of times the thread executes the function call instruction and the number of times it executes the function return instruction is equal. Therefore, in this case, performing the stack pop and convergence operation can ensure that the recursion depth of each thread that finally converges at the convergence point is consistent.

[0103] In this embodiment, the specific value of the second preset value is not limited, and any value can be selected as the second preset value in this application example according to the actual situation. In order to facilitate calculation and save storage space, in some optional embodiments, the second preset value can be set to 0, that is: if the current instruction is a branch jump instruction, new current instruction execution information is generated, the current instruction execution information is pushed onto the stack, and all recursion depth values ​​in the information are set to 0.

[0104] Optionally, in some embodiments, the recursion depth information includes: a function call count value and a return count value; wherein, the function call count value represents the number of times the function call instruction has been executed; and the return count value represents the number of times the function return instruction has been executed.

[0105] If the current instruction is a function call instruction, then the sum of the function call count in the previous instruction execution information and the third preset value is used as the function call count in the current instruction execution information; the return count in the previous instruction execution information is used as the return count in the current instruction execution information.

[0106] If the current instruction is a function return instruction, then the function call count value in the previous instruction execution information is determined as the function call count value in the current instruction execution information; the sum of the return count value in the previous instruction execution information and the third preset value is determined as the return count value in the current instruction execution information.

[0107] Specifically, as described above, in the example above, the function call count and the return count are used as two parameters to jointly characterize the recursion depth information. In this case, the difference between the function call count and the return count represents the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed.

[0108] When the current instruction is a function call instruction, the function call count, which represents the number of times the function call instruction has been executed, is increased, while the return count, which represents the number of times the function return instruction has been executed, remains unchanged. Conversely, when the current instruction is a function return instruction, the return count is increased, while the function call count remains unchanged. Furthermore, it can be set that: when the current instruction is a function call instruction, a third preset value is added to the previously calculated function call count to obtain an updated function call count; and when the current instruction is a function return instruction, a third preset value is added to the previously calculated return count to obtain an updated return count.

[0109] In this embodiment, the specific value of the third preset value is not limited, and any positive value can be selected as the third preset value in this application example according to the actual situation. In order to facilitate calculation and save storage space, in some optional embodiments, the third preset value can also be set to 1, that is: when the current instruction is a function call instruction, the function call count value obtained by the previous calculation is added by 1 to obtain the updated function call count value; when the current instruction is a function return instruction, the return count value obtained by the previous calculation is added by 1 to obtain the updated return count value.

[0110] Optionally, in some embodiments, if it is determined based on the read instruction execution information that the instruction address of the next instruction to be executed is different from the address of the convergence instruction, and / or it is determined that the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed is non-zero, then the next instruction to be executed is taken as the updated current instruction, and the steps of generating current instruction execution information and storing current instruction execution information on the stack during the execution of the current instruction are returned until the stack is empty.

[0111] Specifically, if the next instruction to be executed is different from the convergence instruction, or if the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed is not 0, that is, the number of times the function call instruction has been executed and the number of times the function return instruction has been executed are not equal, it indicates that the thread convergence condition is not met at this time. Therefore, the next instruction to be executed can be used as the new current instruction, and the previous instruction execution operation can be repeated.

[0112] To facilitate understanding of the technical solutions of the embodiments of this disclosure, and the effects that the embodiments of this disclosure can achieve, the following also uses... Figure 2 Taking the instruction stream in a nested recursive function scenario as an example, the specific process of instruction stream processing using the solution provided in this embodiment is explained in detail:

[0113] See Figure 4As shown in (1), during the execution of A, the current instruction (denoted as CPC) of each thread is A, and the next instruction to be executed (denoted as NPC) is B; the mask value is 111; Warp_SP = 0. Correspondingly, V4 of thread 1 is 1, V4 of thread 2 is 2, and V4 of thread 3 is 3; at this time, the actual stack pointer C_SP = Warp_SP = 0 of each thread; since the function call calculation has not yet been performed, V2 of each thread is a random value; during the execution of A, the instruction processing unit 1002 will generate the current instruction execution information and store the information in the stack 1004, specifically: NPC = B, VP (that is, the above mask value) = 111, recursion depth value (the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed) RC (Recurssive Counter) = 0 (since A is neither a function call instruction nor a function return instruction, RC here takes the initial value of 0). After A is executed, the next instruction to be executed will be B.

[0114] See Figure 4 As shown in (2), during the execution of B, the current instruction (denoted as CPC) of each thread is also B, and the next instruction to be executed (denoted as NPC) is D; the mask value is 111; Warp_SP = 0. Correspondingly, the V4 value, V2 value, and actual stack pointer C_SP of each thread remain unchanged; since the B instruction is a function call instruction, the RC stored in stack 1004 changes from 0 to 1 (here, the first preset value is set to 1 for example, and this setting method does not constitute a restriction on the value of the first preset value), and the rest of the information remains unchanged. After the B instruction is executed, the next instruction to be executed will be D.

[0115] See Figure 4 As shown in (3), during the execution of D, the current instruction (denoted as CPC) of each thread is also D, and the next instruction to be executed (denoted as NPC) is E; the mask value is 111; since the specific operation at D includes: assigning SP+1 to SP, during the execution of D, the C_SP and Warp_SP of each thread are changed from 0 to 1; the V4 and V2 values ​​of each thread remain unchanged; the NPC of the top element of stack 1004 changes from D to E, and the rest of the information remains unchanged. After D is executed, the next instruction to be executed will be E.

[0116] See Figure 4As shown in (4), during the execution of E, the CPC of each thread is E; since E is a branch jump instruction, the threads will perform different branch jumps after E: thread 1 jumps to F, and threads 2 and 3 jump to G; the V4 value, V2 value, C_SP, and Warp_SP of each thread remain unchanged; since E is a branch jump instruction, a stack push operation will be performed, pushing the newly generated current instruction execution information into stack 1004, and setting RC in the newly pushed instruction execution information to 0 (see [reference]). Figure 4 In (4) of the stack table, the last two rows of stack elements are exemplarily set to 0 for the second preset value. This setting does not constitute a restriction on the value of the second preset value. In addition, for the instructions after the fork, since the number of threads corresponding to F is less than the number of threads corresponding to G, in order to save hardware stack depth, F is executed first, that is, the next instruction to be executed is determined to be F.

[0117] See Figure 4 As shown in (5), during the execution of F by thread 1, the CPC of thread 1 is F, and the NPC of thread 1 is J (this instruction point is also the convergence point RPC); the CPC of threads 2 and 3 are both E, and the NPC is both G; according to the specific operation of point F, the V2 value of thread 1 can be changed from a random value to 1; as for the top element in stack 1004, since NPC = RPC = J, and RC = 0, a pop operation can be performed on the top element (that is, the element is removed from stack 1004), so that the previous stack element is used as the new top element. After thread 1 finishes executing B, threads 2 and 3 will execute G, that is: the next instruction to be executed is G.

[0118] See Figure 5 As shown in (6), during the execution of G by threads 2 and 3, thread 1 will pause at F, that is: the CPC of thread 1 remains unchanged at F, and the NPC of thread 1 remains unchanged at J; the NPC of threads 2 and 3 are both H; since the specific operation of G includes: assigning V3-1 to V4, V4 of thread 3 changes from 3 to 2, and V4 of thread 2 changes from 2 to 1; the NPC of the top element of stack 1004 changes from G to H, and the rest of the information remains unchanged. After the G instruction is executed, threads 2 and 3 will execute the next instruction to be executed: H.

[0119] See Figure 5 As shown in (7), during the execution of instruction H by threads 2 and 3, the CPC and NPC of thread 1 remain unchanged; the NPC of threads 2 and 3 are both D; since H is a function call instruction, the RC of the top element in stack 1004 changes from 0 to 1, the NPC changes from H to D, and the rest of the information remains unchanged. After threads 2 and 3 finish executing instruction H, they will return to execute the next instruction to be executed, D.

[0120] See Figure 5 As shown in (8), during the execution of D by threads 2 and 3, the CPC and NPC of thread 1 remain unchanged; the NPC of threads 2 and 3 is E; since the specific operation at D includes assigning SP+1 to SP, during the execution of D, the C_SP and Warp_SP of threads 2 and 3 are changed from 1 to 2; the NPC of the top element of stack 1004 changes from D to E. After threads 2 and 3 finish executing D, the next instruction to be executed will be E.

[0121] See Figure 5 As shown in (9), during the execution of E by threads 2 and 3, the CPC and NPC of thread 1 remain unchanged; since E is a branch jump instruction, threads 2 and 3 will perform different branch jumps after E: thread 2 jumps to F, and thread 3 jumps to G; the V4 value, V2 value, C_SP, and Warp_SP of each thread remain unchanged; since E is a branch jump instruction, a stack push operation will be performed, pushing the newly generated current instruction execution information into stack 1004, and setting RC in the newly pushed instruction execution information to 0 (see [reference]). Figure 5 (The last two rows of stack elements in the stack table in (9)). After threads 2 and 3 finish executing E, thread 2 will execute the next instruction F.

[0122] See Figure 5 As shown in (10), during the execution of F by thread 2, the CPC and NPC of thread 1 remain unchanged; according to the specific operation at point F, the V2 value of thread 2 changes from a random value to 1; regarding the top element of stack 1004, since NPC = RPC = J and RC = 0, a pop operation can be performed on the top element, thereby making the previous stack element the new top element. After thread 2 finishes executing instruction F, thread 3 will execute G, that is: the next instruction to be executed is G.

[0123] See Figure 6 As shown in (11), during the execution of G by thread 3, the CPC and NPC of threads 1 and 2 remain unchanged; since the specific operation of point G includes: assigning V3-1 to V4, V4 of thread 3 changes from 2 to 1; the NPC of the top element of stack 1004 changes from G to H, and the rest of the information remains unchanged. After G is executed, the next instruction to be executed will be H.

[0124] See Figure 6As shown in (12), during the execution of H by thread 3, the CPC and NPC of threads 1 and 2 remain unchanged; since H is a function call instruction, the RC of the top element in stack 1004 changes from 0 to 1, the NPC changes from H to D, and the rest of the information remains unchanged. After thread 3 finishes executing H, it will return to execute the next instruction to be executed: D.

[0125] See Figure 6 As shown in (13), during the execution of D by thread 3, the CPC and NPC of threads 1 and 2 remain unchanged; since the specific operation at D includes assigning SP+1 to SP, during the execution of D, the C_SP and Warp_SP of thread 3 both change from 2 to 3; the NPC of the top element of stack 1004 changes from D to E. After thread 3 finishes executing D, the next instruction to be executed will be E.

[0126] See Figure 6 As shown in (14), during the execution of E by thread 3, the CPC and NPC of threads 1 and 2 remain unchanged. At this time, although E is a branch jump instruction, no different branches appear after E. Instead, only thread 3 executes G. Therefore, only the NPC in the top element of stack 1004 is updated, changing from E to F. That is, after thread 3 finishes executing E, thread 3 will continue to execute the next instruction F.

[0127] See Figure 6 As shown in (15), during the execution of F by thread 3, the CPC and NPC of threads 1 and 2 remain unchanged; according to the specific operation of point F, the V2 value of thread 3 changes from a random value to 1; as for the top element of stack 1004, although NPC = RPC = J, RC is not 0. Therefore, it is not possible to perform a pop operation on the top element of the stack, but instead, the convergence point J is bypassed and thread 3 continues to execute the next instruction.

[0128] See Figure 7 As shown in (16), during the execution of J by thread 3, the CPC and NPC of threads 1 and 2 remain unchanged; according to the specific operation at point J, the CSP value of thread 3 and the value of Warp_SP both change from 3 to 2; as for the top element of stack 1004, since J is a function return instruction and returns to I, the RC value will change from 1 to 0, and the NPC will change from J to I. After thread 3 finishes executing J, thread 3 will continue to execute the next instruction I.

[0129] See Figure 7As shown in (17), during the execution of I by thread 3, the CPC and NPC of threads 1 and 2 remain unchanged. According to the specific operation of point I, the V2 value of thread 3 changes from 1 to 2. As for the top element of stack 1004, since NPC = RPC = J and RC = 0, the top element can be popped, and the previous element can be used as the new top element. As for the new top element, although NPC = RPC = J, RC is not 0. Therefore, the top element cannot be popped. Instead, the convergence point J is skipped, and the next instruction is executed by threads 2 and 3.

[0130] See Figure 7 As shown in (18), during the execution of J by threads 2 and 3, the CPC and NPC of thread 1 remain unchanged. According to the specific operation of point J, the CSP values ​​of threads 2 and 3, as well as the value of Warp_SP, all change from 2 to 1. When the value of Warp_SP is 0, it returns to C; when the value of Warp_SP is not 0, it returns to I. Since the value of Warp_SP changes to 1, it returns to I. As for the top element of stack 1004, since J is a function return instruction and returns to I, the value of RC will change from 1 to 0, and the NPC will change from J to I. After threads 2 and 3 finish executing J, threads 2 and 3 will continue to execute the next instruction I.

[0131] See Figure 7 As shown in (19), during the execution of I by threads 2 and 3, the CPC and NPC of thread 1 remain unchanged. According to the specific operation of point I, the V2 value of thread 3 changes from 2 to 6, and the V2 value of thread 2 changes from 1 to 2. As for the top element of stack 1004, since NPC = RPC = J and RC = 0, a pop operation can be performed on the top element of the stack, so that the previous stack element is used as the new top element of the stack. After threads 2 and 3 finish executing I, threads 1, 2, and 3 will converge to execute the next instruction J.

[0132] See Figure 7 As shown in (20), during the convergence of threads 1, 2, and 3 in executing J, the specific operations at point J result in the following: the CSP values ​​of threads 1, 2, and 3, as well as the value of Warp_SP, all change from 1 to 0. Regarding the top element of stack 1004, since J is a function return instruction, RC changes from 1 to 0, and NPC changes from J to C. After threads 1, 2, and 3 finish executing J, they will return together to execute C in the main program, thus obtaining the final calculation result. According to the V2 value of each thread, the final result is: the calculation result of thread 1 is 1, the calculation result of thread 2 is 2, and the calculation result of thread 3 is 6. The results are correct.

[0133] This disclosure also provides a chip, including the processor described in the above embodiments.

[0134] This disclosure also provides an electronic device, including: the processor in the above embodiments, or the chip in the above embodiments.

[0135] Figure 8 A flowchart illustrating an instruction processing method according to an embodiment of this disclosure is shown. This instruction processing method can be executed by the processor 100 in the above embodiments. Figure 8 As shown, the instruction processing method includes the following steps:

[0136] Step 802: During the execution of the current instruction, the instruction processing unit generates current instruction execution information and stores the current instruction execution information into the stack.

[0137] The current instruction execution information includes: the instruction address information of the next instruction to be executed, the address information of the convergence point instruction, and the recursion depth information; the recursion depth information represents the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed.

[0138] Step 804: After the current instruction has been executed, the instruction processing unit reads the instruction execution information from the stack.

[0139] Step 806: If the address of the next instruction to be executed is the same as the address of the convergence point instruction based on the read instruction execution information, and the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed is 0, then a pop operation is performed on the stack, and the operation of reading instruction execution information from the stack is returned until the stack is empty.

[0140] According to the instruction processing method provided in this embodiment, during instruction execution, the instruction processing unit in the processor adds recursion depth information to the stack storage, representing the difference between the number of times a function call instruction has been executed and the number of times a function return instruction has been executed. Then, when performing thread pop-and-convergence judgment, two factors are considered simultaneously: whether the next instruction to be executed is a convergence instruction, and whether the number of times a function call instruction has been executed equals the number of times a function return instruction has been executed, i.e., whether the recursion depths of the threads to be converged are consistent. Only when both factors are met is a pop operation performed. This ensures that the recursion depths of all threads converging at the convergence point are the same, meaning that threads with the same recursion depth converge to the same convergence instruction. Because the recursion depths of all threads at the convergence point are the same, it ensures that the software stack pointer shared by all threads is the same as the actual stack pointer of each thread, thereby avoiding the problem of thread calculation errors in nested recursive function scenarios.

[0141] Optionally, in some embodiments, the recursion depth information is presented in the form of a recursion depth value;

[0142] If the current instruction is a function call instruction, then the sum of the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information;

[0143] If the current instruction is a function return instruction, then the difference between the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information;

[0144] Among them, the previous instruction execution information is the instruction execution information generated during the execution of the previous instruction before the current instruction is executed;

[0145] Store the current instruction execution information onto the stack, including:

[0146] Update the top element of the stack using the information from the current instruction execution.

[0147] Optionally, in some embodiments, if the current instruction is a branch jump instruction, the recursion depth value in the generated current instruction execution information is set to a second preset value;

[0148] Store the current instruction execution information onto the stack, including:

[0149] Push the current instruction execution information onto the stack;

[0150] If, based on the read instruction execution information, it is determined that the address of the next instruction to be executed is the same as the address of the convergence point instruction, and the difference is 0, then a pop operation is performed on the top element of the stack, including:

[0151] If the address of the next instruction to be executed is determined to be the same as the address of the convergence point instruction based on the read instruction execution information, and the recursion depth value is equal to the second preset value, then a pop operation is performed on the top element of the stack.

[0152] Optionally, in some embodiments, the first preset value is 1 and the second preset value is 0.

[0153] Optionally, in some embodiments, the recursion depth information includes: a function call count value and a return count value; wherein, the function call count value represents the number of times the function call instruction has been executed; and the return count value represents the number of times the function return instruction has been executed.

[0154] If the current instruction is a function call instruction, then the sum of the function call count in the previous instruction execution information and the third preset value is used as the function call count in the current instruction execution information; the return count in the previous instruction execution information is used as the return count in the current instruction execution information.

[0155] If the current instruction is a function return instruction, then the function call count value in the previous instruction execution information is determined as the function call count value in the current instruction execution information; the sum of the return count value in the previous instruction execution information and the third preset value is determined as the return count value in the current instruction execution information.

[0156] Optionally, in some embodiments, the third preset value is 1.

[0157] Optionally, in some embodiments, the method further includes:

[0158] If, based on the read instruction execution information, it is determined that the instruction address of the next instruction to be executed is different from the address of the convergence point instruction, and / or the difference is determined to be non-zero, then the instruction processing unit will use the next instruction to be executed as the updated current instruction, and return to the steps of generating current instruction execution information and storing current instruction execution information on the stack during the current instruction execution process, until the stack is empty.

[0159] It should be noted that the details of the instruction processing method have been described in detail in conjunction with the structural diagram in the processor embodiment section above. For the specific process, please refer to the description in the aforementioned processor embodiment, and it will not be repeated here.

[0160] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0161] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0162] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0163] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A processor, comprising: Instruction processing unit and stack; The instruction processing unit is used for: During the execution of the current instruction, current instruction execution information is generated and stored in the stack; the current instruction execution information includes: address information of the next instruction to be executed, address information of the convergence point instruction, and recursion depth information; the recursion depth information represents the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed. After the current instruction is executed, instruction execution information is read from the stack. If the address of the next instruction to be executed is the same as the address of the convergence point instruction based on the read instruction execution information, and the difference is 0, then a pop operation is performed on the stack, and the operation of reading instruction execution information from the stack is returned until the stack is empty.

2. The processor according to claim 1, wherein, The recursion depth information is presented in the form of a recursion depth value; If the current instruction is a function call instruction, then the sum of the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information; If the current instruction is a function return instruction, then the difference between the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information; The previous instruction execution information refers to the instruction execution information generated during the execution of the previous instruction before the current instruction is executed. The step of storing the current instruction execution information into the stack includes: Update the top element of the stack using the current instruction execution information.

3. The processor according to claim 2, wherein, If the current instruction is a branch jump instruction, then the recursion depth value in the generated current instruction execution information will be set to the second preset value; The step of storing the current instruction execution information into the stack includes: Push the current instruction execution information onto the stack; If, based on the read instruction execution information, it is determined that the address of the next instruction to be executed is the same as the address of the convergence point instruction, and the difference is 0, then a pop operation is performed on the top element of the stack, including: If the address of the next instruction to be executed is determined to be the same as the address of the convergence point instruction based on the read instruction execution information, and the recursion depth value is equal to the second preset value, then a pop operation is performed on the top element of the stack.

4. The processor according to claim 3, wherein, The first preset value is 1, and the second preset value is 0.

5. The processor according to claim 1, wherein, The recursion depth information includes: the function call count value and the return count value; wherein, the function call count value represents the number of times the function call instruction has been executed; and the return count value represents the number of times the function return instruction has been executed. If the current instruction is a function call instruction, then the sum of the function call count in the previous instruction execution information and the third preset value [P-137014-CN-PRI-1][HS2410896CCN] is determined as the function call count in the current instruction execution information; the return count in the previous instruction execution information is determined as the return count in the current instruction execution information. If the current instruction is a function return instruction, then the function call count value in the previous instruction execution information is determined as the function call count value in the current instruction execution information; the sum of the return count value in the previous instruction execution information and the third preset value is determined as the return count value in the current instruction execution information.

6. The processor according to claim 5, wherein, The third preset value is 1.

7. The processor according to any one of claims 1-6, wherein, The processor is also used for: If, based on the read instruction execution information, it is determined that the instruction address of the next instruction to be executed is different from the address of the convergence point instruction, and / or, the difference is determined to be non-zero, then the next instruction to be executed is taken as the updated current instruction, and the process of generating current instruction execution information and storing the current instruction execution information into the stack is returned until the stack is empty.

8. A chip, comprising: The processor as described in any one of claims 1-7.

9. An electronic device, comprising: The processor as described in any one of claims 1-7, or the chip as described in claim 8.

10. An instruction processing method applied to a processor including an instruction processing unit and a stack, the method comprising: During the execution of the current instruction, the instruction processing unit generates current instruction execution information and stores the current instruction execution information into the stack. The current instruction execution information includes: instruction address information of the next instruction to be executed, address information of the convergence point instruction, and recursion depth information; the recursion depth information represents the difference between the number of times the function call instruction has been executed and the number of times the function return instruction has been executed. After the current instruction is executed, the instruction processing unit reads instruction execution information from the stack. If the address of the next instruction to be executed is the same as the address of the convergence point instruction based on the read instruction execution information, and the difference is 0, then a pop operation is performed on the stack, and the operation of reading instruction execution information from the stack is returned until the stack is empty.

11. The method according to claim 10, wherein, The recursion depth information is presented in the form of a recursion depth value; If the current instruction is a function call instruction, then the sum of the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information; If the current instruction is a function return instruction, then the difference between the recursion depth value in the previous instruction execution information and the first preset value is determined as the recursion depth value in the current instruction execution information; The previous instruction execution information refers to the instruction execution information generated during the execution of the previous instruction before the current instruction is executed. The step of storing the current instruction execution information into the stack includes: Update the top element of the stack using the current instruction execution information.

12. The method according to claim 11, wherein, If the current instruction is a branch jump instruction, then the recursion depth value in the generated current instruction execution information is set to the second preset value; [P-137014-CN-PRI-1][HS2410896CCN] The step of storing the current instruction execution information into the stack includes: Push the current instruction execution information onto the stack; If, based on the read instruction execution information, it is determined that the address of the next instruction to be executed is the same as the address of the convergence point instruction, and the difference is 0, then a pop operation is performed on the top element of the stack, including: If the address of the next instruction to be executed is determined to be the same as the address of the convergence point instruction based on the read instruction execution information, and the recursion depth value is equal to the second preset value, then a pop operation is performed on the top element of the stack.

13. The method according to claim 10, wherein, The recursion depth information includes: the function call count value and the return count value; wherein, the function call count value represents the number of times the function call instruction has been executed; and the return count value represents the number of times the function return instruction has been executed. If the current instruction is a function call instruction, then the sum of the function call count in the previous instruction execution information and the third preset value is used as the function call count in the current instruction execution information; the return count in the previous instruction execution information is used as the function call count in the current instruction execution information. If the current instruction is a function return instruction, then the function call count value in the previous instruction execution information is determined as the function call count value in the current instruction execution information; the sum of the return count value in the previous instruction execution information and the third preset value is determined as the function call count value in the current instruction execution information.

14. The method according to any one of claims 10-13, wherein, The method further includes: If, based on the read instruction execution information, it is determined that the instruction address of the next instruction to be executed is different from the address of the convergence point instruction, and / or, the difference is determined to be non-zero, then the instruction processing unit uses the next instruction to be executed as the updated current instruction, and returns to the step of generating current instruction execution information and storing the current instruction execution information into the stack during the current instruction execution process, until the stack is empty.

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