Computing chip, reduction operation method, related device and medium

Abstract

The invention provides a computing chip, a reduction operation method, a related device and a medium, and the computing chip comprises a plurality of computing units which are used for executing a computing task containing a thread bundle and a working group, and each computing unit comprises a loading storage unit and a local shared memory; the data caching unit is used for caching the work group level reduction results from the plurality of computing units and executing a reduction operation across work groups; the global memory is used for storing a grid-level reduction result after the reduction operation of the data cache unit; wherein a first-level hardware reduction module is integrated in the loading storage unit, and is used for executing a thread bundle and reduction operation in a working group, and submitting an obtained working group reduction result to a local shared memory; and a second-stage hardware reduction module is integrated in the data cache unit, is coupled with the first-stage hardware reduction module and is used for executing reduction operation across working groups. According to the method, the memory access delay and the calling overhead are reduced, and the execution efficiency of the grid reduction operation is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a computing chip, a reduction operation method, related apparatus and medium. Background Technology

[0002] In massively parallel computing architectures such as GPUs (Graphics Processing Units), grid reduction is a key parallel computing operation used to aggregate data held by all threads within a computing grid, ultimately generating a global result. This operation is commonly used in high-performance computing scenarios such as deep learning gradient synchronization, matrix operations, and statistical analysis, and its execution efficiency directly impacts the overall system performance. A typical grid reduction operation requires merging the values ​​calculated by thousands of threads into a single output value through reduction methods such as addition, maximum value, and minimum value. Currently, the industry widely adopts multi-core functions or multi-stage (Multi-Kernel / Multi-Pass) methods to implement this process. This method first starts a massively parallel kernel, allowing each workgroup (WG) to perform workgroup-level reduction (WG Reduce) internally, generating local reduction results and writing these results to an intermediate array in global memory; subsequently, after the previous kernel has finished executing, a second, smaller kernel is started to read all the local results in the intermediate array and further perform the final global reduction. When the number of local results is still large, it may be necessary to introduce a third or more kernel calls to complete the reduction task step by step.

[0003] However, this multi-core function or multi-stage implementation has many inherent drawbacks. First, each kernel startup and termination is accompanied by significant scheduling overhead and synchronization latency, and the accumulated time cost of multiple kernel calls severely restricts overall execution efficiency. Second, intermediate results must be transferred through global memory, resulting in a large number of unnecessary memory read and write operations, which not only consume valuable global memory bandwidth but also become a performance bottleneck due to the high-latency memory access path. In addition, the amount of data processed in the subsequent reduction stage is much smaller than that in the initial stage, causing the GPU's massive parallel computing resources to be underutilized, resulting in serious resource idleness. Summary of the Invention

[0004] This disclosure provides a computing chip, a reduction operation method, related devices, and a medium, aiming to achieve integrated and efficient reduction from the thread bundle level to the grid level without the need for global memory transfer and multiple kernel startups. This significantly reduces memory access latency and call overhead, fully leverages the massive parallel computing capabilities of GPUs, and improves the execution efficiency of grid reduction operations.

[0005] According to one aspect of this disclosure, a computing chip is provided, characterized in that it comprises:

[0006] Multiple computing units are used to execute computing tasks that include thread bundles and workgroups. Each computing unit includes a load storage unit and local shared memory.

[0007] The data caching unit is used to cache workgroup-level reduction results from multiple computing units and perform reduction operations across workgroups;

[0008] Global memory is used to store the grid-level reduction results after the data cache unit reduction operation;

[0009] The loading storage unit integrates a first-level hardware reduction module, which is used to perform reduction operations within thread bundles and workgroups, and submit the obtained workgroup-level reduction results to the local shared memory.

[0010] The data caching unit integrates a second-level hardware reduction module, which is coupled to the first-level hardware reduction module and is used to perform reduction operations across workgroups.

[0011] Optionally, the first-level hardware reduction module includes:

[0012] The reduction tree hardware unit is used to perform parallel reduction calculations on the data of each thread within a single thread bundle and output the thread bundle-level reduction results.

[0013] The first atomic operation unit is used to perform atomic reduction operations on the thread bundle-level reduction results of multiple thread bundles within the same workgroup, and store the obtained workgroup-level reduction results into the local shared memory.

[0014] Optionally, the second-level hardware reduction module includes:

[0015] The second atomic operation unit is used to perform atomic reduction operations on multiple workgroup-level reduction results obtained from the local shared memory of multiple workgroups to generate the grid-level reduction result.

[0016] Optionally, the first-level hardware reduction module and the second-level hardware reduction module work together in an asynchronous pipeline manner.

[0017] Optionally, the reduction operation is atomic accumulation, finding the maximum value, or finding the minimum value.

[0018] Optionally, the reduction tree hardware unit includes multiple comparators or adders connected in a hierarchical cascade to form a tree topology, wherein the number of comparators or adders at each level is half that of the previous level.

[0019] Optionally, the number of comparators or adders is determined based on the total number of threads in each thread bundle.

[0020] According to one aspect of this disclosure, a reduction operation method is provided, applied to the computing chip described above, the reduction operation method comprising:

[0021] In each computing unit, the first-level hardware reduction module performs reduction operations on the data of each thread within the same thread bundle to generate thread bundle-level reduction results.

[0022] The first-level hardware reduction module performs atomic reduction operations on the thread bundle-level reduction results of each thread bundle within the same workgroup in local shared memory to obtain the workgroup-level reduction result of the workgroup.

[0023] The second-level hardware reduction module performs atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit, generating the grid-level reduction result of the grid and writing it back to global memory.

[0024] Optionally, in each computing unit, a first-level hardware reduction module performs a reduction operation on the data of each thread within the same thread bundle to generate a thread bundle-level reduction result, including:

[0025] The reduction tree hardware unit performs hierarchical pairwise reduction on the data of each thread within the same thread bundle until the thread bundle-level reduction result is generated.

[0026] Optionally, the step of performing an atomic reduction operation in local shared memory on the thread bundle-level reduction results of each thread bundle within the same workgroup through the first-level hardware reduction module to obtain the workgroup-level reduction result of the workgroup includes:

[0027] Obtain the first destination address in the local shared memory where the workgroup-level reduction result is stored;

[0028] For each thread bundle within the same workgroup, an atomic reduction operation is performed on the current value at the first destination address and the thread bundle-level reduction result of the current thread bundle through the first atomic operation unit, and the value at the first destination address is updated.

[0029] Optionally, the step of performing atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit through the second-level hardware reduction module to generate the grid-level reduction result of the grid and write it back to global memory includes:

[0030] Obtain the second destination address in the global memory where the grid-level reduction result is stored;

[0031] Determine whether the data corresponding to the second destination address is cached in the data cache unit;

[0032] If a cache hit occurs, an atomic reduction operation is performed on the current value in the hit cache line and the workgroup-level reduction result obtained from the local shared memory through the second atomic operation unit.

[0033] If a cache miss occurs, the data corresponding to the second destination address is loaded from the global memory into the data cache unit before the atomic reduction operation is performed.

[0034] Optionally, the step of performing atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit through the second-level hardware reduction module to generate the grid-level reduction result of the grid and write it back to global memory further includes:

[0035] After all working groups within the grid have completed atomic reduction operations, a global synchronization operation is performed.

[0036] The grid-level reduction result obtained in the data cache unit is written back to the second destination address of the global memory.

[0037] According to one aspect of this disclosure, a reduction operation device is provided, applied to the computing chip described above, the reduction operation device comprising:

[0038] The thread bundle-level reduction unit is used to perform reduction operations on the data of each thread within the same thread bundle in each computing unit through the first-level hardware reduction module, and generate thread bundle-level reduction results.

[0039] The workgroup-level reduction unit is used to perform atomic reduction operations on the thread bundle-level reduction results of each thread bundle within the same workgroup in local shared memory through the first-level hardware reduction module, so as to obtain the workgroup-level reduction result of the workgroup.

[0040] The grid-level reduction unit is used to perform atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit through the second-level hardware reduction module, generate the grid-level reduction result of the grid, and write it back to global memory.

[0041] According to one aspect of this disclosure, an electronic device is provided, the electronic device including a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing connection communication between the processor and the memory, wherein the program is executed by the processor to implement the reduction operation method as described above.

[0042] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores one or more programs, which can be executed by one or more processors to implement the reduction operation method described above.

[0043] In the computing chip proposed in this embodiment, the first-level hardware reduction module integrated in the loading storage unit performs reduction operations within thread bundles and workgroups, and submits the obtained workgroup-level reduction results to local shared memory. The second-level hardware reduction module integrated in the data cache unit is coupled with the first-level hardware reduction module. The second-level hardware reduction module performs reduction operations across workgroups and stores the grid-level reduction results in global memory. Thus, through the two-level hardware reduction modules, a full-process hardware-accelerated reduction mechanism from thread bundle level, workgroup level to grid level is realized without writing intermediate results to global memory or starting multiple kernel functions. This architecture effectively overcomes the scheduling overhead and synchronization latency caused by frequent kernel startup in traditional multi-stage reduction methods, avoids a large number of high-latency memory access operations caused by the transfer of workgroup-level reduction results through global memory, and significantly reduces the latency and bandwidth pressure of the overall execution process. The two-level hardware reduction modules execute asynchronously, making full use of computing resources and improving the execution efficiency of grid reduction operations.

[0044] Furthermore, the first-level hardware reduction module includes a reduction tree hardware unit and a first atomic operation unit. The reduction tree hardware unit performs parallel reduction calculations on the data of each thread within a single thread bundle, outputting thread bundle-level reduction results. The first atomic operation unit performs atomic reduction operations on the thread bundle-level reduction results of multiple thread bundles within the same workgroup, and stores the resulting workgroup-level reduction results in local shared memory. The second atomic operation unit in the second-level hardware reduction module performs atomic reduction operations on multiple workgroup-level reduction results obtained from the local shared memory of multiple workgroups, generating grid-level reduction results. In this way, thread-beam-level reduction is performed by the reduction tree hardware unit, workgroup-level reduction is completed by the first atomic operation unit in local shared memory, and cross-workgroup atomic reduction is directly executed by the second atomic operation unit in the second-level hardware reduction module in the data cache unit. As more and more reduction computation tasks are taken over by the dedicated two-level hardware reduction module, a large number of reduction instructions that were originally executed by the general-purpose ALU unit in traditional implementations are eliminated. The pressure on general-purpose registers is significantly reduced, and local shared memory no longer needs to allocate a lot of space for storing and updating intermediate reduction variables, thereby freeing up valuable computing and storage resources for other parallel tasks, significantly improving the utilization rate of chip resources and overall computing throughput. By sinking the reduction operation to the loading memory unit and data cache unit level, deep integration of memory access and computation is achieved, further compressing the data movement path and reducing power consumption.

[0045] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objectives and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0046] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0047] Figure 1 This is a system architecture diagram of the computing chip used in the reduction operation method of this embodiment;

[0048] Figure 2 This is a main flowchart of a reduction operation method according to an embodiment of the present disclosure;

[0049] Figure 3 This is a schematic diagram of the structure of a first-level hardware reduction module according to an embodiment of this disclosure;

[0050] Figure 4 This is a schematic diagram of the structure of a reduction tree hardware unit according to an embodiment of the present disclosure;

[0051] Figure 5 This is a schematic diagram of the structure of the first atomic operation unit according to an embodiment of the present disclosure;

[0052] Figure 6 This is one embodiment of the present disclosure. Figure 2 A flowchart of a sub-step of one embodiment of step S220.

[0053] Figure 7 This is a schematic diagram of the structure of a second-level hardware reduction module according to an embodiment of this disclosure;

[0054] Figure 8 This is one embodiment of the present disclosure. Figure 2 A flowchart of a sub-step of one embodiment of step S230.

[0055] Figure 9 This is a schematic diagram of the structure of a reduction operation device according to an embodiment of the present disclosure;

[0056] Figure 10 This is an architecture diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this disclosure.

[0058] Before providing a further detailed description of the embodiments of this disclosure, the terms and concepts used in these embodiments are explained, and they are subject to the following interpretations:

[0059] A thread is the smallest unit of execution in a graphics processing unit (GPU) when performing data processing tasks. Each thread can independently perform the same pattern of processing on different data.

[0060] A warp is the basic unit of scheduling and execution in a graphics processing unit (GPU). It contains a fixed number of threads, typically 32 or 64. All threads execute the same instructions within the same clock cycle, but can operate on different data, enabling Single Instruction Multiple Data (SIMD) parallel computation. When a grid is activated (equivalent to a kernel being activated, with each kernel corresponding to its own grid), the grid contains workgroups. After a workgroup is assigned to a computational unit, it is divided into multiple warps. Within a warp, all threads execute in a SIMT manner, performing the same instructions at each step, but processing private data—data that corresponds to a specific thread.

[0061] Work Group (WG): A group of threads consisting of multiple threads, also known as a thread block. Threads in a single work group are generally used to perform the same pattern of processing on different data.

[0062] A grid consists of multiple workgroups. Each workgroup is a grid point in the grid, and each workgroup has corresponding grid point coordinates. A grid can be one-dimensional, two-dimensional, or three-dimensional. The shape of the grid is defined by the user during the programming process.

[0063] A Compute Unit (CU) is a processing module in electronic devices such as a graphics processing unit (GPU). In some architectures, a CU may also be called a Stream Multiprocessor (SM). A GPU can include multiple CUs. A CU can be considered a processing core within a GPU. Each CU can execute instructions independently, and the GPU can process data in parallel through multiple CUs.

[0064] Execution Unit (EU, also known as a multi-stream processor (SM)): It is the execution unit in a microprocessor. It is responsible for executing instructions and performing computational tasks such as arithmetic operations, logical operations, and shift operations. In fact, it has both the functions of a controller and an arithmetic unit.

[0065] Shared memory (SMEM) refers to a certain amount of memory in a multiprocessor computer system that can be accessed by different processors. Because multiple processors need to access memory quickly, memory caching is necessary. When any cached data is updated, the shared memory needs to be updated immediately, otherwise different processors might use different data.

[0066] General Purpose Registers (GPRs) are used to store thread-private data, such as address indices, loop variables, or temporary calculation results. Each thread has its own independent GPR space, which is accessed extremely quickly and is a key resource for achieving thread-level parallel computing. In the Single Instruction Multithreaded (SIMT) execution model, GPRs and SMEMs work together: GPRs store thread-private states, while SMEMs carry shared data between thread bundles. Together, they support the efficient execution of high-concurrency computing tasks.

[0067] Data Cache (D-Cache): This refers to a high-speed, small-capacity storage structure located between the computing unit and global memory. It is used to cache frequently accessed global memory data to reduce data access latency and the number of direct accesses to high-power main memory. D-Cache is usually implemented as L1 or L2 cache in a multi-level cache system, shared by multiple computing units, and features high bandwidth and low latency.

[0068] Global memory refers to the large-capacity main memory inside or outside the computing chip, typically composed of high-bandwidth memory (such as GDDR6, HBM2 / HBM3), used to store program input data, output results, and persistent intermediate data for cross-kernel calls. Global memory has a large storage capacity, but suffers from high access latency, high power consumption, and limited bandwidth resources, making it one of the key performance bottlenecks in parallel computing systems.

[0069] Scalar General Purpose Register (SGPR): Used to store scalar data, such as control flow variables, loop counters, and address offsets.

[0070] Vector General Purpose Register (VGPR): Used to store vector data, such as operands for floating-point or integer vector operations.

[0071] Load Store Unit (LSU): A key functional module in GPUs or general-purpose processors, responsible for performing all memory access-related operations, including data loading and storage. In parallel computing architectures, the LSU manages data transfer from registers to various storage levels (such as global memory, local shared memory, cache, etc.), directly impacting memory access efficiency and overall computing performance.

[0072] Atomic operations are fundamental memory operations that cannot be interrupted in a multi-threaded concurrent environment and possess an "all-or-nothing" characteristic. In parallel computing architectures such as GPUs, atomic operations are used to ensure that the read-modify-write process of multiple threads on the same memory address does not lead to data races or inconsistencies due to concurrent access. Common atomic operations include atomic add, atomic compare-and-swap (atomicCAS), atomic maximum (atomicMax), and atomic minimum (atomicMin).

[0073] The Arithmetic Logic Unit (ALU) is a core component in the processor architecture that performs basic arithmetic and logical operations. The ALU is responsible for processing integer and floating-point calculation instructions (such as addition, subtraction, multiplication, division, and bitwise operations), and is an indispensable functional unit in the CPU / GPU. Based on differences in data width, the ALU can be divided into scalar ALUs and vector ALUs.

[0074] In massively parallel computing architectures such as GPUs, grid reduction is a key parallel computing operation used to aggregate data held by all threads within a computing grid, ultimately generating a global result. This operation is commonly used in high-performance computing scenarios such as gradient synchronization in deep learning, matrix operations, and statistical analysis, and its execution efficiency directly impacts the overall system performance. A typical grid reduction operation requires merging the values ​​calculated by thousands of threads into a single output value through reduction methods such as addition, maximum value, and minimum value. Currently, the industry widely adopts multi-core functions or multi-stage (Multi-Kernel / Multi-Pass) methods to implement this process. However, this multi-core function or multi-stage implementation has several inherent drawbacks. First, each kernel startup and termination is accompanied by significant scheduling overhead and synchronization latency, and the accumulated time cost of multiple kernel calls severely restricts the overall execution efficiency. Second, intermediate results must be transferred through global memory, resulting in a large number of unnecessary memory read and write operations, which not only consume valuable global memory bandwidth but also become a performance bottleneck due to the high-latency memory access path. Furthermore, the amount of data processed in the subsequent reduction phase is much smaller than that in the initial phase, resulting in the GPU's massive parallel computing resources not being fully utilized, leading to a serious resource idle phenomenon.

[0075] Based on this, the present disclosure provides a computing chip, a reduction operation method, related devices and media to solve the problems of high scheduling overhead, frequent global memory access and low computing resource utilization caused by multi-stage kernel calls in the prior art. Without the need for global memory transfer and multiple kernel startups, it achieves integrated and efficient reduction from the thread bundle level to the grid level, significantly reduces memory access latency and call overhead, fully leverages the large-scale parallel computing capabilities of the GPU, and improves the execution efficiency of grid reduction operations.

[0076] System architecture description applied in the embodiments of this disclosure

[0077] Figure 1This is a system architecture diagram of the computing chip used in the reduction operation method of this disclosure embodiment. The system mainly includes a computing chip 100, which includes a scheduling unit 110 for workgroup scheduling, multiple computing units 120, a data cache unit 140, and global memory 150. Computing units 0 to 3 are shown in the figure as examples, but it should be understood that the architecture is not limited thereto, and the computing chip 100 may contain more or fewer computing units 120 according to actual design requirements. Multiple computing units 120 may be included in a cluster according to design requirements. Each computing unit 120 further includes a scheduling unit 121 for thread bundle scheduling, multiple execution units 122, a load storage unit 130, and local shared memory 124. Each execution unit 122 includes a register file 123. Execution units 0 to 3 are shown in the figure, and are also only for illustrative purposes; in actual implementation, any number of execution units 122 may be included.

[0078] The computing chip 100 is a computer processing device with parallel processing capabilities, suitable for high-concurrency, high-throughput computing tasks. Typical applications include graphics processing, scientific computing, and artificial intelligence training and inference. This computing component can be implemented using various processor architectures, such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a General-Purpose Computing on Graphics Processing Units (GPGPU), a Neural Processing Unit (NPU), or a Tensor Processing Unit (TPU). When processing graphics-related tasks, such as image recognition, 3D rendering, or animation generation, the computing chip 100 typically employs a GPU architecture to fully leverage its massively parallel computing advantages; while when performing general computing tasks, such as operating system scheduling or serial logic processing, a CPU architecture can be used to balance flexibility and control efficiency.

[0079] During task execution, the scheduling unit 110 is responsible for dividing the received computing tasks into several workgroups and assigning these workgroups to appropriate computing units 120 for processing. Each workgroup consists of multiple warps. After entering the computing unit, the scheduling unit 121 within the workgroup further distributes the warps to various execution units 122 for parallel computation. During execution, the register file 123 provides low-latency data storage and access support for each thread. The local shared memory 124 serves as the global storage medium within the computing unit 120, used to temporarily store data to be shared between workgroups and intermediate computation results. The global memory 150, as the unified address space in the chip system, provides a unified data access interface for multiple computing units 120, supporting data sharing and collaborative computation across computing units 120 (i.e., across workgroups), further improving task processing efficiency. The global memory 150 is connected to each computing unit 120 through a high-bandwidth interconnect network, supporting cache coherency protocols to ensure data read / write consistency across multiple computing units. The data caching unit 140 manages the data cache between the global memory 150 and each computing unit 120, reducing access latency and improving bandwidth utilization through intelligent prefetching and replacement strategies. Each computing unit 120 exclusively uses its allocated register file 123 and local shared memory 124 physical resource areas, ensuring resource isolation between different computing units. Within the same computing unit 120, multiple execution units 122 can share access to the local shared memory 124 resources allocated to that computing unit 120 to support inter-thread collaboration; while the resources of the register file 123 are divided according to threads or execution units, with each execution unit 122 exclusively using its allocated register space, thereby ensuring the independence of thread execution, avoiding data conflicts, and improving overall execution efficiency. In the computing chip 100, multiple computing units 120 can share access to the global memory 150 resources, supporting cross-workgroup task collaboration and data exchange. Multiple computing units 120 can share access to the cache resources in the data caching unit 140, achieving data consistency and efficient reuse through a unified cache management mechanism. This architecture provides the hardware foundation for the subsequent implementation of fine-grained, non-contiguous resource allocation mechanisms.

[0080] The reduction operation method provided in this disclosure is applied to... Figure 1 The system architecture shown.

[0081] Specifically, multiple computing units 120 are responsible for executing computing tasks that include thread bundles and workgroups. Within the same computing unit 120, one or more related execution units 122 can be invoked through thread bundles to enable the execution unit 122 to perform operations related to its own functions. A thread bundle can also invoke the load storage unit 130 to perform reduction operations. In some embodiments, the load storage unit 130 includes a first-level hardware reduction module 131, and the data cache unit 140 includes a second-level hardware reduction module 141. The second-level hardware reduction module 141 is coupled to the first-level hardware reduction module 131. Figure 2 This is a main flowchart of a reduction operation method according to an embodiment of this disclosure. Figure 2 As shown, the reduction operation method includes the following steps:

[0082] Step S210: In each computing unit, the data of each thread within the same thread bundle is reduced by the first-level hardware reduction module to generate thread bundle-level reduction results.

[0083] Step S220: Using the first-level hardware reduction module, the thread-beam-level reduction results of each thread bundle within the same workgroup are atomically reduced in local shared memory to obtain the workgroup-level reduction result of the workgroup.

[0084] Step S230: Through the second-level hardware reduction module, the workgroup-level reduction results of each workgroup within the same grid are atomically reduced in the data cache unit to generate the grid-level reduction result of the grid and write it back to global memory.

[0085] In the embodiments of steps S210 to S230, the intermediate results or raw data generated by each thread during execution are stored in the register file 123 of its respective execution unit 122. These data constitute the initial input of the reduction operation. The first-level hardware reduction module 131 and the second-level hardware reduction module 141 work together in an asynchronous pipeline manner to implement the reduction operation method of this disclosure embodiment. In some embodiments, the first-level hardware reduction module 131 reads the initial data of each thread in the same thread bundle from the register file 123, performs the reduction operation within the thread bundle and the work group within the first-level hardware reduction module 131, and submits the obtained work group-level reduction result to the local shared memory 124 for temporary storage. Specifically, in each computing unit 120, the first-level hardware reduction module 131 performs the reduction operation on the data of each thread in the same thread bundle to generate the thread bundle-level reduction result, and also performs the thread bundle-level reduction result of each thread bundle in the same work group on the local shared memory 124 to obtain the work group-level reduction result of the work group. Data caching unit 140 is used to cache workgroup-level reduction results from multiple computing units 120 and perform cross-workgroup reduction operations. The second-level hardware reduction module 141 is responsible for performing cross-workgroup reduction operations, reading the workgroup-level reduction results of each workgroup from local shared memory 124, performing atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid within the second-level hardware reduction module 141, and writing the final generated grid-level reduction result back to global memory 150. It can be understood that the reduction operations here are atomic accumulation, finding the maximum or minimum value.

[0086] It is understood that, in this embodiment of the disclosure, a full-process hardware-accelerated reduction mechanism from the thread bundle level, workgroup level, to the grid level is achieved through a two-level hardware reduction module, without writing intermediate results to global memory 150 or starting multiple kernel functions. This architecture effectively overcomes the scheduling overhead and synchronization latency caused by frequent kernel startup in traditional multi-stage reduction methods, avoids a large number of high-latency memory access operations caused by the transfer of workgroup-level reduction results through global memory 150, and significantly reduces the latency and bandwidth pressure of the overall execution process. The two-level hardware reduction module executes asynchronously, making full use of computing resources and improving the execution efficiency of grid reduction operations.

[0087] Structure of the computing chip in this embodiment

[0088] Figure 3 This is a schematic diagram of the structure of a first-level hardware reduction module according to an embodiment of this disclosure. Figure 3As shown, the computing unit 120 includes multiple execution units 122 and a load-memory unit 130, wherein the load-memory unit 130 is coupled to the execution units 122. The first-level hardware reduction module 131 in the load-memory unit 130 includes a reduction tree hardware unit 132 and a first atomic operation unit 133.

[0089] Multiple execution units 122 employ a Multiple Instruction Multiple Thread (SIMT) architecture, with each execution unit 222 capable of simultaneously acquiring and executing instructions from multiple threads. The load-memory unit 130, acting as a crucial hub connecting the execution units 122 to the memory hierarchy, not only performs conventional data loading and storage functions but also, through the integration of a first-level hardware reduction module 131, provides hardware acceleration support for thread bundle-level and workgroup-level reduction operations. When a workgroup is scheduled to execute in a computing unit 120, its multiple threads are organized into several thread bundles, which are then distributed by the scheduling unit 121 to different execution units 122 for parallel processing. The raw data or intermediate results generated by each thread during execution are temporarily stored in the register file 123 of its respective execution unit 122. After the reduction operation is initiated, the load-memory unit 130, through its internal first-level hardware reduction module 131, directly retrieves data from the register files 123 of the multiple execution units 122 for each thread bundle. Without relying on a general-purpose arithmetic logic unit, the reduction tree hardware unit 132 performs parallel reduction calculations on the data of each thread within a single thread bundle and outputs the thread bundle-level reduction result. Figure 4 This is a schematic diagram of the structure of a reduction tree hardware unit according to an embodiment of this disclosure. Figure 4 As shown, the reduction tree hardware unit 132 includes multiple comparators or adders connected in a hierarchical cascade, forming a tree topology. The number of comparators or adders at each level is half the number of the level above. The lowest-level comparators or adders interface with the register file 123 in the multiple execution units 122 to receive the data to be reduced from each thread bundle in the grid. The highest-level comparators or adders output the thread bundle-level reduction result. The number of comparators or adders is determined based on the total number of threads in each thread bundle. As an example, Figure 4The diagram illustrates a five-layer adder. The first layer contains 16 adders, receiving 32 initial values ​​from 32 thread inputs and outputting 16 partial sums. The second layer contains 8 adders, merging the 16 partial sums from the first layer and outputting 8 partial sums. The third layer contains 4 adders, merging the 8 partial sums from the second layer and outputting 4 partial sums. The fourth layer contains 2 adders, merging the 4 partial sums from the third layer and outputting 2 partial sums. The fifth layer contains 1 adder, summing the 2 partial sums from the fourth layer, ultimately outputting a unique thread bundle-level reduction result. This result can be temporarily stored in a local buffer of the load storage unit 130 for subsequent workgroup-level reduction.

[0090] In this embodiment, the reduction tree hardware unit 132 performs hierarchical pairwise reduction on the data of each thread within the same thread bundle until a thread bundle-level reduction result is generated. This tree-structured hardware implementation enables parallel reduction calculations on the data of each thread within a single thread bundle, significantly reducing the latency of the reduction operation and significantly improving execution efficiency compared to traditional software reduction methods.

[0091] After the thread bundle-level reduction result is generated, the first atomic operation unit 133 in the first-level hardware reduction module 131 further performs the inter-thread bundle reduction operation, performs the atomic reduction operation on the thread bundle-level reduction results of multiple thread bundles in the same workgroup, and stores the obtained workgroup-level reduction result in the local shared memory 124. Figure 5 This is a schematic diagram of the structure of the first atomic operation unit according to an embodiment of this disclosure. Figure 5 As shown, the local shared memory 124 can also be located in the first atomic operation unit 133 of the loading storage unit 130. The local shared memory 124 can be divided into multiple independent storage units (Sram Banks), and the number of storage units typically corresponds to the total number of threads within a thread bundle, thus facilitating the processing of data for a thread bundle within a single cycle. The first atomic operation unit 133 also includes an arithmetic logic unit 134, which performs atomic operations, including atomic maximum and minimum values, addition, and swapping, and supports integer and floating-point types. In some embodiments, the arithmetic logic unit 134 performs atomic addition operations, atomically accumulating the reduction results of each thread bundle to a designated storage unit of the local shared memory 124, ensuring that the data of all thread bundles within the workgroup participates in the reduction without conflict. This process is achieved through the collaborative implementation of the multi-bank structure of the arithmetic logic unit 134 and the local shared memory 124, supporting high-concurrency access and indivisible read-modify-write operations, thereby completing the aggregation of multiple thread bundle-level results within a single cycle and significantly improving the workgroup-level reduction efficiency. Figure 6 This is one embodiment of the present disclosure. Figure 2 A flowchart illustrating a sub-step of step S220 in one embodiment. (See attached flowchart.) Figure 6 As shown, the sub-steps of step S220 include the following steps:

[0092] Step S221: Obtain the first destination address in the local shared memory where the workgroup-level reduction result is stored.

[0093] Step S222: For each thread bundle within the same workgroup, perform an atomic reduction operation on the current value at the first destination address and the thread bundle-level reduction result of the current thread bundle through the first atomic operation unit, and update the value at the first destination address.

[0094] In the embodiments of steps S221 to S222, the first atomic operation unit 133 obtains the first destination address in the local shared memory 124 that stores the workgroup-level reduction result. The arithmetic logic unit 134, for each thread bundle within the same workgroup, performs an atomic reduction operation on the current value at the first destination address in the local shared memory 124 and the thread bundle-level reduction result of the current thread bundle obtained from the reduction tree hardware unit 132, and writes the atomic reduction operation result back to the first destination address to update the value at the first destination address, until all thread bundles within the same workgroup have completed the atomic reduction operation. At this point, the current value at the first destination address is the workgroup-level reduction result. Similarly, for each workgroup within the same grid, steps S221 to S222 are executed using the first atomic operation unit 133 to obtain the workgroup-level reduction result for each workgroup within the same grid, wherein the workgroup-level reduction results for all workgroups within the same grid are stored at different storage addresses in the local shared memory 124.

[0095] After the workgroup-level reduction results are generated, the chip system enters the global reduction phase. The main thread holding the workgroup-level reduction results executes a storage instruction to write the workgroup-level reduction results stored in local shared memory 124 to a preset destination address in shared memory 150. After detecting the storage instruction, the data cache unit 140 caches the workgroup-level reduction results from multiple computing units 120 and performs cross-workgroup reduction operations based on the second-level hardware reduction module 141. Figure 7 This is a schematic diagram of the structure of a second-level hardware reduction module according to an embodiment of this disclosure. Figure 7As shown, the second-level hardware reduction module 141 includes a second atomic operation unit 142, a buffer 143, a tag memory 144, a comparator 145, a request FIFO 146, a data FIFO 147, and a memory access request queue 148. In some embodiments, the request FIFO 146 receives a storage instruction and stores the second destination address in the global memory 150 that stores the grid-level reduction result. The data FIFO 147 stores the workgroup-level reduction result corresponding to the storage instruction. The buffer 143 is used to cache frequently accessed data blocks in the global memory 150 to reduce the overhead of direct access to the global memory. The tag memory 144 is used to store cache line tag information for each storage address in the global memory 150. The request FIFO 146 provides the second destination address to the comparator 145 in a first-in-first-out order. The comparator 145 compares the second destination address with the cache line tag information to determine whether the cache line corresponding to the second destination address has been hit. If a hit occurs, data FIFO 147 provides the workgroup-level reduction result of the current workgroup to the second atomic operation unit 142. Using the second atomic operation unit 142, the workgroup-level reduction results of each workgroup within the same grid are atomically reduced in the hit cache line in cache 143 to generate the grid-level reduction result for the grid. If a miss occurs, comparator 145 stores the second destination address in the memory access request queue 148 so that an access request to global memory 150 can be initiated based on the address in the memory access request queue 148. After obtaining the corresponding cache line data and loading it into cache 143, the second atomic operation unit 142 performs the atomic reduction operation.

[0096] Figure 8 This is one embodiment of the present disclosure. Figure 2 A flowchart illustrating a sub-step of step S230 in one embodiment. (See attached flowchart.) Figure 8 As shown, the sub-steps of step S230 include the following steps:

[0097] Step S231: Obtain the second destination address in the global memory where the grid-level reduction result is stored.

[0098] Step S232: Determine whether the data corresponding to the second destination address is cached in the data cache unit.

[0099] Step S233: If a cache hit occurs, then through the second atomic operation unit, perform an atomic reduction operation on the current value in the hit cache line and the workgroup-level reduction result obtained from the local shared memory.

[0100] Step S234: If a miss occurs, the data corresponding to the second destination address is loaded from the global memory into the data cache unit before the atomic reduction operation is performed.

[0101] In the embodiments of steps S231 to S234, it is determined whether the data corresponding to the second destination address is cached in the data cache unit (i.e. Figure 7 In the cache 143, if a cache hit occurs, the second atomic operation unit 142 directly performs an atomic reduction operation on the current value of the hit cache line in the cache 143 and the workgroup-level reduction result from the local shared memory 124, avoiding frequent access to global memory 150, thereby significantly reducing memory access latency and improving reduction efficiency. If a cache miss occurs, the second destination address is added to the memory access request queue 148. After the corresponding cache line is loaded from global memory 150 to the cache 143, the second atomic operation unit 142 completes the atomic reduction operation. This mechanism effectively reduces the frequency of access to global memory by fully utilizing the locality characteristics of the data cache unit, further optimizing the execution performance of grid-level reduction while ensuring atomicity. At the same time, this process coordinates with the thread bundle scheduling in the SIMT architecture to ensure that each workgroup initiates a global grid-level reduction request immediately after completing its local workgroup-level reduction, improving the utilization rate of the atomic operation units of the data cache unit and avoiding resource idleness.

[0102] Understandably, as reduction computation tasks are increasingly handled by dedicated two-level hardware reduction modules, a large number of reduction instructions that were traditionally executed by the general-purpose ALU unit are eliminated. This significantly reduces the pressure on general-purpose registers, and the local shared memory 124 no longer needs to allocate significant space for storing and updating intermediate reduction variables. This frees up valuable computational and storage resources for other parallel tasks, significantly improving chip resource utilization and overall computational throughput. By pushing the reduction operation down to the level of the load memory unit 130 and the data cache unit 140, deep integration of memory access and computation is achieved, further compressing the data movement path and reducing power consumption.

[0103] In some embodiments, after all workgroups within the grid have completed atomic reduction operations, a global synchronization operation is performed to write the grid-level reduction result obtained in the data cache unit 140 back to the second destination address in the global memory 150. This global synchronization operation is coordinated by the scheduling unit 110 to ensure that all workgroups have successfully submitted their workgroup-level reduction results, and that the second-level hardware reduction module 141 in the data cache unit 140 has completed the aggregation processing of all input results. Only after confirming that all reduction write requests have been processed is the final value stored in the corresponding cache line in the cache 143 considered a complete grid-level reduction result. At this time, a write-back mechanism is triggered, and the current value at the second destination address is transmitted to the target address in the global memory 150 through a high-bandwidth interconnect network, completing the final disk write of the entire reduction process. This write-back process can be executed asynchronously in the background without affecting the startup and scheduling of subsequent computing tasks, further improving the overall pipeline efficiency of the system.

[0104] The introduction of the aforementioned two-level hardware reduction mechanism transforms the reduction operation from a traditional model relying on software control, multi-stage kernel calls, and global memory transfers into an integrated execution process automatically driven by dedicated hardware. Throughout the process, thread-beam-level reduction is completed within the loading storage unit 130, workgroup-level reduction is implemented atomically in local shared memory 124, and cross-workgroup global reduction is directly completed in the data cache unit 140, without exposing intermediate results to the general programming model or explicitly writing them to global memory 150. This architecture design not only significantly reduces the number of accesses to high-latency storage resources but also effectively avoids the context switching and synchronization overhead caused by multiple kernel startups. More importantly, because the reduction operation is deeply integrated into the memory access path, it achieves a near-data computation paradigm of "computing wherever the data is," significantly shortening the data movement distance and reducing power consumption and latency. This solution is particularly suitable for applications highly sensitive to reduction performance, such as gradient aggregation, large-scale sparse matrix statistics, and distributed parameter synchronization in deep learning training, significantly improving the effective computing power and energy efficiency of parallel systems without increasing additional computing resources.

[0105] Description of apparatus and devices according to embodiments of this disclosure

[0106] Reference Figure 9 , Figure 9 This is a schematic diagram of a reduction operation device 900 disclosed herein. The reduction operation device 900 is integrated into a computing chip and applied to the computing chip. The reduction operation device 900 includes:

[0107] The thread bundle-level reduction unit 910 is used to perform reduction operations on the data of each thread within the same thread bundle through the first-level hardware reduction module in each computing unit, and generate thread bundle-level reduction results.

[0108] The workgroup-level reduction unit 920 is used to perform atomic reduction operations on the thread bundle-level reduction results of each thread bundle within the same workgroup in local shared memory through the first-level hardware reduction module, so as to obtain the workgroup-level reduction result of the workgroup.

[0109] The grid-level reduction unit 930 is used to perform atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit through the second-level hardware reduction module, generate the grid-level reduction result of the grid, and write it back to global memory.

[0110] The reduction operation apparatus disclosed herein is used to execute the reduction operation method as described in the above embodiments. Its specific processing procedure is the same as the reduction operation method in the above embodiments, and will not be repeated here.

[0111] This disclosure also provides an electronic device 1000, comprising:

[0112] At least one processor, and,

[0113] A memory that is communicatively connected to at least one processor; wherein,

[0114] The memory stores instructions that are executed by at least one processor to cause the at least one processor to perform the method as described in any of the above embodiments of this application when executing the instructions.

[0115] The following is combined with Figure 10 The hardware structure of the electronic device is described in detail. The electronic device includes: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050.

[0116] The processor 1010 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this disclosure.

[0117] The memory 1020 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010 using the reduction operation method of the embodiments of this disclosure.

[0118] The input / output interface 1030 is used to implement information input and output;

[0119] The communication interface 1040 is used to enable communication and interaction between this device and other devices. Communication can be achieved via wired means (e.g., USB, Ethernet cable) or wireless means (e.g., mobile network, Wi-Fi, Bluetooth).

[0120] Bus 1050 transmits information between various components of the device (e.g., processor 1010, memory 1020, input / output interface 1030, and communication interface 1040);

[0121] The processor 1010, memory 1020, input / output interface 1030 and communication interface 1040 are connected to each other within the device via bus 1050.

[0122] This application also provides a computer-readable storage medium that stores one or more programs, which can be executed by one or more processors to implement the reduction operation method of the above embodiments, which will not be described again here.

[0123] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0124] It should be understood that in this disclosure, "at least one item" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0125] It should be understood that in the description of the embodiments of this disclosure, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0126] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0129] It should also be understood that the various implementation methods provided in this disclosure can be combined arbitrarily to achieve different technical effects.

[0130] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A computing chip, characterized in that, include: Multiple computing units are used to execute computing tasks that include thread bundles and workgroups. Each computing unit includes a load storage unit and local shared memory. The data caching unit is used to cache workgroup-level reduction results from multiple computing units and perform reduction operations across workgroups; Global memory is used to store the grid-level reduction results after the data cache unit reduction operation; The loading storage unit integrates a first-level hardware reduction module, which is used to perform reduction operations within thread bundles and workgroups, and submit the obtained workgroup-level reduction results to the local shared memory. The data caching unit integrates a second-level hardware reduction module, which is coupled to the first-level hardware reduction module and is used to perform reduction operations across workgroups.

2. The computing chip according to claim 1, characterized in that, The first-level hardware reduction module includes: The reduction tree hardware unit is used to perform parallel reduction calculations on the data of each thread within a single thread bundle and output the thread bundle-level reduction results. The first atomic operation unit is used to perform atomic reduction operations on the thread bundle-level reduction results of multiple thread bundles within the same workgroup, and store the obtained workgroup-level reduction results into the local shared memory.

3. The computing chip according to claim 1, characterized in that, The second-level hardware reduction module includes: The second atomic operation unit is used to perform atomic reduction operations on multiple workgroup-level reduction results obtained from the local shared memory of multiple workgroups to generate the grid-level reduction result.

4. The computing chip according to claim 1, characterized in that, The first-level hardware reduction module and the second-level hardware reduction module work together in an asynchronous pipeline manner.

5. The computing chip according to claim 1, characterized in that, The reduction operation is atomic accumulation, finding the maximum value, or finding the minimum value.

6. The computing chip according to claim 2, characterized in that, The reduction tree hardware unit includes multiple comparators or adders connected in a hierarchical cascade to form a tree topology, wherein the number of comparators or adders at each level is half that of the previous level.

7. The computing chip according to claim 6, characterized in that, The number of comparators or adders is determined based on the total number of threads in each thread bundle.

8. A reduction operation method, applied to a computing chip as described in any one of claims 1 to 7, the reduction operation method comprising: In each computing unit, the first-level hardware reduction module performs reduction operations on the data of each thread within the same thread bundle to generate thread bundle-level reduction results. The first-level hardware reduction module performs atomic reduction operations on the thread bundle-level reduction results of each thread bundle within the same workgroup in local shared memory to obtain the workgroup-level reduction result of the workgroup. The second-level hardware reduction module performs atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit, generating the grid-level reduction result of the grid and writing it back to global memory.

9. The reduction operation method according to claim 8, characterized in that, In each computing unit, a first-level hardware reduction module performs a reduction operation on the data of each thread within the same thread bundle to generate a thread bundle-level reduction result, including: The reduction tree hardware unit performs hierarchical pairwise reduction on the data of each thread within the same thread bundle until the thread bundle-level reduction result is generated.

10. The reduction operation method according to claim 8, characterized in that, The step of performing an atomic reduction operation in local shared memory on the thread bundle-level reduction results of each thread bundle within the same workgroup through the first-level hardware reduction module to obtain the workgroup-level reduction result of the workgroup includes: Obtain the first destination address in the local shared memory where the workgroup-level reduction result is stored; For each thread bundle within the same workgroup, an atomic reduction operation is performed on the current value at the first destination address and the thread bundle-level reduction result of the current thread bundle through the first atomic operation unit, and the value at the first destination address is updated.

11. The reduction operation method according to claim 8, characterized in that, The process involves using a second-level hardware reduction module to perform atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in a data cache unit, generating the grid-level reduction result of the grid, and writing it back to global memory. This includes: Obtain the second destination address in the global memory where the grid-level reduction result is stored; Determine whether the data corresponding to the second destination address is cached in the data cache unit; If a cache hit occurs, an atomic reduction operation is performed on the current value in the hit cache line and the workgroup-level reduction result obtained from the local shared memory through the second atomic operation unit. If a cache miss occurs, the data corresponding to the second destination address is loaded from the global memory into the data cache unit before the atomic reduction operation is performed.

12. The reduction operation method according to claim 11, characterized in that, The step of performing atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit through the second-level hardware reduction module to generate the grid-level reduction result of the grid and write it back to global memory also includes: After all working groups within the grid have completed atomic reduction operations, a global synchronization operation is performed. The grid-level reduction result obtained in the data cache unit is written back to the second destination address of the global memory.

13. A reduction operation device, applied to a computing chip as described in any one of claims 1 to 7, the reduction operation device comprising: The thread bundle-level reduction unit is used to perform reduction operations on the data of each thread within the same thread bundle in each computing unit through the first-level hardware reduction module, and generate thread bundle-level reduction results. The workgroup-level reduction unit is used to perform atomic reduction operations on the thread bundle-level reduction results of each thread bundle within the same workgroup in local shared memory through the first-level hardware reduction module, so as to obtain the workgroup-level reduction result of the workgroup. The grid-level reduction unit is used to perform atomic reduction operations on the workgroup-level reduction results of each workgroup within the same grid in the data cache unit through the second-level hardware reduction module, generate the grid-level reduction result of the grid, and write it back to global memory.

14. An electronic device comprising a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for enabling communication between the processor and the memory, wherein the program, when executed by the processor, implements the reduction operation method as described in any one of claims 8 to 12.

15. A computer-readable storage medium storing one or more programs, said one or more programs being executable by one or more processors to implement the reduction operation method as described in any one of claims 8 to 12.

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