Processor performance test method and device, equipment and storage medium

Abstract

The invention discloses a processor performance test method, device and equipment and a storage medium, and relates to the technical field of performance test.The processor performance test method comprises the steps that a performance test program is compiled into a machine instruction, the machine instruction is divided into a plurality of instruction blocks, and all the instruction blocks are marked according to target labels; the target label comprises an instruction type and a memory access mode; the instruction type comprises a floating point calculation type and an integer calculation type; obtaining performance data of each kernel when the processor executes the task; the performance data comprises a core utilization rate, a cache hit rate, memory delay and inter-core communication delay; distributing the instruction block to a target kernel of the processor based on the target label and the performance data, so that the target kernel executes the instruction block to obtain corresponding test data; and recording the test data, and determining a performance test result of the processor according to the test data. Therefore, the effectiveness of the performance test can be improved.

Description

Technical Field

[0001] This invention relates to the field of performance testing technology, and in particular to a processor performance testing method, apparatus, device, and storage medium. Background Technology

[0002] As computer systems become increasingly complex, traditional performance testing techniques often struggle to cover diverse testing scenarios. Computer performance is closely tied to its application scenarios, which may include CPU (Central Processing Unit) intensive applications (e.g., scientific research), I / O (Input / Output) intensive applications (e.g., web servers), or memory-intensive applications (e.g., video editing). Existing processor performance testing solutions primarily combine multi-dimensional quantitative metrics with simulated scenarios. Basic methods include using standardized benchmark tools to measure single / multi-threaded computing power, such as integer floating-point operations, memory bandwidth, and latency testing; stress testing to verify stability and thermal design under sustained high loads; and power efficiency analysis to compare performance and energy consumption.

[0003] The best practice for evaluating computer performance is to run actual applications on the machine. However, for multi-core processors, conventional test programs often only reflect performance under ideal conditions and cannot adequately reflect the performance under multi-process operation and high load in daily use environments.

[0004] It is evident that, for performance testing scenarios involving multi-core processors, how to address the issues of insufficient rigor and incomplete coverage in existing technologies is a problem that those skilled in the art need to consider. Summary of the Invention

[0005] The purpose of this invention is to provide a processor performance testing method, apparatus, device, and storage medium, which can solve the problems of insufficient rigor and incomplete coverage of results in existing technologies, improve the effectiveness and accuracy of performance testing, and provide a reference for processor performance optimization. The specific solution is as follows: In a first aspect, the present invention provides a processor performance testing method, comprising: The performance test program is compiled into machine instructions, which are then broken down into several instruction blocks. Each instruction block is labeled according to a target label. The target label includes the instruction type and memory access mode. The instruction type includes floating-point calculation type and integer calculation type. Obtain performance data of each core of the processor when executing tasks; performance data includes core utilization, cache hit rate, memory latency, and inter-core communication latency; Instruction blocks are assigned to the target kernel of the processor based on target labels and performance data, so that the target kernel can execute the instruction blocks and obtain the corresponding test data. Record the test data and determine the processor's performance test results based on the test data.

[0006] Optionally, the machine instructions can be broken down into several instruction blocks, including: Based on the pre-set principles of low correlation and fine granularity, different functions in the machine instructions are split into several instruction blocks.

[0007] Optionally, obtain performance data of each core of the processor while executing tasks, including: The CPU acquires performance data of each core during task execution through performance monitoring units and sensors within the CPU.

[0008] Optionally, before allocating instruction blocks to the processor's target kernel based on target tags and performance data, the following may also be included: Determine the allocation strategy for instruction blocks; the allocation strategy includes a preset busy load pin insertion strategy and a preset random pin insertion strategy. Among them, the preset busy load pin insertion strategy is a strategy to allocate instruction blocks to processor cores whose load meets preset conditions; the preset random pin insertion strategy is a strategy to randomly allocate instruction blocks. Accordingly, instruction blocks are allocated to the processor's target kernel based on target tags and performance data, so that the target kernel executes the instruction blocks and obtains the corresponding test data, including: Based on the allocation strategy, the target kernel in the processor corresponding to the instruction block is determined according to the target label and performance data; The instruction block is assigned to the target kernel so that the target kernel can execute the instruction block to obtain the corresponding test data; the test data includes the total execution time of the instruction block and the calculation results after the instruction block is executed.

[0009] Optional, also includes: Acquire target data; target data includes CPU temperature, clock speed, core utilization, and memory usage. The target kernel of the processor is determined based on the target data, target label, and performance data, so that instruction blocks can be allocated to the target kernel.

[0010] Optionally, the processor's performance test results can be determined based on the test data, including: After multiple tests, all test data are summarized to obtain the summarized data; The processor's performance test results are determined based on the difference between the current test data and the current average of the aggregated data.

[0011] Optionally, the processor performance test result is determined based on the difference between the current test data and the current average of the aggregated data, including: If the difference between the current test data and the current average of the aggregated data is greater than or equal to the preset threshold, a new average is generated based on the current test data and the aggregated data, and the process jumps back to the step of obtaining the performance data of each core of the processor when executing the task. If the difference between the current test data and the current average value of the aggregated data is less than a preset threshold, then the current test data is determined as the processor's performance test result.

[0012] Secondly, the present invention provides a processor performance testing apparatus, comprising: The tagging module is used to compile the performance test program into machine instructions, break down the machine instructions into several instruction blocks, and tag each instruction block according to the target label; the target label includes instruction type and memory access mode; the instruction type includes floating-point calculation type and integer calculation type; The performance data acquisition module is used to acquire the performance data of each core of the processor when executing tasks; the performance data includes core utilization, cache hit rate, memory latency, and inter-core communication latency; The instruction block execution module is used to allocate instruction blocks to the target kernel of the processor based on the target label and performance data, so that the target kernel can execute the instruction blocks and obtain the corresponding test data. The performance test result determination module is used to record test data and determine the processor's performance test results based on the test data.

[0013] Thirdly, the present invention provides an electronic device, comprising: Memory, used to store computer programs; A processor is used to execute computer programs to implement the steps of the processor performance testing method described above.

[0014] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned processor performance testing method.

[0015] In this invention, the performance test program is compiled into machine instructions, which are then broken down into several instruction blocks. Each instruction block is labeled according to a target tag. The target tag includes the instruction type and memory access mode. The instruction type includes floating-point calculation type and integer calculation type. Performance data of each core of the processor is obtained when executing the task. The performance data includes core utilization, cache hit rate, memory latency, and inter-core communication latency. Based on the target tag and performance data, the instruction blocks are allocated to the target cores of the processor so that the target cores can execute the instruction blocks and obtain the corresponding test data. The test data is recorded, and the performance test results of the processor are determined based on the test data.

[0016] Beneficial Effects: As can be seen, this invention breaks down the performance testing program into fine-grained, unrelated instruction blocks, and then allocates them according to the load of each processor core. Finally, the results are collected to generate the final performance data. In this way, this invention improves the accuracy of performance testing by implementing a pin-scheduling and scheduling mechanism to break down large-scale performance testing programs and evaluate the performance of multiple cores under different states using instruction blocks. Attached Figure Description

[0017] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart of a processor performance testing method provided in an embodiment of the present invention; Figure 2 A flowchart illustrating a specific processor performance testing method provided in this embodiment of the invention; Figure 3 An example diagram of program preprocessing provided in an embodiment of the present invention; Figure 4 This is an overall framework diagram of a processor performance testing method provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a processor performance testing device provided in an embodiment of the present invention; Figure 6 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0020] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0021] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Traditional performance testing methods, which primarily rely on single-threaded benchmark testing and fixed task allocation, suffer from the following problems: Load imbalance: Static task allocation cannot reflect the randomness of dynamic workloads; resource contention interference: Fixed core binding amplifies interference factors such as cache contention and memory bandwidth bottlenecks; evaluation bias: Existing benchmarks (such as SpecCPU and Geekbench) focus on theoretical peak performance and lack simulation of random interference in real-world scenarios. To address these technical problems, this invention discloses a processor performance testing method, apparatus, device, and storage medium. These solutions resolve the issues of insufficient rigor and incomplete result coverage in existing technologies, improving the effectiveness and accuracy of performance testing and providing a reference for processor performance optimization.

[0023] See Figure 1 As shown, this embodiment of the invention provides a processor performance testing method, including: Step S11: Compile the performance test program into machine instructions, break the machine instructions into several instruction blocks, and mark each instruction block according to the target label; the target label includes instruction type and memory access mode; the instruction type includes floating-point calculation type and integer calculation type.

[0024] In embodiments of the present invention, such as Figure 2 As shown, the system link is initialized first, and then the performance test program, instruction block dispatch strategy, and other information are imported after the system link initialization. Instruction block dispatch strategies include random insertion, busy load insertion, and idle load insertion. Under different strategies, instruction blocks will be scheduled and dispatched to processor cores with different statuses. The performance test program is used to test the performance of multi-core processors.

[0025] After initialization, the performance test program undergoes preprocessing. The program's software code is broken down into instruction blocks using a general-purpose compiler. These instruction blocks contain information such as instruction types. Since performance test programs typically contain numerous loop operations, the preprocessing process breaks down these operations, transforming multiple loop operations into instruction blocks that are executed multiple times by a scheduling and control unit. For example... Figure 3 As shown, in one specific embodiment, the Coremark performance testing program, CoreMark, comprises three core modules: list operations, matrix operations, and a state machine. By breaking down the program into smaller, more manageable parts, different functions within each program are further divided to ensure instruction independence, ultimately forming code blocks. This minimizes program granularity for the scheduling module to distribute to different kernels. A timestamp is added to each code block to track runtime and evaluate processor performance. In this process, different functions within machine instructions are split based on preset principles of low dependency and fine granularity to obtain several instruction blocks. This means compiling the test program into instruction blocks that can run on a specified kernel, maintaining fine granularity and eliminating strong dependencies between instruction blocks. The processed instruction blocks are labeled with information such as instruction type (floating-point / integer) and memory access mode (sequential / random) for subsequent scheduling. Maintaining fine granularity and low dependency means that instruction blocks must be small enough for flexible scheduling; blocks must have no strong dependencies and can execute relatively independently on different cores. This simulates the "task parallelism" scenario in modern parallel computing. Tagging: Label each instruction block with attributes, such as: Instruction type: Is it primarily floating-point calculation (suitable for scientific computing and graphics processing) or integer calculation (suitable for general logic and data processing)? Memory access mode: Is it sequential access (e.g., processing arrays) or random access (e.g., querying hash tables)? The final output is a set of independently schedulable "test task packages" with clear labels.

[0026] Step S12: Obtain the performance data of each core of the processor when executing tasks; the performance data includes core utilization, cache hit rate, memory latency and inter-core communication latency.

[0027] In this embodiment of the invention, performance data of each core of the processor is acquired through the performance monitoring unit and sensors within the central processing unit (CPU) during task execution. Specifically, after preprocessing, the monitoring and management interface begins to collect and statistically analyze the core load. This is accomplished through the CPU's internal PMU (Performance Monitoring Unit, a hardware module within modern processors specifically designed to collect various hardware event counts with minimal overhead, such as the number of executed instructions, cache hits / misses, and branch prediction errors) and other performance monitoring and sensor components. Temperature sensors and frequency controllers are also included. Performance data of each core of the multi-core processor is acquired, synchronously collecting indicators such as core utilization, cache hit rate, memory latency, and inter-core communication latency (the speed at which data is transferred between different cores). Detailed status data of the processor during task execution is acquired in real time, providing a basis for intelligent scheduling. Therefore, based on industry-standard hardware characteristics, the accuracy and reliability of the monitoring data are ensured.

[0028] Step S13: Based on the target label and performance data, the instruction block is allocated to the target kernel of the processor so that the target kernel can execute the instruction block and obtain the corresponding test data.

[0029] In this embodiment, instruction blocks are allocated, which is the scheduling behavior performed by the scheduler. The scheduling behavior is determined by a dispatch policy file imported during system initialization. This makes the system very flexible, allowing for easy switching of different policies for comparative testing. Before allocating instruction blocks to the target kernels of the processor based on target tags and performance data, this invention determines the instruction block allocation policy; the allocation policy includes a preset busy load pinning policy and a preset random pinning policy; wherein, the preset busy load pinning policy is a policy of allocating instruction blocks to processor kernels whose load meets preset conditions; the preset random pinning policy is a policy of randomly allocating instruction blocks. Then, based on the allocation policy, the target kernel in the processor corresponding to the instruction block is determined based on the target tag and performance data; the instruction block is allocated to the target kernel so that the target kernel executes the instruction block to obtain corresponding test data; the test data includes the total execution time of the instruction block and the calculation results after the instruction block is executed. Specifically, instruction dispatch is performed based on the dispatch policy imported during system initialization and the kernel load information provided by the monitoring and management interface. For example, if the imported dispatch strategy is busy load pinning, instruction blocks are dispatched to processor cores with high load. If it's random pinning, program blocks are randomly dispatched to different cores. Information such as runtime is collected and summarized for the evaluation and analysis unit. Based on the preset strategy, it determines which instruction block to send to which core for execution. In one specific embodiment, if a core's floating-point computing unit is found to be particularly strong, floating-point instruction blocks are prioritized for it. If a core's cache hit rate is found to be high, random access tasks requiring frequent memory access are dispatched to it to see if its cache advantage can be utilized. Busy load pinning: This is a stress testing strategy. It deliberately dispatches new tasks to already heavily loaded cores. The purpose is to "add fuel to the fire," testing the processor's extreme performance, heat dissipation, and stability (whether it will throttle) on the busiest and hottest cores. Random pinning strategy: This is a basic load balancing strategy. Tasks are randomly assigned, and the processor's natural performance without specific scheduling intervention is observed. Finally, after the instruction block execution is complete, the calculation results and actual runtime are collected, which are the most direct performance data.

[0030] Meanwhile, the scheduling unit can obtain CPU temperature, clock speed, core utilization, memory usage, etc., based on other high-level management interfaces, supporting more detailed and complex scheduling schemes. It acquires target data, including CPU temperature, clock speed, core utilization, and memory usage; based on the target data, it determines the target core of the processor using target tags and performance data, so that instruction blocks can be allocated to the target core. In other words, in addition to core load, the scheduler can obtain richer system status (temperature, clock speed, memory usage). This means that more intelligent and complex strategies can be designed, such as: "Temperature-aware scheduling": avoiding assigning tasks to cores with excessively high temperatures to prevent frequency throttling; "Energy-efficient scheduling": attempting to concentrate tasks on a few cores, allowing other cores to enter a low-power state.

[0031] Step S14: Record the test data and determine the processor's performance test results based on the test data.

[0032] In this embodiment, after multiple tests, all test data are summarized to obtain summarized data. The processor performance test result is determined based on the difference between the current test data and the current average value of the summarized data. Determining the processor performance test result based on the difference between the current test data and the current average value of the summarized data includes: if the difference between the current test data and the current average value of the summarized data is greater than or equal to a preset threshold, a new average value is generated based on the current test data and the summarized data, and the process jumps back to the step of obtaining the performance data of each core of the processor during task execution; if the difference between the current test data and the current average value of the summarized data is less than the preset threshold, the current test data is determined as the processor performance test result. After all program blocks based on a complete set of test programs have been executed, performance test data is collected and recorded. After multiple tests, all results are summarized and analyzed. If the running result deviates significantly from the average value of the previous results, a new average value is generated, and the test process is re-executed. If the deviation between the average value and the new running result is within a certain range, it is considered to meet expectations, and the final value is output. The final test report will include information such as scheduling strategy, environmental parameters, performance score, number of runs and time, for users to analyze and optimize. In other words, the iterative convergence process: Step 1 (Initialization and Collection): Run the test and collect performance data (such as total execution time).

[0033] Step 2 (Judging the bias): Compare the current result with the average of all previous results.

[0034] Scenario A (Large Deviation): If the new result deviates significantly from the historical average, it indicates that the result is still unstable (possibly due to system background tasks, cache not being warmed up, etc.). The system will incorporate the new result into the calculation, generate a new average, and then automatically restart the entire testing process.

[0035] Case B (small deviation): If the deviation between the new result and the historical average is within the preset allowable range (threshold), the data is considered to have converged and the test results are stable and reliable.

[0036] The final output is a comprehensive test report, which includes: Scheduling strategy: which strategy was used (e.g., "busy load pinning"); Environmental parameters: the hardware status during the test (e.g., CPU frequency, temperature, memory usage); Performance score: the final quantitative results (e.g., total execution time, instructions processed per second); Number of runs and time: the actual number of runs for convergence, and the total test duration. The test report is then provided for user analysis: engineers can analyze the effectiveness of different scheduling strategies under different hardware conditions. It also provides optimization data support for operating system scheduler optimization, compiler optimization, and even chip design.

[0037] This ensures that the final output performance data is not the result of a single, accidental run, but rather a repeatable and statistically significant value.

[0038] Furthermore, this invention can also leverage reinforcement learning to allow the scheduler to learn the optimal allocation strategy during testing. Monitoring data serves as the state, dispatching actions as actions, and total execution time as a reward. It simultaneously optimizes multiple dimensions such as performance (speed), energy efficiency (power consumption / performance), and temperature balance, and allows users to set weights. Based on instruction block labels (e.g., "floating-point + random access"), it predicts the execution characteristics of instructions on a specific type of core, making optimal placement decisions in advance. Moreover, when splitting the program into finer-grained, less correlated instruction blocks, dynamic granularity adjustments can be made: when high inter-core communication latency is detected, small task blocks are automatically merged to reduce communication overhead; when core utilization is insufficient, large blocks are split to increase parallelism. Alternatively, it can be based on intelligent partitioning of cache lines and memory pages: aligning the memory access range of instruction blocks with the processor's cache line size and memory page boundaries to maximize cache utilization.

[0039] Beneficial Effects: As can be seen, this invention breaks down the performance testing program into fine-grained, unrelated instruction blocks, and then allocates them according to the load of each processor core. Finally, the results are collected to generate the final performance data. In this way, this invention improves the accuracy of performance testing by implementing a pin-scheduling and scheduling mechanism to break down large-scale performance testing programs and evaluate the performance of multiple cores under different states using instruction blocks.

[0040] As can be seen from the previous embodiment, the present invention is aimed at the performance testing scenario of multi-core processors. In view of the problems of the lack of rigor and incomplete coverage of existing technology tests, a processor performance testing method is disclosed. The specific processor performance testing method will be described in detail below.

[0041] like Figure 4 As shown, the performance test program is a test program used to test the performance of multi-core processors (including various computing tasks such as solving equations, sorting, image processing, etc.).

[0042] The preprocessing unit compiles the test program into instruction blocks that can run on a specified kernel, maintaining fine-grainedness and eliminating strong dependencies between instruction blocks. The processed instruction blocks are tagged with information such as instruction type (floating-point / integer) and memory access mode (sequential / random) to facilitate subsequent scheduling. The compilation and splitting process involves compiling the test program into machine instructions and then breaking it down into multiple smaller instruction blocks. Maintaining fine-grainedness and low dependency means the instruction blocks are small enough for flexible scheduling; there are no strong dependencies between blocks, allowing them to execute relatively independently on different cores. This simulates the "task parallelism" scenario in modern parallel computing. Tagging involves labeling each instruction block with attributes such as: Instruction type: primarily floating-point calculation (suitable for scientific computing and graphics processing) or integer calculation (suitable for general logic and data processing); Memory access mode: sequential access (e.g., processing arrays) or random access (e.g., querying hash tables). The final output is a set of clearly tagged, independently schedulable "test task packages."

[0043] Monitoring and Management Interface: Acquires performance data for each core of the multi-core processor, synchronously collecting metrics such as core utilization, cache hit rate, memory latency, and inter-core communication latency. Monitoring content includes: Core Utilization: How busy is each core? Cache Hit Rate: The success rate of the processor retrieving data from the cache; a low hit rate indicates slow memory performance. Memory Latency: How long does it take to read data from memory? Inter-core Communication Latency: The speed at which data is transferred between different cores. This allows for real-time acquisition of detailed status data of the processor during task execution, providing a basis for intelligent scheduling.

[0044] The scheduling and control unit, based on information from the monitoring and management interface and a preset distribution strategy, dispatches instruction blocks to designated kernels for execution and collects information such as execution results and runtime. The scheduling and control unit obtains tagged instruction blocks from the preprocessing unit. It acquires real-time performance data for each core from the monitoring and management interface. Based on the preset strategy, it determines which instruction block to send to which core for execution.

[0045] Example Strategy 1: If a certain core's floating-point calculation unit is found to be particularly powerful, then floating-point instruction blocks are preferentially assigned to it.

[0046] Example Strategy 2: If a certain core has a high cache hit rate, assign random access tasks that require frequent memory access to it to see if its cache advantage can be utilized.

[0047] After the instruction block is executed, the calculation results and actual running time are collected, which are the most direct performance data.

[0048] Evaluation and Analysis Unit: This unit records and evaluates the generated test data. When multiple performance evaluations converge, the test data is considered convincing. It systematically records the runtime collected by the scheduling control unit and various metrics collected by the monitoring interface. Analyzing this data yields conclusions about the processor's performance, such as: "Under mixed floating-point and random memory access loads, the parallel efficiency of an 8-core processor is 70%." Ensuring credibility: A key point is—multiple calculations until the performance evaluation results converge. This means the system repeatedly runs tests (possibly adjusting scheduling strategies). Only when the results of multiple tests stabilize and no longer fluctuate significantly is the data considered reliable and convincing enough for the final report.

[0049] In this way, the present invention breaks down the performance testing program into fine-grained, unrelated instruction blocks, which are then allocated by the scheduling unit according to the load of each core. The allocation strategy can follow a random scheme or be directed based on kernel load. Finally, the results are collected to generate the final performance data. Through intelligent scheduling and comprehensive monitoring, it deeply reveals the micro-behavior of the processor under different types of tasks (such as cache efficiency and memory latency impact), thus providing invaluable data insights for chip design, system tuning, and compiler optimization. Its ultimate goal is to produce scientific, reliable, and repeatable performance evaluation results.

[0050] See Figure 5 As shown, an embodiment of the present invention provides a processor performance testing device, comprising: The tagging module 11 is used to compile the performance test program into machine instructions, split the machine instructions into several instruction blocks, and tag each instruction block according to the target label; the target label includes instruction type and memory access mode; the instruction type includes floating-point calculation type and integer calculation type; The performance data acquisition module 12 is used to acquire the performance data of each core of the processor when executing tasks; the performance data includes core utilization, cache hit rate, memory latency and inter-core communication latency; The instruction block execution module 13 is used to allocate instruction blocks to the target kernel of the processor based on the target label and performance data, so that the target kernel executes the instruction blocks and obtains the corresponding test data. The performance test result determination module 14 is used to record test data and determine the processor's performance test results based on the test data.

[0051] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0052] Beneficial Effects: As can be seen, this invention breaks down the performance testing program into fine-grained, unrelated instruction blocks, and then allocates them according to the load of each processor core. Finally, the results are collected to generate the final performance data. In this way, this invention improves the accuracy of performance testing by implementing a pin-scheduling and scheduling mechanism to break down large-scale performance testing programs and evaluate the performance of multiple cores under different states using instruction blocks.

[0053] Furthermore, embodiments of the present invention also disclose an electronic device, Figure 6 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of the invention. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the processor performance testing method disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0054] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this invention, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0055] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0056] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the processor performance testing method executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0057] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned processor performance testing method. The specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0058] Furthermore, this application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned disclosed processor performance testing method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0059] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0060] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0061] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0062] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0063] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A processor performance testing method, characterized in that, include: The performance test program is compiled into machine instructions, and the machine instructions are broken down into several instruction blocks. Each instruction block is marked according to a target label. The target label includes the instruction type and memory access mode. The instruction type includes floating-point calculation type and integer calculation type. Acquire performance data of each core of the processor when executing tasks; the performance data includes core utilization, cache hit rate, memory latency, and inter-core communication latency; Based on the target label and the performance data, the instruction block is assigned to the target kernel of the processor, so that the target kernel executes the instruction block and obtains the corresponding test data. The test data is recorded, and the performance test results of the processor are determined based on the test data.

2. The processor performance testing method according to claim 1, characterized in that, The step of splitting the machine instructions into several instruction blocks includes: Based on the preset principles of low correlation and fine granularity, the different functions in the machine instructions are split into several instruction blocks.

3. The processor performance testing method according to claim 1, characterized in that, The acquisition of performance data of each core of the processor during task execution includes: The CPU acquires performance data of each core during task execution through performance monitoring units and sensors within the CPU.

4. The processor performance testing method according to claim 1, characterized in that, Before allocating the instruction block to the target kernel of the processor based on the target label and the performance data, the method further includes: Determine the allocation strategy for the instruction block; the allocation strategy includes a preset busy load pin insertion strategy and a preset random pin insertion strategy; The preset busy load pin insertion strategy is a strategy to allocate the instruction block to a processor core whose load meets preset conditions; the preset random pin insertion strategy is a strategy to randomly allocate the instruction block. Accordingly, the allocation of the instruction block to the target kernel of the processor based on the target label and the performance data, so that the target kernel executes the instruction block and obtains the corresponding test data, includes: Based on the target label and the performance data, the target kernel in the processor corresponding to the instruction block is determined according to the allocation strategy. The instruction block is assigned to the target kernel so that the target kernel executes the instruction block to obtain corresponding test data; the test data includes the total execution time of the instruction block and the calculation results after the instruction block is executed.

5. The processor performance testing method according to claim 1, characterized in that, Also includes: Acquire target data; the target data includes central processing unit temperature, clock frequency, kernel utilization, and memory usage. Based on the target data, the target kernel of the processor is determined according to the target label and the performance data, so that the instruction block is allocated to the target kernel.

6. The processor performance testing method according to any one of claims 1 to 5, characterized in that, Determining the processor's performance test results based on the test data includes: After multiple tests, all test data are summarized to obtain the summarized data; The processor's performance test result is determined based on the difference between the current test data and the current average value of the aggregated data.

7. The processor performance testing method according to claim 6, characterized in that, Determining the processor's performance test result based on the difference between the current test data and the current average of the aggregated data includes: If the difference between the current test data and the current average value of the aggregated data is greater than or equal to a preset threshold, a new average value is generated based on the current test data and the aggregated data, and the process jumps back to the step of obtaining the performance data of each core of the processor when executing the task. If the difference between the current test data and the current average value of the aggregated data is less than the preset threshold, then the current test data is determined as the performance test result of the processor.

8. A processor performance testing device, characterized in that, include: A tagging module is used to compile the performance test program into machine instructions, split the machine instructions into several instruction blocks, and tag each instruction block according to a target label; the target label includes instruction type and memory access mode; the instruction type includes floating-point calculation type and integer calculation type; The performance data acquisition module is used to acquire the performance data of each core of the processor when executing tasks; the performance data includes core utilization, cache hit rate, memory latency, and inter-core communication latency. An instruction block execution module is used to allocate the instruction block to the target kernel of the processor based on the target label and the performance data, so that the target kernel executes the instruction block and obtains the corresponding test data. The performance test result determination module is used to record the test data and determine the performance test result of the processor based on the test data.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the processor performance testing method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the processor performance testing method as described in any one of claims 1 to 7.

Images