Data operation method and device
By finding and updating entries in the commit storage buffer in the cache, the high power consumption problem caused by frequent evictions and backfills in the cache is solved, improving cache management efficiency and reducing system power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU QUNXIN MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2025-12-24
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, frequent eviction and refilling of cache lines with the same address in the cache leads to high system power consumption.
When an eviction event occurs in the cache, the commit storage buffer (CSB) is searched for an entry that matches the cache line address, the cache line data is updated, and the entry is evicted to the next level cache. At the same time, the entry is released and the entry is backed up in the CSB for subsequent load operations.
It effectively reduces unnecessary caching operations, improves cache management efficiency, and reduces system power consumption.
Smart Images
Figure CN122019409A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of computer technology, and in particular to a data manipulation method and apparatus. Background Technology
[0002] In computer systems, data storage devices (such as hard drives and databases) have relatively slow read and write speeds. Caching stores frequently accessed data in high-speed storage media (such as memory and cache chips), enabling data to be accessed faster and reducing memory access latency. With the development of computer technology, multi-level caching architectures have emerged, including Level 1 Cache (L1D Cache) and Level 2 Cache (L2D Cache). Level 1 Cache is typically integrated inside the CPU chip, has a smaller capacity but the fastest speed; Level 2 Cache can be a larger capacity cache integrated inside the CPU chip or a high-speed cache chip located outside the CPU chip.
[0003] Because cache capacity is limited, some cache lines will be evicted from the cache under certain conditions, moving them to lower-level caches or other storage media to allow the cache to accommodate new data. When the cache needs certain data, the required cache lines need to be refilled from lower-level caches or storage media. Evicting and refilling data in the cache need to be performed at different cache levels. Frequent eviction and refilling of cache lines at the same address increases memory access frequency, thereby increasing system power consumption.
[0004] How to control data operations in the cache to reduce the frequent eviction and refilling of cache lines at the same address, thereby reducing system power consumption, is an urgent problem to be solved. Summary of the Invention
[0005] To address the problems in the prior art, this specification provides a data manipulation method and apparatus that solves the problem of high system power consumption caused by frequent eviction and refilling of cache lines with the same address in the prior art.
[0006] This specification provides a data manipulation method, which includes:
[0007] When an event occurs in the cache that evicts the first cache line, look up the first entry in the Committed Storage Buffer (CSB) that has an address that matches the first cache line;
[0008] Update the data of the first cache line based on the data in the first table entry;
[0009] The first cache line is evicted to the next lower-level cache, and the first entry is released.
[0010] As a further aspect of this specification, when an event occurs in the cache that evicts a first cache line, the process includes, before looking up a first entry in the Committed Storage Buffer (CSB) that has an address matching the first cache line:
[0011] When performing a storage operation, the CSB searches the cache for a first cache line that matches the first address corresponding to the storage operation;
[0012] An event occurs in the cache that evicts the first cache line when no data is written to the first cache line.
[0013] As a further aspect of this specification, evicting the first cache line to a lower-level cache and releasing the first entry further includes: backing up the first entry to form a backup entry.
[0014] As a further aspect of this specification, when updating the cached line data in the cache based on the data of the table entry in the CSB, the data of the backup table entry that matches the address of the CSB table entry is also updated.
[0015] As a further aspect of this specification, after evicting the first cache line to a lower-level cache and releasing the first entry, the method further includes:
[0016] When performing a load operation, the target entry in the backup table that matches the second address is found based on the second address corresponding to the load operation.
[0017] Load the data for the target table entry.
[0018] As a further aspect of this specification, based on the second address corresponding to the load operation, the following target table entry or target cache line matching the second address is located:
[0019] Find the target entry in the storage queue list that matches the second address;
[0020] Locate the target entry in the CSB that matches the second address;
[0021] Locate the target cache line in the cache that matches the second address.
[0022] As a further aspect of this specification, after obtaining the target table entry or target cache line that matches the second address of the load operation, the following is also included:
[0023] Load the data of the target table entry or target cache row.
[0024] As a further aspect of this specification, the data for loading the target table entry or target cache row also includes:
[0025] The target entry or target cache line that matches the second address is selected for loading based on priority.
[0026] As another further aspect of this specification, the order of priority from highest to lowest includes:
[0027] Storage queue list entries, CSB entries, backup entries, and cache lines in the cache.
[0028] This specification also provides a data manipulation device, including:
[0029] The lookup unit is configured to, when an event occurs in the cache that evicts a first cache line, look up a first entry in the commit storage buffer (CSB) that has an address that matches the address of the first cache line;
[0030] The update unit is configured to update the data of the first cache line based on the data in the first table entry;
[0031] The eviction unit is configured to evict the first cache line to a lower-level cache and release the first entry.
[0032] This specification also provides a loading / storage unit, including a storage queue, a submission storage buffer, and a cache, wherein the loading / storage unit performs the above-described method.
[0033] This specification also provides a processor, including the above-described load / store unit, in its embodiments.
[0034] This specification also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is the processor described above.
[0035] This specification also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the above-described method.
[0036] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.
[0037] Using the embodiments in this specification, the data in the commit storage buffer is directly updated to update the evicted cache line, and the cache line is then transmitted to the next level cache (L2D). This effectively reduces these unnecessary operations, improves the efficiency of cache management, and reduces system power consumption. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 The diagram shown is a schematic representation of the process by which the CPU stores data in the L1D according to an embodiment of this specification.
[0040] Figure 2 The diagram shown is a flowchart of a data manipulation method according to an embodiment of this specification;
[0041] Figure 3 The diagram shown is a data structure diagram of the backup device in an embodiment of this specification;
[0042] Figure 4 The diagram shown is a flowchart of a data storage method according to an embodiment of this specification.
[0043] Figure 5 The diagram shown is a flowchart of a data loading method according to an embodiment of this specification.
[0044] Figure 6 The diagram shown is a structural schematic of the Load / Storage Unit (LSU) in an embodiment of this specification.
[0045] Figure 7 The diagram shows a different loading operation.
[0046] Figure 8 The diagram shown is a schematic diagram of a data manipulation device according to an embodiment of this specification.
[0047] Figure 9 This is a computer device provided as an embodiment of the present specification.
[0048] [Explanation of Labels in the Attached Image]
[0049] 801. Search Unit;
[0050] 802. Update Unit;
[0051] 803, Expulsion Unit;
[0052] 902. Computer equipment;
[0053] 904, Processor;
[0054] 906. Memory;
[0055] 908. Drive mechanism;
[0056] 910. Input / Output Module;
[0057] 912. Input devices;
[0058] 914. Output devices;
[0059] 916. Presentation equipment;
[0060] 918. Graphical User Interface;
[0061] 920. Network interface;
[0062] 922. Communication link;
[0063] 924. Communication bus. Detailed Implementation
[0064] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.
[0065] To further optimize processor performance, a store queue was introduced. A store queue is a small, high-speed storage area within the processor used to temporarily store data about to be written to main memory or cache. Its primary purpose is to address write operation latency and memory consistency issues. The commit store buffer (CSB) lies between the store queue and the cache / main memory, and it merges (i.e., updates) write requests to the store on a cache line-by-line basis.
[0066] When data in the Commit Store Buffer is ready to be written to the L1D Cache (Level 1 data cache, hereinafter referred to as L1D), a Cache Lookup is first performed to confirm whether the target address of the data table entry to be stored is in a cache line of the L1D cache, so as to complete the subsequent write operation to L1D. If the cache line for the target address is not in L1D, the processor will initiate a request to load the entire cache line into L1D from a higher-level cache (such as L2D Cache or L3D Cache) or main memory (this process is called cache line fill). Once the cache line is successfully loaded into L1D, the processor will write the data in the Commit Store Buffer to the corresponding position in that cache line.
[0067] If the Commit Store Buffer has completed a lookup and confirmed that the cache line at the target address is in the L1D, but the cache line is evicted before the data is written to it (usually triggered by a cache replacement algorithm), the Commit Store Buffer needs to look up the L1D again and retrieve the data from the next level cache / memory to fill the L1D.
[0068] like Figure 1 The diagram illustrates the process of the CPU storing data in the L1D according to an embodiment of this specification. The store instruction, also known as a write instruction or store instruction, involves the CPU temporarily storing the data to be stored in the Store Queue. When the data is ready to be stored in the L1D, it is placed in the Commit Store Buffer (CSB). The Commit Store Buffer can merge write operations, reducing cache access and operations. When the Commit Store Buffer wants to write data to the L1D, it first searches the L1D. If the cache line at the corresponding address is in the L1D, the data can be written. If the cache line at the corresponding address is not in the L1D (cache miss), a lookup request is sent to the lower-level cache to fill the cache line back into the L1D. Afterward, the Commit Store Buffer can access the L1D and write the data.
[0069] When the L1D (Lack of Cache) evicts a cache line, if the commit store buffer already has a corresponding entry that has completed a cache lookup, it clears the lookup completion flag for that entry. The commit store buffer then performs another cache lookup (which, given that the cache line was just evicted, usually results in a cache miss). After the cache miss, it sends a request to the lower-level cache to refill the cache line into the L1D. The commit store buffer can then access the cache (L1D) and write the data. This leads to the problem of frequent evictions and refills of cache lines targeting the same address.
[0070] This specification provides a data manipulation method and apparatus that can reconstruct the behavior strategy for committing storage buffers during cache eviction, and further optimize this strategy to avoid frequent data eviction and refilling in L1D. Figure 2The diagram shows a flowchart of a data operation method according to an embodiment of this specification. The flowchart describes how, when evicting a cache line, the method involves querying an entry in the CSB with the same address, updating the cache line data using the data from that entry, and then evicting both the entry in the CSB and the cache line in the cache to the next-level cache. The order of steps in this method is only one implementation and does not preclude the use of other orders to achieve the same purpose as the embodiments of this specification. The method specifically includes:
[0071] Step 201: When an event occurs in the cache that evicts the first cache line, look up the first entry in the Committed Storage Buffer (CSB) that has an address that matches the first cache line.
[0072] Step 202: Update the data of the first cache row according to the data in the first table entry;
[0073] Step 203: Evict the first cache line to the next level cache and release the first table entry.
[0074] The method described in this specification directly updates the evicted cache line with data from the commit storage buffer and transmits the cache line to the next-level cache (L2D), effectively reducing these unnecessary operations, improving cache management efficiency, and reducing system power consumption.
[0075] In this embodiment of the specification, when an event occurs in the cache that evicts a first cache line, the method further includes, before looking up a first entry in the Committed Storage Buffer (CSB) that has an address matching the first cache line:
[0076] When performing a storage operation, the CSB searches the cache for a first cache line that matches the first address corresponding to the storage operation;
[0077] An event occurs in the cache that evicts the first cache line when no data is written to the first cache line.
[0078] In this embodiment, when executing the `store` instruction to store data to the cache, the commit storage buffer first checks if there is a cache line in the L1D cache with the same address as the table entry to be stored. If a cache line with the same address exists, the data is then written to the corresponding cache line in the L1D cache. If, during this process, before writing the data to the L1D cache, an L1D cache line is evicted, the check completion flag in the commit storage buffer is cleared. When continuing to execute the `store` instruction to store data to the cache, it is necessary to check again if there is a cache line in the L1D cache with the same address as the table entry to be stored. Due to the aforementioned eviction, the corresponding cache line does not exist in the L1D cache, so the cache line needs to be refilled from the lower-level cache, and the data is written to the L1D. This process not only increases cache access contention but also leads to multiple data transfers between different levels of cache, increasing power consumption. By updating the evicted cache line with data from the entry at the same address in the commit storage cache during the process of evicting the cache line in L1D, and then completing the eviction of the L1D cache line, the storage instruction is completed during the eviction process, thus avoiding the problem of repeatedly refilling the cache after the cache line is evicted.
[0079] In the embodiments of this specification, evicting the first cache line to the lower-level cache and releasing the first table entry further includes: backing up the first table entry to form a backup table entry.
[0080] In this embodiment, while evicting the first cache line to the next lower-level cache, the first entry in the commit storage cache with the same address as the evicted first cache line can be released, or the first entries in the commit storage cache with the same address as the evicted first cache line can be released sequentially. Simultaneously, the evicted first cache line or first entry can be stored in a backup device. This backup device can be a high-speed storage medium similar to the commit storage cache or L1D, used to store the data of the evicted first cache line or first entry. This allows the CPU to quickly retrieve the data of the evicted cache line from the backup device when performing a load operation on a cache line with the same address within a certain period of time.
[0081] In this embodiment, the eviction of a cache line may include the following steps: determining the cache line to be evicted, i.e., the first cache line; determining whether the state of the first cache line is modified; writing the data in the first cache line to the next-level cache (e.g., L2D or main memory); marking the state of the first cache line as invalid; and deleting the first cache line from L1D; subsequent new cache lines occupy the physical address of the first cache line. The release may refer to physically deleting and releasing the resources in the committed storage cache area, or it may not involve directly deleting the table entry, but simply clearing the valid bits of the table entry.
[0082] In the embodiments of this specification, when updating the cache line data in the cache according to the data of the table entry in the CSB, the data of the backup table entry that matches the address of the CSB table entry is also updated.
[0083] In this embodiment, the structure of the backup device is similar to that of the commit storage cache, but the number of entries is significantly reduced, such as... Figure 3 The diagram shown is a data structure diagram of the backup device according to an embodiment of this specification. The diagram describes the data structure of the backup device, which includes at least a valid field, indicating whether the entry is valid; an addr field, indicating the address of the entry; a data field, indicating the data content; and a byte valid field, indicating the valid bits of the data.
[0084] In this embodiment, when backing up the updated first cache line or the first entry of the committed storage cache to the backup device, an entry can be directly inserted into the backup device. Alternatively, the backup device can first be checked to see if there is a backup entry with the same address. If there is an entry with the same address as the first cache line (which is equivalent to the same address as the first entry of the committed storage cache), the data of the updated first cache line or the first entry of the committed storage cache can be used to update the backup entry. This ensures that the backup device maintains the latest data, so that the latest data can be obtained when performing a load operation on that address.
[0085] In the embodiments of this specification, after evicting the first cache line to the lower-level cache and releasing the first table entry, the method further includes:
[0086] When performing a load operation, the target entry in the backup table that matches the second address is found based on the second address corresponding to the load operation.
[0087] Load the data for the target table entry.
[0088] In this embodiment, when a subsequent load instruction requires a load operation, it is necessary to check whether the address corresponding to the load operation exists in the storage queue or L1D, and also to check whether it exists in the backup device. As can be seen from the previous embodiments, when a cache line is evicted in L1D, the cache line in L1D and the entry in the committed storage cache are cleared. If the address involved in the load operation does not exist in the storage queue, the data of the corresponding cache line needs to be backfilled into L1D from the lower-level cache, so that the data of the cache line can be obtained from L1D through the load operation. In this embodiment, the CPU can query whether a corresponding cache line address exists in the storage queue, backup device, or L1D. If any memory includes the cache line address, the data of the cache line or table entry can be directly loaded. When the cache line address is not included in the storage queue and L1D, but is included in the backup device, it means that the cache line with the same address in the aforementioned L1D operation was evicted, and there is no cache line with the corresponding address in the storage queue. The backup device can avoid the operation of backfilling cache line data from the lower-level cache to the L1D. The target table entry that was just evicted from the L1D can be directly obtained from the backup device for loading operations.
[0089] In this embodiment of the specification, based on the second address corresponding to the load operation, the following target table entry or target cache line matching the second address is searched:
[0090] Find the target entry in the storage queue list that matches the second address;
[0091] Locate the target entry in the CSB that matches the second address;
[0092] Locate the target cache line in the cache that matches the second address.
[0093] In this embodiment, when a loading operation is to be performed, the CPU can simultaneously search for a target entry or target cache line that matches the second address in the storage queue, the commit storage buffer, the backup device, and the L1D. When any of them has a record (target entry or target cache line) with the same second address, the data of that record can be loaded into the CPU for processing.
[0094] In another embodiment, the storage queue, commit storage buffer, and backup device are all high-speed memories compared to L1D. Therefore, the selection order is determined primarily based on the memory speed. For example, the storage queue is searched; if no record with the same second address is found in the storage queue, the commit storage buffer is searched; if no record with the same second address is found in the storage queue, the backup device is searched; if no record with the same second address is found in the backup device, the L1D is searched. If a record can be obtained from any of the memories, the record can be selected for loading based on the memory priority. For example, the data of the target entry or target cache line obtained from the storage queue, commit storage buffer, backup device, and L1D is selected for loading based on their priorities. For instance, if no matching target entry is found in the storage queue or commit storage buffer, but the backup device finds a matching target entry, and the L1D finds a matching target cache line, and the priority of the backup device is higher than that of the L1D, then the target entry found by the backup device is selected for loading.
[0095] The method described in the embodiments of this specification directly merges the data in the commit storage buffer with the evicted cache line and transmits them together to the lower-level cache, effectively reducing the repeated operation of refilling evicted cache lines and improving the efficiency of cache management. By adding a backup device, it is ensured that during L1D cache eviction operations, the data in the merged commit storage buffer is backed up to the backup device. Subsequent load operations can directly retrieve data from the backup device, avoiding cache miss delays and significantly improving the efficiency of load operations.
[0096] like Figure 4 The diagram shown is a flowchart of a data storage method according to an embodiment of this specification. This diagram describes the process of storing data to be stored in the L1D via a storage queue and a commit storage buffer when the CPU stores data. The method includes:
[0097] Step 401: Submit the storage operation from the storage queue to the CSB.
[0098] In this step, there is a Store operation in the Store Queue: address (Addr) is 0x0, data length (size) is 4 bytes, and data (Data) is 0xF. After this operation is submitted to the CSB, let's assume it's CSB entry 0. Entry 0 is automatically aligned to the address granularity of the cache line, the data length is marked as 32 bytes (matching the address range of the cache line), the address remains 0x0, and the data to be written is still 0xF.
[0099] Step 402: The CSB table entry performs an L1D cache lookup.
[0100] In this step, the CSB entry checks if a cache line matching the address exists in the L1D (i.e., whether there is a cache hit), preparing for data writing. Specifically, CSB entry 0 has an address of 0x0, and a cache line with address 0x0 and a size of 64 bytes already exists in the L1D. Since the address of entry 0 falls within the address range of this cache line (0x0~0x3F), a cache hit occurs, and entry 0 gains permission to write data to this cache line.
[0101] In another embodiment, if a cache miss occurs, the cache line at address 0x0 is searched from the lower-level cache (e.g., L2D), and once found, the cache line is backfilled into L1D.
[0102] Step 403, L1D cache line eviction.
[0103] In this step, if L1D cache line is found to be out of space, the cache line at address 0x0 is selected as the object to be evicted and prepared to be moved to L2 Cache. The L1D cache line to be evicted has the following characteristics: address 0x0, size 64 bytes, current data 0xF.
[0104] This step occurs after the storage operation has located the corresponding cache line and modified its state. However, this step may not occur. If it does not occur, a regular storage operation is performed, writing the data in the CSB table entry into the cache line corresponding to the L1D.
[0105] Step 404: The CSB entry is merged with the cache line to be evicted.
[0106] In this step, the data to be written in the CSB entry is merged into the corresponding address of the cache line to be evicted, generating the latest data, and the CSB entry is released. Specifically, when L1D looks up the CSB, it finds that the address of entry 0 (0x0) matches the address of the cache line to be evicted. A merge operation is performed, writing the data to be written, 0xF, of entry 0 into the address range 0x0~0x3 in the cache line, merging it with the original data in the cache line to generate the latest data 0xF. After the merge is complete, CSB entry 0 is released (i.e., removed from the CSB).
[0107] Step 405: The L1D cache line is evicted into the L2 cache.
[0108] In this step, the cache line containing the latest data after merging is moved from L1D to L2 Cache, thus freeing up space in L1D. Specifically, L1D uses a cacheline evict operation to move the cache line at address 0x0, with a size of 64 bytes and data of 0xF, to L2 Cache; at the same time, the valid bits of this cache line in L1D are marked as invalid, freeing up space for subsequent loading of new data.
[0109] like Figure 5 The diagram shown is a flowchart of a data loading method according to an embodiment of this specification. This diagram describes the basic process and logic of the CPU evicting a cache line at a specific address. Figure 4 The process is similar, but the difference lies in that the CSB entry is also stored in a backup device when it is merged with the cache line to be evicted. This allows for rapid loading of the cache line data when it is needed. The method includes:
[0110] Step 501: The Load operation enters the Load Queue and initiates a multi-component search request.
[0111] In this step, after the Load operation is scheduled, it enters the Load Queue and simultaneously sends address matching lookup requests to the Store Queue, CSB, backup settings, and L1D cache to obtain the target data. In this embodiment, lookup requests can be sent to multiple components simultaneously. Specifically, this step includes: the target Load operation has an address (Addr) of 0x0 and a data length (size) of 2 bytes; after entering the Load Queue, the operation synchronously sends lookup requests to the Store Queue, CSB, backup settings, and L1D, with the request content being the search for the corresponding data at address 0x0.
[0112] Step 502, the storage queue reports a miss.
[0113] In this step, the Load operation searches for an uncommitted store entry with a matching address in the Store Queue, but no matching record is found. Specifically, the Load operation searches for the entry at address 0x0 in the Store Queue, but no corresponding record is found. Therefore, the result is a Store Queue Miss, and data cannot be retrieved from the Store Queue.
[0114] Step 503, CSB reports a miss.
[0115] In this step, the Load operation searches for a committed store entry with a matching address in the CSB, but no matching record is found. Specifically, the Load operation searches for the entry at address 0x0 in the CSB. Since this entry was released in a previous store operation, no corresponding record was found, resulting in a CSB Miss, and data cannot be retrieved from the CSB.
[0116] Step 504, the backup device reports a successful hit.
[0117] In this step, the Load operation searches for data with a matching address in the backup settings, finds the corresponding record, and extracts the data of the target length. Specifically, the Load operation searches for data at address 0x0 in the backup settings and finds that the corresponding entry (Addr:0x0, size:4, Data:0xF) is stored in the backup settings. Since the target length of the Load operation is 2 bytes, the corresponding part is extracted from this data, and finally the data 0x3 is obtained. This state indicates a hit.
[0118] It can also be like Figure 6 The diagram shown is a structural schematic of the Load / Store Unit (LSU) according to an embodiment of this specification. The internal structure of the LSU is described in this diagram. The LSU is a Load / Store Unit, which includes components such as a storage queue, a load queue, a CSB, a backup device, and an L1D. The LSU also includes other components not shown in this diagram. The load queue can also be connected to components such as the storage queue, CSB, backup device, and L1D. The backup device can receive data backed up by the CSB and can also transfer data with the storage queue and the load queue through a pipeline.
[0119] Step 505, L1D feedback missed.
[0120] In this step, the Load operation searches for the corresponding cache line in the L1D cache, but no valid cache line is found. Specifically, the Load operation searches for the cache line at address 0x0 in L1D, but this cache line has been moved to the L2 cache by a previous eviction operation. There is no valid record in L1D, so the result is an L1D Cache Miss.
[0121] Step 506: Backfill data from L2 cache to L1D.
[0122] In this step, due to an L1D cache miss, an operation to find the corresponding cache line in the L2 cache is triggered, and the data is then filled back into the L1D cache. Specifically, L1D sends a fill request to the L2 cache, requesting a cache line with address 0x0 and a size of 64 bytes; the L2 cache returns the previously received evicted cache line (Addr:0x0, size:64, Data:0xF) to L1D, completing the filling of the L1D cache line for subsequent operations.
[0123] like Figure 7 The diagram shown illustrates another loading operation process, which you can refer to. Figure 5 Content comprehension Figure 7 The process is as follows: after the load operation is initiated, it simultaneously checks whether there is a record with the same address as the target address in the storage queue, the commit storage buffer, the backup device, and the Level 1 cache (L1D). If any component has a record with the same address (i.e., a hit), the load operation can be completed. The priority order for selecting records in each type of storage is: storage queue > commit storage buffer > backup device > backup device > cache (L1D). If there is no record with the same address in any of them (a hit), a request is sent to the L2 cache to request data to be filled back into the L1D, and then the load queue loads the target data from the L1D.
[0124] like Figure 8 The diagram shown is a schematic representation of a data manipulation device according to an embodiment of this specification. The units in this diagram may be composed of circuits or machine instructions. Specifically, the device includes:
[0125] The lookup unit 801 is configured to look up a first entry in the commit storage buffer that has an address matching the address of the first cache line when an event occurs in the cache that evicts the first cache line.
[0126] The update unit 802 is configured to update the data of the first cache line based on the data in the first table entry;
[0127] Eviction unit 803 is configured to evict the first cache line to a lower-level cache and release the first entry.
[0128] It also includes a backup device 804, configured to evict the first cache line to the lower-level cache and release the first table entry to back up the first table entry; when performing a loading operation, according to the second address corresponding to the loading operation, it searches for a target table entry in the backup table entry of the backup device that matches the second address, and loads the data of the target table entry.
[0129] This specification also provides a load / store unit (LSU) including a storage queue, a commit storage buffer, and a cache, wherein the load / store unit performs the methods described above.
[0130] In a further embodiment, the load / store unit further includes a backup device configured to store the first entry to form a backup entry when the first cache line is evicted to a lower-level cache and the first entry is released. The method described in the foregoing embodiments can be implemented in conjunction with other components in the LSU, such as load queues, store queues, commit store buffers, and caches.
[0131] In another embodiment, the backup device can also perform the same function outside of the loading / storage unit.
[0132] This specification also provides a processor, including the above-described load / store unit, in its embodiments.
[0133] like Figure 9 The illustration shows a computer device provided in an embodiment of this specification. The methods described in this embodiment can be run on the computer device described above. The computer device 902 may include one or more processors 904, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 902 may also include any memory 906 for storing information of any kind, such as code, settings, data, etc. Non-limitingly, for example, the memory 906 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the computer device 902. In one case, when the processor 904 executes associated instructions stored in any memory or combination of memories, the computer device 902 can perform any operation of the associated instructions. The computer device 902 also includes one or more drive mechanisms 408 for interacting with any memory, such as hard disk drive mechanisms, optical disk drive mechanisms, etc.
[0134] Computer device 902 may also include an input / output module 910 (I / O) for receiving various inputs (via input device 912) and providing various outputs (via output device 914). A specific output mechanism may include a presentation device 916 and an associated graphical user interface (GUI) 918. In other embodiments, the input / output module 910 (I / O), input device 912, and output device 914 may be omitted, and the device may function solely as a computer device within a network. Computer device 902 may also include one or more network interfaces 920 for exchanging data with other devices via one or more communication links 922. One or more communication buses 924 couple the components described above together.
[0135] Communication link 922 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 922 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.
[0136] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the methods described above.
[0137] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.
[0138] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.
[0139] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.
[0140] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0141] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.
[0142] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.
[0143] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0144] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0145] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.
Claims
1. A data manipulation method, characterized in that, The method includes: When an event occurs in the cache that evicts the first cache line, look up the first entry in the Committed Storage Buffer (CSB) that has an address that matches the first cache line. Update the data of the first cache line based on the data in the first table entry; The first cache line is evicted to the next lower-level cache, and the first entry is released.
2. The method according to claim 1, characterized in that, When an event occurs in the cache that evicts the first cache line, the process of finding the first entry in the Committed Storage Buffer (CSB) that has an address matching the first cache line includes: When performing a storage operation, the CSB searches the cache for a first cache line that matches the first address corresponding to the storage operation; An event occurs in the cache that evicts the first cache line when no data is written to the first cache line.
3. The method according to claim 1, characterized in that, Evicting the first cache line to a lower-level cache and releasing the first table entry further includes: backing up the first table entry to form a backup table entry.
4. The method according to claim 3, characterized in that, When updating the cached line data in the cache based on the data of the table entries in the CSB, update the data of the backup table entries that match the table entry address of the CSB.
5. The method according to claim 3, characterized in that, After evicting the first cache line to the next-level cache and releasing the first entry, the process further includes: When performing a load operation, the target entry in the backup table that matches the second address is found based on the second address corresponding to the load operation. Load the data for the target table entry.
6. The method according to claim 5, characterized in that, Based on the second address corresponding to the load operation, find the following target table entry or target cache line that matches the second address: Find the target entry in the storage queue list that matches the second address; Locate the target entry in the CSB that matches the second address; Locate the target cache line in the cache that matches the second address.
7. The method according to claim 6, characterized in that, After obtaining the target table entry or target cache line that matches the second address of the load operation, the following is also included: Load the data of the target table entry or target cache row.
8. The method according to claim 7, characterized in that, The data loaded for the target table entry or target cache row also includes: The target entry or target cache line that matches the second address is selected for loading based on priority.
9. The method according to claim 8, characterized in that, The order of priority from largest to smallest includes: Storage queue list entries, CSB entries, backup entries, and cache lines in the cache.
10. A data manipulation device, characterized in that... include: The lookup unit is configured to, when an event occurs in the cache that evicts the first cache line, look up a first entry in the commit storage buffer (CSB) that has an address that matches the address of the first cache line. The update unit is configured to update the data of the first cache line based on the data in the first table entry; The eviction unit is configured to evict the first cache line to a lower-level cache and release the first entry.
11. A loading / storage unit, characterized in that... It includes a storage queue, a submission storage buffer, and a cache, wherein the loading / storage unit performs the method described in any one of claims 1-9.
12. The load / store unit according to claim 11, characterized in that, It also includes a backup device, wherein the loading / storage unit performs the method described in any one of claims 3-9.
13. A processor, characterized in that, Includes the loading / storage unit as described in claim 11 or 12.
14. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor is the processor described in claim 13.
15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the method of any one of claims 1-9.
16. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1-9.