Interrupt information processing system, method and chip

Abstract

According to the interrupt information processing system, method and chip provided by the invention, interrupt strategy processing is carried out on user interrupt information through interrupt strategy configuration information built in an interrupt strategy management module, so that distribution, priority scheduling, shielding management, interrupt information statistics and interrupt aggregation of the user interrupt information are realized in sequence; and the interrupt reporting module and the interrupt processing module are combined to finish differentiated reporting and processing of different types of user interrupt information. According to the scheme, through unified management of the user interrupt information, the interrupt reporting efficiency is improved, and the problem of low efficiency caused by frequent interrupt processing of a CPU is reduced.

Description

Technical Field

[0001] This invention relates to the field of interrupt handling, and in particular to an interrupt information processing system, method, and chip. Background Technology

[0002] In modern electronic devices, industrial control systems, and servers, interrupt handling is a crucial technology for ensuring the collaborative operation of hardware modules with the processor (CPU) and host (HOST). Its performance directly affects the system's response speed, operational stability, and resource utilization. As the interrupt requests that need to be processed in systems become more diverse, and interrupt reporting requirements become more varied, existing interrupt handling technologies are gradually revealing many problems that urgently need to be addressed.

[0003] First, in existing solutions, different types of interrupts often use independent processing channels and management logic, lacking a unified information integration and scheduling mechanism. This leads to chaotic interrupt transmission paths, traffic diversion delays, and difficulty in achieving efficient collaborative reporting of various interrupts. At the same time, the lack of targeted transmission optimization design results in a long overall time from interrupt generation to processing, which cannot meet the needs of high real-time scenarios. Second, in high-frequency interrupt scenarios, existing technologies do not effectively aggregate interrupts. A large number of discrete interrupt requests continuously trigger CPU interrupt responses, causing the CPU to frequently switch task contexts, occupying too many computing resources, and thus affecting the normal operation of the main business, resulting in a significant decrease in the overall system processing efficiency.

[0004] Therefore, there is an urgent need for an interrupt handling solution that can solve the above-mentioned technical problems, so as to optimize the interrupt handling mechanism and improve the efficiency of interrupt reporting and CPU interrupt processing. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an interrupt information processing system, method and chip to solve the technical problem of low efficiency caused by frequent interrupt processing in existing CPUs.

[0006] To achieve the above and other related objectives, this application provides an interruption information processing system, characterized in that it includes: a user interruption source module, used to generate at least one user interruption information, the user interruption information types including level interruption information and message interruption information; an interruption policy management module, connected to the user interruption source module, used to receive at least one user interruption information transmitted by the user interruption source module, and perform interruption policy processing on the user interruption information based on built-in interruption policy configuration information to output user interruption information data, the user interruption information data including at least user interruption information aggregate data; an interruption reporting module, connected to the interruption policy management module, used to receive the user interruption information aggregate data transmitted by the interruption policy management module, and perform reporting processing on the user interruption information aggregate data; and an interrupt processing module, connected to the interruption reporting module, used to receive the user interruption information aggregate data reported by the interruption reporting module and complete the final processing.

[0007] In some embodiments of the first aspect of this application, the interrupt policy management module includes the following sub-modules: an interrupt distribution sub-module, an interrupt scheduling sub-module, an interrupt masking sub-module, an interrupt statistics sub-module, and an interrupt aggregation sub-module; wherein, the interrupt distribution sub-module is connected to the interrupt scheduling sub-module, the interrupt scheduling sub-module is connected to the interrupt masking sub-module, and the interrupt masking sub-module is also connected to the interrupt statistics sub-module and the interrupt aggregation sub-module respectively; each sub-module has its own built-in interrupt policy configuration information for each sub-module to perform corresponding interrupt policy processing.

[0008] In some embodiments of the first aspect of this application, the interrupt distribution submodule is used to determine at least one interrupt reporting behavior mode that matches the user interrupt information, and to report the user interrupt information accordingly based on the determined interrupt reporting behavior mode; wherein, the interrupt reporting behavior mode includes level interrupt reporting and message interrupt reporting.

[0009] In some embodiments of the first aspect of this application, the interrupt scheduling submodule receives the user interrupt information reported by the interrupt distribution submodule; determines at least one scheduling processing method matching the user interrupt information, and schedules the user interrupt information accordingly based on the determined scheduling processing method; wherein the scheduling processing method includes round-robin scheduling and high-priority interrupt scheduling.

[0010] In some embodiments of the first aspect of this application, the interrupt masking submodule receives the user interrupt information scheduled by the interrupt scheduling submodule and determines whether the user interrupt information needs to be masked: the user interrupt information that needs to be masked is transmitted to the interrupt statistics submodule for interrupt information statistics; the user interrupt information that does not need to be masked is transmitted to the interrupt statistics submodule for interrupt information statistics, and the user interrupt information is reported to the interrupt aggregation submodule accordingly.

[0011] In some embodiments of the first aspect of this application, the interruption aggregation submodule aggregates at least one of the user interruption information to output aggregated user interruption information data; wherein, the interruption policy configuration information of the interruption aggregation submodule includes a preset reporting number and a preset reporting time, and its aggregation processing method includes: when a first condition and / or a second condition are met, the interruption aggregation submodule reports all currently aggregated user interruption information; the first condition is configured as the cumulative reporting number reaches the preset reporting number threshold; the second condition is configured as the aggregation time reaches the preset reporting time threshold.

[0012] In some embodiments of the first aspect of this application, the interrupt reporting module includes: a level interrupt hierarchical reporting submodule and a message interrupt configuration management submodule; wherein, the level interrupt hierarchical reporting submodule is used to report the level interrupt information to the interrupt processing module according to the built-in level reporting strategy configuration information.

[0013] In some embodiments of the first aspect of this application, the message interruption configuration management submodule includes: a non-protocol interruption management submodule and a protocol interruption management submodule, and the message interruption information includes non-protocol message interruption information and protocol message interruption information; wherein, the non-protocol interruption management submodule includes a non-protocol message configuration submodule and a ring buffer update management submodule; and wherein, the non-protocol message configuration submodule includes: the destination address information of the non-protocol message interruption information in the ring buffer update management submodule and the message content of the non-protocol message interruption information; the protocol interruption management submodule is used to receive and report the protocol message interruption information to the interruption processing module.

[0014] To achieve the above and other related objectives, a second aspect of this application provides an interrupt information processing method applied to the aforementioned interrupt information processing system. The method includes: generating at least one user interrupt information through a user interrupt source module, wherein the user interrupt information type includes level interrupt information and message interrupt information; receiving the user interrupt information through an interrupt policy management module and performing interrupt policy processing on the user interrupt information based on built-in interrupt policy configuration information to obtain user interrupt information data, wherein the user interrupt information data includes at least aggregated user interrupt information data; receiving the aggregated user interrupt information data through an interrupt reporting module and performing reporting processing on the aggregated user interrupt information data; and receiving the aggregated user interrupt information data through an interrupt processing module and completing the final processing.

[0015] To achieve the above and other related objectives, a third aspect of this application provides an interrupt information processing chip, characterized in that it integrates the aforementioned interrupt information processing system.

[0016] As described above, the interrupt information processing system, method, and chip of this application have the following beneficial effects: This invention processes user interrupt information through interrupt policy configuration information built into the interrupt policy management module, sequentially realizing the distribution, priority scheduling, masking management, interrupt information statistics, and interrupt aggregation of user interrupt information. Furthermore, it combines the interrupt reporting module and the interrupt processing module to complete differentiated reporting and processing of different types of user interrupt information. This solution improves interrupt reporting efficiency and reduces the inefficiency caused by frequent CPU interrupt processing through unified management of user interrupt information. Attached Figure Description

[0017] Figure 1 The diagram shown is a structural schematic of an interrupt information processing system according to an embodiment of the present invention.

[0018] Figure 2 The diagram shown is a structural schematic of the interrupt policy management module in one embodiment of the present invention.

[0019] Figure 3 The diagram shown is a structural schematic of the interrupt reporting module in one embodiment of the present invention.

[0020] Figure 4 The diagram shown is a structural schematic of the message interruption configuration management submodule in one embodiment of the present invention.

[0021] Figure 5 The diagram shown is a structural schematic of a non-protocol interrupt management submodule in one embodiment of the present invention.

[0022] Figure 6aThe flowchart shown is a process for transmitting user interruption information in an interruption information processing system according to a specific embodiment of the present invention.

[0023] Figure 6b The diagram shown is a structural schematic of an interrupt information processing system according to a specific embodiment of the present invention.

[0024] Figure 7 The flowchart shown is a method for handling interruption information according to an embodiment of the present invention. Detailed Implementation

[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0026] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of this application. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of this application. The following detailed description should not be considered limiting, and the scope of the embodiments of this application is defined only by the claims of the published patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0027] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," and "holding" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0028] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data used can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising,” “including,” indicate the presence of the stated features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. It should be further understood that the terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will only occur if the combination of elements, functions, or operations is inherently mutually exclusive in some way.

[0029] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0030] <1> System on a Chip (SOC): SOC refers to integrating a complete electronic system onto a single chip. This system typically includes a central processing unit (CPU), graphics processing unit (GPU), memory, digital signal processor (DSP), various input / output interfaces, and wireless communication modules, etc.

[0031] <2> Memory-Mapped Input / Output (Memory-Mapped Input / Output) is a computer I / O architecture. Its core idea is to map the registers of hardware devices (such as network cards and graphics cards) into the processor's physical memory address space. This allows the central processing unit (CPU) to access and control these devices using ordinary memory read / write instructions without requiring dedicated I / O instructions, thus simplifying hardware design and software programming.

[0032] <3> Peripheral Component Interconnect Express (PCIe) is a high-performance, point-to-point, serial system bus standard used to connect high-speed peripheral devices on a computer motherboard.

[0033] <4> Serial Peripheral Interface (SPI): SPI is a high-speed, full-duplex, synchronous serial communication bus standard widely used in embedded systems to enable communication between microcontrollers and various peripheral devices over short distances (usually on the same circuit board).

[0034] <5> General-Purpose Input / Output (GPIO): GPIO is a general-purpose, programmable digital signal pin used in embedded systems, microcontrollers, and single-board computers. It does not have a specific function itself, but engineers can program it to "sense" or "control" the external world, forming the basis for implementing various interactive functions in embedded systems.

[0035] <6> Message Signaled Interrupts (MSI): MSI is a set of hardware and software protocols defined by the PCI / PCIe bus standard for generating and handling interrupts.

[0036] <7> Extended Message Signaled Interrupts (MSI-X): MSI-X is an extended version of MSI.

[0037] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the invention.

[0038] like Figure 1 The diagram shows a structural schematic of an interrupt information processing system 10 according to an embodiment of the present invention, including: a user interrupt source module 11, an interrupt policy management module 12, an interrupt reporting module 13, and an interrupt processing module 14.

[0039] User interrupt source module 11, as the core of interrupt request initiation, refers to all hardware functional units capable of generating interrupt signals, specifically covering two main categories: internal system integrated units and external system access devices. Internal system integrated units include, but are not limited to, the processing core, peripheral controllers, timers, counters, logic operation modules, and internal business subsystems built into the System-on-Chip (SoC), which are inherent components of the system architecture. External system access devices include, but are not limited to, external sensors, independent storage controllers, hardware acceleration cards, and communication modules connected to the system via interconnect buses such as PCIe, SPI, and GPIO, which are entities that generate interrupts extended from the system. This module dynamically generates corresponding user interrupt information with clear information type attributes and unique interrupt numbers by real-time sensing of various operational states and event triggering conditions (including but not limited to data transmission completion, computation task readiness, hardware state changes, error / anomaly alarms, and timer period arrivals). This ensures that subsequent processing modules can accurately identify the source and type of user interrupt information, laying the foundation for the orderly execution of interrupt strategies.

[0040] User interruption information is divided into two differentiated data types based on the transmission medium and signal form, with the following specific characteristics:

[0041] One type is level-based interrupt information, which uses dedicated physical signal lines as the transmission carrier. The validity of the level-based interrupt information is represented by a continuous and stable high / low level state (level triggering) or a signal edge transition (edge ​​triggering). Its data content is essentially an unstructured physical level signal, lacking data encapsulation and field carrying capabilities. Its unique interrupt number is determined through a preset binding relationship with the physical signal line and is pre-placed as an identifier in the hardware configuration or system mapping table. This hardware configuration or system mapping table also contains field information such as a type identifier corresponding to the unique interrupt number. The advantages of level-based interrupt information are its simple transmission path and low response latency, making it suitable for scenarios with high real-time interrupt requirements (such as emergency fault alarms and hardware reset requests).

[0042] Another type is message interrupt information, which uses the memory-mapped I / O (MMIO) mechanism to transmit structured messages to the address space specified by the system bus through memory write operations. Its data content is structured data frames, and it is further subdivided into protocol-based message interrupt information and non-protocol-based message interrupt information according to protocol adaptability. Protocol-based message interrupt information follows industry standard specifications such as PCIe (e.g., MSI / MSIX), and the data frame structure conforms to the standard protocol format. The data content includes a unique interrupt number, protocol header identifier, checksum, and other protocol adaptation fields. Non-protocol-based message interrupt information uses a custom frame structure. In addition to a unique interrupt number and type identifier, its data frame content can be flexibly expanded as needed to carry rich business-related sideband data (e.g., sensor sampling values, storage operation status codes), data buffer pointers, effective data length, and business scenario tags, etc., to adapt to the local CPU's needs for accurate parsing and processing of interrupt background information.

[0043] It should be understood that the user interrupt information generated by the user interrupt source module 11 is not limited to a single instance in terms of quantity and triggering form, but rather exhibits multi-dimensional and high-concurrency characteristics, specifically manifested in the following scenarios:

[0044] Single-source, multi-event scenario: A single user interrupt source (whether an internal system integration unit or an external access device) can correspond to multiple independent operation events or state changes. Each independent event can trigger a specific user interrupt message carrying a unique interrupt number, and the user interrupt message type can be adapted to level-based or message-based depending on the event characteristics. For example, a network controller, acting as a single user interrupt source, can generate multiple user interrupt messages with unique interrupt numbers when different events occur, such as data reception completion, data transmission completion, link anomaly alarm, and bandwidth overload. Among these, emergency alarm events can correspond to level-based interrupt messages for rapid response, while data transmission completion events can correspond to message-based interrupt messages carrying context such as transmission length and data address.

[0045] Multi-source concurrent scenarios in systems: In modern complex computing architectures, systems typically integrate or connect to a large number of user interrupt sources with different functions (such as on-chip timers, external sensors, memory controllers, hardware acceleration modules, etc.) via interconnect buses. These user interrupt sources operate independently and can generate multiple user interrupt messages concurrently or even in parallel based on their respective task progress or state conditions, thus forming a continuous and highly concurrent raw interrupt stream.

[0046] The user interrupt information generated by different interrupt sources or different events from the same interrupt source includes both level interrupt information and protocol-based and non-protocol-based message interrupt information. Together, they constitute a high-dimensional, concurrent set of interrupt requests that the system needs to process, providing a complex input scenario for the subsequent interrupt policy management module 12.

[0047] Interrupt policy management module 12 is the core policy execution unit of this interrupt information processing system 10. As a key intermediate node connecting the user interrupt source module 11 and the interrupt reporting module 13, its input end establishes a stable signal and data transmission link with the user interrupt source module 11, and can completely receive multi-channel concurrent user interrupt information (including level interrupt information, protocol-type message interrupt information and non-protocol message interrupt information) output by the user interrupt source module 11.

[0048] The core features and interrupt policy processing flow of interrupt policy management module 12 include:

[0049] Supports a flexible interrupt policy system: The operation logic of the interrupt policy management module 12 is not a fixed design, but is driven by software-definable built-in interrupt policy configuration information. This interrupt policy configuration information is associated with the unique interrupt number and type identifier of the user interrupt information. It can be loaded and updated through firmware parameter settings, hardware configuration units (such as registers, non-volatile memory), etc. Specifically, it includes core configuration items such as interrupt distribution rules, scheduling priority rules, masking trigger conditions, aggregation threshold parameters, and statistical dimension definitions. It can flexibly adapt the interrupt handling logic according to the business needs of different application scenarios.

[0050] An integrated interrupt handling mechanism: The interrupt policy management module 12 performs a coherent and streamlined process on the received user interrupt information. The processing flow, based on the module's built-in interrupt policy configuration information, sequentially completes operations such as interrupt distribution method determination, multi-interrupt scheduling and sorting, interrupt masking and filtering, interrupt data statistics, and interrupt aggregation and merging. This design ensures that all user interrupt information undergoes unified and standardized processing.

[0051] Core Data Output: After the above integrated processing, the interrupt policy management module 12 finally outputs user interrupt information data. This user interrupt information data includes aggregated user interrupt information data. This aggregated user interrupt information data merges multiple discrete interrupt events into a single interrupt notification based on a preset threshold, significantly reducing the response overhead of the subsequent interrupt reporting module 13 and the interrupt processing module 14. This is a key technical means to ensure the system maintains a high response rate and high resource utilization under high load. Simultaneously, the user interrupt information data also includes user interrupt information statistics.

[0052] Interrupt reporting module 13, as a key intermediate node connecting interrupt policy management module 12 and interrupt processing module 14, establishes a stable data interaction link with interrupt policy management module 12 at its input end, and can completely receive user interrupt information aggregation data output by interrupt policy management module 12 and perform corresponding interrupt reporting processing.

[0053] To facilitate understanding by those skilled in the art, the reporting process of the interrupt reporting module 13 is described below: First, the received user interrupt information aggregation data is type-identified to distinguish between level interrupt information aggregation data and message interrupt information aggregation data; for level interrupt information aggregation data, interrupt requests are transmitted step-by-step through physical signal lines according to preset reporting rules to ensure the continuous and effective representation of the interrupt status; for message interrupt information aggregation data, the corresponding transmission channel (e.g., system bus, memory-mapped address space) is selected according to the inherent attributes of the data to accurately transmit the message interrupt information aggregation data to the specified interrupt processing target address; finally, the reporting status is fed back and recorded to ensure the integrity and traceability of the aggregated data transmission.

[0054] Through the aforementioned differentiated reporting process, the interrupt reporting module 13 not only meets the real-time requirements of level interrupt information but also ensures the accurate transmission of message interrupt information, thereby achieving efficient transmission of user interrupt information to the subsequent interrupt processing module 14.

[0055] The interrupt handling module 14, comprising a CPU (local processing unit) and a HOST (host processing unit), is the final processing unit of the interrupt information processing system 10. Its input establishes a stable data interaction link with the interrupt reporting module 13, enabling it to fully receive aggregated user interrupt information transmitted by the interrupt reporting module 13. Based on the type and target of the aggregated data, it performs differentiated final processing, achieving a closed-loop transformation from user interrupt information to service handling. For aggregated user interrupt information reported to the CPU (including non-protocol message interrupt information aggregated data and level interrupt information aggregated data), the CPU performs the final processing; for aggregated user interrupt information reported to the HOST (including protocol message interrupt information aggregated data), data transmission and interaction are completed through the HOST interface.

[0056] In one embodiment of this application, as Figure 2 As shown, the interrupt policy management module 12 includes an interrupt distribution submodule 121, an interrupt scheduling submodule 122, an interrupt masking submodule 123, an interrupt statistics submodule 124, and an interrupt aggregation submodule 125. The submodules are connected in an orderly manner through a preset data interaction interface.

[0057] The specific connection relationships between the submodules are as follows: The input terminal of the interrupt distribution submodule 121 establishes a data transmission link with the user interrupt source module 11 to receive the original user interrupt information (including level interrupt information and protocol / non-protocol message interrupt information) output by the user interrupt source module 11; its output terminal is unidirectionally connected to the input terminal of the interrupt scheduling submodule 122 to realize the directional transmission of the user interrupt information after preliminary distribution processing to the scheduling stage, ensuring the orderliness of data transmission; the output terminal of the interrupt scheduling submodule 122 is connected to the input terminal of the interrupt masking submodule 123 to transmit the user interrupt information after scheduling processing to the masking judgment stage as needed, and after masking judgment, a branch data stream is formed, as follows:

[0058] 1. The output of the interrupt masking submodule 123 is connected to the input of the interrupt statistics submodule 124. All user interrupt information (whether masked or not) is synchronously transmitted to the interrupt statistics submodule 124 for full recording of interrupt events. After receiving the data, the interrupt statistics submodule 124 classifies, records, and stores the key information of various user interrupt information events (such as interrupt number, occurrence timestamp, processing stage identifier, status result, etc.) locally, and temporarily stores the statistical data in the internal storage unit of the interrupt statistics submodule 124. It is not connected to the main interrupt data stream, but a dedicated interface is reserved for access triggered by system software reading or firmware calls, which can support the needs of system fault diagnosis, interrupt event backtracking, performance analysis, etc.

[0059] 2. The output of the interrupt masking submodule 123 is connected to the input of the interrupt aggregation submodule 125. User interrupt information that is determined by the interrupt masking submodule 123 to not need to be masked will continue to be sent to the input of the interrupt aggregation submodule 125 and enter the subsequent aggregation processing flow; user interrupt information that is determined by the interrupt masking submodule 123 to need to be masked will not enter the subsequent processing flow.

[0060] Finally, the output of the interrupt aggregation submodule 125 (i.e., user interrupt information aggregation data) is transmitted to the interrupt reporting module 13 as the main data output of the interrupt policy management module 12 to complete the subsequent reporting process.

[0061] It should be understood that, to achieve flexible adaptation and independent management of the functions of each submodule, each submodule has its own built-in interrupt policy configuration information. This interrupt policy configuration information maintains logical consistency with the system's global interrupt policy framework and is configured differently for the core functions of each submodule: for example, the interrupt distribution policy configuration information of interrupt distribution submodule 121 focuses on the definition of distribution rules; the interrupt scheduling policy configuration information of interrupt scheduling submodule 122 focuses on the setting of scheduling priorities; the interrupt masking policy configuration information of interrupt masking submodule 123 focuses on the determination of masking triggers; and the interrupt statistics policy configuration information and interrupt aggregation policy configuration information of interrupt statistics submodule 124 and interrupt aggregation submodule 125 correspond to the definition of statistical dimensions and aggregation rules, respectively. Each submodule can independently complete the corresponding interrupt policy processing operations based on its built-in interrupt policy configuration information. Simultaneously, through the collaborative linkage between submodules, the processing flow of the entire interrupt policy management module 12 is ensured to be coherent and unified. This not only guarantees the efficiency of interrupt processing but also achieves the traceability of interrupt events through the local storage design of interrupt statistics submodule 124, providing reliable support for the system to adapt to interrupt processing needs in different scenarios.

[0062] In one embodiment of this application, the interrupt distribution submodule 121 matches the corresponding interrupt reporting behavior mode for each user interrupt information according to a preset distribution rule, and completes the distribution and reporting of user interrupt information according to the matching result.

[0063] The specific implementation is as follows: First, after receiving the original user interrupt information transmitted by the user interrupt source module 11, the interrupt distribution submodule 121 extracts the feature information (including interrupt number, interrupt type identifier, event trigger characteristics, etc.) as the basis for distribution determination. Second, the submodule calls the built-in interrupt distribution strategy configuration information (covering the mapping table between interrupt number and reporting behavior mode, the reporting rules corresponding to interrupt type identifier, etc.) and matches the extracted feature information with the interrupt distribution strategy configuration information: for example, if the interrupt type identifier is a level interrupt, then the level interrupt reporting behavior mode is matched; if the interrupt type identifier is a message interrupt (including protocol type / non-protocol type), then the message interrupt reporting behavior mode is matched; for user interrupt information carrying a specific interrupt number, the preset reporting behavior mode can also be directly associated through the mapping table to achieve accurate matching. Finally, the interrupt distribution submodule 121 distributes the user interrupt information to the corresponding processing channel according to the matching result: for example, user interrupt information reported by matching level interrupt is sent to the subsequent link of the level interrupt processing logic; user interrupt information reported by matching message interrupt is sent to the subsequent link of the message interrupt processing logic, thereby completing the determination of the interrupt reporting behavior mode and the corresponding distribution operation.

[0064] Through the above distribution mechanism, the interrupt distribution submodule 121 can classify and manage interrupt information of different types of users, ensuring that each user interrupt information can flow according to the preset reporting behavior, laying a unified distribution foundation for subsequent interrupt scheduling, masking and other processing links, and improving the processing efficiency and adaptability of the entire interrupt policy management module 12.

[0065] In one embodiment of this application, the interrupt scheduling submodule 122 receives the user interrupt information reported by the interrupt distribution submodule 121, and matches an appropriate scheduling processing method for multiple concurrent user interrupt information based on preset scheduling strategy configuration information. Through orderly scheduling, interrupt conflicts are avoided, and real-time response to high-priority interrupts and balanced utilization of system resources are ensured.

[0066] The specific implementation is as follows: First, after receiving the user interrupt information output by the interrupt distribution submodule 121, the interrupt scheduling submodule 122 extracts the core scheduling basis from the user interrupt information, including key parameters such as the preset priority level corresponding to the interrupt number, interrupt type (level / message), and interrupt trigger timestamp. Then, the interrupt scheduling submodule 122 calls the built-in interrupt scheduling strategy configuration information (covering parameters such as scheduling mode selection rules, priority level mapping table, round-robin scheduling cycle, and preemption enable switch), matches the extracted core parameters with the interrupt scheduling strategy configuration information, and determines the scheduling processing method corresponding to the current user interrupt information. Finally, according to the determined scheduling processing method, the user interrupt information is arranged into the corresponding scheduling queue according to the rules, and the process is completed by directing the interrupt to the interrupt masking submodule 123.

[0067] In one embodiment of this application, the scheduling method is round-robin scheduling. Round-robin scheduling is suitable for user interrupt information with the same priority level or no explicit urgency requirement. It mainly ensures that multiple interrupts fairly occupy system processing resources through equal time slice allocation and cyclic scheduling, avoiding a single interrupt from occupying the link for an extended period.

[0068] To facilitate understanding by those skilled in the art, the specific implementation of round-robin scheduling is described below: The interrupt scheduling submodule 122 has a built-in round-robin scheduling queue and a time slice counter. The interrupt scheduling strategy configuration information presets a fixed time slice length (e.g., 1ms) and a queue rotation order. When multiple user interrupt information matches the round-robin scheduling method, the interrupt scheduling submodule 122 arranges the user interrupt information into the round-robin queue in the order of interrupt reception (or the preset queue sorting rules). During scheduling execution, the interrupt scheduling submodule 122 allocates a fixed processing time to each interrupt in the round-robin queue according to the time slice. After the time slice of the current interrupt is exhausted, it automatically switches to the next interrupt for processing until all interrupts in the queue have completed the scheduling flow.

[0069] In one embodiment of this application, the scheduling processing method is high-priority interrupt scheduling. High-priority interrupt scheduling is applicable to user interrupt information marked as high priority (such as emergency alarm level interrupts, critical business message interrupts) or requiring immediate response. It mainly uses priority determination and a direct flow mechanism to allow high-priority user interrupt information to skip the round-robin queue and directly enter the subsequent processing flow, ensuring real-time requirements.

[0070] To facilitate understanding by those skilled in the art, the specific implementation of high-priority interrupt scheduling is described below: The interrupt scheduling submodule 122 has built-in high-priority interrupt determination rules (e.g., a preset high-priority threshold in the interrupt scheduling strategy configuration information; an interrupt priority ≥ this threshold is determined to be a high-priority interrupt, or an interrupt number corresponding to a high priority is specified); when user interrupt information is determined to be high-priority, the interrupt scheduling submodule 122 immediately suspends the current round-robin scheduling process (if any) and directly transmits the high-priority user interrupt information to the interrupt masking submodule 123 to enter the subsequent processing stage, without waiting for time slice allocation or queue rotation; if there is a high-priority interrupt currently being processed, a newly triggered higher-priority interrupt (supporting multi-level priority determination) can directly preempt the processing link, suspend the processing of the current high-priority interrupt, and prioritize responding to interrupts of higher priority; after the high-priority interrupt completes its subsequent processing, the interrupt scheduling submodule 122 resumes the previously suspended round-robin scheduling process (if any), ensuring that the normal processing of ordinary interrupts is not blocked for a long time.

[0071] In one embodiment of this application, the interrupt shielding submodule 123 performs precise shielding determination and differentiated traffic splitting for each user interrupt information based on the built-in interrupt shielding strategy configuration information. By intercepting the user interrupt information that needs to be shielded, it reduces the invalid data flow in subsequent links and ensures the efficiency of the interrupt handling link.

[0072] The determination logic is as follows: After receiving user interrupt information, the interrupt masking submodule 123 extracts the unique interrupt number and matches it with the masking rules defined in the built-in interrupt masking strategy configuration information. The masking rules define the set of user interrupt sources that the system needs to mask. If the interrupt number matches the masking rules, it is determined that it needs to be masked; otherwise, it is determined that it does not need to be masked.

[0073] In one embodiment of this application, after receiving user interrupt information data, the interrupt statistics submodule 124 first parses the input user interrupt information in real time and extracts key information dimensions, including a unique interrupt number, a precise timestamp of the interrupt occurrence (based on system global clock synchronization, with an accuracy of up to microseconds), a processing stage identifier, an interrupt status result, and an interrupt type identifier, etc. Subsequently, according to the statistical rules defined by the built-in interrupt statistics strategy configuration information, the received user interrupt information data is integrated into a structured statistical record, and the record is stored in an internal storage unit. The internal storage unit adopts a circular buffer or partitioned storage design.

[0074] To achieve efficient interactive access, the interrupt statistics submodule 124 reserves dedicated access interfaces (such as memory mapping interfaces, register read interfaces, or bus access interfaces). System software can actively read statistical data through these interfaces, and firmware can also call the interfaces as needed to obtain statistical information of specified dimensions, such as querying historical trigger records by interrupt number or performing indicator analysis by time period. In addition, the interrupt statistics submodule 124 also supports configuring statistical rules, such as setting data storage duration, filtering the range of interrupt numbers to be focused on, and defining the field dimensions of statistical records, further improving the flexibility and targeting of statistics.

[0075] In one embodiment of this application, the interrupt aggregation submodule 125 aggregates multiple discrete user interrupt signals according to the built-in interrupt aggregation strategy configuration information (including preset reporting number threshold and preset reporting time). The core is to reduce the frequency of system interrupt reporting by batch reporting, thereby improving the overall efficiency of the interrupt processing link.

[0076] Specifically, after receiving user interrupt information, the interrupt aggregation submodule 125 first caches it in the built-in temporary storage area and starts two parallel monitoring mechanisms: one is to start the interrupt accumulation counter to count the number of interrupt information currently cached in real time, and the other is to start the aggregation timer to accumulate the duration of the current aggregation cycle.

[0077] When the interrupt accumulation counter reaches a preset reporting frequency threshold (first condition) or the aggregation timer reaches a preset reporting time threshold (second condition), the interrupt aggregation submodule 125 immediately initiates the reporting process: all user interrupt information currently cached in the temporary storage area is treated as a complete data batch and directly transmitted to the interrupt reporting module 13. The aggregated interrupt information data is the batch set of all user interrupt information within that batch. After the aggregation reporting is completed, the interrupt aggregation submodule 125 automatically resets the interrupt accumulation counter (clears it to zero) and the aggregation timer (resets it to zero), clears the temporary storage area, and enters the preparation state for the next aggregation cycle.

[0078] It should be noted that if the first condition and the second condition happen to meet the preset threshold simultaneously within the aggregation period, the interruption aggregation submodule 125 will trigger the aggregation reporting operation by default according to the first condition (accumulated number of times reaches the target), or trigger the aggregation reporting according to the preset reporting rules in the built-in interruption aggregation strategy configuration information (e.g., configured to prioritize triggering based on time conditions), thereby ensuring the orderly execution of the aggregation reporting operation; in addition, the interruption information aggregation data can be a batch set of interruption information of the same user type (such as level interruption information or message interruption information of the same type), or a batch set of user interruption information belonging to the same business user / device user, according to actual application needs, to ensure that the aggregation data has classification attributes and business relevance.

[0079] Through this batch reporting mechanism triggered by both the number of times and the time, the interrupt aggregation submodule 125 can avoid frequent reporting caused by frequent interruptions and prevent information transmission delays caused by sparse interruptions, thus achieving high efficiency and balance in the aggregation and reporting of interrupt information.

[0080] In one embodiment of the application, as Figure 3 As shown, the interrupt reporting module 13 includes: a level interrupt hierarchical reporting submodule 131 and a message interrupt configuration management submodule 132.

[0081] Among them, the level interrupt hierarchical reporting submodule 131 realizes hierarchical reporting of level interrupt information based on the built-in level reporting strategy configuration information, ensuring that level interrupt information of different priorities can be accurately matched with the corresponding processing resources of the interrupt processing module 14 (CPU), thereby improving the timeliness and pertinence of interrupt response.

[0082] The level reporting strategy configuration information includes a composite configuration structure of a hardware mapping layer and a policy attribute layer. The hardware mapping layer configures the mapping between interrupt numbers and CPU pins, defining the CPU pin associations for different interrupt numbers (supporting both different interrupt numbers associated with different pins and different interrupt numbers associated with the same pin). The policy attribute layer, based on the hardware mapping layer, adds priority parameters that are bound one-to-one with the interrupt numbers in the mapping table, including preemption priority level and response priority level. For example, in scenarios where different interrupt numbers are associated with different pins, the level reporting strategy configuration information configures a unique CPU pin identifier for each interrupt number (e.g., interrupt number 0 corresponds to pin 1, interrupt number 1 corresponds to pin 2), along with corresponding independent priority parameters. In scenarios where different interrupt numbers are associated with the same pin, the level reporting strategy configuration information configures the same CPU pin identifier for multiple interrupt numbers (e.g., interrupt numbers 2 and 3 both correspond to pin 3), and configures preemption priority level 0 and response priority level 0 for interrupt number 2, and preemption priority level 1 and response priority level 0 for interrupt number 3. Through differentiated priority parameter definitions, the response priority order of different interrupt numbers under the same pin is clearly defined.

[0083] During execution, when the level interrupt hierarchical reporting submodule 131 reads the level reporting strategy configuration information, it can simultaneously obtain the pin mapping relationship and priority parameters: if the pin is exclusively occupied by the current interrupt number, the level interrupt signal is directly transmitted to the signal channel corresponding to the pin, triggering a change in the pin level state; if the pin is shared by multiple interrupt numbers, the level interrupt hierarchical reporting submodule 131 transmits the pin identifier and priority parameters to the interrupt controller, and the interrupt controller will arbitrate and determine the order of reporting based on the obtained priority parameters.

[0084] This design maintains the integrity of interrupt reporting configuration information, achieves unified management of hardware mapping and policy attributes, simplifies the configuration hierarchy, and ensures that pin association and priority control rules can be updated synchronously with the interrupt reporting policy, thereby improving the flexibility and consistency of configuration.

[0085] In one embodiment of this application, as Figure 4 and Figure 5 As shown, the message interruption configuration management submodule 132 includes: a non-protocol interruption management submodule 1321 and a protocol interruption management submodule 1322; wherein, the non-protocol interruption management submodule 1321 includes a non-protocol message configuration submodule 13211 and a ring buffer update management submodule 13212.

[0086] The non-protocol interrupt management submodule 1321 is responsible for efficiently reporting non-protocol message interrupt information to the local CPU. Its reporting mechanism is based on the coordination of ring buffer temporary storage and level interrupt notification. Specifically, when a non-protocol message interrupt arrives, the non-protocol message configuration submodule 13211 has pre-configured its destination address (i.e., its write position in the ring buffer) and message content format. The message interrupt information is directly written to the position pointed to by the current producer pointer of the ring buffer managed by the ring buffer update management submodule 13212, and then the producer pointer is automatically incremented. This process is completed automatically by hardware without CPU intervention. Simultaneously, the ring buffer update management submodule 13212 continuously monitors the ring buffer's fill status. When the amount of newly written but not yet read by the CPU reaches a preset update threshold, the ring buffer update management submodule 13212 does not directly process the message interrupt information itself, but actively generates a level interrupt signal. This level interrupt signal is sent to the level interrupt hierarchical reporting submodule 131 and reported to the CPU according to the priority rules configured in the level interrupt hierarchical reporting submodule 131. After the CPU responds to this interrupt, its interrupt service routine (ISR) queries the circular buffer update management submodule 13212 to obtain the range of data to be processed, and actively polls the circular buffer to read data in batches starting from the consumer pointer position. After reading is completed, the CPU is responsible for updating the consumer pointer to release the processed circular buffer space. The producer pointer is maintained by the circular buffer update management submodule 13212, indicating the address where the next non-protocol interrupt information data should be written; the consumer pointer is maintained by the CPU after reading the data, indicating the address of the next non-protocol interrupt information data to be read.

[0087] In one embodiment of this application, the protocol interruption management submodule 1322 is responsible for reporting protocol interruption information to the host. This submodule 1322 has built-in protocol reporting policy configuration information, which presets the address of the target host and the required industry standard protocol format. When protocol interruption information arrives, the submodule 1322 does not need to perform complex format conversion or caching; instead, it directly encapsulates the protocol interruption information content and routing information into a standard-compliant (e.g., PCIe MSI-X) message format according to its built-in configuration. Subsequently, it directly sends the message to the preset host address via the system bus (e.g., PCIe bus).

[0088] To better describe the specific implementation scheme of the interrupt information processing system 10, we will now combine... Figure 6a and Figure 6b The specific implementation examples are described below:

[0089] When the system generates a user interrupt message, it first enters the interrupt type distribution stage: the system automatically identifies the interrupt type attribute. If it is a level interrupt message, it is routed to the level interrupt scheduling module; if it is a message interrupt message, it is routed to the message interrupt scheduling module. Both types of interrupts use a round-robin scheduling mechanism to complete the initial queuing, avoiding concurrent congestion of interrupts of the same type.

[0090] For level interrupt information, after scheduling, the system enters the mask state determination: If the level interrupt information is configured to be masked, the system will perform an interrupt record drop operation, but will also perform statistics on the masked level interrupt information (including interrupt number, trigger time, etc.); if it is not masked, the level interrupt information statistics process is triggered synchronously (recording the trigger frequency, duration, and other data of this type of interrupt), and then the interrupt aggregation stage is entered; the interrupt aggregation stage integrates multiple discrete level interrupt information into a batch of interrupt data according to preset rules; after aggregation, the system reports the aggregated level interrupt data to the CPU according to the reporting priority determination rules (based on the priority mapping relationship between interrupt number and CPU pin), and the CPU performs subsequent processing.

[0091] For message interruption information, after scheduling, a mask state determination is also performed: if configured to mask state, interrupt record dropping operation is executed, but masked message interruption information is statistically analyzed; if not masked, the message interruption information statistical process is triggered, followed by the interrupt aggregation stage to complete batch message integration. The aggregated message interruption information needs further differentiation by interrupt type: if it is a non-protocol message interruption, the system writes it to the ring buffer and triggers a CPU_MSG interrupt notification. After the CPU responds to the notification, it reads batch messages by polling the ring buffer; if it is a protocol message interruption, it is encapsulated into a HOST interrupt message according to a preset protocol format and directly transmitted to the HOST via the system high-speed bus, where the HOST completes subsequent processing.

[0092] Through the above end-to-end process, the system achieves differentiated hierarchical reporting of level interrupt information to the local CPU and message interrupt information to the CPU / HOST. It filters invalid interrupts through a masking mechanism, reduces the reporting frequency through an aggregation mechanism, and ensures timely response to high-urgency interrupts based on priority rules, ultimately improving the overall efficiency and resource utilization of interrupt handling.

[0093] It should be understood that Figure 6b The specific implementation methods of each module have been described in detail in the above system embodiments, and will not be repeated here for the sake of brevity.

[0094] Figure 7This is a schematic diagram of an interrupt information processing method provided in an embodiment of this application. The method is applied to the interrupt information processing system 10 described above, and the method includes:

[0095] Step S71: Generate at least one user interrupt information through the user interrupt source module 11, wherein the user interrupt information type includes level interrupt information and message interrupt information;

[0096] Step S72: Receive the user interrupt information through the interrupt policy management module 12, and perform interrupt policy processing on the user interrupt information based on the built-in interrupt policy configuration information to obtain user interrupt information data. The user interrupt information data includes at least user interrupt information aggregated data.

[0097] Step S73: Receive the user interrupt information aggregation data through the interrupt reporting module 13, and perform reporting processing on the user interrupt information aggregation data;

[0098] Step S74: Receive the aggregated user interrupt information data through the interrupt handling module 14 and complete the final processing.

[0099] It should be understood that the specific process of performing the above-mentioned steps has been described in detail in the above system embodiments, and will not be repeated here for the sake of brevity.

[0100] Another embodiment of the present invention provides an interrupt information processing chip, including the interrupt information processing system 10 mentioned above. The specific implementation of the interrupt information processing system 10 in this embodiment has been described in the above embodiments and will not be repeated here.

[0101] In summary, the interrupt information processing system, method, and chip provided by this invention process user interrupt information through interrupt policy configuration information built into the interrupt policy management module. This sequentially achieves user interrupt information distribution, priority scheduling, masking management, interrupt information statistics, and interrupt aggregation. Furthermore, it combines an interrupt reporting module and an interrupt processing module to complete differentiated reporting and processing of different types of user interrupt information. This solution improves interrupt reporting efficiency and reduces the inefficiency caused by frequent CPU interrupt processing through unified management of user interrupt information.

[0102] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0103] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. An interruption information processing system, characterized in that, include: The user interrupt source module is used to generate at least one user interrupt information, the user interrupt information types including level interrupt information and message interrupt information; An interrupt policy management module is connected to the user interrupt source module and is used to receive at least one user interrupt information transmitted by the user interrupt source module, and to perform interrupt policy processing on the user interrupt information based on the built-in interrupt policy configuration information to output user interrupt information data. The user interrupt information data includes at least user interrupt information aggregate data. An interrupt reporting module, connected to the interrupt policy management module, is used to receive the user interrupt information aggregation data transmitted by the interrupt policy management module and to report the user interrupt information aggregation data. An interrupt handling module, connected to the interrupt reporting module, is used to receive the aggregated user interrupt information data reported by the interrupt reporting module and complete the final processing.

2. The interruption information processing system according to claim 1, characterized in that, The interruption policy management module includes the following sub-modules: Interrupt distribution submodule, interrupt scheduling submodule, interrupt masking submodule, interrupt statistics submodule, and interrupt aggregation submodule; The interrupt distribution submodule is connected to the interrupt scheduling submodule, the interrupt scheduling submodule is connected to the interrupt masking submodule, and the interrupt masking submodule is also connected to the interrupt statistics submodule and the interrupt aggregation submodule. Each submodule has its own built-in interrupt policy configuration information for each submodule to perform corresponding interrupt policy processing.

3. The interruption information processing system according to claim 2, characterized in that, The interrupt distribution submodule is used to determine at least one interrupt reporting behavior mode that matches the user interrupt information, and to report the user interrupt information accordingly based on the determined interrupt reporting behavior mode; wherein, the interrupt reporting behavior mode includes level interrupt reporting and message interrupt reporting.

4. The interruption information processing system according to claim 3, characterized in that, The interrupt scheduling submodule receives the user interrupt information reported by the interrupt distribution submodule; determines at least one scheduling processing method matching the user interrupt information, and schedules the user interrupt information accordingly based on the determined scheduling processing method; wherein, the scheduling processing method includes round-robin scheduling and high-priority interrupt scheduling.

5. The interruption information processing system according to claim 4, characterized in that, The interrupt masking submodule receives the user interrupt information scheduled by the interrupt scheduling submodule and determines whether the user interrupt information needs to be masked: The user interruption information that needs to be masked is transmitted to the interruption statistics submodule for interruption information statistics. The user interrupt information that does not require masking is transmitted to the interrupt statistics submodule for interrupt information statistics, and the user interrupt information is reported to the interrupt aggregation submodule accordingly.

6. The interruption information processing system according to claim 2, characterized in that, The interruption aggregation submodule aggregates at least one of the user interruption information to output the user interruption information aggregated data. The interrupt policy configuration information of the interrupt aggregation submodule includes a preset reporting number and a preset reporting time, and its aggregation processing method includes: When the first condition and / or the second condition are met, the interruption aggregation submodule will report all user interruption information currently aggregated; the first condition is configured to the cumulative number of reports reaching the preset reporting number threshold; the second condition is configured to the aggregation time reaching the preset reporting time threshold.

7. The interruption information processing system according to claim 1, characterized in that, The interrupt reporting module includes: a level interrupt hierarchical reporting submodule and a message interrupt configuration management submodule; The level interrupt hierarchical reporting submodule is used to report the level interrupt information to the interrupt processing module according to the built-in level reporting strategy configuration information.

8. The interruption information processing system according to claim 7, characterized in that, The message interruption configuration management submodule includes: a non-protocol interruption management submodule and a protocol interruption management submodule; the message interruption information includes non-protocol message interruption information and protocol message interruption information. The non-protocol interruption management submodule includes a non-protocol message configuration submodule and a ring buffer update management submodule. Furthermore, the non-protocol message configuration submodule includes: the destination address information of the non-protocol message interruption information in the ring buffer update management submodule and the message content of the non-protocol message interruption information; The protocol interruption management submodule is used to receive and report the protocol interruption information to the interruption processing module.

9. A method for processing interruption information, characterized in that, The method, applied to the interruption information processing system as described in any one of claims 1 to 8, comprises: At least one user interrupt information is generated by the user interrupt source module, and the user interrupt information types include level interrupt information and message interrupt information. The interrupt policy management module receives the user interrupt information and processes it according to the built-in interrupt policy configuration information to obtain user interrupt information data. The user interrupt information data includes at least aggregated user interrupt information data. The interruption reporting module receives the aggregated user interruption information data and processes the aggregated user interruption information data for reporting. The interrupt handling module receives the aggregated user interrupt information data and completes the final processing.

10. An interrupt information processing chip, characterized in that, It integrates the interrupt information processing system as described in any one of claims 1 to 8.

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