Circuit fragile node identification method based on static feature fusion
By constructing a basic circuit information database and integrating multi-dimensional static features, combined with machine learning models, the problem of low efficiency in identifying circuit vulnerable nodes in traditional methods has been solved, achieving efficient and accurate identification of circuit vulnerable nodes, which is applicable to high-security fields such as aerospace, automotive electronics, and medical equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CIVIL AVIATION UNIV OF CHINA
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional methods for identifying vulnerable nodes in circuits rely on dynamic timing simulation, which is inefficient and incomplete, and it is difficult to take into account both the static structural features and comprehensive performance features of the circuit. Existing feature extraction tools lack a unified process library parsing and feature calculation framework, which limits the accuracy of identification.
By extracting circuit gate-level netlists and process library files, a basic circuit information database is constructed. Multi-dimensional static features of trigger topology, bus association, feedback loop and process attributes are integrated. The feature weights are calculated using min-max normalization and entropy method to construct a weighted fusion feature matrix. Then, random forest, K-linear and Xgboost models are used for integrated training to identify vulnerable nodes.
It enables rapid and accurate identification of vulnerable circuit nodes without dynamic simulation, improving the accuracy and generalization ability of identification. It is applicable to large-scale complex circuits, adapts to digital circuit designs with different architectures, and reduces the iteration cycle of fault-tolerant design.
Smart Images
Figure CN122020102A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design and fault diagnosis technology, specifically involving a circuit vulnerability node identification method based on static feature fusion, which is applicable to vulnerability assessment and fault injection optimization of gate-level circuits in the EDA (Electronic Design Automation) process. Background Technology
[0002] As integrated circuit process nodes continue to shrink, circuit complexity increases exponentially. Traditional vulnerable node identification methods, which rely on gate-level simulation and fault injection, face problems of low efficiency and incomplete coverage. Existing technologies largely rely on dynamic timing simulation, which consumes significant computational resources and time, and struggles to comprehensively extract both static structural features and overall performance characteristics. Furthermore, existing feature extraction tools lack a unified framework for process library parsing, netlist processing, and feature computation, resulting in limitations such as single feature dimensions, incomplete bus signal decomposition, and inaccurate feedback loop identification. These shortcomings limit the accuracy of subsequent machine learning model training.
[0003] Furthermore, in traditional methods, the static structural features (such as fan-in / fan-out, PI / PO connection relationships), bus attributes, and feedback loops of flip-flops (FFs), which are core components of sequential logic, are not systematically integrated, making it difficult to form a multi-dimensional feature dataset to support accurate identification of vulnerable nodes. Therefore, there is an urgent need for an efficient and comprehensive static feature extraction method to construct a unified parsing-modeling-feature extraction framework, combined with machine learning, to achieve fast and accurate identification of vulnerable nodes in circuits. Summary of the Invention
[0004] To address the aforementioned problems, the present invention aims to provide a method for identifying vulnerable nodes in circuits based on static feature fusion.
[0005] To achieve the above objectives, the circuit vulnerability node identification method based on static feature fusion provided by the present invention includes the following steps performed in sequence:
[0006] Step 0): Extract module structure, signal topology and device attributes, parse the circuit gate-level netlist and technology library file, then parse the module structure, signal topology, signal splitting and device attributes, complete the sub-module flattening, bus signal expansion and constant signal extraction, construct the circuit topology diagram, and thus construct the circuit basic information database;
[0007] Step 1): Using the circuit basic information database built in Step 0), extract multi-dimensional static features including flip-flop topology, bus association, feedback loop and process attributes to form a standardized feature set;
[0008] Step 2): The standardized feature set obtained in Step 1) is processed using the min-max standardization method to eliminate the influence of dimensions. Then, the feature weights are calculated using the entropy method, and a weighted fusion feature matrix is constructed.
[0009] Step 3): Using the weighted fusion feature matrix constructed in Step 2), train three models: Random Forest, K-linear, and Xgboost, respectively. Then, integrate the three trained models through a weighted voting strategy to construct a vulnerable node identification model.
[0010] Step 4): Input the weighted fusion feature matrix obtained after processing the circuit to be identified in steps 0) to 2) into the vulnerable node identification model obtained in step 3), output the vulnerability score of the node, and finally determine the list of vulnerable nodes based on the statistical threshold.
[0011] In step 0), the extraction of module structure, signal topology, and device attributes involves parsing the circuit gate-level netlist and technology library file, then parsing the module structure, signal topology, signal decomposition, and device attributes to complete sub-module flattening, bus signal expansion, and constant signal extraction. The method for constructing the circuit topology diagram is as follows:
[0012] (1) Using regular expression matching and recursive traversal algorithms, the attribute information of modules, instances, ports, signals and devices is extracted, the circuit gate-level netlist and process library files are parsed, and a multi-dimensional association table and dictionary are established;
[0013] (2) By recursively tracing the instances within the submodules, the underlying instances of non-utility submodules are promoted to the top level to flatten the submodules, while preserving the original signal connection relationships. The formula is as follows:
[0014] ;
[0015] In the formula, For a flattened collection of instances, Let m be the set of underlying instances of the k-th submodule, and m be the number of submodules.
[0016] (3) Based on the signal naming format, the signals, including bus signals and unit width signals, are split into transmission signals and constant signals. Then, the constant signals are extracted, associated with the corresponding ports and connection lines, and saved in the dictionary.
[0017] (4) The bus format is identified based on regular expressions, and the signals are split bit by bit to generate independent unit-width signals. The bus signals are then expanded, and the expansion logic formula is as follows:
[0018] ;
[0019] In the formula, This is the expanded set of bus signals, where M and N are the bus bit width boundaries;
[0020] (5) Using instance ports and signals as nodes and driving relationships as directed edges, construct a circuit topology graph G=(V,E) to represent the topological relationships, where V is the set of nodes and E is the set of directed edges.
[0021] In step 1), the multi-dimensional static features include:
[0022] (1) Flip-flop fan-in number :
[0023] ;
[0024] In the formula, For target trigger, For other triggers, A collection of combinational logic devices. Indicates the signal driving relationship. Indicates the number of elements in the set;
[0025] (2) Flip-flop fanout :
[0026] ;
[0027] In the formula, For other triggers;
[0028] (3) Total number of FFs affecting the input :
[0029] ;
[0030] In the formula, For trigger To target trigger The effective signal path;
[0031] (4) The total number of FFs affecting the output :
[0032] ;
[0033] In the formula, To trigger the target To trigger The effective signal path;
[0034] (5) Path characteristics to the PI / PO port:
[0035] ;
[0036] In the formula, For the target node, , These are the sets of reachable PI and PO ports, respectively. This represents the number of path instances; this set of formulas calculates the shortest path level, average path level, and longest path level from the target node to all PI / PO ports, respectively. The shorter the path level, the better.
[0037] (6) Bus ownership identifier :
[0038] ;
[0039] In the formula, This is the expanded set of bus signals obtained in step 0); nodes marked as 1 belong to the bus signals;
[0040] (7) Bus location :
[0041] ;
[0042] (8) Bus length :
[0043] ;
[0044] (9) Feedback loop identifier :
[0045] ;
[0046] In the formula, The closed-loop path of the trigger itself, starting from the output, passing through several instances, and returning to the input;
[0047] (10) Feedback loop depth :
[0048] ;
[0049] (11) Constant number of drive connections :
[0050] ;
[0051] In the formula, The set of constant signals identified in step 0); For the signal from constant signal c to target node n i The effective path;
[0052] (12) Driving strength :
[0053] ;
[0054] In the formula, For devices in the process library The driving strength parameters.
[0055] In step 2), the standardized feature set obtained in step 1) is processed using the min-max standardization method to eliminate the influence of dimensions. Then, the feature weights are calculated using the entropy method, and the weighted fusion feature matrix is constructed as follows:
[0056] (1) Perform min-max standardization on the original feature values in the standardized feature set obtained in step 1):
[0057] ;
[0058] In the formula, Let j be the j-th original feature value of the i-th node. The standardized feature values are denoted as n, where n is the total number of nodes.
[0059] (2) Based on the standardized feature values, calculate the feature weights using the entropy method:
[0060] ① Calculate the weight of the i-th node under the j-th standardized eigenvalue:
[0061] ;
[0062] ② Based on the above proportions, calculate the entropy value of the j-th feature:
[0063] ;
[0064] ③ Based on the above entropy value, calculate the weight of the j-th feature:
[0065] ;
[0066] In the formula, m is the total number of features, satisfying ;
[0067] (3) Based on the standardized eigenvalues and weights, construct a weighted fusion feature matrix:
[0068] .
[0069] In step 3), the method for constructing a vulnerable node identification model by using the weighted fusion feature matrix constructed in step 2) to train three models—random forest, K-linear, and Xgboost—and then integrating the three trained models through a weighted voting strategy is as follows:
[0070] (1) Data set partitioning: The weighted fusion feature matrix is divided into training set, validation set and test set in a ratio of 7:1.5:1.5;
[0071] (2) Single model training: Using the above training set, validation set, and test set, train, validate, and test the following three models respectively, and obtain the output score. The physical meaning of the output score is the error contribution rate, expressed as a percentage, with a maximum of 100%:
[0072] ① Random Forest: Based on multi-decision tree ensemble, using the Gini coefficient as the splitting criterion;
[0073] ②K-linear: A regularized linear model that minimizes the squared loss function;
[0074] ③Xgboost: Gradient boosting tree model, optimized through residual iteration;
[0075] (3) A vulnerable node identification model is constructed by weighted voting integration: model weights are assigned according to the accuracy of the validation set, and the vulnerability score of the node is calculated using the following formula:
[0076] ;
[0077] In the formula, Score the vulnerability of the i-th node. Score the output of the k-th model. For model weights, satisfying And model weights It is positively correlated with the accuracy of the model validation set.
[0078] In step 4), the weighted fusion feature matrix obtained after processing the circuit to be identified in steps 0) to 2) is input into the vulnerable node identification model obtained in step 3), and the vulnerability score of the node is output. The method for finally determining the list of vulnerable nodes based on the statistical threshold is as follows:
[0079] (1) Statistical threshold calculation: The statistical threshold is determined based on the mean and standard deviation of the vulnerability scores of all nodes, using the following formula:
[0080] ;
[0081] In the formula, The mean of the vulnerability score. The standard deviation of the rating;
[0082] (2) Vulnerable node determination: When the vulnerability score of a node is... When a node is identified as a vulnerable node, all vulnerable nodes are then sorted from highest to lowest vulnerability score to form a vulnerable node list. The formula is as follows:
[0083] ;
[0084] In the formula, A set of vulnerable nodes;
[0085] The higher the vulnerability score of a node, the stronger its vulnerability.
[0086] The circuit vulnerability node identification method based on static feature fusion provided by this invention has the following beneficial effects:
[0087] This invention relies solely on static circuit information for feature extraction and model training, eliminating the need for complex dynamic simulations or irradiation experiments. This significantly shortens the identification cycle and makes it suitable for large-scale, complex circuits. It encompasses four categories of static features: trigger topology, bus association, feedback loops, and process attributes, fully capturing the inherent attributes and correlation characteristics of circuit nodes and solving the problem of single-dimensional feature extraction in traditional methods. Data integrity is ensured through submodule flattening and bus signal expansion. The use of entropy-based objective weighting and multi-model integration strategies effectively improves the accuracy and generalization ability of vulnerable node identification. Furthermore, the unified framework for process library parsing, netlist processing, and feature calculation allows for adaptation to digital circuit designs with different architectures. It provides accurate vulnerable node references in the early stages of circuit reliability design, reducing the iteration cycle of fault-tolerant design and making it suitable for circuit reliability optimization in high-security fields such as aerospace, automotive electronics, and medical equipment. Attached Figure Description
[0088] Figure 1 is a flowchart of the circuit vulnerable node identification method based on static feature fusion provided by the present invention;
[0089] Figure 2 is a flowchart of the circuit basic information database established in step 0) of this invention;
[0090] Figure 3 shows a schematic diagram of a gate-level circuit network;
[0091] Figure 4 is a schematic diagram of the circuit module flattening process;
[0092] Figure 5 is a schematic diagram of the multi-model integration strategy. Detailed Implementation
[0093] The present invention will now be described in detail with reference to the accompanying drawings.
[0094] like Figure 1 As shown, the circuit vulnerability node identification method based on static feature fusion provided by the present invention includes the following steps performed in sequence:
[0095] Step 0): As Figure 2 As shown, the module structure, signal topology, and device attributes are extracted. Figure 3The circuit gate-level netlist and technology library file shown are parsed, and then the module structure, signal topology, signal splitting and device attributes are parsed. Sub-module flattening, bus signal expansion and constant signal extraction are completed to construct the circuit topology diagram, thereby constructing the basic circuit information library.
[0096] The method is as follows:
[0097] (1) Using regular expression matching and recursive traversal algorithms, the attribute information of modules, instances, ports, signals and devices is extracted, the circuit gate-level netlist and process library files are parsed, and multi-dimensional association tables and dictionaries are established to ensure that the data is stored in a structured manner.
[0098] (2) such as Figure 4 As shown, by recursively tracing the instances within submodules, the underlying instances of non-utility submodules are promoted to the top level to flatten the submodules while preserving the original signal connection relationships. The formula is as follows:
[0099] ;
[0100] In the formula, For a flattened collection of instances, Let m be the set of underlying instances of the k-th submodule, and m be the number of submodules.
[0101] (3) Based on the signal naming format, the signals, including bus signals and unit width signals, are split into transmission signals and constant signals. Then, the constant signals are extracted, associated with the corresponding ports and connection lines, and saved in the dictionary.
[0102] (4) Identify the bus format (e.g., bus[M:N]) based on regular expressions, split it bit by bit and generate independent unit-width signals, thereby expanding the bus signals. The expansion logic formula is:
[0103] ;
[0104] In the formula, This is the expanded set of bus signals, where M and N are the bus bit width boundaries;
[0105] (5) Using instance ports and signals as nodes and driving relationships as directed edges, construct a circuit topology graph G=(V,E) to represent the topological relationships, where V is the set of nodes and E is the set of directed edges.
[0106] Step 1): Using the circuit basic information database built in Step 0), extract multi-dimensional static features including flip-flop topology, bus association, feedback loop and process attributes to form a standardized feature set;
[0107] The multi-dimensional static features include:
[0108] (1) Flip-flop fan-in number :
[0109] ;
[0110] In the formula, For target trigger, For other triggers, A collection of combinational logic devices. Indicates the signal driving relationship. This indicates the number of elements in the set. This formula is used to count the number of preceding flip-flops that are indirectly connected to the input of the target flip-flop via combinational logic. The larger the fan-in number, the more preceding memory units the target flip-flop is affected by, the higher the probability of a fault propagating to this node, and the stronger its vulnerability.
[0111] (2) Flip-flop fanout :
[0112] ;
[0113] In the formula, For other flip-flops; this formula is used to count the number of subsequent flip-flops that are indirectly connected to the output of the target flip-flop through combinational logic. The larger the fan-out number, the more the fault of the target flip-flop will propagate to more subsequent memory units, the wider the impact on the overall function of the circuit, and the stronger the vulnerability.
[0114] (3) Total number of FFs affecting the input :
[0115] ;
[0116] In the formula, For trigger To target trigger The effective signal path; this formula expands the statistical range of the fan-in number, and is used to count the total number of triggers that can indirectly affect the input of the target trigger through the signal path, reflecting the "upstream influence surface" of the target node. The larger the influence surface, the higher the probability that the node is affected by upstream failure.
[0117] (4) The total number of FFs affecting the output :
[0118] ;
[0119] In the formula, To trigger the target To trigger The effective signal path; this formula expands the statistical range of fan-out number, and is used to count the total number of flip-flops that can be indirectly affected by the output of the target flip-flop, reflecting the "downstream influence surface" of the target node. The larger the influence surface, the wider the damage range of the node failure to the downstream circuit.
[0120] (5) Path characteristics to the PI / PO port:
[0121] ;
[0122] In the formula, For the target node, , These are the sets of reachable PI and PO ports, respectively. The number of path instances is denoted by . This set of formulas calculates the shortest path order, average path order, and longest path order from the target node to all PI / PO ports, respectively. The shorter the path order, the closer the connection between the target node and the PI / PO port, the more susceptible it is to input noise, and the higher its vulnerability.
[0123] (6) Bus ownership identifier :
[0124] ;
[0125] In the formula, The expanded set of bus signals obtained in step 0) is used to distinguish whether the target node is an independent signal after the bus is split. Nodes marked as 1 belong to bus signals, and their failure usually involves the data transmission of the entire bus, making them the focus of vulnerability identification.
[0126] (7) Bus location :
[0127] ;
[0128] This formula is used to mark the bit index of the target node in the original bus. Different bits of some buses (such as the address bus) may perform functions of different importance. This feature provides a basis for subsequent accurate identification of key vulnerable bits in the bus.
[0129] (8) Bus length :
[0130] ;
[0131] This formula is used to calculate the total number of bits on the bus to which the target node belongs. The longer the bus length, the more signal bits are transmitted in parallel, and the higher the probability that a single bit failure will cause the overall function to fail. It also provides a bus size reference for feature weight calculation.
[0132] (9) Feedback loop identifier :
[0133] ;
[0134] In the formula, This is the closed-loop path of the trigger itself, starting from the output and returning to the input after several instances. This formula is used to determine whether the target trigger has a feedback loop. The path length ≥ 2 is to exclude false "self-loop" judgments (such as invalid paths that directly connect to their own input and output). Node faults marked as 1 will propagate in the loop, which has a great impact on circuit stability.
[0135] (10) Feedback loop depth :
[0136] ;
[0137] This formula is used to calculate the total number of instances of the shortest closed-loop path. The shorter the feedback loop depth, the faster the fault loop propagates and the more quickly it damages the circuit function. Therefore, the feedback node with the smaller the feedback loop depth, the more vulnerable it is.
[0138] (11) Constant number of drive connections :
[0139] ;
[0140] In the formula, The set of constant signals identified in step 0); For the signal from constant signal c to target node n i The effective path; this formula is used to count the number of constant signals that directly or indirectly drive the target node. The higher the stability of the constant signals, the more drivers there are, the less the node is affected by external interference, and the lower its vulnerability. It is a key indicator for judging the stability of the node.
[0141] (12) Driving strength :
[0142] ;
[0143] In the formula, For devices in the process library The driving strength parameter is used to extract the driving strength of the target node driving device from the process library attribute dictionary. The driving strength reflects the signal driving capability of the device. The greater the driving strength, the stronger the anti-interference capability of the device, the more stable the driven node, and the lower the vulnerability. If there is no explicit parameter in the process library, the default baseline value of 4.0 is taken to ensure the consistency of feature calculation.
[0144] Step 2): The standardized feature set obtained in Step 1) is processed using the min-max standardization method to eliminate the influence of dimensions. Then, the feature weights are calculated using the entropy method, and a weighted fusion feature matrix is constructed.
[0145] The method is as follows:
[0146] (1) Perform min-max standardization on the original feature values in the standardized feature set obtained in step 1):
[0147] ;
[0148] In the formula, Let j be the j-th original feature value of the i-th node. The standardized feature values are represented by n, which is the total number of nodes. Different features have different dimensions, such as the fan-in number being an integer and the driving strength being a floating-point number. Direct fusion in this case would lead to the feature with the larger dimension dominating the result. This formula maps all feature values to the interval [0,1], effectively eliminating the influence of dimensions and making features of different dimensions comparable, thus laying the foundation for subsequent weight calculation and matrix fusion.
[0149] (2) Based on the standardized feature values, calculate the feature weights using the entropy method:
[0150] ① Calculate the weight of the i-th node under the j-th standardized eigenvalue:
[0151] ;
[0152] This formula is used to calculate the relative proportion of a single node in a certain feature dimension, reflecting the distribution of the node in that feature dimension, and is the basic data for subsequent entropy calculation.
[0153] ② Based on the above proportions, calculate the entropy value of the j-th feature:
[0154] ;
[0155] Entropy reflects the degree of dispersion of a feature. The smaller the entropy, the greater the dispersion of the feature and the stronger its ability to distinguish the vulnerability of different nodes. Conversely, the larger the entropy, the weaker the feature's ability to distinguish.
[0156] ③ Based on the above entropy value, calculate the weight of the j-th feature:
[0157] ;
[0158] In the formula, m is the total number of features, satisfying This formula uses entropy values to infer feature weights. The smaller the entropy value (the stronger the discriminative ability), the greater the weight of the feature. This achieves "objective weighting," avoids weight bias caused by subjective experience, and ensures that the feature contribution matches the actual recognition needs.
[0159] (3) Based on the standardized eigenvalues and weights, construct a weighted fusion feature matrix:
[0160] ;
[0161] This formula multiplies the standardized feature values by their corresponding weights, highlighting the contribution of important features while compressing the data dimension to form a unified "node-feature" matrix. Each row in the matrix corresponds to a weighted fused feature vector of a node, which can provide standardized input for subsequent machine learning model training.
[0162] Step 3): As Figure 5 As shown, using the weighted fusion feature matrix constructed in step 2), three models, namely Random Forest, K-linear, and Xgboost, are trained respectively. The three trained models are then integrated through a weighted voting strategy to construct a vulnerable node identification model.
[0163] The method is as follows:
[0164] (1) Data set partitioning: The weighted fusion feature matrix is divided into training set, validation set and test set in a ratio of 7:1.5:1.5;
[0165] (2) Single model training: Using the above training set, validation set, and test set, train, validate, and test the following three models respectively, and obtain the output score. The physical meaning of the output score is the error contribution rate, expressed as a percentage, with a maximum of 100%:
[0166] ① Random Forest: Based on multi-decision tree ensemble, using the Gini coefficient as the splitting criterion;
[0167] ②K-linear: A regularized linear model that minimizes the squared loss function;
[0168] ③Xgboost: Gradient boosting tree model, optimized through residual iteration;
[0169] The three models mentioned above each have their own advantages: Random Forest has strong anti-interference ability, K-linear ensures basic recognition efficiency, and Xgboost improves accuracy in complex scenes. The combination of the three can cover the feature patterns of different circuit architectures.
[0170] (3) A vulnerable node identification model is constructed by weighted voting integration: model weights are assigned according to the accuracy of the validation set, and the vulnerability score of the node is calculated using the following formula:
[0171] ;
[0172] In the formula, Score the vulnerability of the i-th node. Score the output of the k-th model. For model weights, satisfying And model weights It is positively correlated with the accuracy of the model validation set. This formula integrates the outputs of three individual models through a weighted voting strategy, with the model having a higher validation set accuracy having a larger weight. This makes the integrated result more inclined towards the better-performing model, while avoiding the limitations of a single model, thereby improving the stability and reliability of the recognition results.
[0173] Step 4): Input the weighted fusion feature matrix obtained after processing the circuit to be identified in steps 0) to 2) into the vulnerable node identification model obtained in step 3), output the vulnerability score of the node, and finally determine the list of vulnerable nodes based on the statistical threshold.
[0174] The method is as follows:
[0175] (1) Statistical threshold calculation: The statistical threshold is determined based on the mean and standard deviation of the vulnerability scores of all nodes, using the following formula:
[0176] ;
[0177] In the formula, The mean of the vulnerability score. The standard deviation of the rating;
[0178] (2) Vulnerable node determination: When the vulnerability score of a node is... When a node is identified as a vulnerable node, all vulnerable nodes are then sorted from highest to lowest vulnerability score to form a vulnerable node list. The formula is as follows:
[0179] ;
[0180] In the formula, A set of vulnerable nodes;
[0181] The higher the vulnerability score of a node, the more vulnerable it is. This provides a clear priority order for circuit reliability optimization, making it easier for designers to prioritize hardening highly vulnerable nodes.
Claims
1. A method for identifying vulnerable nodes in a circuit based on static feature fusion, characterized in that: The method includes the following steps performed in sequence: Step 0): Extract module structure, signal topology and device attributes, parse the circuit gate-level netlist and technology library file, then parse the module structure, signal topology, signal splitting and device attributes, complete the sub-module flattening, bus signal expansion and constant signal extraction, construct the circuit topology diagram, and thus construct the circuit basic information database; Step 1): Using the circuit basic information database built in Step 0), extract multi-dimensional static features including flip-flop topology, bus association, feedback loop and process attributes to form a standardized feature set; Step 2): The standardized feature set obtained in Step 1) is processed using the min-max standardization method to eliminate the influence of dimensions. Then, the feature weights are calculated using the entropy method, and a weighted fusion feature matrix is constructed. Step 3): Using the weighted fusion feature matrix constructed in Step 2), train three models: Random Forest, K-linear, and Xgboost, respectively. Then, integrate the three trained models through a weighted voting strategy to construct a vulnerable node identification model. Step 4): Input the weighted fusion feature matrix obtained after processing the circuit to be identified in steps 0) to 2) into the vulnerable node identification model obtained in step 3), output the vulnerability score of the node, and finally determine the list of vulnerable nodes based on the statistical threshold.
2. The circuit vulnerability node identification method based on static feature fusion according to claim 1, characterized in that: In step 0), the extraction of module structure, signal topology, and device attributes involves parsing the circuit gate-level netlist and technology library file, then parsing the module structure, signal topology, signal decomposition, and device attributes to complete sub-module flattening, bus signal expansion, and constant signal extraction. The method for constructing the circuit topology diagram is as follows: (1) Using regular expression matching and recursive traversal algorithms, the attribute information of modules, instances, ports, signals and devices is extracted, the circuit gate-level netlist and process library files are parsed, and a multi-dimensional association table and dictionary are established; (2) By recursively tracing the instances within the submodules, the underlying instances of non-utility submodules are promoted to the top level to flatten the submodules, while preserving the original signal connection relationships. The formula is as follows: ； In the formula, For a flattened collection of instances, Let m be the set of underlying instances of the k-th submodule, and m be the number of submodules. (3) Based on the signal naming format, the signals, including bus signals and unit width signals, are split into transmission signals and constant signals. Then, the constant signals are extracted, associated with the corresponding ports and connection lines, and saved in the dictionary. (4) The bus format is identified based on regular expressions, and the signals are split bit by bit to generate independent unit-width signals. The bus signals are then expanded, and the expansion logic formula is as follows: ； In the formula, This is the expanded set of bus signals, where M and N are the bus bit width boundaries; (5) Using instance ports and signals as nodes and driving relationships as directed edges, construct a circuit topology graph G=(V,E) to represent the topological relationships, where V is the set of nodes and E is the set of directed edges.
3. The circuit vulnerability node identification method based on static feature fusion according to claim 1, characterized in that: In step 1), the multi-dimensional static features include: (1) Flip-flop fan-in number : ； In the formula, For target trigger, For other triggers, A collection of combinational logic devices. Indicates the signal driving relationship. Indicates the number of elements in the set; (2) Flip-flop fanout : ； In the formula, For other triggers; (3) Total number of FFs affecting the input : ； In the formula, For trigger To target trigger The effective signal path; (4) The total number of FFs affecting the output : ； In the formula, To trigger the target To trigger The effective signal path; (5) Path characteristics to the PI / PO port: ； In the formula, For the target node, , These are the sets of reachable PI and PO ports, respectively. This represents the number of path instances; this set of formulas calculates the shortest path level, average path level, and longest path level from the target node to all PI / PO ports, respectively. The shorter the path level, the better. (6) Bus ownership identifier : ； In the formula, This is the expanded set of bus signals obtained in step 0); nodes marked as 1 belong to the bus signals; (7) Bus location : ； (8) Bus length : ； (9) Feedback loop identifier : ； In the formula, The closed-loop path of the trigger itself, starting from the output, passing through several instances, and returning to the input; (10) Feedback loop depth : ； (11) Constant number of drive connections : ； In the formula, The set of constant signals identified in step 0); For the signal from constant signal c to target node n i The effective path; (12) Driving strength : ； In the formula, For devices in the process library The driving strength parameters.
4. The circuit vulnerability node identification method based on static feature fusion according to claim 1, characterized in that: In step 2), the standardized feature set obtained in step 1) is processed using the min-max standardization method to eliminate the influence of dimensions. Then, the feature weights are calculated using the entropy method, and the weighted fusion feature matrix is constructed as follows: (1) Perform min-max standardization on the original feature values in the standardized feature set obtained in step 1): ； In the formula, Let j be the j-th original feature value of the i-th node. The standardized feature values are denoted as n, where n is the total number of nodes. (2) Based on the standardized feature values, calculate the feature weights using the entropy method: ① Calculate the weight of the i-th node under the j-th standardized eigenvalue: ； ② Based on the above proportions, calculate the entropy value of the j-th feature: ； ③ Based on the above entropy value, calculate the weight of the j-th feature: ； In the formula, m is the total number of features, satisfying ; (3) Based on the standardized eigenvalues and weights, construct a weighted fusion feature matrix: 。 5. The circuit vulnerability node identification method based on static feature fusion according to claim 1, characterized in that: In step 3), the method for constructing a vulnerable node identification model by using the weighted fusion feature matrix constructed in step 2) to train three models—random forest, K-linear, and Xgboost—and then integrating the three trained models through a weighted voting strategy is as follows: (1) Data set partitioning: The weighted fusion feature matrix is divided into training set, validation set and test set in a ratio of 7:1.5:1.5; (2) Single model training: Using the above training set, validation set, and test set, train, validate, and test the following three models respectively, and obtain the output score. The physical meaning of the output score is the error contribution rate, expressed as a percentage, with a maximum of 100%: ① Random Forest: Based on multi-decision tree ensemble, using the Gini coefficient as the splitting criterion; ②K-linear: A regularized linear model that minimizes the squared loss function; ③Xgboost: Gradient boosting tree model, optimized through residual iteration; (3) A vulnerable node identification model is constructed by weighted voting integration: model weights are assigned according to the accuracy of the validation set, and the vulnerability score of the node is calculated using the following formula: ； In the formula, Score the vulnerability of the i-th node. Score the output of the k-th model. For model weights, satisfying And model weights It is positively correlated with the accuracy of the model validation set.
6. The circuit vulnerability node identification method based on static feature fusion according to claim 1, characterized in that: In step 4), the weighted fusion feature matrix obtained after processing the circuit to be identified in steps 0) to 2) is input into the vulnerable node identification model obtained in step 3), and the vulnerability score of the node is output. The method for finally determining the list of vulnerable nodes based on the statistical threshold is as follows: (1) Statistical threshold calculation: The statistical threshold is determined based on the mean and standard deviation of the vulnerability scores of all nodes, using the following formula: ； In the formula, The mean of the vulnerability score. The standard deviation of the rating; (2) Vulnerable node determination: When the vulnerability score of a node is... When a node is identified as a vulnerable node, all vulnerable nodes are then sorted from highest to lowest vulnerability score to form a vulnerable node list. The formula is as follows: ； In the formula, A set of vulnerable nodes; The higher the vulnerability score of a node, the stronger its vulnerability.