High-speed serial interface physical ip verification platform, method, device and medium

Abstract

The application relates to the technical field of integrated circuits and provides a high-speed serial interface physical IP verification platform, method, device and medium. The application provides a unified design and verification platform supporting coexistence and fusion of multiple protocol types and a multi-protocol physical layer intellectual property core design and verification, is based on a modular, parameterized, multi-protocol and harmonious coexistence design idea and a top-level architecture circuit design method, can effectively reduce the circuit design and verification manpower cost of various different protocol types in project development, significantly shortens the function and performance verification period of the physical layer intellectual property core, significantly improves the full-stack and full-field research and development efficiency of the architecture design, circuit development and full-amount function / performance verification for different protocol types, improves the design and verification platform reuse degree between different protocols, and provides an excellent paradigm of unified design and verification with high platform level.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a verification platform, method, device and medium for a high-speed serial interface physical IP. Background Technology

[0002] In applications such as high-speed digital communication and high-speed interfaces, serializer / deserializer (Serdes), sometimes also called SERDES, is widely used. Several communication protocols and interface standards utilize high-speed Serdes serial interfaces, such as the PCI Express (PCIe) high-speed serial peripheral interconnect bus protocol, the Serial Advanced Technology Attachment (SATA) protocol, the Universal Serial Bus (USB) protocol, the DisplayPort (DP) protocol, the Ethernet (ETH) protocol, and the JESD protocol for high-speed serial interfaces between data converters and logic devices. These different types of Serdes protocols are continuously iterating and evolving, and the product forms and application scenarios of physical layer intellectual property cores (PHY IP) developed based on these Serdes protocols are becoming increasingly diverse, thus posing challenges to chip design and verification. From top-level architecture planning to circuit design and interface function and performance verification, it is necessary to consider how to provide scalability and compatibility for different protocol types, such as constructing different stimulus sequence modes for different protocol types, and providing modeling and automated verification of protocol-related registers. Existing chip verification solutions typically only provide verification during the design and development process for a single protocol type or two single protocol types. They require pre-determining which protocols have interfacing needs and retaining the corresponding network interfaces or supporting the corresponding protocol ports by changing configurations. For example, Chinese patent application CN102929756A discloses a bus development and verification platform that retains low-speed bus interfaces for compatibility with low-speed buses, and also retains high-speed serial bus interfaces such as the high-speed serial SATA storage interface for the development and verification of the SATA storage bus. Another example is Chinese patent application CN118540248A, which discloses measuring the transmit / receive latency of SerDes interfaces for various protocols by updating the protocol port configuration of a protocol conversion chip, such as configuring it as a PCIe protocol port or an Ethernet protocol port. However, existing chip verification solutions that support multi-protocol verification lack overall optimization starting from top-level design. They are difficult to adapt to newly emerging protocol types or new versions, and require additional hardware resources to retain interfaces or to increase latency for configuration switching between protocol ports. This is not conducive to reducing the overall project design, development and verification costs and time, and it is also difficult to match the various high-speed serial SerDes protocols that are constantly being updated and evolving. It is also difficult to meet the rapid iteration and verification needs of high-speed SerDes PHY IP products.

[0003] To address these technical challenges, this application provides a verification platform, method, device, and medium for high-speed serial interface physical IP. Summary of the Invention

[0004] Firstly, this application provides a verification platform for a high-speed serial interface physical IP. The verification platform includes: a transaction layer for generating stimulus sequences of a single protocol type and stimulus sequences of multiple protocol types, wherein the transaction layer includes a high-speed serial interface multi-protocol type physical interface proxy component and a unified type serial interface proxy component; an interface layer for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component to sample stimulus sequences sent through the multi-protocol type physical interface itself and received by the multi-protocol type physical interface from the unified type serial interface, and to sample stimulus sequences sent through the unified type serial interface itself and received by the unified type serial interface from the multi-protocol type physical interface; and a signal layer for providing the multi-protocol type physical interface and the unified type serial interface for interfacing with the design under test (DUT). The serial port protocol associated with the DUT is a single protocol or a combination of multiple protocols. When the serial port protocol associated with the design under test (DUT) is a single protocol, the verification platform parses the highest rate of the interface signal of the DUT and generates an excitation sequence for the single protocol type, thereby initiating protocol conformance verification for the single protocol type associated with the serial port protocol of the DUT. When the serial port protocol associated with the DUT is a combination of multiple protocols, the verification platform determines that the serial port protocol associated with the DUT is a combination of a first serial port protocol and a second serial port protocol. Then, it parses the key parameters of the first serial port protocol and the second serial port protocol respectively, generates an excitation sequence for the multiple protocol type, thereby initiating protocol conformance verification for the multiple protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol, where the first serial port protocol is different from the second serial port protocol.

[0005] The first aspect of this application provides a unified design and verification platform that supports the coexistence and integration of multiple protocol types and utilizes the design and verification of multi-protocol physical layer intellectual property cores. Based on the design philosophy of modularization, parameterization, and harmonious coexistence of multiple protocols, and a top-level architecture circuit design method, it can call upon a rich underlying library of general verification methodologies. It provides verification interface components that are easily extended hierarchically by users, as well as a variety of stimulus sequences. It possesses key characteristics and advantages such as matching kernels of multiple protocol types, general design, and flexible parameterization combinations. Furthermore, based on this unified design and verification platform that simultaneously supports single and multiple protocol types, it can effectively reduce the manpower costs of circuit design and verification for various protocol types during project development, significantly shorten the functional and performance verification cycle of physical layer intellectual property cores (PHY IP), and significantly improve the full-stack, full-domain R&D efficiency of architecture design, circuit development, and full functional / performance verification for different protocol types (multiple single protocols coexisting or multiple protocol combinations). It also enhances the reusability of the design and verification platform across different protocols, providing an excellent paradigm for unified design and verification with a very high platform standard.

[0006] In one possible implementation of the first aspect of this application, the serial port protocol associated with the design under test is the SerDes protocol, and the design under test is one or more SerDes physical layer intellectual property cores conforming to the SerDes protocol.

[0007] In one possible implementation of the first aspect of this application, the high-speed serial interface multi-protocol type physical interface proxy component is used to generate the multi-protocol type excitation sequence transmitted through the multi-protocol type physical interface, the unified type serial interface proxy component is used to generate the multi-protocol type excitation sequence transmitted through the unified type serial interface, and the interface layer includes a physical interface transmit-side sampler for sampling the excitation sequence transmitted through the multi-protocol type physical interface itself and a physical interface receive-side sampler for sampling the excitation sequence received by the multi-protocol type physical interface and transmitted through the unified type serial interface. The interface layer also includes a serial interface transmit-side sampler for sampling the excitation sequence transmitted through the unified type serial interface itself and a serial interface receive-side sampler for sampling the excitation sequence received by the unified type serial interface and transmitted through the multi-protocol type physical interface.

[0008] In one possible implementation of the first aspect of this application, the transaction layer further includes a physical interface receiving-side automatic verifier for automatically verifying the excitation sequence sampled by the physical interface receiving-side sampler of the interface layer and sent through the unified type serial interface by the multi-protocol type physical interface, and a serial interface transmitting-side automatic verifier for automatically verifying the excitation sequence sampled by the serial interface transmitting-side sampler of the interface layer and sent through the unified type serial interface itself.

[0009] In one possible implementation of the first aspect of this application, the interface layer includes a driver component for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component. Furthermore, the driver component, the physical interface transmit-side sampler, the physical interface receive-side sampler, the serial interface transmit-side sampler, and the serial interface receive-side sampler included in the interface layer can be used for bottom-to-top-level integration of the system-on-a-chip and physical layer multiplexing.

[0010] In one possible implementation of the first aspect of this application, the serial port protocol associated with the design under test belongs to the SerDes protocol set, which includes various versions of the High-Speed ​​Serial Peripheral Interconnect Bus protocol, various versions of the Serial Hard Disk Interface Advanced Specification protocol, various versions of the Universal Serial Bus protocol, various versions of the Display Interface protocol, various versions of the Ethernet protocol, and various versions of the High-Speed ​​Serial Interface Protocol for Data Converters and Logic Devices.

[0011] In one possible implementation of the first aspect of this application, when the serial port protocol associated with the design under test is a single protocol, the serial port protocol associated with the design under test is any one of the SerDes protocol sets, and when the serial port protocol associated with the design under test is a combination of multiple protocols, the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe protocol and SATA protocol, a combination of PCIe protocol and USB protocol, or a combination of USB protocol and DP protocol.

[0012] In one possible implementation of the first aspect of this application, the signal layer further includes an assertion checker for the multi-protocol type physical interface. The assertion checker is associated with the top-level physical interface of the design under test through a binding method to perform timing-level assertion verification. The protocol consistency verification of the multi-protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol includes the timing-level assertion verification.

[0013] In one possible implementation of the first aspect of this application, the layered structure of the verification platform includes the transaction layer, the interface layer, and the signal layer. The layered structure of the verification platform is determined based on functional differentiation. The transaction layer represents the communication environment of the design under test, the interface layer represents the behavioral-level description of the functional modules, and the signal layer represents the transmission of commands and data in the communication process of the design under test.

[0014] In one possible implementation of the first aspect of this application, the transaction layer further includes a behavior-level reference model that supports a physical layer register abstraction layer model. The physical layer register abstraction layer model includes register data structures and memory data structures. The behavior-level reference model is used to perform independent configuration and software read / write access operations on multi-protocol common circuits and multi-protocol differentiated circuits, respectively.

[0015] In one possible implementation of the first aspect of this application, the multi-protocol common circuit is the intersection of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol, and the multi-protocol differentiated circuit is the union of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol minus the intersection of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol.

[0016] In one possible implementation of the first aspect of this application, when the serial port protocol associated with the design under test is a combination of multiple protocols and the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe 3.0 protocol and USB 3.0 protocol, the common circuit of the multiple protocols includes an encoding and decoding circuit, a clock generation circuit and a phase-locked loop circuit, and the differentiated circuit of the multiple protocols includes a periodic low-frequency signal detection circuit and a low-power management circuit.

[0017] In one possible implementation of the first aspect of this application, the verification platform utilizes the transaction layer to simulate a control plane based on the PCIe 3.0 protocol for issuing input / output read / write commands, and to simulate a power and energy management plane based on the USB 3.0 protocol for providing system-level power supply and low-power management settings.

[0018] In one possible implementation of the first aspect of this application, when the serial port protocol associated with the design under test is a combination of multiple protocols and the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe 5.0 protocol and SATA protocol, the common circuit of the multiple protocols includes a low-speed codec circuit, a low-power management circuit and a physical layer calibration and adaptation circuit, and the differentiating circuit of the multiple protocols includes a high-speed codec circuit, a high-speed receiver-side channel margin circuit and a high-speed transmitter-side equalization circuit.

[0019] In one possible implementation of the first aspect of this application, the verification platform utilizes the transaction layer to simulate a control plane based on the PCIe 5.0 protocol for issuing high-speed, low-latency memory read / write commands and to simulate a storage plane based on the SATA protocol for initiating physical-level low-to-medium speed hard drive data access and transfer operations.

[0020] Secondly, this application provides a verification method for a high-speed serial interface physical IP. The verification method includes: determining whether the serial port protocol associated with the design under test (DUT) is a single protocol or a combination of multiple protocols; when the serial port protocol associated with the DUT is a single protocol, parsing the highest rate of the interface signal of the DUT, generating an excitation sequence of a single protocol type, thereby initiating protocol conformance verification of the single protocol type corresponding to the serial port protocol associated with the DUT, for use in the design of the functional characteristics, performance, and protocol specification compliance of the DUT; when the serial port protocol associated with the DUT is a combination of multiple protocols, determining that the serial port protocol associated with the DUT is a combination of a first serial port protocol and a second serial port protocol, then parsing the key parameters of the first serial port protocol and the second serial port protocol respectively, generating an excitation sequence of multiple protocol types, thereby initiating protocol conformance verification of the multiple protocol types corresponding to the combination of the first serial port protocol and the second serial port protocol, wherein the first serial port protocol is different from the second serial port protocol. The single-protocol type stimulus sequence and the multi-protocol type stimulus sequence are both generated by the transaction layer of the verification platform. The transaction layer includes a high-speed serial interface multi-protocol type physical interface proxy component and a unified type serial interface proxy component. The verification platform also includes an interface layer for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component. The verification platform also includes a signal layer for providing multi-protocol type physical interfaces and unified type serial interfaces for interfacing with the design under test. The interface layer is also used to sample the stimulus sequences sent through the multi-protocol type physical interface itself and received by the multi-protocol type physical interface from the unified type serial interface.

[0021] The second aspect of this application provides a unified design and verification platform that supports the coexistence and integration of multiple protocol types and utilizes the design and verification of multi-protocol physical layer intellectual property cores. Based on modular, parameterized, and multi-protocol harmonious coexistence design principles and top-level architecture circuit design methods, it can call upon a rich underlying library of general verification methodologies. It provides easily user-expandable verification interface components and a wide variety of stimulus sequences, possessing key characteristics and advantages such as matching multi-protocol type kernels, general design, and flexible parameterized combinations. Furthermore, based on this unified design and verification platform that simultaneously supports single and multiple protocol types, it effectively reduces the manpower costs of circuit design and verification for various protocol types during project development, significantly shortens the functional and performance verification cycle of physical layer intellectual property cores (PHY IP), and significantly improves the full-stack, full-domain R&D efficiency for architecture design, circuit development, and full functional / performance verification for different protocol types (multiple single protocols coexisting or multiple protocol combinations). It also enhances the reusability of the design and verification platform across different protocols, providing an excellent paradigm for unified design and verification with a very high platform standard.

[0022] In one possible implementation of the second aspect of this application, the serial port protocol associated with the design under test is the SerDes protocol, and the design under test is one or more SerDes physical layer intellectual property cores conforming to the SerDes protocol.

[0023] In one possible implementation of the second aspect of this application, the layered structure of the verification platform includes the transaction layer, the interface layer, and the signal layer. The layered structure of the verification platform is determined based on functional differentiation. The transaction layer represents the communication environment of the design under test, the interface layer represents the behavioral-level description of the functional modules, and the signal layer represents the transmission of commands and data in the communication process of the design under test.

[0024] Thirdly, embodiments of this application also provide a computer device, the computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a method according to any of the above-mentioned implementations.

[0025] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer instructions that, when executed on a computer device, cause the computer device to perform a method according to any of the above-described implementations.

[0026] Fifthly, embodiments of this application also provide a computer program product, the computer program product including instructions stored on a computer-readable storage medium, which, when executed on a computer device, cause the computer device to perform a method according to any of the above-described aspects. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a verification platform for a high-speed serial interface physical IP provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating a serial port protocol using a combination of multiple protocols in multiple application scenarios, provided as an embodiment of this application. Figure 3 A flowchart illustrating a method for verifying the physical IP of a high-speed serial interface provided in this application embodiment; Figure 4 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0029] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0030] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0031] Figure 1 This is a schematic diagram of a verification platform for a high-speed serial interface physical IP provided in an embodiment of this application. Figure 1As shown, the verification platform includes a transaction layer 101, an interface layer 103, and a signal layer 105. Here, considering that in applications such as high-speed digital communication and high-speed interfaces, communication protocols and interface standards using serializer / de-serializer (Serdes) technology may have different layered structures and protocol compositions, this is important. High-speed serial interfaces, also called high-speed Serdes serial interfaces, commonly include, but are not limited to, high-speed serial peripheral interconnect bus protocols (PCI Express, PCIe), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), DisplayPort (DP), Ethernet (ETH), and High-Speed ​​Serial Interface for Data Converters and Logic Devices (JESD). Taking PCIe5 or other PCIe protocols as an example, the layered structure of the PCIe5 protocol includes the application layer, transaction layer, data link layer, and physical layer. Taking the JESD protocol, a high-speed serial interface protocol for data converters and logic devices, as an example, its layered structure includes the application layer, transport layer, data link layer, and physical layer, unlike the PCIe protocol's layered structure (application layer, transaction layer, data link layer, physical layer). Furthermore, different high-speed serial port protocols have optimized their protocol structure and data formats for different application scenarios. For example, the DisplayPort protocol (DP) is a standardized digital video interface standard, specifically designed for high-speed serial interface standard for digital video and audio transmission. To ensure compatibility with various high-speed serial port protocols, adapt to new protocol types and versions, and implement a top-down optimization approach, transaction layer 101, interface layer 103, and signal layer 105 are used as three functionally independent interface layers, each with parameterized, modular, and polymorphic optimized designs. Thus, by providing an optimized layered structure and modular core components, reference functions are differentiated, allowing for planning based on environmental requirements, functional module operation, and command and data transmission. This facilitates object-oriented scalability and support for multiple modes and polymorphism. Specifically, transaction layer 101 is used to generate stimulus sequences for single protocol types and stimulus sequences for multiple protocol types.The transaction layer 101 includes a high-speed serial interface multi-protocol physical interface agent component 110 (Multi-Protocol PIPE Agent) and a uniform type serial interface agent component 120 (Uniform Multi-Protocol Serdes Agent). The interface layer 103 drives the high-speed serial interface multi-protocol physical interface agent component 110 and the uniform type serial interface agent component 120 to sample stimulus sequences transmitted through the multi-protocol physical interface 114 and received by the multi-protocol physical interface 114, and to sample stimulus sequences transmitted through the multi-protocol physical interface 114 and received by the uniform type serial interface 124. The signal layer 105 provides the multi-protocol physical interface 114 and the uniform type serial interface 124 for interfacing with the design under test (physical interface level design under test 194). The serial port protocol associated with the design under test is a single protocol or a combination of multiple protocols. When the serial port protocol associated with the design under test (DUT) is a single protocol, the verification platform parses the highest rate of the interface signal of the DUT and generates an excitation sequence for the single protocol type, thereby initiating protocol conformance verification for the single protocol type associated with the serial port protocol of the DUT. When the serial port protocol associated with the DUT is a combination of multiple protocols, the verification platform determines that the serial port protocol associated with the DUT is a combination of a first serial port protocol and a second serial port protocol. Then, it parses the key parameters of the first serial port protocol and the second serial port protocol respectively, generates an excitation sequence for the multiple protocol type, thereby initiating protocol conformance verification for the multiple protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol, where the first serial port protocol is different from the second serial port protocol.

[0032] See Figure 1By distinguishing between two scenarios—a single serial port protocol associated with the design under test (DUT) and a combination of multiple serial port protocols—and taking corresponding measures, adjustments can be made to the generation of stimulus sequences and the protocol consistency verification. Furthermore, adjustments can be made to functional verification, performance verification, and protocol consistency verification. Specifically, when the serial port protocol associated with the DUT is a single protocol, functional verification, performance verification, and protocol consistency verification of the single protocol type corresponding to the DUT are initiated. When the serial port protocol associated with the DUT is a combination of multiple protocols, functional verification, performance verification, and protocol consistency verification of the multi-protocol type corresponding to the combination of the first and second serial port protocols are initiated. This supports the design of the functional characteristics, performance, and protocol specification compliance of the DUT. Furthermore, considering the various protocol types that may correspond to the serial port protocols associated with the design under test, a top-down modular and parameterized design is adopted. The architecture is divided into single-protocol and multi-protocol combinations. By parsing key information (the highest rate of the interface signals of the design under test, or the key parameters of the first and second serial port protocols respectively), and combining this with an optimized layered structure differentiated by reference functions, a unified core component for polymorphic, parameterized, and modular design and verification is provided. Thus, not only can top-level architecture planning, circuit design, interface function, and performance verification be performed based on a single protocol type, but also top-level architecture planning, circuit design, interface function, and performance verification can be performed based on any combination of two different protocol types (the first serial port protocol differs from the second serial port protocol). Furthermore, it provides object-oriented scalability, multi-mode and polymorphism, supports the calling of public libraries, supports the construction of stimulus sequences for different protocol types, supports the modeling of protocol-related registers and automated verification methods, can meet the highest rate and bandwidth requirements of various high-speed SerDes serial interfaces, match the needs of continuous parallel iteration and evolution of different types of SerDes protocols, supports rich product forms and diversified application scenarios of multi-protocol SerDes physical layer intellectual property cores (SerDes PHY IP), adapts to newly emerging protocol types or new versions, helps to reduce the cost and time of overall project design, development and verification, helps to match various high-speed serial SerDes protocols that are constantly being updated and evolved, and is conducive to meeting the rapid iteration and verification needs of high-speed SerDes PHY IP products.

[0033] Continue reading Figure 1The system allows for the integration of multiple protocols of any two different protocol types (with the first serial port protocol differing from the second) to meet the increasingly diverse external interface forms required for chip development. Examples include PCIe bus interfaces, USB bus interfaces, SATA storage bus interfaces, DP display interfaces, and ETH ports. It supports the coexistence of different protocol types, integrating various high-speed serial interfaces while also supporting various single protocol types and pairwise combinations of multiple protocol types. For instance, it supports single protocol types such as various versions of the High-Speed ​​Serial Peripheral Interconnect Bus protocol, various versions of the Advanced Specification for Serial Hard Disk Interface (ADI) protocol, various versions of the Universal Serial Bus (USB) protocol, various versions of display interface protocols, various versions of Ethernet protocols, and various versions of high-speed serial interface protocols for data converters and logic devices. Furthermore, it supports pairwise combinations of multiple protocol types, such as PCIe + SATA, PCIe + USB, USB + DP, etc. Thus, by supporting the coexistence and integration of multiple protocols, it can meet the diverse application scenario requirements, providing flexible and rich user-customizable protocol type combination options. Furthermore, by utilizing the optimized layered structure and corresponding core components described above, the power consumption / performance area (PPA) metrics can be improved from the top-level architecture. Employing a design philosophy that integrates versatility, parameterization, and multi-protocol types, it goes beyond simple modularization and fine-grained decomposition. Instead, it integrates a circuit design flow supporting SerDes PHY IPs for multiple protocol types. This allows for differentiation between single-protocol and multi-protocol combinations based on the user's static configuration scenario, enabling further subdivision and extraction of key information, followed by execution of appropriate processing flows. This achieves a unified, universal verification platform that integrates multiple protocol types. Figure 1The verification platform for the high-speed serial interface physical IP shown has the following improvements and beneficial technical effects: 1) It supports relevant protocols of the high-speed serial interface physical IP, such as PCIe, SATA, USB, DP, ETH, and JESD. It adopts a top-down modular and parameterized design and considers the needs of multiple protocol types, including constructing stimulus sequences for different protocol types and providing register modeling and verification methods for different protocol types. 2) In terms of architecture design, it supports various single protocol types and combinations of multiple protocols, such as PCIe plus SATA, PCIe plus USB, and USB plus DP, which helps to provide inclusiveness and flexibility while taking into account power consumption / performance / area indicators. 3) Based on single protocol types and combinations of two protocol types, it parses the corresponding protocol rate, phase-locked loop frequency, and other key information, and performs corresponding processing according to the highest rate and protocol type of the interface signal. 4) Provides a unified universal verification platform for the fusion of corresponding multi-protocol types, supporting the generation of stimulus sequences for single and multiple protocol types. It supports parameterized verification interface components that include and match different protocol types, and parameterized interface and control signal handshake timings that include and match different protocol types. 5) Through configuration interfaces and parameterized design, it supports behavioral reference models such as Register Abstraction Level (RAL) models, including typical data structures like register data structures and memory data structures, and different attributes such as read / write, read-only, read-clear, and software write-clear. 6) Supports independent configuration and software read / write access for common circuits (circuits reflecting common characteristics among multiple protocols) and differentiated circuits (circuits reflecting differentiated characteristics among multiple protocols) across various protocols.

[0034] Continue reading Figure 1In transaction layer 101, through physical layer register abstraction layer model 190 and reference model 192, and through high-speed serial interface multi-protocol type physical interface proxy component 110 and unified type serial interface proxy component 120, parameterized multi-protocol type stimulus sequences and parameterized behavioral reference models are implemented, which can be used for system-level and chip-level integration and reuse by users. Furthermore, based on the data flow direction, it can be divided into high-speed serial interface multi-protocol type physical interface proxy component 110 and unified type serial interface proxy component 120, which can be used to generate multi-protocol type stimulus sequences and single-protocol type stimulus sequences respectively. In addition, through physical interface receiver-side automatic checker 150 and serial interface transmitter-side automatic checker 152, corresponding automatic check is provided based on whether the data flow is in the sending or receiving direction. In interface layer 103, parameterized and modular driver components are supported, namely physical interface driver component 112 and serial interface driver component 122. Additionally, depending on whether the data flow is sending or receiving, a physical interface send-side sampler 130 and a physical interface receive-side sampler 132 are provided. This allows sampling of the excitation sequences sent through the multi-protocol type physical interface 114 itself and received by the multi-protocol type physical interface 114 via the unified type serial interface 124. Furthermore, depending on whether the data flow is sending or receiving, a serial interface send-side sampler 142 and a serial interface receive-side sampler 140 are provided. This allows sampling of the excitation sequences sent through the unified type serial interface 124 itself and received by the unified type serial interface 124 via the multi-protocol type physical interface 114. Moreover, both the driver components and samplers can be used for bottom-up integration and physical layer multiplexing at the customer's system-on-chip level. At the signal layer 105, by providing the multi-protocol type physical interface 114 and the unified type serial interface 124, which are of common standard for multiple protocols, timing-level assertion checks can be performed in conjunction with an assertion checker, thereby facilitating protocol conformance verification.

[0035] In short, Figure 1The high-speed serial interface physical IP verification platform shown provides a unified design and verification platform that supports the coexistence and integration of multiple protocol types and can be used for the design and verification of multi-protocol physical layer intellectual property cores. Based on the design philosophy of modularization, parameterization, and harmonious coexistence of multiple protocols, and the top-level architecture circuit design method, it can call a rich underlying library of general verification methodologies. It provides verification interface components that are easy for users to extend hierarchically and offers a variety of stimulus sequences. It has key characteristics and advantages such as matching multi-protocol type cores, general design, and flexible parameterization combination. Furthermore, based on the unified design and verification platform that simultaneously supports single and multiple protocol types, it can effectively reduce the manpower costs of circuit design and verification for various protocol types in project development, significantly shorten the functional and performance verification cycle of physical layer intellectual property cores (PHY IP), and significantly improve the full-stack and full-domain R&D efficiency of architecture design, circuit development, and full functional / performance verification for different protocol types (multiple single protocols coexisting or multiple protocol combinations). It also enhances the reusability of the design and verification platform between different protocols, providing an excellent paradigm of unified design and verification with a very high platform level.

[0036] Figure 2 This is a schematic diagram illustrating a serial port protocol using a combination of multiple protocols in various application scenarios, as provided in an embodiment of this application. For example... Figure 2 As shown, in application scenario A201 (high-performance computing), a multi-protocol combination is used as the serial port protocol, and this combination includes a physical layer intellectual property core combination that mixes PCIe3 and USB3 protocols. In application scenario B203 (solid-state storage), such as a solid-state drive (SSD), a multi-protocol combination is used as the serial port protocol, and this combination includes PCIe5 and SATA. Furthermore, in application scenario C205, a multi-protocol combination is used as the serial port protocol, and this combination includes PCIe3 and USB4. In application scenario D207, a multi-protocol combination is used as the serial port protocol, and this combination includes PCIe4 and SATA.

[0037] See Figure 2As can be seen, different application scenarios may have overlapping requirements, such as using the same communication protocol or interface standard. However, even if two application scenarios use the same communication protocol or interface standard, such as application scenario A201 (high-performance computing) and application scenario C205 both using PCIe3, these two application scenarios may have different settings for key parameters, such as protocol speed, phase-locked loop frequency, reference clock frequency, and cascaded division factor. Therefore, for the circuit design of SerDes PHY IP that integrates multiple protocol types (such as PCIe, SATA, USB, and DP), after determining that the user's static configuration scenario is suitable for multi-protocol combination, it is necessary to further extract the key information of each protocol. For example, if it is a combination of PCIe and SATA, the key information such as the speed of each protocol (e.g., PCIe Gen1 to Gen5, SATA Gen1 to Gen3), main phase-locked loop frequency, reference clock frequency, and cascaded division factor needs to be parsed and processed. For PCIe and USB combinations, the system analyzes and extracts key information such as the speed of each protocol and the main phase-locked loop (PLL) frequency, and then processes it. For USB and DisplayPort combinations, the system analyzes and extracts key information such as the speed of each protocol and the main PLL frequency, and then processes it. Figure 2 Unlike serial port protocols that use multiple protocol combinations in various application scenarios, if a single protocol type is configured by the user, the highest rate of the interface signal can distinguish which sub-item it is, such as PCIe5 or PCIe3, and perform corresponding processing. This provides a universal verification platform for the fusion and unification of multiple protocol types, supporting the generation of stimulus sequences for single and multiple protocol types, supporting parameterized verification interface components that include and match different protocol types, and supporting parameterized interface signal and control signal handshake timing that includes and matches different protocol types. Furthermore, through the configuration interface and parameterized design, it supports behavioral-level reference models such as register abstraction layer models, including two typical data structures—register data structures and memory data structures—and different attributes such as read / write, read-only, read-clear, and software write-clear. It supports independent configuration and software read / write access for common circuits (circuits reflecting the common characteristics of multiple protocols) and differentiated circuits (circuits reflecting the differentiated characteristics of multiple protocols) among various protocols.

[0038] See Figure 1 and Figure 2In one possible implementation, the serial port protocol associated with the design under test (DUT) is the SerDes protocol, and the DUT is one or more SerDes physical layer intellectual property (PHY) cores conforming to the SerDes protocol. This satisfies the highest speed and bandwidth requirements of various high-speed SerDes serial interfaces, matches the need for continuous parallel iteration and evolution of different types of SerDes protocols, supports a rich variety of product forms and diverse application scenarios for multi-protocol SerDes PHY IP cores, adapts to newly emerging protocol types or versions, helps reduce the overall project design, development, and verification costs and time, facilitates matching with various continuously updated and evolving high-speed serial SerDes protocols, and is beneficial for meeting the rapid iteration and verification needs of high-speed SerDes PHY IP products.

[0039] In one possible implementation, the high-speed serial interface multi-protocol type physical interface proxy component is used to generate the multi-protocol type excitation sequence transmitted through the multi-protocol type physical interface, and the unified type serial interface proxy component is used to generate the multi-protocol type excitation sequence transmitted through the unified type serial interface. Furthermore, the interface layer includes a physical interface transmit-side sampler for sampling the excitation sequence transmitted through the multi-protocol type physical interface itself and a physical interface receive-side sampler for sampling the excitation sequence received by the multi-protocol type physical interface and transmitted through the unified type serial interface. The interface layer also includes a serial interface transmit-side sampler for sampling the excitation sequence transmitted through the unified type serial interface itself and a serial interface receive-side sampler for sampling the excitation sequence received by the unified type serial interface and transmitted through the multi-protocol type physical interface. Thus, by supporting multi-protocol coexistence and integration, diverse application scenario requirements can be met, providing flexible and rich user-customizable protocol type combination options. Furthermore, by utilizing the optimized layered structure and corresponding core components described above, power consumption, performance, and area metrics can be improved from the top-level architecture. Employing a design philosophy that integrates versatility, parameterization, and multiple protocol types, it goes beyond simple modularization and fine-grained decomposition. Instead, it incorporates a circuit design flow that supports multiple protocol types for Serdes PHY IP. This allows for differentiation between single-protocol and multi-protocol combinations based on the user's static configuration scenario. Further subdivision and extraction of key information are then possible, followed by the execution of corresponding processing flows. This achieves a unified and universal verification platform that integrates multiple protocol types.

[0040] In one possible implementation, the transaction layer further includes a physical interface receive-side automatic verifier for automatically verifying the stimulus sequence sampled by the physical interface receive-side sampler of the interface layer and transmitted through the unified type serial interface, received by the multi-protocol type physical interface; and a serial interface transmit-side automatic verifier for automatically verifying the stimulus sequence sampled by the serial interface transmit-side sampler of the interface layer and transmitted through the unified type serial interface itself. This adopts a top-down modular and parameterized design, considering the needs of multiple protocol types, including constructing stimulus sequences for different protocol types, providing register modeling and verification methods for different protocol types. In terms of architecture design, it supports various single protocol types, as well as pairwise combinations of multiple protocols, such as PCIe plus SATA, PCIe plus USB, and USB plus DP, which helps to provide inclusiveness and flexibility while considering power consumption / performance / area metrics.

[0041] In one possible implementation, the interface layer includes a driver component for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component. Furthermore, the driver component, the physical interface transmit-side sampler, the physical interface receive-side sampler, the serial interface transmit-side sampler, and the serial interface receive-side sampler included in the interface layer can be used for bottom-to-top-level integration and physical layer multiplexing within a system-on-a-chip. This provides a unified design and verification platform that supports the coexistence and integration of multiple protocol types and utilizes multi-protocol physical layer intellectual property cores for design and verification. Based on modular, parameterized, and multi-protocol harmonious coexistence design principles and top-level architecture circuit design methods, it can call upon a rich underlying library of general verification methodologies. It provides easily user-expandable verification interface components and a wide variety of stimulus sequences, possessing key characteristics and advantages such as matching multi-protocol type kernels, general design, and flexible parameterized combination.

[0042] In one possible implementation, the serial port protocol associated with the design under test (DUT) belongs to the SerDes protocol set, which includes various versions of the High-Speed ​​Serial Peripheral Interconnect Bus protocol, various versions of the Serial Hard Disk Interface Advanced Specification protocol, various versions of the Universal Serial Bus protocol, various versions of the Display Interface protocol, various versions of the Ethernet protocol, and various versions of the High-Speed ​​Serial Interface Protocol for Data Converters and Logic Devices. Thus, based on a single protocol type and combinations of two protocol types, key information such as the corresponding protocol rate and phase-locked loop frequency is analyzed, and corresponding processing is performed according to the highest rate and protocol type of the interface signal. A unified universal verification platform for the fusion of corresponding multi-protocol types is provided, supporting the generation of excitation sequences for single and multiple protocol types, supporting parameterized verification interface components that include and match different protocol types, and supporting parameterized interface signal and control signal handshake timing that includes and matches different protocol types.

[0043] In one possible implementation, when the serial port protocol associated with the design under test (DUT) is a single protocol, the serial port protocol associated with the DUT is any one of the SerDes protocol sets. Furthermore, when the serial port protocol associated with the DUT is a combination of multiple protocols, the combination of the first and second serial port protocols is a combination of PCIe and SATA protocols, a combination of PCIe and USB protocols, or a combination of USB and DP protocols. Thus, a universal verification platform that integrates and unifies multiple protocol types is provided, supporting the generation of stimulus sequences for single and multiple protocol types, supporting parameterized verification interface components that include and match different protocol types, and supporting parameterized interface signal and control signal handshake timing that includes and matches different protocol types.

[0044] In one possible implementation, the signal layer further includes an assertion checker for the multi-protocol type physical interface. The assertion checker is associated with the top-level physical interface of the design under test via a binding method to perform timing-level assertion verification. The protocol conformance verification for the multi-protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol includes the timing-level assertion verification. Thus, combining the assertion checker with timing-level assertion verification facilitates protocol conformance verification.

[0045] In one possible implementation, the layered structure of the verification platform includes the transaction layer, the interface layer, and the signal layer. This layered structure is determined based on functional distinctions. The transaction layer represents the communication environment of the design under test (DUT), the interface layer represents the behavioral-level description of functional modules, and the signal layer represents the transmission of commands and data during the communication process of the DUT. Taking PCIe5 or other PCIe protocols as examples, the layered structure of the PCIe5 protocol includes the application layer, the transaction layer, the data link layer, and the physical layer. Taking the JESD protocol, a high-speed serial interface protocol for data converters and logic devices, as an example, the JESD protocol's layered structure includes the application layer, transport layer, data link layer, and physical layer, thus differing from the layered structure of the PCIe protocol (application layer, transaction layer, data link layer, physical layer). Furthermore, different high-speed serial port protocols have been optimized in terms of protocol structure design and data format for different application scenarios. For example, the Display Interface Protocol (DP) is a standardized digital video interface standard, a high-speed serial interface standard specifically designed for digital video and audio transmission. To ensure compatibility with various high-speed serial port protocols, adapt to new protocol types and versions, and implement a top-down optimization approach, a transaction layer, interface layer, and signal layer are used as three functionally independent interface layers, each with optimized parametric, modular, and polymorphic designs. Thus, by providing an optimized layered structure and modular core components, reference functions are differentiated, allowing for planning based on environmental requirements, functional module operation, and command and data transmission. This facilitates object-oriented scalability and support for multiple modes and polymorphism. Specifically, transaction layer 101 is used to generate stimulus sequences for a single protocol type and stimulus sequences for multiple protocol types.

[0046] In one possible implementation, the transaction layer further includes a behavioral reference model that supports a physical layer register abstraction layer model. This physical layer register abstraction layer model includes register data structures and memory data structures. The behavioral reference model is used to independently configure and perform software read / write access operations on common circuits and differentiated circuits across multiple protocols. Thus, through a configuration interface and parameterized design, the behavioral reference model can support register abstraction layer models, for example, including two typical data structures—register data structures and memory data structures—and different attributes such as read / write, read-only, read-clear, and software write-clear. Independent configuration and software read / write access are supported for common circuits (circuits reflecting common characteristics across multiple protocols) and differentiated circuits (circuits reflecting differentiated characteristics across multiple protocols).

[0047] In one possible implementation, the multi-protocol common circuit is the intersection of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol. Furthermore, the multi-protocol differentiated circuit is the union of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol minus the intersection of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol. Thus, based on the aforementioned unified components of polymorphic, parameterized, and modular design and verification, and utilizing a behavioral reference model, the circuit design for SerDes PHY IP integrating multiple protocol types (such as PCIe, SATA, USB, and DP) can be better realized. After determining that the user's static configuration scenario is suitable for multi-protocol combination, the key information of each protocol is further extracted, and independent configuration and access operations are performed. This improves reusability and caters to the needs of different protocol types and application scenarios.

[0048] In one possible implementation, when the serial port protocol associated with the design under test is a combination of multiple protocols, and the combination of the first and second serial port protocols is a combination of PCIe 3.0 and USB 3.0 protocols, the common circuitry of the multiple protocols includes an encoding / decoding circuit, a clock generation circuit, and a phase-locked loop circuit, while the differentiated circuitry of the multiple protocols includes a periodic low-frequency signal detection circuit and a low-power management circuit. Here, the combination of the PCIe 3.0 protocol and the USB 3.0 protocol can be applied to application scenarios such as high-performance computing. In high-performance computing applications, the PCIe 3 interface serves as a control plane for issuing input / output read / write commands from the host computer system level. The USB 3 interface serves as a power and power management plane, providing system-level 1.8 volt or 3.3 volt power supply, and offering different levels of low-power management and differentiated strategies for U1 / U2 / U3. Therefore, when the serial port protocol associated with the design under test is a combination of multiple protocols, and the combination of the first and second serial port protocols is a combination of PCIe 3.0 and USB 3.0 protocols, the common circuitry for the multiple protocols may include, for example, encoding / decoding circuitry. For instance, PCIe Gen1 to Gen2 (2.5G / 5Gbps) and USB Gen1 (5Gbps) share the same 8b / 10b encoding / decoding circuitry. As another example, PCIe Gen3 (8Gbps) and USB3 Gen2 (10Gbps) share the same 128b / 130b (PCIe3) and 128b / 132b (USB3) encoding / decoding circuitry. Here, the subtle difference lies only in the fact that PCIe3 uses a 2-bit synchronization header format, while USB3 uses a 4-bit synchronization header format; therefore, PCIe3 and USB3 correspond to 130b and 132b encoding overheads, respectively. Additionally, the common circuitry for the multiple protocols may include clock generation circuitry and phase-locked loop (PLL) circuitry. For example, 2) PCIe Gen1 to Gen2 and USB3 Gen1 have similar speeds, so one set of phase-locked loop (PLL) circuits can be reused, while PCIe Gen3 and USB3 Gen2 have similar speeds, so another set of PLL circuits can be reused. Correspondingly, the multi-protocol differentiation circuit includes a periodic low-frequency signal detection circuit. Here, different periodic low-frequency signal detection mechanisms and circuits are used. The PCIe protocol uses a beacon interface signal as the periodic low-frequency signal, while the USB protocol uses a Low Frequency Period Signal (LFPS) interface signal as the periodic low-frequency signal; their frequency ranges and detection circuits differ. Additionally, the multi-protocol differentiation circuit includes a low-power management circuit. Here, low-power management is based on differentiation.The PCIe protocol distinguishes different low-power levels and provides fine-grained management based on P0 / P0s / P1 / P2, while the USB protocol distinguishes low-power levels and provides fine-grained management based on U0 / U1 / U2 / U3. While they share similarities in the granularity of these levels, they differ in the strategies for enabling or disabling specific low-power circuit units. Therefore, for the combination of PCIe 3.0 and USB 3.0 protocols, a top-down modular and parameterized design considers the needs of multiple protocol types, including constructing stimulus sequences for different protocol types and providing register modeling and verification methods for different protocol types.

[0049] In some embodiments, the verification platform utilizes the transaction layer to simulate a control plane based on the PCIe 3.0 protocol for issuing input / output read / write commands, and to simulate a power and power management plane based on the USB 3.0 protocol for providing system-level power supply and low-power management settings. This supports independent configuration and software read / write access to common circuits (circuits reflecting common characteristics across multiple protocols) and differentiated circuits (circuits reflecting differentiated characteristics across multiple protocols) across various protocols. This verification platform better supports verification requirements using a combination of PCIe 3.0 and USB 3.0 protocols in application scenarios such as high-performance computing.

[0050] In one possible implementation, when the serial port protocol associated with the design under test is a combination of multiple protocols, and the combination of the first and second serial port protocols is a combination of PCIe 5.0 and SATA protocols, the common circuitry of the multiple protocols includes low-speed encoding / decoding circuitry, low-power management circuitry, and physical layer calibration and adaptation circuitry. The differentiated circuitry of the multiple protocols includes high-speed encoding / decoding circuitry, high-speed receive-side channel margin circuitry, and high-speed transmit-side equalization circuitry. Here, the combination of PCIe 5.0 and SATA protocols can be applied to application scenarios such as solid-state storage. In solid-state storage application scenarios, the PCIe 5 interface serves as the control plane, used by the application layer to issue high-speed, high-performance, and low-latency memory read / write commands. SATA serves as the storage plane, used by the physical layer to initiate medium / low-speed data access and transfer operations on storage media such as solid-state drives or hard disk drives. Therefore, when the serial port protocol associated with the design under test is a combination of multiple protocols, and the combination of the first and second serial port protocols is a combination of PCIe 5.0 and SATA protocols, the common circuitry of the multiple protocols includes low-speed encoding / decoding circuitry. Here, for medium / low-speed bus transmission rates, the encoding / decoding methods and modules are shared. PCIe Gen1 to Gen2 (2.5G / 5Gbps) and SATA Gen1 to Gen3 (1.5G / 3G / 6Gbps) share the same 8b / 10b encoding / decoding circuitry. The common circuitry of the multiple protocols includes low-power management circuitry. Here, differentiated, different levels of fine-grained low-power management are shared. PCIe 5 and SATA can reuse low-power management codes and corresponding low-power circuitry as a whole. For example: P0 (normal operation) and differentiated low-power management (P0s / P1 / P2), etc. The multi-protocol common circuitry includes physical layer calibration and adaptive circuitry. Here, coarse-grained and coarse-tuning circuitry is activated based on low data rates, while fine-grained and fine-tuning circuitry is selectively activated based on medium / high data rates. Conversely, the multi-protocol differentiation circuitry includes high-speed codec circuitry. Here, different encoding / decoding methods and modules are used for different high-speed bus transmission rates. For example, PCIe Gen3 to Gen5 (8G / 16G / 32Gbps) uses 128b / 130b codec circuitry, while SATA does not support 128b / 130b codec circuitry. The multi-protocol differentiation circuitry includes high-speed receiver-side channel margin circuitry. Here, PCIe Gen4 and above rates support receiver margin features (Rx Margin Feature) and circuitry in the receiver direction, iteratively measuring the left / right lateral timing boundaries and the upper / lower vertical voltage amplitude boundaries of the eye diagram through hardware circuitry, while SATA does not support receiver margin circuitry. The multi-protocol differentiation circuitry includes a high-speed transmit-side equalization circuit. Here, PCIe5 high-speed transmission supports transmit-direction equalization circuitry and preset index configurations for different voltage amplitude levels and channel insertion losses. SATA, however, does not support equalization circuitry.Thus, for the combination of PCIe 5.0 and SATA protocols, a top-down modular and parameterized design was adopted to consider the requirements of various protocol types, including constructing stimulus sequences for different protocol types, providing register modeling and verification methods for different protocol types.

[0051] In some embodiments, the verification platform utilizes the transaction layer to simulate a control plane based on the PCIe 5.0 protocol for issuing high-speed, low-latency memory read / write commands and a storage plane based on the SATA protocol for initiating physical-level low-to-medium speed hard drive data access and transfer operations. This supports independent configuration and software read / write access for common circuits (circuits reflecting common characteristics across multiple protocols) and differentiated circuits (circuits reflecting differentiated characteristics across multiple protocols) between various protocols. This verification platform better supports verification requirements using a combination of the PCIe 5.0 and SATA protocols in application scenarios such as solid-state storage.

[0052] Figure 3 This is a flowchart illustrating a method for verifying the physical IP of a high-speed serial interface provided in an embodiment of this application. Figure 3 As shown, the verification method includes the following steps.

[0053] Step S301: Determine whether the serial port protocol associated with the design under test is a single protocol or a combination of multiple protocols.

[0054] Step S303: When the serial port protocol associated with the design under test is a single protocol, parse the highest rate of the interface signal of the design under test, generate an excitation sequence of the single protocol type, thereby initiating protocol conformance verification of the single protocol type corresponding to the serial port protocol associated with the design under test, so as to be used for the design of the functional characteristics, performance design and protocol specification compliance of the design under test.

[0055] Step S305: When the serial port protocol associated with the design under test is a combination of multiple protocols, determine that the serial port protocol associated with the design under test is a combination of the first serial port protocol and the second serial port protocol. Then, parse the key parameters of the first serial port protocol and the second serial port protocol respectively, generate the multi-protocol type excitation sequence, and start the protocol consistency verification of the multi-protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol, wherein the first serial port protocol is different from the second serial port protocol.

[0056] See Figure 3Both the single-protocol type stimulus sequence and the multi-protocol type stimulus sequence are generated by the transaction layer of the verification platform. The transaction layer includes a high-speed serial interface multi-protocol type physical interface proxy component and a unified type serial interface proxy component. The verification platform also includes an interface layer for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component. The verification platform also includes a signal layer for providing multi-protocol type physical interfaces and unified type serial interfaces for interfacing with the design under test. The interface layer is also used to sample the stimulus sequences sent through the multi-protocol type physical interface itself and received by the multi-protocol type physical interface from the unified type serial interface.

[0057] Figure 3 The verification method for high-speed serial interface physical IP presented here provides a unified design and verification platform that supports the coexistence and integration of multiple protocol types and utilizes multi-protocol physical layer intellectual property cores for design and verification. Based on modular, parameterized, and multi-protocol harmonious coexistence design principles and top-level architecture circuit design methods, it can call upon a rich underlying library of general verification methodologies. It provides easily user-expandable verification interface components and a wide variety of stimulus sequences, possessing key characteristics and advantages such as matching multi-protocol type kernels, general design, and flexible parameterized combinations. Furthermore, based on a unified design and verification platform that simultaneously supports single and multiple protocol types, it effectively reduces the manpower costs of circuit design and verification for various protocol types during project development, significantly shortens the functional and performance verification cycle of physical layer intellectual property cores (PHY IP), and significantly improves the full-stack, full-domain R&D efficiency for architecture design, circuit development, and full functional / performance verification for different protocol types (multiple single protocols coexisting or multiple protocol combinations). It also enhances the reusability of the design and verification platform across different protocols, providing an excellent paradigm for unified design and verification with extremely high platform standards.

[0058] See Figure 3In one possible implementation, the serial port protocol associated with the design under test (DUT) is the SerDes protocol, and the DUT is one or more SerDes physical layer intellectual property (PHY) cores conforming to the SerDes protocol. This satisfies the highest speed and bandwidth requirements of various high-speed SerDes serial interfaces, matches the need for continuous parallel iteration and evolution of different types of SerDes protocols, supports a rich variety of product forms and diverse application scenarios for multi-protocol SerDes PHY IP cores, adapts to newly emerging protocol types or versions, helps reduce the overall project design, development, and verification costs and time, facilitates matching with various continuously updated and evolving high-speed serial SerDes protocols, and is beneficial for meeting the rapid iteration and verification needs of high-speed SerDes PHY IP products.

[0059] In one possible implementation, the layered structure of the verification platform includes the transaction layer, the interface layer, and the signal layer. This layered structure is determined based on functional differentiation. The transaction layer represents the communication environment of the design under test (DUT), the interface layer represents the behavioral description of functional modules, and the signal layer represents the transmission of commands and data during the communication process of the DUT. To ensure compatibility with various high-speed serial port protocols, adapt to new protocol types and versions, and implement a top-down optimization approach, the transaction layer, interface layer, and signal layer are used as three functionally independent interface layers, each with parameterized, modular, and polymorphic optimized designs. Thus, by providing an optimized layered structure and modular core components, reference functions are differentiated, allowing for planning from aspects such as environmental requirement representation, functional module operation, and command and data transmission. This contributes to providing object-oriented scalability and support for multiple modes and polymorphism. Specifically, the transaction layer 101 is used to generate stimulus sequences for a single protocol type and stimulus sequences for multiple protocol types.

[0060] Figure 4This is a schematic diagram of a computing device 400 provided in an embodiment of this application. The computing device 400 includes one or more processors 410, a communication interface 420, and a memory 430. The processors 410, communication interface 420, and memory 430 are interconnected via a bus 440. Optionally, the computing device 400 may further include an input / output interface 450, which is connected to input / output devices for receiving user-set parameters, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment described above in this application; the processor 410 can also be used to implement some or all of the operation steps of the method embodiment described above in this application. For example, the specific implementation of various operations performed by the computing device 400 can be referred to the specific details in the above embodiments, such as the processor 410 being used to execute some or all of the steps or operations in the above method embodiments. For example, in the embodiments of this application, the computing device 400 can be used to implement some or all of the functions of one or more components in the above-described device embodiments. In addition, the communication interface 420 can be used specifically for communication functions necessary to implement the functions of these devices and components, and the processor 410 can be used specifically for processing functions necessary to implement the functions of these devices and components.

[0061] It should be understood that, Figure 4 The computing device 400 may include one or more processors 410, and the multiple processors 410 may collaboratively provide processing power in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or an arbitrary connection mode; or the multiple processors 410 may form a processor sequence or a processor array; or the multiple processors 410 may be divided into a main processor and an auxiliary processor; or the multiple processors 410 may have different architectures, such as adopting a heterogeneous computing architecture. Furthermore, Figure 4 The structural and functional descriptions of the computing device 400 shown are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include... Figure 4 The diagram shows more or fewer components, or combinations of some components, or splitting of some components, or different arrangements of components.

[0062] The processor 410 can have various specific implementations. For example, it can include one or more combinations of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or a data processing unit (DPU). This application embodiment does not impose specific limitations. The processor 410 can also be a single-core or multi-core processor. The processor 410 can be a combination of a CPU and hardware chips. The aforementioned hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs can be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. The processor 410 can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs). The communication interface 420 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0063] Memory 430 may be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 430 may also be volatile memory, which may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 430 can also be used to store program code and data, so that the processor 410 can call the program code stored in the memory 430 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Furthermore, the computing device 400 may include, compared to... Figure 4 The number of components displayed may be more or less, or there may be different component configurations.

[0064] Bus 440 can be a Peripheral Component Interconnect Express (PCIe) bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. Bus 440 can be divided into address bus, data bus, control bus, etc. In addition to the data bus, bus 440 can also include a power bus, control bus, and status signal bus. However, for clarity, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0065] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computing devices, the structure of each computing device of which can refer to the structure of the computing devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0066] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0067] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless network communication, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0068] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0069] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A verification platform for a high-speed serial interface physical IP, characterized in that, The verification platform includes: The transaction layer is used to generate stimulus sequences of a single protocol type and stimulus sequences of multiple protocol types. The transaction layer includes a high-speed serial interface multi-protocol type physical interface proxy component and a unified type serial interface proxy component. An interface layer is used to drive the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component, to sample the excitation sequences sent by the multi-protocol type physical interface itself and received by the multi-protocol type physical interface and sent by the unified type serial interface, and to sample the excitation sequences sent by the unified type serial interface itself and received by the unified type serial interface and sent by the multi-protocol type physical interface. The signal layer is used to provide the multi-protocol physical interface and the unified type serial interface for interfacing with the design under test. The serial port protocol associated with the design under test is either a single protocol or a combination of multiple protocols. When the serial port protocol associated with the design under test (DUT) is a single protocol, the verification platform parses the highest rate of the interface signal of the DUT, generates an excitation sequence for the single protocol type, and thus initiates protocol conformance verification for the single protocol type corresponding to the serial port protocol associated with the DUT. When the serial port protocol associated with the design under test is a combination of multiple protocols, the verification platform determines that the serial port protocol associated with the design under test is a combination of a first serial port protocol and a second serial port protocol. Then, it parses the key parameters of the first serial port protocol and the second serial port protocol respectively, generates the excitation sequence of the multi-protocol type, and thus starts the protocol consistency verification of the multi-protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol, wherein the first serial port protocol is different from the second serial port protocol.

2. The verification platform of claim 1, wherein, The serial port protocol associated with the design under test is the SerDes protocol, and the design under test is one or more SerDes physical layer intellectual property cores that conform to the SerDes protocol.

3. The verification platform of claim 2, wherein, The high-speed serial interface multi-protocol type physical interface proxy component is used to generate the multi-protocol type excitation sequence transmitted through the multi-protocol type physical interface. The unified type serial interface proxy component is used to generate the multi-protocol type excitation sequence transmitted through the unified type serial interface. Furthermore, the interface layer includes a physical interface transmitting-side sampler for sampling the excitation sequence transmitted through the multi-protocol type physical interface itself and a physical interface receiving-side sampler for sampling the excitation sequence received by the multi-protocol type physical interface and transmitted through the unified type serial interface. The interface layer also includes a serial interface transmitting-side sampler for sampling the excitation sequence transmitted through the unified type serial interface itself and a serial interface receiving-side sampler for sampling the excitation sequence received by the unified type serial interface and transmitted through the multi-protocol type physical interface.

4. The verification platform of claim 3, wherein, The transaction layer further includes a physical interface receiver-side automatic verifier for automatically verifying the excitation sequence sampled by the physical interface receiver-side sampler of the interface layer and sent through the unified type serial interface by the multi-protocol type physical interface, and a serial interface transmitter-side automatic verifier for automatically verifying the excitation sequence sampled by the serial interface transmitter-side sampler of the interface layer and sent through the unified type serial interface itself.

5. The verification platform according to claim 4, characterized in that, The interface layer includes a driver component for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component. Furthermore, the driver component, the physical interface transmit-side sampler, the physical interface receive-side sampler, the serial interface transmit-side sampler, and the serial interface receive-side sampler included in the interface layer can be used for bottom-to-top integration of system-on-a-chip and physical layer multiplexing.

6. The verification platform according to claim 2, characterized in that, The serial port protocol associated with the design under test belongs to the SerDes protocol set, which includes various versions of the High-Speed ​​Serial Peripheral Interconnect Bus protocol, various versions of the Advanced Specification for Serial Hard Disk Interface protocol, various versions of the Universal Serial Bus protocol, various versions of the Display Interface protocol, various versions of the Ethernet protocol, and various versions of the High-Speed ​​Serial Interface Protocol for Data Converters and Logic Devices.

7. The verification platform according to claim 6, characterized in that, When the serial port protocol associated with the design under test is a single protocol, the serial port protocol associated with the design under test is any one of the SerDes protocol sets. When the serial port protocol associated with the design under test is a combination of multiple protocols, the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe protocol and SATA protocol, a combination of PCIe protocol and USB protocol, or a combination of USB protocol and DP protocol.

8. The verification platform according to claim 2, characterized in that, The signal layer also includes an assertion checker for the multi-protocol type physical interface. The assertion checker is associated with the top-level physical interface of the design under test through a binding method to perform timing-level assertion verification. The protocol consistency verification of the multi-protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol includes the timing-level assertion verification.

9. The verification platform according to claim 2, characterized in that, The layered structure of the verification platform includes the transaction layer, the interface layer, and the signal layer. The layered structure of the verification platform is determined based on functional differentiation. The transaction layer represents the communication environment of the design under test, the interface layer represents the behavioral-level description of the functional modules, and the signal layer represents the transmission of commands and data in the communication process of the design under test.

10. The verification platform according to claim 9, characterized in that, The transaction layer also includes a behavior-level reference model, which supports a physical layer register abstraction layer model. The physical layer register abstraction layer model includes register data structures and memory data structures. The behavior-level reference model is used to perform independent configuration and software read / write access operations on multi-protocol common circuits and multi-protocol differentiated circuits respectively.

11. The verification platform according to claim 10, characterized in that, The multi-protocol common circuit is the intersection of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol, and the multi-protocol differentiated circuit is the union of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol minus the intersection of the circuit associated with the first serial port protocol and the circuit associated with the second serial port protocol.

12. The verification platform according to claim 10, characterized in that, When the serial port protocol associated with the design under test is a combination of multiple protocols and the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe 3.0 protocol and USB 3.0 protocol, the common circuit of the multiple protocols includes an encoding and decoding circuit, a clock generation circuit and a phase-locked loop circuit, and the differentiated circuit of the multiple protocols includes a periodic low-frequency signal detection circuit and a low-power management circuit.

13. The verification platform according to claim 12, characterized in that, The verification platform utilizes the transaction layer to simulate a control plane based on the PCIe 3.0 protocol for issuing input / output read / write commands, and to simulate a power and energy management plane based on the USB 3.0 protocol for providing system-level power supply and low-power management settings.

14. The verification platform according to claim 10, characterized in that, When the serial port protocol associated with the design under test is a combination of multiple protocols and the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe 5.0 protocol and SATA protocol, the common circuit of the multiple protocols includes a low-speed codec circuit, a low-power management circuit and a physical layer calibration and adaptation circuit, and the differentiated circuit of the multiple protocols includes a high-speed codec circuit, a high-speed receiver-side channel margin circuit and a high-speed transmitter-side equalization circuit.

15. The verification platform according to claim 14, characterized in that, The verification platform uses the transaction layer to simulate the control plane based on the PCIe 5.0 protocol for issuing high-speed, low-latency memory read and write commands, and to simulate the storage plane based on the SATA protocol for initiating physical-level hard drive low-to-medium speed data access and transfer operations.

16. A method for verifying the physical IP of a high-speed serial interface, characterized in that, The verification method includes: Determine whether the serial port protocol associated with the design under test is a single protocol or a combination of multiple protocols; When the serial port protocol associated with the design under test is a single protocol, the highest rate of the interface signal of the design under test is parsed to generate an excitation sequence of the single protocol type, thereby initiating protocol conformance verification of the single protocol type corresponding to the serial port protocol associated with the design under test, so as to be used for the design of the functional characteristics, performance design and protocol specification compliance of the design under test. When the serial port protocol associated with the design under test (DUT) is a combination of multiple protocols, it is determined that the serial port protocol associated with the DUT is a combination of a first serial port protocol and a second serial port protocol. Then, the key parameters of the first serial port protocol and the second serial port protocol are parsed respectively to generate a multi-protocol type stimulus sequence, thereby initiating a protocol consistency verification of the multi-protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol, where the first serial port protocol is different from the second serial port protocol. The single-protocol type stimulus sequence and the multi-protocol type stimulus sequence are both generated by the transaction layer of the verification platform. The transaction layer includes a high-speed serial interface multi-protocol type physical interface proxy component and a unified type serial interface proxy component. The verification platform also includes an interface layer for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component. The verification platform also includes a signal layer for providing multi-protocol type physical interfaces and unified type serial interfaces for interfacing with the design under test. The interface layer is also used to sample the stimulus sequences sent through the multi-protocol type physical interface itself and received by the multi-protocol type physical interface from the unified type serial interface.

17. The verification method according to claim 16, characterized in that, The serial port protocol associated with the design under test is the SerDes protocol, and the design under test is one or more SerDes physical layer intellectual property cores that conform to the SerDes protocol.

18. The verification method according to claim 17, characterized in that, The layered structure of the verification platform includes the transaction layer, the interface layer, and the signal layer. The layered structure of the verification platform is determined based on functional differentiation. The transaction layer represents the communication environment of the design under test, the interface layer represents the behavioral-level description of the functional modules, and the signal layer represents the transmission of commands and data in the communication process of the design under test.

19. An electronic device, characterized in that, The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method according to any one of claims 16 to 18.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer device, cause the computer device to perform the method according to any one of claims 16 to 18.

Images