Pixel driving circuit of display panel and display panel

Abstract

The invention discloses a pixel driving circuit of a display panel and the display panel, the pixel driving circuit is provided with a first pixel driving circuit in an open hole display area, and the pixel driving circuit comprises a data write-in module, a storage module, a reset module, a first driving transistor, a light emitting control module, a light emitting unit and a compensation module; the control end of the first driving transistor is connected to a first node, the input end of the first driving transistor is connected to a second node, and the output end of the first driving transistor is connected to a third node; one end of the light-emitting unit is connected with the fourth node, the compensation module is connected with the first node and / or the fourth node and used for providing a compensation signal for the first node and / or the fourth node, and the compensation signal is used for compensating insufficient data writing caused by uneven impedance of the scanning line or the data line. According to the display panel, the pixel driving circuit of the perforated display area of the display panel is subjected to compensation design, so that the phenomena of display screen splitting, uneven brightness and the like of the perforated display area and the non-perforated display area are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a pixel driving circuit and a display panel. Background Technology

[0002] OLED (Organic Light-Emitting Diode) devices, with their advantages of self-illumination, low power consumption, and the absence of a liquid crystal flow layer, are gradually replacing LCD panels, especially in mobile display devices such as smartphones, where they completely drive LCD panels. Furthermore, with the rapid development of mobile display devices, users have increasingly higher demands for screen-to-body ratio. Taking smartphones as an example, functional components such as cameras, sensors, or earpieces need to be placed on the display panel, and these components will affect the screen-to-body ratio. To address this, in order to achieve a full-screen display, a perforated area is typically created within the display area of ​​the panel, and the camera, sensor, or earpiece is placed below this perforated area, thus achieving a full-screen display.

[0003] For the pixel driving circuit in the OLED display panel, due to the setting of the aperture area, the scan lines or data lines connected to the pixel driving circuit need to be wound in the aperture area. This causes the pixels connected to the scan lines or data lines to have differences in capacitance and resistance with the pixels in the normal area, resulting in brightness differences in the display area corresponding to the scan lines or data lines, such as uneven display and screen splitting. Summary of the Invention

[0004] The purpose of this application is to provide a pixel driving circuit and a display panel, which improves the phenomenon of screen splitting and uneven brightness between the open-hole display area and the non-open-hole display area by using a compensation design for the pixel driving circuit of the open-hole display area of ​​the display panel.

[0005] This application discloses a pixel driving circuit for a display panel. The display panel includes an open-hole display area and a non-open-hole display area. The pixel driving circuit has a first pixel driving circuit disposed in the open-hole display area. The first pixel driving circuit includes a data writing module, a storage module, a reset module, a first driving transistor, a light-emitting control module, a light-emitting unit, and a compensation module. The control terminal of the first driving transistor is connected to a first node, the input terminal of the first driving transistor is connected to a second node, and the output terminal of the first driving transistor is connected to a third node. One end of the light-emitting unit is connected to a fourth node, and the other end of the light-emitting unit is connected to a ground signal terminal. The reset module is used to reset the first node, the second node, and the third node. The potentials of the first node and the fourth node; the storage module is connected to the first node and the fourth node respectively; the light emission control module is connected to the second node, the third node and the fourth node respectively, and is used to input a power signal from the second node and electrically connect the third node and the fourth node under the control of the light emission control signal; the data writing module is connected to the third node and is used to acquire a data signal from the data line under the control of the scan line; the compensation module is connected to the first node and / or the fourth node and is used to provide a compensation signal for the first node and / or the fourth node, the compensation signal being used to compensate for insufficient data writing caused by the uneven impedance of the scan line or the data line.

[0006] Optionally, the display panel includes multiple first scan lines and multiple second scan lines, and the open-hole display area includes a first open-hole display area; the first scan lines are disposed in the first open-hole display area, and the second scan lines are disposed in the non-open-hole display area; an open-hole area is disposed within the first open-hole display area, and the first open-hole display area is located on both sides of the open-hole area along the length direction of the first scan lines; the first scan lines are wound around the open-hole area, and the line resistance of the first scan lines is greater than the line resistance of the second scan lines.

[0007] Optionally, the display panel includes multiple first data lines and multiple second data lines, and the open-hole display area includes a second open-hole display area; the first data lines are disposed in the second open-hole display area, and the second data lines are disposed in the non-open-hole display area; an open-hole area is disposed within the second open-hole display area, and the second open-hole display area is located on both sides of the open-hole area along the length direction of the first data lines; the first data lines are wound around the open-hole area, and the line resistance of the first data lines is greater than that of the second data lines.

[0008] Optionally, the compensation module includes a first compensation circuit, which includes a first compensation signal, a first active switch, and a first compensation control signal; the output terminal of the first active switch is connected to the first node, the first compensation signal is connected to the input terminal of the first active switch, and the first compensation control signal is connected to the control terminal of the first active switch.

[0009] Optionally, the compensation module includes a second compensation circuit, which includes a second compensation signal, a second active switch, and a second compensation control signal; the output terminal of the second active switch is connected to the fourth node, the second compensation signal is connected to the input terminal of the second active switch, and the second compensation control signal is connected to the control terminal of the second active switch.

[0010] Optionally, the compensation module includes a first compensation circuit and a second compensation circuit. The first compensation circuit includes a first compensation signal, a first active switch, and a first compensation control signal. The output terminal of the first active switch is connected to the first node, the first compensation signal is connected to the input terminal of the first active switch, and the first compensation control signal is connected to the control terminal of the first active switch. The second compensation circuit includes a second compensation signal, a second active switch, and a second compensation control signal. The output terminal of the second active switch is connected to the fourth node, the second compensation signal is connected to the input terminal of the second active switch, and the second compensation control signal is connected to the control terminal of the second active switch.

[0011] Optionally, the data writing module includes a third active switch, the control terminal of which is connected to a first scan signal, and the input terminal of which is connected to a data signal; the light emission control module includes a fourth active switch and a fifth active switch, the input terminal of which is connected to the power signal, the control terminal of which is connected to the light emission control signal, and the output terminal of which is connected to the second node; the input terminal of which is connected to the third node, the output terminal of which is connected to the fourth node, and the control terminal of which is connected to the light emission control signal; the reset module includes a sixth active switch and a seventh active switch, the input terminal of which is connected to the second node, the output terminal of which is connected to the first node, and the control terminal of which is connected to a reset control signal; the input terminal of which is connected to the reset signal, the control terminal of which is connected to the reset control signal, and the output terminal of which is connected to the fourth node; the storage module includes a first capacitor, one end of which is connected to the first node, and the other end of which is connected to the second node.

[0012] Optionally, the first pixel driving circuit includes a reset phase, a data writing phase, a compensation phase, and a light emission phase; in the reset phase, the sixth active switch and the seventh active switch are in a conducting state; in the data writing phase, the sixth active switch, the seventh active switch, and the third active switch are in a conducting state; in the compensation phase, the first active switch or the second active switch is in a conducting state; in the light emission phase, the fourth active switch and the fifth active switch are in a conducting state.

[0013] Optionally, the higher the grayscale voltage of the data signal, the higher the voltage of the compensation signal.

[0014] This application also discloses a display panel, including the pixel driving circuit of the above-described display panel, wherein the pixel driving circuit is used to drive the display panel to display.

[0015] This application incorporates a compensation module that inputs a compensation signal into either the first or fourth node of the first pixel driving circuit. This compensation signal adjusts the potential of the first or fourth node, effectively compensating for the brightness difference caused by impedance differences between the scan lines or data lines in the punch-hole display area and the non-punch-hole display area due to the winding configuration of the scan lines or data lines. Through the compensation module, the brightness of the punch-hole display area and the non-punch-hole display area remains consistent at the same grayscale, avoiding issues such as screen splitting and brightness differences between the punch-hole and non-punch-hole display areas, thereby improving the display panel's performance. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the display panel of this application; Figure 2 This is a schematic diagram of the pixel driving circuit of the display panel of this application; Figure 3 This is a schematic diagram of the second type of display panel in this application; Figure 4 This application is Figure 2 Timing diagram of the pixel driving circuit; Figure 5 This is a schematic diagram of the pixel driving circuit of the display panel according to the second embodiment of this application; Figure 6This is a timing diagram of the pixel driving circuit according to the second embodiment of this application; Figure 7 This is a schematic diagram of the pixel driving circuit of the display panel according to the third embodiment of this application; Figure 8 This is a timing diagram of the pixel driving circuit according to the third embodiment of this application.

[0017] Among them, 100 is a display panel; 101 is a display area; 102 is a non-display area; 103 is a perforated display area; 1031 is a first perforated display area; 1032 is a second perforated display area; 104 is a non-perforated display area; 105 is a perforated area; 110 is a first pixel driving circuit; 111 is a data writing module; 112 is a first storage module; 113 is a reset module; 114 is a light-emitting control module; 115 is a light-emitting unit; 120 is a compensation module; 121 is a first compensation circuit; 122 is a second compensation circuit; 130 is a first scan line; 131 is a second scan line; 132 is a first data... Line; 133, Second data line; T1, First active switch; T2, Second active switch; T3, Third active switch; T4, Fourth active switch; T5, Fifth active switch; T6, Sixth active switch; T7, Seventh active switch; DT, First driving transistor; C1, First capacitor; N1, First node; N2, Second node; N3, Third node; N4, Fourth node; GAn, Reset control signal; GBn, First scan signal; Vint, Reset signal; G1, First compensation control signal; G2, Second compensation control signal; Data, Data signal; VDD, Power signal. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature specified as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. Furthermore, terms such as "upper," "lower," "left," "right," "vertical," and "horizontal," indicating orientation or positional relationships, are based on the orientation or relative positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this application, not indicating that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0021] Figure 1 This is a schematic diagram of the display panel of this application; see below. Figure 1 As shown, this application discloses a display panel 100, which includes a display area 101 and a non-display area 102. The non-display area 102 is generally located at the edge of the display panel 100 and surrounds the display area 101. The display panel 100 also includes a perforated display area 103, a perforated area 105, and a non-perforated display area 104 within the display area 101. The perforated area 105 is generally located within the display area 101, such as at the upper left, center, or right side of the display area 101. Generally, the perforated area 105 of the perforated display panel 100 is not used for display. The perforated display area 103 and the non-perforated display area 104 both participate in the display of the display panel 100.

[0022] The display panel 100 generally includes a pixel driving circuit disposed within the display panel 100. Different pixel driving circuits are provided for the hole-punch display area 103 and the non-hole-punch display area 104. Through different pixel driving circuits, the differences in capacitance and resistance between the pixels connected to the scan lines or data lines in the hole-punch display area 103 and the pixels in the normal area are compensated for. This is because the scan lines or data lines are wound, which causes brightness differences in the display area 101 corresponding to the scan lines or data lines, such as uneven display or screen splitting.

[0023] Figure 2 This is a schematic diagram of the pixel driving circuit of the display panel of this application, see [link / reference]. Figures 1 to 2As shown, this application discloses a pixel driving circuit for a display panel 100. Specifically, the display panel 100 is provided with a first pixel driving circuit 110 for the opening display area 103. The first pixel driving circuit 110 includes a data writing module 111, a storage module, a reset module 113, a first driving transistor DT, a light emission control module 114, a light emission unit 115, and a compensation module 120. The control terminal of the first driving transistor DT is connected to the first node N1, the input terminal of the first driving transistor DT is connected to the second node N2, and the output terminal of the first driving transistor DT is connected to the third node N3; one end of the light-emitting unit 115 is connected to the fourth node N4, and the other end of the light-emitting unit 115 is connected to the ground signal terminal; the reset module 113 is used to reset the potentials of the first node N1, the second node N2, and the fourth node N4; the storage module is connected to the first node N1 and the fourth node N4 respectively; the light-emitting control module 114 is connected to the second node N2, the third node N3, and the fourth node N4 respectively, and is used to input the power supply signal VDD from the second node N2 and electrically connect the third node N3 and the fourth node N4 under the control of the light-emitting control signal; the data writing module 111 is connected to the third node N3 and is used to obtain the data signal Data from the data line under the control of the scan line.

[0024] The compensation module 120 is connected to the first node N1 and / or the fourth node N4, and is used to provide a compensation signal for the first node N1 and / or the fourth node N4. The compensation signal is used to compensate for insufficient data writing caused by uneven impedance of the scan line or the data line.

[0025] This application incorporates a compensation module 120, which inputs a compensation signal to either the first node N1 or the fourth node N4 in the first pixel driving circuit 110. This compensation signal adjusts the potential of either node N1 or node N4, effectively compensating for the brightness difference caused by impedance differences between the scan lines or data lines in the punch-hole display area 103 and the non-punch-hole display area 104 due to their winding configuration. Through the compensation function of the compensation module 120, the brightness of the punch-hole display area 103 and the non-punch-hole display area 104 remains consistent at the same grayscale, preventing issues such as screen splitting and brightness differences between the punch-hole display area 103 and the non-punch-hole display area 104, thereby improving the display effect of the display panel 100.

[0026] The compensation signal can be calculated during the testing phase by taking into account the difference between the RC loading of the scan lines or data lines in the punch-hole display area 103 and the non-punch-hole display area 104. This difference is then substituted into the simulation model to determine the potential difference in the actual pixel driving circuit, which serves as the initial value for the compensation signal. Alternatively, brightness testing of the panel can be used to adjust the compensation signal at different grayscale levels, ensuring that the pixel brightness of the punch-hole display area 103 and the non-punch-hole display area 101 remains consistent at the same grayscale.

[0027] Within the aperture display area 103, each pixel driving circuit drives one sub-pixel, i.e., one light-emitting unit 115, to emit light. Specifically, the display panel 100 generally has multiple pixels, and each pixel is provided with at least three sub-pixels of different colors. Different colors are displayed by assigning different gray levels to the sub-pixels of different colors. Typically, one sub-pixel corresponds to one light-emitting unit 115, and the area where the sub-pixel is located is called a sub-pixel area. A pixel driving circuit, such as the first pixel driving circuit 110 mentioned above, is provided in each sub-pixel area of ​​the aperture display area 103.

[0028] See also Figure 1 As shown, the display panel 100 includes multiple first scan lines 130 and multiple second scan lines 131, and the open-hole display area 103 includes a first open-hole display area 1031; the first scan lines 130 are disposed in the first open-hole display area 1031, and the second scan lines 131 are disposed in the non-open-hole display area 104; an open-hole area 105 is disposed within the first open-hole display area 1031, and the first open-hole display area 1031 is located on both sides of the open-hole area 105 along the length direction of the first scan lines 130; the first scan lines 130 are wound around the open-hole area 105, and the line resistance of the first scan lines 130 is greater than the line resistance of the second scan lines 131.

[0029] It is understood that the first opening display area 1031 in this embodiment mainly relates to the situation where the scan lines need to be arranged around the opening area. Specifically, on the orthographic projection of the light-emitting surface of the display panel 100, the first scan line 130 does not overlap with the opening area 105, and this part of the first scan line 130 is arranged around the opening area 105.

[0030] Relatively speaking, when the aperture area 105 is set to the left, center or right, the first aperture display area 1031 has sub-pixel areas on both sides of the aperture area 105 for display. The capacitance and resistance of the scan lines corresponding to these sub-pixel areas are different from the capacitance and resistance of the scan lines corresponding to the sub-pixels of the non-aperture display area 104. That is, at least the line resistance of the first scan line 130 is greater than the line resistance of the second scan line 131, which causes the sub-pixels of the first aperture display area 1031 to be darker.

[0031] Figure 3 This is a schematic diagram of the second type of display panel of this application, see [link / reference]. Figure 3 As shown, the display panel 100 includes multiple first data lines 132 and multiple second data lines 133, and the open-hole display area 103 includes a second open-hole display area 1032; the first data lines 132 are disposed in the second open-hole display area 1032, and the second data lines 133 are disposed in the non-open-hole display area 104; an open-hole area 105 is disposed within the second open-hole display area 1032, and the second open-hole display area 1032 is located on both sides of the open-hole area 105 along the length direction of the first data lines 132; the first data lines 132 are wound around the open-hole area 105, and the line resistance of the first data lines 132 is greater than that of the second data lines 133.

[0032] The length direction of the second opening display area 1032 is perpendicular to the length direction of the first opening display area 1031. On the orthographic projection of the light-emitting surface of the display panel 100, the first data line 132 does not overlap with the opening area 105, and this portion of the first data line 132 is arranged around the opening area 105.

[0033] In this embodiment, the second hole display area 1032 is mainly divided according to the data line routing. The data lines connected to the sub-pixels in the second hole display area 1032 need to be wound at the hole area 105, which causes the line resistance of the first data line 132 and the second data line 133 to be different, resulting in the second hole display area 1032 and the non-hole display area 104 being darker at the same gray level.

[0034] Among them, combined Figures 1 to 3As shown, the first pixel driving circuit 110 provided in this application can be disposed not only in the first aperture display area 1031, but also simultaneously in the first aperture display area 1031 and the second aperture display area 1032. Relatively speaking, compensation for the data line can also be achieved in the second aperture display area 1032 by compensating the entire data line. That is, the first pixel driving circuit 110 of this application can be disposed only in the first aperture display area 1031. However, the compensation method for the entire data line is relatively complex, especially for different grayscale data signals Data, where the complexity is greater, and the problem of uneven wiring impedance is often complicated by the superimposed problem. By using the compensation module 120 to directly compensate the internal structure of the first pixel driving circuit 110 of each sub-pixel area, the aforementioned uneven wiring impedance and uneven winding impedance can be solved.

[0035] It is understandable that the first aperture display area 1031 and the second aperture display area 1032 mentioned above do not overlap with each other, and no sub-pixels are provided at the intersection of the first scan line 130 and the first data line 132, that is, no display is performed in the aperture area 105.

[0036] See also Figure 2 As shown, the compensation module 120 includes a first compensation circuit 121, which includes a first compensation signal, a first active switch T1, and a first compensation control signal G1. The output terminal of the first active switch T1 is connected to the first node N1, the first compensation signal is connected to the input terminal of the first active switch T1, and the first compensation control signal G1 is connected to the control terminal of the first active switch T1.

[0037] In this embodiment, the compensation module 120 mainly compensates for the potential of the first node N1, that is, by transmitting a compensation signal to the first node N1 when the first active switch T1 is in the on state. Its first compensation control signal G1 needs to control the first active switch T1 to be in the on state after the data is written.

[0038] Specifically, the data writing module 111 includes a third active switch T3. The control terminal of the third active switch T3 is connected to a first scan signal GBn, and the input terminal of the third active switch T3 is connected to a data signal Data. When the first pixel driving circuit 110 is located in the first aperture display area 1031, the first scan signal GBn is obtained from the first scan line 130, and the data signal Data is obtained from the second data line 133. When the first pixel driving circuit 110 is located in the second aperture display area 1032, the first scan signal GBn is obtained from the second scan line 131, and the data signal Data is obtained from the first data line 132. It is understood that the terms "first" and "second" used to define the scan line and data line do not limit their structure, but only their position.

[0039] In one specific embodiment, when the first driving transistor DT is a dual-gate driving transistor, the output terminal of the third active switch T3 is also connected to the second gate of the first driving transistor DT. The first gate of the first driving transistor DT is connected to the first node N1.

[0040] In the light emission control module 114, the light emission control module 114 includes a fourth active switch T4 and a fifth active switch T5. The input terminal of the fourth active switch T4 is connected to the power signal VDD, the control terminal of the fourth active switch T4 is connected to the light emission control signal, and the output terminal of the fourth active switch T4 is connected to the second node N2. The input terminal of the fifth active switch T5 is connected to the third node N3, the output terminal of the fifth active switch T5 is connected to the fourth node N4, and the control terminal of the fifth active switch T5 is connected to the light emission control signal.

[0041] The fourth active switch T4 and the fifth active switch T5 can be connected to a single light emission control signal in the same timing sequence, or they can be connected to light emission control signals in a progressively sequential timing sequence. Taking the pixel driving circuit corresponding to the first scan line 130 of the nth row as an example, the fourth active switch T4 is connected to the (n+1)th level light emission control signal, and the fifth active switch T5 is connected to the nth level light emission control signal. In other words, the light emission control signal is also set and scanned line by line, with the fourth active switch T4 connected to the next row's light emission control signal line and the fifth active switch T5 connected to the previous row's light emission control signal line. Of course, it is also possible for the fourth active switch T4 and the fifth active switch T5 to be connected to the same row's light emission control signal line.

[0042] In the reset module 113, the reset module 113 includes a sixth active switch T6 and a seventh active switch T7. The input terminal of the sixth active switch T6 is connected to the second node N2, the output terminal of the sixth active switch T6 is connected to the first node N1, and the control terminal of the sixth active switch T6 is connected to the reset control signal GAn. The input terminal of the seventh active switch T7 is connected to the reset signal Vint, the control terminal of the seventh active switch T7 is connected to the reset control signal GAn, and the output terminal of the seventh active switch T7 is connected to the fourth node N4.

[0043] In the reset module 113, before the data writing module 111 operates, the potential of the first node N1 and the potential of the second node N2 are turned on, resetting the potentials of the first node N1 and the second node N2. Furthermore, the potential of the fourth node N4, which is the anode of the light-emitting unit 115, is reset to prevent inaccurate brightness in the next light emission if the potential of the fourth node N4 is not reset.

[0044] The storage module includes a first capacitor C1, one end of which is connected to the first node N1, and the other end of which is connected to the second node N2.

[0045] In this embodiment, the first active switch T1, the third active switch T3, the fourth active switch T4, the fifth active switch T5, the sixth active switch T6, and the seventh active switch T7 are all N-type thin-film transistors, which are in the on state when the logic level is high and in the off state when the logic level is low.

[0046] This embodiment only uses the above-mentioned 6T1C circuit as an example for illustration, and does not limit the pixel driving circuit of this application to only this circuit design. Other types of pixel driving circuits such as 7T1C and 4T2C are also applicable when the compensation module 120 can be added in this embodiment.

[0047] Figure 4 This application is Figure 2 See the timing diagram of the pixel driving circuit. Figure 4 As shown, GAn is the reset control signal GAn, GBn is the first scan signal GBn, Vint is the reset signal Vint, G1 is the first compensation control signal G1, EMn is the nth level light emission control signal, EMn+1 is the n+1th level light emission control signal, Data is Data, D(n-1) is the data signal Data received by the sub-pixel corresponding to the (n-1)th scan line, Dn is the data signal Data received by the sub-pixel corresponding to the nth scan line, and D(n+1) is the data signal Data received by the sub-pixel corresponding to the n+1th scan line.

[0048] This timing sequence is for the pixel driving circuit corresponding to the first scan line 130 in the nth row. The first pixel driving circuit 110 includes a reset phase, a data writing phase, a compensation phase, and a light emission phase. During the reset phase, when the reset control signal GAn is at a logic high level, the sixth active switch T6 and the seventh active switch T7 are turned on. The first node N1 is connected to the second node N2, and the fourth node N4 is connected to the reset signal Vint, thereby resetting the potentials of the first node N1, the second node N2, and the fourth node N4. During the data writing phase, when the first scan signal GBn is at a high level, the reset control signal GAn is also at a high level. At this time, the sixth active switch T6, the seventh active switch T7, and the third active switch T3 are turned on. The circuit of the third active switch T3, the first driving transistor DT, the sixth active switch T6, the first capacitor C1, and the seventh active switch T7 charges the first circuit, writing the data signal Data into the first capacitor C1. After the data writing is complete, the first scan signal GBn is at a logic low level, the reset control signal GAn is also at a logic low level, and the first compensation control signal G1 is at a logic high level, transmitting the compensation signal to the first node N1 to compensate for the data signal Data stored in the first capacitor C1. Subsequently, under the control of the light emission control signal, the light emission unit 115 is driven to emit light.

[0049] In this embodiment, the compensation module 120 directly compensates for the data at the first node N1 after data writing, thereby compensating for the potential difference of the first node N1 connected to the gate of the first driving transistor DT, and compensating for the brightness of the light-emitting unit 115 of the hole-punch display area 103 during the light-emitting stage. For the pixel driving circuit of the non-hole-punch display area 104, it is as follows... Figure 2 As shown, the pixel driving circuit after removing the first compensation circuit 121 is the pixel driving circuit of the non-aperture display area 104.

[0050] Figure 5 This is a schematic diagram of the pixel driving circuit of the display panel according to the second embodiment of this application. Figure 6 This is a timing diagram of the pixel driving circuit according to the second embodiment of this application. See also... Figures 5 to 6 As shown, the compensation module 120 includes a second compensation circuit 122, which includes a second compensation signal, a second active switch T2, and a second compensation control signal G2. The output terminal of the second active switch T2 is connected to the fourth node N4, the second compensation signal is connected to the input terminal of the second active switch T2, and the second compensation control signal G2 is connected to the control terminal of the second active switch T2.

[0051] See Figure 6As shown, G2 is the second compensation control signal G2. The second compensation control signal G2 starts working after the data is written, that is, after the first scan signal GBn is at a low logic level, that is, the second compensation control signal G2 is at a high logic level, which is the compensation potential of the fourth node N4.

[0052] In this embodiment, the second compensation circuit 122 is used to compensate the voltage at the anode of the fourth node N4, i.e., the light-emitting unit 115. Compared with the previous embodiment, the second compensation circuit 122 in this embodiment is used to compensate the potential at the anode of the light-emitting unit 115. Relatively speaking, compensation from the anode, i.e., adjusting the voltage at the other end of the first capacitor C1, is relatively more complex, but its compensation accuracy is higher.

[0053] In this embodiment, the configuration of the first driving transistor DT, the third active switch T3, the fourth active switch T4, the fifth active switch T5, the sixth active switch T6, and the seventh active switch T7 is the same as in the above embodiment, and will not be repeated here.

[0054] Figure 7 This is a schematic diagram of the pixel driving circuit of the display panel according to the third embodiment of this application. Figure 8 This is a timing diagram of the pixel driving circuit according to the third embodiment of this application. See also... Figures 7 to 8 As shown, based on the first and second embodiments described above, this embodiment can also combine the first compensation circuit 121 and the second compensation circuit 122.

[0055] The compensation module 120 includes a first compensation circuit 121 and a second compensation circuit 122. The first compensation circuit 121 includes a first compensation signal, a first active switch T1, and a first compensation control signal G1. The output terminal of the first active switch T1 is connected to the first node N1, the first compensation signal is connected to the input terminal of the first active switch T1, and the first compensation control signal G1 is connected to the control terminal of the first active switch T1. The second compensation circuit 122 includes a second compensation signal, a second active switch T2, and a second compensation control signal G2. The output terminal of the second active switch T2 is connected to the fourth node N4, the second compensation signal is connected to the input terminal of the second active switch T2, and the second compensation control signal G2 is connected to the control terminal of the second active switch T2.

[0056] In this embodiment, by superimposing the first active switch T1 and the second active switch T2, the compensation circuit can simultaneously compensate for the first node N1 and the fourth node N4. Its first compensation control signal G1 and second compensation control signal G2 can be in a logic high-level state after data is written, thereby sequentially achieving potential compensation for the first node N1 and the fourth node N4.

[0057] In this embodiment, the configuration of the first driving transistor DT, the third active switch T3, the fourth active switch T4, the fifth active switch T5, the sixth active switch T6, and the seventh active switch T7 is the same as in the above embodiment, and will not be repeated here.

[0058] In another embodiment, the first compensation circuit 121 and the second compensation circuit 122 share the first compensation signal and the first compensation control signal G1, and the first active switch T1 in this embodiment adopts a P-type thin film transistor, while the second active switch T2 adopts an N-type thin film transistor.

[0059] The second compensation circuit 122 includes a second active switch T2; the output terminal of the second active switch T2 is connected to the fourth node N4, the first compensation signal is connected to the input terminal of the second active switch T2, and the first compensation control signal G1 is connected to the control terminal of the second active switch T2.

[0060] When the pixel driving circuit is in the compensation stage, the first compensation signal is controlled to be at a logic high level first and then at a logic low level. In the non-compensation stage, the first compensation signal is controlled to be in a floating state, so that the first active switch T1 and the second active switch T2 are kept in the off state, or the first compensation signal is kept in a floating state. At this time, even if the first active switch T1 and the second active switch T2 are in the on state, it will not affect the potential of the first node N1 and the fourth node N4.

[0061] Specifically, when the first compensation control signal G1 is at a logic high level, it compensates for the potential of the fourth node N4; when the first compensation control signal G1 is at a logic low level, it compensates for the potential of the first node N1. In other states, the first compensation control signal G1 is in a floating state.

[0062] It can be understood that the first active switch T1 can employ a dual P-type thin-film transistor to prevent leakage. By using the first active switch T1 in conjunction with the second active switch T2, it can compensate for the poor reset effect of the fourth node N4 during the reset phase, caused by the reset control signal GAn line being set up like a scan line, resulting in incomplete removal of the anode voltage of the light-emitting unit 115 in the previous frame and thus causing brightness differences. Through the coordinated setting of the first active switch T1 and the second active switch T2, the display effect of the punch-hole display area 103 and the non-punch-hole display area 104 is improved without adding additional control signals.

[0063] The compensation signal in this application can be calculated based on simulation and test results of display panels 100 of different types and processes. For greater brightness differences, a larger compensation signal voltage is required. Generally, the higher the potential of the data signal Data, the higher the corresponding grayscale voltage, and the more significant its impedance effect, thus requiring a larger compensation signal potential. In other words, the higher the grayscale voltage of the data signal Data, the higher the voltage of the compensation signal.

[0064] Specifically, the potential of the preset compensation signal can be set by using the key gray level voltage. For example, a compensation signal with a step is set for gray levels 32 and 48 respectively. When the gray level is between 32 and 48, the compensation signal of the corresponding potential is compensated by interpolation.

[0065] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0066] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A pixel driving circuit for a display panel, the display panel comprising a hole-punch display area and a non-hole-punch display area, characterized in that, The pixel driving circuit is provided in the hole display area. The first pixel driving circuit includes a data writing module, a storage module, a reset module, a first driving transistor, a light emission control module, a light emission unit, and a compensation module. The control terminal of the first driving transistor is connected to the first node, the input terminal of the first driving transistor is connected to the second node, and the output terminal of the first driving transistor is connected to the third node. One end of the light-emitting unit is connected to the fourth node, and the other end of the light-emitting unit is connected to the ground signal terminal; The reset module is used to reset the potentials of the first node, the second node, and the fourth node; The storage module is connected to the first node and the fourth node respectively; The light-emitting control module is connected to the second node, the third node and the fourth node respectively, and is used to input a power signal from the second node and electrically connect the third node and the fourth node under the control of the light-emitting control signal. The data writing module is connected to the third node and is used to acquire data signals from the data line under the control of the scan line; The compensation module is connected to the first node and / or the fourth node and is used to provide a compensation signal to the first node and / or the fourth node. The compensation signal is used to compensate for insufficient data writing caused by uneven impedance of the scan line or the data line.

2. The pixel driving circuit of the display panel according to claim 1, characterized in that, The display panel includes multiple first scan lines and multiple second scan lines, and the opening display area includes a first opening display area; The first scan line is disposed in the first aperture display area, and the second scan line is disposed in the non-aperture display area; The first opening display area is provided with an opening area, and the first opening display area is located on both sides of the opening area along the length direction of the first scan line; The first scan line is wound around the opening area, and the line resistance of the first scan line is greater than that of the second scan line.

3. The pixel driving circuit of the display panel according to claim 1 or 2, characterized in that, The display panel includes multiple first data lines and multiple second data lines, and the opening display area includes a second opening display area; The first data line is disposed in the second open-hole display area, and the second data line is disposed in the non-open-hole display area; The second opening display area is provided with an opening area, and the second opening display area is located on both sides of the opening area along the length direction of the first data line; The first data line is wound around the opening area, and the resistance of the first data line is greater than that of the second data line.

4. The pixel driving circuit of the display panel according to claim 1, characterized in that, The compensation module includes a first compensation circuit, which includes a first compensation signal, a first active switch, and a first compensation control signal. The output terminal of the first active switch is connected to the first node, the first compensation signal is connected to the input terminal of the first active switch, and the first compensation control signal is connected to the control terminal of the first active switch.

5. The pixel driving circuit of the display panel according to claim 1, characterized in that, The compensation module includes a second compensation circuit, which includes a second compensation signal, a second active switch, and a second compensation control signal. The output terminal of the second active switch is connected to the fourth node, the second compensation signal is connected to the input terminal of the second active switch, and the second compensation control signal is connected to the control terminal of the second active switch.

6. The pixel driving circuit of the display panel according to claim 1, characterized in that, The compensation module includes a first compensation circuit and a second compensation circuit. The first compensation circuit includes a first compensation signal, a first active switch, and a first compensation control signal. The output terminal of the first active switch is connected to the first node, the first compensation signal is connected to the input terminal of the first active switch, and the first compensation control signal is connected to the control terminal of the first active switch. The second compensation circuit includes a second compensation signal, a second active switch, and a second compensation control signal; the output terminal of the second active switch is connected to the fourth node, the second compensation signal is connected to the input terminal of the second active switch, and the second compensation control signal is connected to the control terminal of the second active switch.

7. The pixel driving circuit of the display panel according to claim 4, 5, or 6, characterized in that, The data writing module includes a third active switch, the control terminal of which is connected to a first scan signal, and the input terminal of which is connected to a data signal. The light-emitting control module includes a fourth active switch and a fifth active switch. The input terminal of the fourth active switch is connected to the power signal, the control terminal of the fourth active switch is connected to the light-emitting control signal, and the output terminal of the fourth active switch is connected to the second node. The input terminal of the fifth active switch is connected to the third node, the output terminal of the fifth active switch is connected to the fourth node, and the control terminal of the fifth active switch is connected to the light emission control signal. The reset module includes a sixth active switch and a seventh active switch. The input terminal of the sixth active switch is connected to the second node, the output terminal of the sixth active switch is connected to the first node, and the control terminal of the sixth active switch is connected to the reset control signal. The input terminal of the seventh active switch is connected to a reset signal, the control terminal of the seventh active switch is connected to the reset control signal, and the output terminal of the seventh active switch is connected to the fourth node; The storage module includes a first capacitor, one end of which is connected to the first node, and the other end of which is connected to the second node.

8. The pixel driving circuit of the display panel according to claim 7, characterized in that, The first pixel driving circuit includes a reset stage, a data writing stage, a compensation stage, and a light emission stage; During the reset phase, the sixth active switch and the seventh active switch are in the ON state; During the data writing phase, the sixth active switch, the seventh active switch, and the third active switch are in the ON state; During the compensation phase, either the first active switch or the second active switch is turned on; During the light-emitting phase, the fourth active switch and the fifth active switch are in the on state.

9. The pixel driving circuit of the display panel according to claim 4, characterized in that, The higher the grayscale voltage of the data signal, the higher the voltage of the compensation signal.

10. A display panel, characterized in that, The display panel includes a pixel driving circuit as described in any one of claims 1-9, wherein the pixel driving circuit is used to drive the display panel to display.

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