Bidirectional annular topology network data acquisition and transmission system

Abstract

According to the bidirectional ring topology network data acquisition and transmission system provided by the invention, a bidirectional ring topology network architecture is adopted, so that the reliability and the fault-tolerant capability of data transmission can be improved. The bidirectional ring topology network data acquisition and transmission system comprises a plurality of data acquisition modules, a signal processor and a bidirectional ring topology network, the data acquisition modules are in one-to-one correspondence with the signal output channels of the controlled object, acquire analog signals output by the corresponding signal output channels of the controlled object, and complete analog / digital (A / D) conversion and packaging of the analog signals; the data acquisition module summarizes the data through the bidirectional ring topology network and transmits the data to the signal processor; the bidirectional annular topology network comprises a plurality of convergence transmission modules, the plurality of convergence transmission modules and the signal processor are connected to form an annular structure, and each convergence transmission module is respectively accessed to the annular network structure clockwise and anticlockwise through double ports, thereby forming a bidirectional annular topology network architecture.

Description

Technical Field

[0001] This invention relates to a data acquisition and transmission system for multi-channel underwater acoustic detection equipment, specifically a bidirectional ring topology network data acquisition and transmission system, belonging to the field of intelligent control technology for underwater acoustic detection equipment. Background Technology

[0002] In underwater acoustic detection equipment, the data acquisition and transmission system is a key component for signal acquisition and processing. Traditional systems often employ single-bus or simple network topologies, which suffer from poor data synchronization, low transmission reliability, and weak anti-interference capabilities. Especially in complex underwater environments, conventional network transmission structures are prone to system paralysis due to node failures, lacking redundancy design, resulting in low reliability and poor fault tolerance. Summary of the Invention

[0003] In view of this, the present invention proposes a bidirectional ring topology network data acquisition and transmission system, which is suitable for high-precision synchronous acquisition, data processing and reliable transmission of multi-channel analog signals; the bidirectional ring topology network architecture can improve the reliability of data transmission and fault tolerance.

[0004] To achieve the above objectives, the present invention provides a bidirectional ring topology network data acquisition and transmission system, comprising: several data acquisition modules, a signal processor, and a bidirectional ring topology network;

[0005] The data acquisition module corresponds one-to-one with the signal output channel of the controlled object, acquires the analog signal output by the corresponding signal output channel of the controlled object, and completes the A / D conversion and packaging of the analog signal;

[0006] The data acquisition module aggregates the data through the bidirectional ring topology network and transmits it to the signal processor.

[0007] The bidirectional ring topology network includes: several convergence transmission modules, which are connected to the signal processor in a ring structure. Each convergence transmission module is connected to the ring network structure through two ports, one clockwise and one counterclockwise, thereby forming a bidirectional ring topology network architecture.

[0008] In a preferred embodiment of the present invention, when the convergence transmission module sends data to the signal processor, the data is copied into two copies and transmitted to the signal processor from its two ports in clockwise and counterclockwise directions, respectively.

[0009] In a preferred embodiment of the present invention, the input terminal of each of the aggregation and transmission modules is capable of aggregating and transmitting the digital signals output by all data acquisition modules; during data transmission, the digital signals output by all data acquisition modules are sent to one or more aggregation and transmission modules in the bidirectional ring topology network.

[0010] In a preferred embodiment of the present invention, data is transmitted in the form of messages in the bidirectional ring topology network;

[0011] The signal processor makes a judgment based on the timestamp, ID, and type of the received message, and automatically selects the message data according to preset rules.

[0012] In a preferred embodiment of the present invention, data in the bidirectional ring topology network is transmitted using dual-end gigabit Ethernet.

[0013] In a preferred embodiment of the present invention, in the bidirectional ring topology network, IP addresses are dynamically allocated, with odd-numbered IPs used for clockwise rings and even-numbered IPs used for counterclockwise rings.

[0014] In a preferred embodiment of the present invention, the data acquisition module includes: an AD acquisition unit and a signal conditioning unit; the convergence and transmission module adopts an FPGA chip;

[0015] The AD acquisition unit is used to complete signal acquisition and analog-to-digital conversion, and the sampling rate is adjustable and supports daisy-chain serial connection; the signal conditioning unit uses a programmable gain amplifier to realize gain control and impedance matching of single-ended analog signals.

[0016] In a preferred embodiment of the present invention, the data acquisition module includes 16 AD acquisition units to acquire 16 single-ended input signals from the front end;

[0017] The 16 AD acquisition units are grouped into four groups of four and connected in series to form four daisy-chain SPIs to the FPGA chip.

[0018] Beneficial effects:

[0019] (1) The data transmission system of the present invention has high reliability: it adopts a bidirectional ring topology network architecture, which allows bidirectional data transmission, enables redundant data transmission, and single node failure does not affect the overall operation of the system. It has high reliability and good fault tolerance, and solves the reliability problem caused by single point failure in traditional networks.

[0020] (2) The data transmission system of the present invention supports dual gigabit Ethernet, which can meet the real-time transmission of massive underwater acoustic data.

[0021] (3) This invention uses a bidirectional ring topology network architecture, dynamic IP allocation, bidirectional data transmission and reception, and is closely integrated with front-end and back-end hardware to ensure stable operation of the system in harsh environments. Attached Figure Description

[0022] Figure 1 This is a structural block diagram of the data acquisition and transmission system of the present invention;

[0023] Figure 2 This is a schematic diagram of the bidirectional ring topology network architecture local area network of the present invention;

[0024] Figure 3 This is a schematic diagram showing the connection between the data acquisition module and the aggregation and transmission module in this invention;

[0025] Figure 4 This is a schematic diagram of a serial link method;

[0026] Figure 5 This is a schematic diagram of a ping-pong storage structure. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0028] Example 1:

[0029] This embodiment proposes a bidirectional ring topology network data acquisition and transmission system for high-precision synchronous acquisition of analog signals and reliable data transmission of multi-channel underwater acoustic detection equipment. The data acquisition and transmission system connects a computer system and physical sensors, and achieves redundant data transmission by adopting bidirectional ring topology network bus technology. The failure of a single node does not affect the overall operation of the system, resulting in high reliability and good fault tolerance.

[0030] like Figure 1 As shown, the data acquisition and transmission system includes: several data acquisition modules, a signal processor, a bidirectional ring topology network, and a controlled object; in this example, the controlled object is a multi-channel underwater acoustic detection equipment, which has 16 channels of hydrophone analog signal output. The data acquisition and transmission system completes the data acquisition of 16 channels of signal time synchronization, frequency synchronization, and clock synchronization through 16 data acquisition modules; the analog-to-digital conversion of the 16 channels of analog signals is performed, and then the acquired data is transmitted via bidirectional gigabit Ethernet.

[0031] The data acquisition module corresponds one-to-one with the signal output channel of the controlled object, acquiring the analog signal output from the corresponding signal output channel of the controlled object and completing the A / D conversion and packaging of the analog signal. The data acquisition module transmits the data to the signal processor after aggregating it through a bidirectional ring topology network. That is, the system connects multiple data acquisition modules into a whole network through a bidirectional ring topology network.

[0032] like Figure 2As shown, the bidirectional ring topology network includes several aggregation transmission modules. These modules are connected to the signal processor in a ring structure, with each module connected to the ring network via two ports (port 1 and port 2) in clockwise and counterclockwise directions respectively, thus forming a bidirectional ring topology network architecture. When an aggregation transmission module sends data to the signal processor, the data is copied twice and transmitted to the signal processor from its two ports (port 1 and port 2) in clockwise and counterclockwise directions respectively. In the bidirectional ring topology network, data flows bidirectionally through the two ports. When a aggregation transmission module or one direction of the link fails, the data can still be transmitted through the link in the other direction, demonstrating a high fault tolerance mechanism.

[0033] Each aggregation and transmission module's input can acquire, aggregate, and transmit 16 channels of hydrophone digital signals. The acquired data is packaged, copied, and transmitted within a bidirectional ring topology network. In other words, each aggregation and transmission module's input can aggregate and transmit the digital signals output from all data acquisition modules. During operation, the digital signals output from all data acquisition modules are sent to one or more aggregation and transmission modules in the bidirectional ring topology network, allowing the data to be transmitted to the signal processor after passing through the network. Data frames are transmitted to the target device via the dual-ring network, ensuring reliable data transmission even in complex environments (such as interference or node failures in underwater acoustic detection).

[0034] In a bidirectional ring topology network, all aggregation transmission modules are connected to the same network (each aggregation transmission module is a node). Any aggregation transmission module, especially between node devices and transport layer devices, can directly exchange information through this network. Each node device is connected to the ring via two ports. For example... Figure 2 As shown, in this example, 12 convergence transmission modules are connected to the signal processor to form a ring network. Each convergence transmission module is connected to the ring network via dual ports in both clockwise and counterclockwise directions. If convergence transmission module 6 needs to send data C to the target machine (such as the signal processor), data C will be copied twice in convergence transmission module 6, resulting in data A and data B, and then transmitted in both directions of the ring network (e.g., ...). Figure 2 (Data A is transmitted clockwise, and data B is transmitted counterclockwise). After data A and data B arrive at the target machine, the target machine will make a judgment based on the content of the messages (data A and data B are transmitted in the network in the form of messages) and perform effective reception, thereby improving the reliability of the array.

[0035] As an example, the target machine makes a decision based on the timestamp, ID, and type of the received message, automatically selects the earliest arriving or complete data frame, discards redundant copies, and ensures transmission continuity.

[0036] As an example, in a bidirectional ring topology network structure, data is transmitted using dual-end gigabit Ethernet.

[0037] As an example, in a bidirectional ring topology network structure, IP addresses are dynamically allocated, with odd-numbered IPs used for the clockwise ring and even-numbered IPs used for the counterclockwise ring.

[0038] In addition, the data acquisition and transmission system is equipped with a display control terminal, which communicates bidirectionally with the signal processor for controlling the data acquisition module and for data acquisition, display, and storage. Furthermore, the system also includes a feedback control module, through which the signal processor connects to the controlled object for feedback control.

[0039] Example 2:

[0040] Based on the above embodiment 1, further, as follows: Figure 3 As shown, the connection scheme between the data acquisition module and the aggregation and transmission module is as follows:

[0041] The data acquisition module includes an AD acquisition unit and a signal conditioning unit; the aggregation and transmission module uses an FPGA chip.

[0042] In this system, the FPGA chip front end uses a multi-channel data acquisition module (in this example, the AD acquisition unit is a 24-bit AD chip) to complete signal acquisition; DDR RAM (double data rate random access memory) is used to implement the data caching function, and combined with the Ethernet transmission module to realize the dual gigabit Ethernet data transmission function.

[0043] As an example, DDR RAM significantly improves memory bandwidth by performing two read / write operations per clock cycle (i.e., double the data rate), making it a key component for high-performance computing. DDR RAM employs methods such as... Figure 4 The ping-pong storage structure shown completes the data transfer process.

[0044] In this example, 16 signals need to be acquired, so the FPGA front end uses a 16-channel data acquisition module.

[0045] The AD acquisition unit is used to complete signal acquisition and analog-to-digital conversion. The sampling rate is adjustable and supports daisy-chain serial links to reduce the number of FPGA interfaces. The signal conditioning unit uses a programmable gain amplifier (such as PGA202) to realize gain control (adjustable by 1, 10, 100, 1000 times) and impedance matching (input impedance ≥1MΩ) of single-ended analog signals.

[0046] The FPGA chip implements data buffering (using a DDR RAM ping-pong storage structure), message control, data multiplexing and framing, and integrates dual Gigabit Ethernet interfaces (using an 88e1111 PHY chip). The FPGA chip connects to a bidirectional ring topology network via dual ports, with data redundantly transmitted in both clockwise and counterclockwise loops. Thus, analog signals are conditioned by the signal conditioning unit and sampled by the AD acquisition unit. The data is buffered by the FPGA and packaged into UDP frames (the frame structure includes a frame header, type, length, data, and checksum), which are then transmitted to the signal processor via the dual-ring network.

[0047] As an example, the AD acquisition unit uses the AD7764 chip, an industrial-grade 24-bit Σ-Δ analog-to-digital converter that combines wide input bandwidth and high speed. The AD7764 is a high-resolution single-channel (24-bit) monolithic data acquisition system, consisting of a differential amplifier, buffer, multi-bit Σ-Δ modulator, FIR digital filter, and SPI-compatible serial communication control interface. The AD7764 has a wide dynamic range, capable of processing wide input signals at 24-bit resolution, with an effective dynamic range from 109dB (input bandwidth of 312kHz) to 115dB (input bandwidth of 78kHz). Its sampling rate can be set via the DEC_RATE pin and monitored via the DEC_RATE1 and DEC_RATE0 bits of the status memory. In practical operation, the on-chip buffer and differential amplifier functions can be selected through the settings of the control register (16 bits in total). The AD7764 can also be set to power-down mode or low-power mode via the controller. It has an SPI-compatible serial communication interface, allowing for easy connection to microcontrollers and DSPs. It supports daisy-chain structures to simplify the readback function of multiple AD7764s in the system. When four consecutive sampled values ​​exceed VREF, the overload detection bit OVR in the status register will be set. The gain register has lower priority than the overload register; the default value of the gain register is 1.25. When the input is 80% of REF, the digital output is full-scale. The maximum analog input voltage range is ±80% of VREF.

[0048] The AD7764 primarily consists of a differential amplifier, a buffer, a multi-bit Σ-Δ modulator, and an FIR digital filter. A key feature of the AD7764 is that it uses the output of an on-chip fully differential amplifier as the input pin of the Σ-Δ modulator. It utilizes an on-chip reference buffer and an FIR filter module to perform digital filtering of the Σ-Δ modulator output. Using Σ-Δ conversion technology and additional digital filters, it converts the analog input signal into an equivalent digital output signal. The AD7764 employs three cascaded FIR filters. By using different combinations of decimation ratios, the AD7764 can achieve three data transmission rates. The first filter receives data from the modulator at a rate of 1CLK MHz (e.g., 20MHz) and then outputs data at a rate of one-quarter 1CLK MHz, i.e., a sampling rate of 4x. The second filter allows sampling rates selectable from 8x to 32x. The third filter has a fixed sampling rate of 2x. The AD7764's digital filtering provides full-band filtering, with stopband attenuation occurring at the Nyquist frequency (output data rate / 2, i.e., ODR / 2). This performance improves anti-aliasing effectiveness, with the filter providing maximum attenuation at the Nyquist frequency and pseudo-samples attenuated by 110 dB.

[0049] In this example, 16 AD7764 chips are used to acquire 16 single-ended input signals from the front end. The 16 AD acquisition chips are grouped into four sets of four daisy-chain SPI connections, which are then connected to the FPGA chip. Figure 5 As shown.

[0050] The reference voltage of the AD acquisition chip can be provided by the voltage reference chip ADR444 with high precision, and the driving circuit for converting single-ended signals to differential signals can be implemented by the ADA4941 chip to better drive the high-performance analog-to-digital converter.

[0051] The bidirectional ring topology network structure has dual gigabit Ethernet transmission capabilities. In this example, each aggregation transmission module uses two gigabit Ethernet PHY chips to achieve dual gigabit Ethernet data transmission. Specifically, the FPGA port and two gigabit Ethernet PHY chips 88e1111 are used to establish the SGMII link, and the EMAC and UDP protocol-based transmission functions are implemented in the FPGA.

[0052] In addition, the system includes a synchronization clock module to achieve time, frequency, and clock synchronization functions. Time synchronization is achieved through a signal processor using the IEEE 1588 protocol to synchronize the data acquisition and transmission system. For clock synchronization, multiple acquisition channels are located on different boards, and different delay constraints are applied to the ADC acquisition channels on different boards to ensure the system's synchronous acquisition requirements.

[0053] Therefore, the data transmission process using this system is as follows: the FPGA chip packages the received data (data output by all data acquisition modules) into UDP frames (the frame structure includes frame header, type, length, data and checksum), and sends them to the bidirectional ring topology network through the dual gigabit Ethernet interface; the data is transmitted simultaneously in clockwise and counterclockwise rings in the bidirectional ring topology network.

[0054] Example 3:

[0055] Based on the above embodiments 1 and 2, further:

[0056] In this system, both the data acquisition module and the aggregation and transmission module use boards. Therefore, the system has several boards (several data acquisition cards and several data transmission cards). To ensure system stability when multiple boards are working simultaneously, the following design is implemented:

[0057] When multiple boards are connected to the system simultaneously, if one board fails due to unforeseen circumstances, isolation is implemented to ensure the operation of the remaining boards is not affected. Electrical connections between boards are primarily based on clock synchronization and gigabit network connectivity. Clock signal connections between different boards utilize opto-isolation, and network port isolation is achieved using the isolation transformer of the network port chip. Data transmission relies on bidirectional data transmission via a two-way ring topology network to enhance reliability.

[0058] In addition, a low-power performance design was implemented for multiple boards operating simultaneously:

[0059] In the circuit design of each board, low-power chips are selected uniformly, and high-performance, high-efficiency DC-DC converters are selected for power conversion chips. To ensure the signal-to-noise ratio, low-dropout LDO linear regulators are selected where necessary.

[0060] Preliminary power consumption estimation: Power consumption is mainly reflected in the AD sampling and Ethernet transmission control sections. In this example, the total power consumption of 16 AD7764s in normal mode is a maximum of 6W. The AD7764 also has a low-power mode, where the total power consumption of 16 AD7764s in low-power mode is a maximum of 3.5W. The power consumption of the FPGA plus dual gigabit network transmission section is empirically estimated to be around 4W. Therefore, based on preliminary design calculations, the ideal total power consumption of the data acquisition card is to be controlled below 8W, with a maximum not exceeding 11W.

[0061] Furthermore, the signal processor's data splicing method is designed so that data from all data acquisition modules can reach the signal processor completely and correctly. The signal processor uses the following strategy for data splicing:

[0062] (1) All data packets have the corresponding data acquisition module's identifier, as well as the data acquisition channel, timestamp, length, and sampling rate information;

[0063] (2) Discard the duplicate data of the bidirectional ring topology network. Based on the data acquisition card identifier, acquisition channel, timestamp, sampling rate and length, data of any time period of any data acquisition card acquisition channel can be extracted.

[0064] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the present invention and should be covered within the scope of the claims of the present invention.

Claims

1. A bidirectional ring topology network data acquisition and transmission system, characterized in that, include: Several data acquisition modules, a signal processor, and a bidirectional ring topology network; The data acquisition module corresponds one-to-one with the signal output channel of the controlled object, acquires the analog signal output by the corresponding signal output channel of the controlled object, and completes the A / D conversion and packaging of the analog signal; The data acquisition module aggregates the data through the bidirectional ring topology network and transmits it to the signal processor. The bidirectional ring topology network includes: several convergence transmission modules, which are connected to the signal processor in a ring structure. Each convergence transmission module is connected to the ring network structure through two ports, one clockwise and one counterclockwise, thereby forming a bidirectional ring topology network architecture.

2. The bidirectional ring topology network data acquisition and transmission system as described in claim 1, characterized in that, When the convergence transmission module sends data to the signal processor, the data is copied into two copies and transmitted to the signal processor from its two ports in clockwise and counterclockwise directions, respectively.

3. The bidirectional ring topology network data acquisition and transmission system as described in claim 2, characterized in that, The input of each of the aforementioned convergence and transmission modules is capable of converging and transmitting the digital signals output by all data acquisition modules; during data transmission, the digital signals output by all data acquisition modules are sent to one or more convergence and transmission modules in the bidirectional ring topology network.

4. The bidirectional ring topology network data acquisition and transmission system as described in claim 2 or 3, characterized in that, Data is transmitted in message form in the bidirectional ring topology network; The signal processor makes a judgment based on the timestamp, ID, and type of the received message, and automatically selects the message data according to preset rules.

5. The bidirectional ring topology network data acquisition and transmission system as described in claim 1 or 2, characterized in that, In the bidirectional ring topology network, data is transmitted using dual-end gigabit Ethernet.

6. The bidirectional ring topology network data acquisition and transmission system as described in claim 1 or 2, characterized in that, In the bidirectional ring topology network, IP addresses are dynamically allocated, with odd-numbered IPs used for the clockwise ring and even-numbered IPs used for the counter-clockwise ring.

7. The bidirectional ring topology network data acquisition and transmission system as described in claim 1 or 2, characterized in that, The data acquisition module includes an AD acquisition unit and a signal conditioning unit; the convergence and transmission module uses an FPGA chip. The AD acquisition unit is used to complete signal acquisition and analog-to-digital conversion, and the sampling rate is adjustable and supports daisy-chain serial connection; the signal conditioning unit uses a programmable gain amplifier to realize gain control and impedance matching of single-ended analog signals.

8. The bidirectional ring topology network data acquisition and transmission system as described in claim 7, characterized in that, The data acquisition module includes 16 AD acquisition units to acquire 16 single-ended input signals from the front end; The 16 AD acquisition units are grouped into four groups of four and connected in series to form four daisy-chain SPIs to the FPGA chip.

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