IGBT device with low switching loss and preparation method thereof
By introducing a split trench gate structure into IGBT devices, the Miller capacitance effect and carrier extraction during the switching process are optimized, solving the problem of high switching losses and achieving more efficient device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2026-03-13
- Publication Date
- 2026-05-12
AI Technical Summary
Existing IGBT devices suffer from significant switching losses during switching, especially under high-frequency or high-current conditions. The Miller capacitance effect and current tailing phenomenon limit device performance and affect overall efficiency and reliability.
A split trench gate structure is adopted. By setting an effective trench gate and a virtual trench gate, the Miller capacitance effect is reduced and the carrier extraction rate is accelerated, thus optimizing the switching process.
It significantly reduces the switching losses of IGBT devices, improves the energy efficiency and thermal stability of devices under high frequency and high power conditions, and enhances the overall efficiency and reliability of application systems.
Smart Images
Figure CN122028446A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductor technology, specifically to an IGBT device with low switching loss and its fabrication method. Background Technology
[0002] IGBT (Insulated Gate Bipolar Transistor) devices are widely used in power electronic systems such as new energy power generation, rail transportation, electric drives, and industrial frequency conversion due to their combination of the high input impedance characteristics of MOSFETs and the low conduction losses of bipolar transistors. As power electronic devices develop towards higher efficiency, higher power density, and higher frequency, power loss during device operation has become one of the key factors limiting the improvement of overall system performance, especially the dynamic loss problem of IGBTs during switching, which is becoming increasingly prominent.
[0003] In practical applications, the total loss of an IGBT typically consists of both conduction loss and switching loss. In existing designs, the on-state voltage drop has been reduced to some extent by introducing carrier storage layers and microtrench structures. However, under high-frequency or high-current operating conditions, the proportion of switching loss in the total loss continues to rise, and may even become the dominant factor.
[0004] On the one hand, during the IGBT turn-on process, the device transitions from a high-resistivity state to a conduction state, causing a rapid drop in collector-emitter voltage and a rapid rise in current. During this process, the gate drive signal needs to charge and discharge the parasitic capacitances within the device, especially the parasitic capacitance between the gate and collector (Miller capacitance). This generates a significant charge-coupling effect during voltage changes, limiting the gate voltage variation within a certain range and forming a relatively long Miller voltage plateau. Within this plateau phase, both the device voltage and current are at relatively high levels, resulting in significant turn-on energy loss. As the device's voltage rating increases or the cell area enlarges, the Miller capacitance effect further intensifies, making it difficult to effectively reduce energy loss during turn-on, thus limiting the performance of IGBTs in high-frequency, low-loss applications.
[0005] On the other hand, during the IGBT turn-off process, the device transitions from the on-state to the off-state, with the collector current decreasing and the voltage increasing. Due to the bipolar conductivity of the IGBT, a large number of charge carriers accumulate in the drift region during the on-state. These carriers need to gradually disappear during turn-off through recombination or extraction. During this process, the device often exhibits a significant current tailing phenomenon, which not only prolongs the turn-off time but also allows the device to continue conducting under higher voltage conditions, thus significantly increasing turn-off energy loss. This turn-off loss not only affects the overall efficiency of the device but may also lead to increased junction temperature and thermal stress, thereby adversely affecting the device's reliability and lifespan.
[0006] Therefore, there is an urgent need for an IGBT device structure and its fabrication method that can effectively improve the switching speed and reduce the switching loss without increasing the on-state voltage drop of the device. Summary of the Invention
[0007] In view of this, this application provides an IGBT device with low switching loss and a method for fabricating the same, so as to improve the switching speed of the device and reduce switching losses.
[0008] The technical solution adopted in this invention is as follows:
[0009] An IGBT device with low switching loss includes a heavily doped P-region, a field cutoff region, and an N-type drift region arranged sequentially from bottom to top.
[0010] The N-type drift region is divided into a first region and a second region adjacent to the first region; a carrier storage layer is formed on the first region of the N-type drift region; a deep P region is formed on the second region, and the deep P region extends downward into the interior of the N-type drift region; the tops of the carrier storage layer and the deep P region are flush, and a P-type body region is formed on it; an N⁺ emitter region and a P⁺ contact region are formed on the same layer of the P-type body region; the carrier storage layer, the deep P region, the P-type body region, the N⁺ emitter region, and the P⁺ contact region together constitute the surface source layer region structure;
[0011] An interlayer dielectric layer and a top metal electrode are sequentially formed on the surface source layer structure; the interlayer dielectric layer has a longitudinally penetrating contact hole; the top metal electrode is connected to the N⁺ emitter region and the P⁺ contact region through the contact hole, respectively.
[0012] The surface source layer region structure contains two trench structures with identical dimensions, designated as the first trench and the second trench. The inner walls of both trench structures are covered with a gate oxide layer, and the trenches are filled with polysilicon material. The polysilicon material within each trench structure is divided into upper and lower parts by the gate oxide layer; the upper polysilicon forms the effective trench gate, and the lower polysilicon forms the virtual trench gate. Electrical isolation between the effective trench gate and the virtual trench gate is achieved through the gate oxide layer. The first trench is located at the N⁺ emission point. The first trench is located on one side of the N⁺ emitter region and is flush with the top of the N⁺ emitter region. Its bottom end passes through the P-type body region and the carrier storage layer from top to bottom and extends into the interior of the N-type drift region. The second trench is arranged laterally at intervals with the first trench and is located in the middle of the P⁺ contact region so that the N⁺ emitter region is located between the first trench and the second trench. Its top end is also flush with the P⁺ contact region. Its bottom end passes through the P-type body region and the deep P region from top to bottom and extends into the interior of the N-type drift region.
[0013] Furthermore, the longitudinal direction is defined as thickness, and the virtual trench gate has the same thickness as the effective trench gate.
[0014] Furthermore, the thickness of the N-drift region is 100 μm.
[0015] Furthermore, the thickness of the effective trench gate is greater than the thickness of the P-type body region, and the thickness of the virtual trench gate is less than the thickness of the deep P-region but greater than the thickness of the carrier storage layer.
[0016] Furthermore, the effective trench gate is electrically connected to the gate potential, and the virtual trench gate is electrically connected to the emitter potential.
[0017] A method for fabricating a low-switching-loss IGBT device, comprising the following steps:
[0018] S1: Provides an N-type single-crystal silicon substrate to form the N-drift region;
[0019] S2: Inject N-type impurities into the upper surface of the N-drift region and push them into a well to form a carrier storage layer;
[0020] S3: Inject P-type impurities into the second region corresponding to the N-drift region within the carrier storage layer and push them into a well to form a deep P-region. The deep P-region is flush with the top of the carrier storage layer.
[0021] S4: Etch to form a second trench penetrating the deep P region and a first trench penetrating the carrier storage layer; thermally grow gate oxide layers on the inner surfaces of the first and second trenches respectively to form gate oxide regions;
[0022] S5: Deposit and etch the first polysilicon layer at the bottom of the first trench and the second trench respectively to form a virtual trench gate;
[0023] S6: A thermally generated oxide layer is formed on the upper surface of the virtual trench gate to form an insulating layer. Subsequently, a second polysilicon layer is deposited and etched on the upper part of the first trench and the second trench to form an effective trench gate.
[0024] S7: P-type impurities are injected and pushed together in the carrier storage layer and deep P region to form a P-type bulk region;
[0025] S8: Inject N-type impurities into the P-type body region and anneal to form an N+ emitter region; the N+ emitter region is located between the first trench and the second trench and is in close contact with the sidewall of the first trench.
[0026] S9: A borosilicate glass layer is deposited on the surface of the device obtained in step S8, and an interlayer dielectric layer is etched to form contact holes that expose the N+ emitter region and the area where the P+ contact region is to be formed.
[0027] S10: P-type impurities are injected into the P-type body region through the contact hole and annealed to form a P+ contact region; the P+ contact region is located on both sides of the second trench, closely attached to the sidewall of the second trench, and flush with the top of the N+ emitter region.
[0028] S11: Deposit and pattern a metal layer on the interlayer dielectric layer to form a top metal electrode that is electrically connected to the N+ emitter region and the P+ contact region through contact holes;
[0029] S12: The back side of the N-type drift region is thinned, and ions are implanted and annealed to form a field cutoff region. Then, boron ions are implanted and annealed to form a heavily doped P-region.
[0030] Furthermore, in step S1, the crystal orientation of the N-type single-crystal silicon substrate is... <100> .
[0031] Furthermore, in step S3, the P-type impurity used to form the deep P region is boron ion.
[0032] This invention forms a split trench gate structure by providing gate oxide layers on the inner walls of both the first and second trenches, with the lower part filled with a virtual trench gate and the upper part filled with an effective trench gate. This effectively reduces the Miller capacitance effect during device switching, weakens the coupling effect of voltage changes on the gate potential during the turn-on phase, and shortens the voltage and current overlap time during the turn-on process, significantly reducing the device's turn-on losses. By setting a deep P-region, the transport path of charge carriers inside the device is rationally guided and enhanced, accelerating the carrier extraction rate in the drift region during the turn-off process, effectively suppressing the current tailing phenomenon during the turn-off phase, shortening the turn-off time, and significantly reducing the device's turn-off losses.
[0033] Compared with the prior art, the present invention has the following beneficial effects:
[0034] 1) The IGBT device of the present invention can achieve the above-mentioned effect of reducing switching losses without significantly increasing the complexity of the manufacturing process, and the device has good process feasibility and parameter consistency.
[0035] 2) The IGBT device of the present invention achieves coordinated optimization of the device's turn-on and turn-off processes by configuring the effective trench gate and the virtual trench gate and adjusting their corresponding dimensions, thereby effectively reducing overall switching losses and solving the performance trade-off problem caused by optimizing only a single switching process in the prior art. At the same time, this design enables the IGBT device to exhibit better energy efficiency and thermal stability under high switching frequency and high power application conditions, which is conducive to improving the overall efficiency and operational reliability of the application system. Attached Figure Description
[0036] Figure 1 This is a schematic diagram of the low switching loss IGBT device in Example 1;
[0037] Figure 2 This is a schematic diagram of the intermediate device obtained in step 1 of Example 2;
[0038] Figure 3 This is a schematic diagram of the intermediate device obtained in step 2 of Example 2;
[0039] Figure 4 This is a schematic diagram of the intermediate device obtained in step 3 of Example 2;
[0040] Figure 5 This is a schematic diagram of the intermediate device obtained in step 4 of Example 2;
[0041] Figure 6 This is a schematic diagram of the intermediate device obtained in step 5 of Example 2;
[0042] Figure 7 This is a schematic diagram of the intermediate device obtained in step 6 of Example 2;
[0043] Figure 8 This is a schematic diagram of the intermediate device obtained in step 7 of Example 2;
[0044] Figure 9 This is a schematic diagram of the intermediate device obtained in step 8 of Example 2;
[0045] Figure 10 This is a schematic diagram of the intermediate device obtained in step 9 of Example 2;
[0046] Figure 11 This is a schematic diagram of the intermediate device obtained in step 10 of Example 2;
[0047] Figure 12 This is a schematic diagram of the intermediate device obtained in step 11 of Example 2;
[0048] Reference numerals: 1-Heavily doped P-region, 2-Field cutoff region, 3-N drift region, 4-Deep P-region, 5-Gate oxide region, 6-Carrier storage layer, 7-Virtual trench gate, 8-Effective trench gate, 9-P-type body region, 10-N+ emitter region, 11-P+ contact region, 12-Interlayer dielectric layer, 13-Top metal electrode, 14-First trench, 15-Second trench. Detailed Implementation
[0049] To make the objectives, technical solutions, features, and advantages of this application clearer and to enable those skilled in the art to better understand the technical solutions of this application, the following detailed description of this application is provided in conjunction with the accompanying drawings and embodiments.
[0050] Example 1:
[0051] like Figure 1 As shown, this embodiment provides a low-switching-loss IGBT device, which includes a heavily doped P-region 1, a field-stop region 2, and an N-type drift region 3 arranged sequentially from bottom to top.
[0052] The N-type drift region 3 is divided into a first region and a second region adjacent to the first region; a carrier storage layer 6 is formed on the first region of the N-type drift region 3; a deep P region 4 is formed on the second region, and the deep P region 4 extends downward into the interior of the N-type drift region 3; the tops of the carrier storage layer 6 and the deep P region 4 are flush, and a P-type body region 9 is formed on it; an N⁺ emitter region 10 and a P⁺ contact region 11 are formed on the same layer of the P-type body region 9; the carrier storage layer 6, the deep P region 4, the P-type body region 9, the N⁺ emitter region 10 and the P⁺ contact region 11 together constitute the surface source layer region structure.
[0053] An interlayer dielectric layer 12 and a top metal electrode 13 are sequentially formed on the surface source layer structure; the interlayer dielectric layer 12 has a longitudinally penetrating contact hole; the top metal electrode 13 is connected to the N⁺ emitter region 10 and the P⁺ contact region 11 through the contact hole.
[0054] The surface source layer region structure contains two trench structures with identical dimensions, namely a first trench 14 and a second trench 15. The inner walls of both trench structures are covered with a gate oxide layer 5, and the trenches are filled with polysilicon material. The polysilicon material within each trench structure is divided into upper and lower parts by the gate oxide layer 5, with the upper polysilicon forming an effective trench gate 8 and the lower polysilicon forming a virtual trench gate 7. Electrical isolation is achieved between the effective trench gate 8 and the virtual trench gate 7 through the gate oxide layer 5. The first trench 14 is located in one of the N⁺ emitter regions 10. The first trench 14 is arranged laterally and closely attached to the N⁺ emitter region 10. Its top end is flush with the top of the N⁺ emitter region 10, and its bottom end passes through the P-type body region 9 and the carrier storage layer 6 from top to bottom, and extends into the interior of the N-type drift region 3. The second trench 15 is arranged laterally and spaced from the first trench 14, located in the middle of the P⁺ contact region 11, so that the N⁺ emitter region 10 is located between the first trench 14 and the second trench 15. Its top end is also flush with the P⁺ contact region 11, and its bottom end passes through the P-type body region 9 and the deep P region 4 from top to bottom, and extends into the interior of the N-type drift region 3.
[0055] In this embodiment, the x-direction is defined as the lateral direction, and the y-direction as the thickness. To achieve low switching losses, the device features key dimensional designs: the thickness of the deep P-region 4 is greater than the thickness of the virtual trench gate 7, forming a deeper P-type hole pathway. This structure, combined with the virtual trench gate 7, effectively accelerates the carrier extraction rate in the drift region during turn-off, thereby reducing turn-off losses; the thickness of the effective trench gate 8 is greater than the thickness of the P-type body region 9, which facilitates electron channel formation and improves the device's conduction capability; the thickness of the virtual trench gate 7 is greater than the thickness of the carrier storage layer 6, which reduces the Miller capacitance effect during switching, weakens the coupling effect of voltage changes during the turn-on phase on the gate potential, and thus shortens the voltage-current overlap time, significantly reducing turn-on losses.
[0056] In one specific embodiment of this example, the thickness of the N-drift region 3 is 100 μm. Preferably, the dummy trench gate 7 has the same thickness as the effective trench gate 8, approximately half the total thickness of the gate oxide region 5 trenches. More preferably, the thickness of the effective trench gate 8 is greater than the thickness of the P-type body region 9, and the thickness of the dummy trench gate 7 is less than the thickness of the deep P-region 4 but greater than the thickness of the carrier storage layer 6. The effective trench gate 8 is electrically connected to the gate potential, and the dummy trench gate 7 is electrically connected to the emitter potential.
[0057] As can be seen, the IGBT device in this embodiment achieves coordinated optimization of the turn-on and turn-off processes by adjusting the structural configuration and thickness of the effective trench gate 8, the virtual trench gate 7, and the deep P-region 4. This effectively reduces the overall switching loss of the device and solves the performance trade-off problem caused by optimizing only a single switching process in the prior art. This coordinated low-loss design enables the IGBT device to have better energy efficiency and thermal stability under high switching frequency and high power application conditions, which is beneficial to improving the overall efficiency and operational reliability of the application system.
[0058] Example 2:
[0059] This embodiment provides a method for fabricating a low-switching-loss IGBT device, which includes the following steps:
[0060] S1: An N-type single-crystal silicon substrate is provided as the N-drift region 3; the crystal orientation of the N-type single-crystal silicon substrate is... <100> The thickness is 100 μm, and the doping element is phosphorus; the intermediate device structure obtained after this step is as follows. Figure 2 As shown.
[0061] S2: Divide the upper surface of the N-drift region 3 into a first region and a second region; inject N-type impurities into the upper surface of the N-drift region 3, and form a carrier storage layer 6 through a push-well process; wherein, the impurity concentration of the carrier storage layer 6 is approximately 10 times that of the N-drift region 3, and its depth is between 4 μm and 5 μm, which is used to enhance the electron injection enhancement effect; the intermediate device structure obtained after completing this step is as follows. Figure 3 As shown.
[0062] S3: P-type impurities are injected into the second region corresponding to the N-drift region 3 within the carrier storage layer 6, and a deep P-region 4 is fabricated using a push-well process; the bottom of the deep P-region 4 extends into the interior of the N-drift region 3; in this embodiment, boron is selected as the P-type dopant; the device structure obtained after completing this step is as follows. Figure 4 As shown.
[0063] S4: A first trench 14 is etched within the carrier storage layer 6 at the position corresponding to the first region of the N drift region 3, and a second trench 15 is etched within the deep P region 4. The first trench 14 penetrates the carrier storage layer 6, and the second trench 15 penetrates the deep P region 4. Subsequently, gate oxide layers are thermally grown on the inner walls of the first trench 14 and the second trench 15, respectively, to form the gate oxide region 5. The intermediate device structure obtained after completing this step is as follows: Figure 5 As shown.
[0064] S5: A first polysilicon layer is deposited on the surface of the gate oxide region 5 in the first trench 14 and the second trench 15, respectively. Then, the upper half of the first polysilicon layer in the first trench 14 and the second trench 15 is etched away, leaving the lower half of the first polysilicon layer, to form a virtual trench gate 7. The virtual trench gate 7 is externally connected to the emitter potential. The intermediate device structure obtained after this step is as follows: Figure 6 As shown.
[0065] S6: An insulating oxide layer is thermally grown on the upper surface of the virtual trench gate 7. Subsequently, a second polysilicon layer is deposited on the surface of the gate oxide region 5 within the first trench 14 and the second trench 15. The polysilicon layers of the first trench 14 and the second trench 15 are etched away, leaving the upper half of the second polysilicon layer to form an effective trench gate 8. The effective trench gate 8 is externally connected to the gate potential. The intermediate device structure obtained after completing this step is as follows: Figure 7 As shown.
[0066] S7: P-type boron impurities are implanted on the upper surface of carrier storage layer 6 and deep P-region 4, and a P-type body region 9 is formed by push-junction process; the P-type body region 9 is longitudinally adjacent to the deep P-region 4; the intermediate device structure obtained after this step is as follows. Figure 8 As shown.
[0067] S8: N-type arsenic impurities are implanted into the P-type body region 9, and an N+ emitter region 10 is formed by rapid thermal annealing. The N+ emitter region 10 is located between the first trench 14 and the second trench 15, and is closely attached to the sidewall of the first trench 14. The intermediate device structure obtained after this step is as follows: Figure 9 As shown.
[0068] S9: Boron phosphosilicate glass (BPSG) material is deposited on the entire upper surface of the device obtained in step S8, and an interlayer dielectric layer 12 is formed by etching. Contact holes are etched to expose the N+ emitter region 10 and to form the P+ contact region 11. The intermediate device structure obtained after this step is as follows: Figure 10 As shown.
[0069] S10: P-type boron difluoride impurities are injected into the P-type body region 9 through the contact hole, and a P+ contact region 11 is formed by rapid thermal annealing. The P+ contact region 11 is located on both sides of the second trench 15, closely attached to the sidewall of the second trench 15, and flush with the top of the N+ emitter region 10. The intermediate device structure obtained after this step is as follows: Figure 11 As shown.
[0070] S11: Deposit aluminum metal on the surface of the interlayer dielectric layer 12, and pattern it using photolithography and etching processes to form a top metal electrode 13 that is electrically connected to the N+ emitter region 10 and the P+ contact region 11 through contact holes; the intermediate device structure obtained after this step is as follows: Figure 12 As shown.
[0071] S12: Thinning is performed on the bottom of the N-drift region 3; hydrogen ions are implanted below the N-drift region 3 to form the field-stop region 2; boron ions are implanted below the field-stop region 2, and a heavily doped P-region 1 is formed by laser annealing. Finally, a low-switching-loss IGBT device is obtained, and the device structure is as follows. Figure 1 As shown.
[0072] Finally, it should be noted that the above description only depicts some embodiments of this application. For those skilled in the art, various changes, modifications, substitutions, and variations can be conceived of these embodiments without departing from the principles and spirit of this application. The scope of protection of this application is defined by the appended claims and their equivalents, and all the above-mentioned behaviors should be covered within the scope of protection of this application.
[0073] Furthermore, in the above description of the embodiments, unless otherwise explicitly specified and limited, the use of terms such as "upper," "lower," "horizontal," and "inner" to indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the invention is in use, is merely for the convenience of describing this application and simplifying the description, and does not limit or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The use of terms such as "first" and "second" is merely for distinguishing descriptions and should not be construed as indicating or implying relative importance. Components shown in the accompanying drawings and described in the embodiments can be arranged and designed in various different configurations; the use of the term "horizontal" does not mean that the component is required to be absolutely horizontal, but rather that it can be slightly tilted. "Horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted. The terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.
Claims
1. A low-switching-loss IGBT device, comprising a heavily doped P-region, a field-stop region, and an N-type drift region arranged sequentially from bottom to top, characterized in that: The N-type drift region is divided into a first region and a second region adjacent to the first region; a carrier storage layer is formed on the first region of the N-type drift region; a deep P region is formed on the second region, and the deep P region extends downward into the interior of the N-type drift region; the tops of the carrier storage layer and the deep P region are flush, and a P-type body region is formed on it; an N⁺ emitter region and a P⁺ contact region are formed on the same layer of the P-type body region; the carrier storage layer, the deep P region, the P-type body region, the N⁺ emitter region, and the P⁺ contact region together constitute the surface source layer region structure; An interlayer dielectric layer and a top metal electrode are sequentially formed on the surface source layer region structure; The interlayer dielectric layer has longitudinally penetrating contact holes; The top metal electrode is connected to the N⁺ emitter region and the P⁺ contact region through contact holes, respectively. The surface source layer region structure contains two trench structures with identical dimensions, designated as the first trench and the second trench. The inner walls of both trench structures are covered with a gate oxide layer, and the trenches are filled with polysilicon material. The polysilicon material within each trench structure is divided into upper and lower parts by the gate oxide layer; the upper polysilicon forms the effective trench gate, and the lower polysilicon forms the virtual trench gate. Electrical isolation between the effective trench gate and the virtual trench gate is achieved through the gate oxide layer. The first trench is located at the N⁺ emission point. The first trench is located on one side of the N⁺ emitter region and is flush with the top of the N⁺ emitter region. Its bottom end passes through the P-type body region and the carrier storage layer from top to bottom and extends into the interior of the N-type drift region. The second trench is arranged laterally at intervals with the first trench and is located in the middle of the P⁺ contact region so that the N⁺ emitter region is located between the first trench and the second trench. Its top end is also flush with the P⁺ contact region. Its bottom end passes through the P-type body region and the deep P region from top to bottom and extends into the interior of the N-type drift region.
2. The IGBT device with low switching loss according to claim 1, characterized in that: The longitudinal direction is defined as the thickness, and the virtual trench gate has the same thickness as the effective trench gate.
3. The IGBT device with low switching loss according to claim 1, characterized in that: The thickness of the N-drift region is 100 μm.
4. The IGBT device with low switching loss according to claim 3, characterized in that: The thickness of the effective trench gate is greater than the thickness of the P-type body region, and the thickness of the virtual trench gate is less than the thickness of the deep P-region but greater than the thickness of the carrier storage layer.
5. The IGBT device with low switching loss according to claim 1, characterized in that: The effective trench gate is connected to the gate potential, and the virtual trench gate is connected to the emitter potential.
6. A method for fabricating a low-switching-loss IGBT device, characterized in that, Includes the following steps: S1: Provides an N-type single-crystal silicon substrate to form the N-drift region; S2: Inject N-type impurities into the upper surface of the N-drift region and push them into a well to form a carrier storage layer; S3: Inject P-type impurities into the second region corresponding to the N-drift region within the carrier storage layer and push them into the well to form a deep P-region; S4: Etching forms a second trench penetrating the deep P region and a first trench penetrating the carrier storage layer; A gate oxide layer is thermally grown on the inner surface of the first trench and the second trench respectively to form a gate oxide region; S5: Deposit and etch the first polysilicon layer at the bottom of the first trench and the second trench respectively to form a virtual trench gate; S6: A thermally generated oxide layer is formed on the upper surface of the virtual trench gate to form an insulating layer. Subsequently, a second polysilicon layer is deposited and etched on the upper part of the first trench and the second trench to form an effective trench gate. S7: P-type impurities are injected and pushed together in the carrier storage layer and deep P region to form a P-type bulk region; S8: Inject N-type impurities into the P-type body region and anneal to form an N+ emitter region; the N+ emitter region is located between the first trench and the second trench and is in close contact with the sidewall of the first trench. S9: A borosilicate glass layer is deposited on the surface of the device obtained in step S8, and an interlayer dielectric layer is etched to form contact holes that expose the N+ emitter region and the area where the P+ contact region is to be formed. S10: P-type impurities are injected into the P-type body region through the contact hole and annealed to form a P+ contact region; the P+ contact region is located on both sides of the second trench, closely attached to the sidewall of the second trench, and flush with the top of the N+ emitter region. S11: Deposit and pattern a metal layer on the interlayer dielectric layer to form a top metal electrode that is electrically connected to the N+ emitter region and the P+ contact region through contact holes; S12: The back side of the N-type drift region is thinned, and ions are implanted and annealed to form a field cutoff region. Then, boron ions are implanted and annealed to form a heavily doped P-region.
7. The method for fabricating a low-switching-loss IGBT device according to claim 6, characterized in that, In step S1, the crystal orientation of the N-type single-crystal silicon substrate is... <100> .
8. The method for fabricating a low-switching-loss IGBT device according to claim 6, characterized in that, In step S3, the P-type impurity used to form the deep P region is boron ion.