Preparation method of semiconductor structure, semiconductor structure, memory and electronic equipment

Abstract

The invention relates to a preparation method of a semiconductor structure, the semiconductor structure, a memory and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, and forming a channel layer on the substrate; forming a sacrificial layer with a preset thickness on the channel layer, wherein a lattice vacancy is formed in a part, close to the sacrificial layer, of the channel layer; repairing the lattice vacancy based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer; and forming a gate dielectric layer on the interface layer. In the preparation method of the semiconductor structure, the lattice vacancies are arranged in the part, close to the sacrificial layer, of the channel layer, and the lattice vacancies can be repaired based on the sacrificial layer and the channel layer in the process of forming the interface layer on the channel layer, so that the interface quality of the interface layer is improved. Therefore, the influence of the interface state between the gate dielectric layer and the channel layer on the device can be improved, and the electrical performance and reliability of the device can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a memory and electronic device. Background Technology

[0002] Due to their excellent compatibility with back-end processes and ultra-long data retention times, thin-film transistors (TFTs) are becoming increasingly important in emerging fields, and their applications are becoming more widespread. For example, they are widely used in flexible displays, the Internet of Things (IoT), wearable electronics, and memory.

[0003] However, even minor variations and defects in the manufacturing process can affect device performance, leading to degradation and instability in electrical properties. Therefore, a method is urgently needed to mitigate the impact of these issues on devices. Summary of the Invention

[0004] Based on this, the present disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory and electronic device, which can improve the influence of the interface state between the gate dielectric layer and the channel layer on the device.

[0005] According to some embodiments, one aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] A substrate is provided, and a trench layer is formed on the substrate;

[0007] A sacrificial layer of predetermined thickness is formed on the channel layer; lattice vacancies are present in the portion of the channel layer near the sacrificial layer.

[0008] Lattice vacancies are repaired using sacrificial layers and channel layers to obtain an interface layer on the channel layer;

[0009] A gate dielectric layer is formed on the interface layer.

[0010] In some embodiments, lattice vacancies include oxygen vacancies; repairing lattice vacancies based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer includes: performing an in-situ annealing process on the resulting structure after the formation of the sacrificial layer, so that the contact interface between the sacrificial layer and the channel layer reacts to form an interface layer.

[0011] In some embodiments, the annealing temperature range of the in-situ annealing process is 300℃-700℃;

[0012] In some embodiments, the annealing time ranges from 1 min to 60 min in the in-situ annealing process;

[0013] In some embodiments, the annealing atmosphere of the in-situ annealing process is a gaseous atmosphere formed by oxygen, ozone, or an inert gas mixture containing oxygen.

[0014] In some embodiments, the range of the preset thickness is:

[0015] In some embodiments, the material of the sacrificial layer includes oxides.

[0016] In some embodiments, the channel layer, sacrificial layer, interface layer, and gate dielectric layer are formed in the same vacuum environment.

[0017] In some embodiments, the sacrificial layer and the gate dielectric layer are made of the same or different materials.

[0018] In some embodiments, after forming a gate dielectric layer on the interface layer, the method further includes performing an annealing process on the resulting structure after forming the gate dielectric layer.

[0019] In some embodiments, the annealing temperature range of the annealing process is 300℃-700℃;

[0020] In some embodiments, the annealing time ranges from 1 min to 60 min;

[0021] In some embodiments, the annealing atmosphere of the annealing process is a gaseous atmosphere formed by oxygen, ozone, nitrogen, or an inert gas mixture containing oxygen.

[0022] According to some embodiments, another aspect of this disclosure provides a semiconductor structure including a substrate and a channel layer, an interface layer, and a gate dielectric layer located on the substrate from bottom to top; wherein the interface layer is a lattice vacancy repair layer.

[0023] According to some embodiments, another aspect of this disclosure provides a memory including the semiconductor structure described above, or including a semiconductor structure formed by the method for preparing the semiconductor structure described above.

[0024] According to some embodiments, another aspect of this disclosure provides an electronic device including the memory described above.

[0025] The embodiments disclosed herein may have, or at least have, the following advantages:

[0026] In the semiconductor structure fabrication method provided in this disclosure, the portion of the channel layer near the sacrificial layer contains lattice vacancies. During the formation of the interface layer on the channel layer, these lattice vacancies can be repaired based on the sacrificial layer and the channel layer, thereby improving the interface quality of the interface layer. This mitigates the impact of the interface states between the gate dielectric layer and the channel layer on the device, enhancing its electrical performance and reliability. Furthermore, the interface layer can also act as a passivation layer to protect the channel layer, suppressing reactions between the precursor and the channel layer during the formation of the gate dielectric on the interface layer, further improving the device's electrical performance and reliability. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0029] Figure 2 This is a cross-sectional schematic diagram of the structure obtained in step S10 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure;

[0030] Figure 3 This is a cross-sectional schematic diagram of the structure obtained in step S30 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure;

[0031] Figure 4 This is a cross-sectional schematic diagram of the structure obtained in step S50 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure;

[0032] Figure 5 This is a cross-sectional schematic diagram of the structure obtained in step S70 of a semiconductor structure fabrication method provided in one embodiment of the present disclosure.

[0033] Explanation of reference numerals in the attached figures:

[0034] 10. Substrate; 20. Channel layer; 30. Sacrificial layer; 31. Interface layer; 40. Gate dielectric layer. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When using “comprising,” “having,” and “including” as described herein, another component may be added unless explicitly qualified terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0038] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0039] In the description of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0040] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0041] Due to their excellent compatibility with back-end processes and ultra-long data retention times, thin-film transistors (TFTs) are becoming increasingly important in emerging fields, and their applications are becoming more widespread. For example, they are widely used in flexible displays, the Internet of Things (IoT), wearable electronics, and memory.

[0042] However, even minor variations and defects in the manufacturing process can affect device performance. For example, in oxide semiconductor thin-film transistors with top-gate structures, when depositing the gate dielectric on the oxide semiconductor channel surface using atomic layer deposition, the strong reducing properties of the precursor can lead to the generation of metal ions and oxygen vacancies on the oxide semiconductor channel surface. This introduces interface states at the interface between the gate dielectric and the channel, resulting in degradation and instability of the device's electrical performance. Therefore, a method is urgently needed to mitigate the impact of these problems on the device.

[0043] Based on this, the present disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, a memory, and an electronic device, the details of which will be described in subsequent embodiments.

[0044] Please see Figure 1 According to some embodiments, a method for fabricating a semiconductor structure is provided, the method comprising the following steps.

[0045] S10: Provide a substrate and form a trench layer on the substrate;

[0046] S30: A sacrificial layer of predetermined thickness is formed on the channel layer; the portion of the channel layer near the sacrificial layer contains lattice vacancies;

[0047] S50: Based on the sacrificial layer and the channel layer, lattice vacancies are repaired to obtain an interface layer on the channel layer;

[0048] S70: A gate dielectric layer is formed on the interface layer.

[0049] In the semiconductor structure fabrication method of the above embodiments, the portion of the channel layer near the sacrificial layer contains lattice vacancies. During the formation of the interface layer on the channel layer, these lattice vacancies can be repaired based on the sacrificial layer and the channel layer, thereby improving the interface quality of the interface layer. This mitigates the impact of the interface states between the gate dielectric layer and the channel layer on the device, improving its electrical performance and reliability. Furthermore, the interface layer can also act as a passivation layer to protect the channel layer, suppressing reactions between the precursor and the channel layer during the formation of the gate dielectric on the interface layer, further enhancing the device's electrical performance and reliability.

[0050] In some embodiments, lattice vacancies include oxygen vacancies.

[0051] In some embodiments, step S50 repairs lattice vacancies based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer, including:

[0052] S51: Perform in-situ annealing on the structure obtained after the formation of the sacrificial layer, so that the contact interface between the sacrificial layer and the channel layer reacts to form an interface layer.

[0053] In some embodiments, the annealing temperature range of the in-situ annealing process is 300℃-700℃;

[0054] In some embodiments, the annealing time ranges from 1 min to 60 min in the in-situ annealing process;

[0055] In some embodiments, the annealing atmosphere of the in-situ annealing process is a gaseous atmosphere formed by oxygen, ozone, or an inert gas mixture containing oxygen.

[0056] In some embodiments, the range of the preset thickness is:

[0057] In some embodiments, the sacrificial layer material is an oxide.

[0058] In some embodiments, the channel layer, sacrificial layer, interface layer, and gate dielectric layer are formed in the same vacuum environment.

[0059] In some embodiments, the sacrificial layer and the gate dielectric layer are made of the same or different materials.

[0060] In some embodiments, after forming a gate dielectric layer on the interface layer, the method further includes:

[0061] S90: Perform an annealing process on the resulting structure after the gate dielectric layer is formed.

[0062] In some embodiments, the annealing temperature range of the annealing process is 300℃-700℃;

[0063] In some embodiments, the annealing time ranges from 1 min to 60 min;

[0064] In some embodiments, the annealing atmosphere of the annealing process is a gaseous atmosphere formed by oxygen, ozone, nitrogen, or an inert gas mixture containing oxygen.

[0065] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, Figure 1 At least some of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0066] To more clearly illustrate the fabrication methods of the semiconductor structures provided in the above embodiments, please refer to the following... Figures 2 to 5 Understand some embodiments of this application.

[0067] This application does not specifically limit the constituent materials of the substrate 10. As an example, the substrate 10 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon-germanium (SiGe) substrate 10, a silicon-germanium-carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistors formed on the substrate 10; therefore, the type of substrate 10 should not limit the scope of protection of this disclosure.

[0068] Please see Figure 2 For example, in step S10, P-type ions can be implanted into the substrate 10 using an ion implantation process to form a first type of doped well region (not shown). The P-type ions can be, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. Alternatively, N-type ions can be implanted into the substrate 10 using an ion implantation process to form a second type of doped well region (not shown). The N-type ions can be, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. In embodiments where the substrate 10 includes a P-type substrate 10, an active region can be formed by implanting N-type ions; correspondingly, in embodiments where the substrate 10 includes an N-type substrate 10, an active region can be formed by implanting P-type ions. Accordingly, the active region can be a P-type active region or an N-type active region.

[0069] For example, the material of the channel layer 20 includes at least one metal oxide semiconductor selected from indium, gallium, zinc, or tin, such as indium gallium zinc oxide (IGZO), to help reduce the leakage current of the device, thereby ensuring the reliability of the device and reducing the refresh time of the device. By using the above materials, the stress and doping problems of conventional materials in the process stacking can be overcome, thereby reducing the difficulty of multilayer deposition processes.

[0070] It is understood that the electrical performance of a transistor depends on the carrier mobility and the magnitude of the leakage current. In embodiments where the channel layer 20 is made of IGZO material, since the carrier mobility of IGZO material is 20 to 30 times that of amorphous silicon, the channel layer 20 made of IGZO material can improve the charge and discharge rate and response speed, and achieve a faster refresh frequency. Furthermore, compared with related technologies, the leakage current of IGZO transistors can be reduced to one-thousandth, which can further reduce the leakage current and thus optimize the electrical performance of the device.

[0071] It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the device meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0072] Please see Figure 3 In step S30, a sacrificial layer 30 with a preset thickness is formed on the channel layer 20, and lattice vacancies are present in the portion of the channel layer 20 near the sacrificial layer 30.

[0073] For example, in step S30, an atomic layer deposition (ALD) process can be used to form a sacrificial layer 30 of a predetermined thickness on the channel layer 20. ASD is a technique that forms a deposited film by alternately pulsed introduction of a gaseous precursor into a reactor, where it is chemically adsorbed and reacts on a deposition substrate. When the precursor reaches the surface of the deposition substrate, it chemically adsorbs and reacts on its surface. The surface reaction in ASD is self-limiting; the desired structure is formed by repeatedly performing this self-limiting reaction during ASD. Therefore, ASD can produce a smooth surface morphology that closely adheres to the underlying structure, thereby reducing stress generated during the deposition process. Based on the inherent characteristics of ASD, the sacrificial layer 30 formed using ASD can achieve uniform coverage of the channel layer 20.

[0074] For example, the precursor materials for atomic layer deposition processes may include non-metallic precursor materials and / or metallic precursor materials. For instance, non-metallic precursors include halides or nitrides; metallic precursors include alkyl precursors, β-diketone precursors, alkoxide precursors, or alkylamine and silane-based precursors.

[0075] It is understandable that, since precursors usually have strong reducing properties, when a sacrificial layer 30 is deposited on the surface of the channel layer 20 using atomic layer deposition, the precursor is likely to react on the surface of the channel layer 20 to form lattice vacancies and metal ions, that is, there are lattice vacancies in the part of the channel layer 20 near the sacrificial layer 30.

[0076] In some embodiments, the deposition temperature range of the atomic layer deposition process is 100°C-400°C. For example, the deposition temperature range of the atomic layer deposition process is 100°C, 200°C, 300°C, or 400°C, etc.

[0077] In some embodiments, the material of the sacrificial layer 30 is an oxide, such as a metal oxide or a non-metal oxide, including but not limited to aluminum oxide, hafnium oxide, or silicon oxide.

[0078] For example, in an embodiment where the channel layer 20 is made of an oxide semiconductor material and the sacrificial layer 30 is made of an oxide material, the lattice vacancies in the portion of the channel layer 20 near the sacrificial layer 30 include oxygen vacancies.

[0079] In some embodiments, the preset thickness of the sacrificial layer 30 ranges from [specific thickness range]. For example, the preset thickness of the sacrificial layer 30 ranges from... or By forming a thinner sacrificial layer 30, the overall thickness of the semiconductor structure is avoided when improving the interface quality of the top layer of the channel layer 20, thereby ensuring that the interface quality of the top layer of the channel layer 20 is improved without significantly increasing the overall thickness of the semiconductor structure.

[0080] Please see Figure 4 In step S50, lattice vacancies are repaired based on the sacrificial layer 30 and the channel layer 20 to obtain the interface layer 31 on the channel layer 20.

[0081] In some embodiments, step S50, repairing lattice vacancies based on the sacrificial layer 30 and the channel layer 20 to obtain an interface layer 31 on the channel layer 20, includes the following steps.

[0082] S51: Perform in-situ annealing on the structure obtained after the formation of sacrificial layer 30, so that the contact interface between sacrificial layer 30 and channel layer 20 reacts to form interface layer 31.

[0083] In-situ annealing is a technique used in material processing to improve the microstructure and properties of materials through heating and holding at specific temperatures. This process is commonly used for processing metals, ceramics, and semiconductors to eliminate internal stress, improve grain structure, and enhance mechanical properties. In-situ annealing typically includes steps such as heating, holding at specific temperatures, and cooling.

[0084] For example, in step S51, the resulting structure after forming the sacrificial layer 30 is heated to a specific temperature. This temperature is maintained for a period of time to ensure that the atoms within the material can rearrange. The material is then cooled slowly to avoid generating new internal stresses.

[0085] In the above embodiments, after the structure obtained by in-situ annealing is processed to obtain the interface layer 31, the sacrificial layer 30 reacts with the channel layer 20 at the interface to form a more stable interface layer 31. This interface layer 31 can not only passivate the surface of the channel layer 20, but also effectively suppress the reaction between the precursor and the channel during subsequent deposition processes. Furthermore, during the annealing process, oxygen atoms in the annealing atmosphere can repair the oxygen vacancies formed at the interface during the deposition of the sacrificial layer 30, further improving the interface quality of the top layer of the channel layer 20.

[0086] In some embodiments, the annealing temperature range of the in-situ annealing process is 300°C-700°C. For example, the annealing temperature range of the in-situ annealing process is 300°C, 400°C, 500°C, 600°C, or 700°C, etc.

[0087] In some embodiments, the annealing time of the in-situ annealing process ranges from 1 min to 60 min. For example, the annealing time range of the in-situ annealing process is 1 min, 10 min, 20 min, 30 min, or 60 min, etc.

[0088] In some embodiments, the annealing atmosphere of the in-situ annealing process is a gaseous atmosphere formed by oxygen, ozone, or an inert gas mixture containing oxygen.

[0089] In some embodiments, the preset thickness of the interface layer 31 ranges from 1 to 10. For example, the preset thickness of interface layer 31 ranges from... or wait.

[0090] Please see Figure 5 In S70, a gate dielectric layer 40 is formed on the interface layer 31.

[0091] For example, a gate dielectric layer 40 can be formed on the interface layer 31 by a deposition process. The deposition process may include, but is not limited to, at least one of the following processes: chemical vapor deposition (CVD), physical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).

[0092] In some embodiments, the sacrificial layer 30 and the gate dielectric layer 40 are made of the same or different materials.

[0093] In one specific embodiment, after step S50, the same material as the sacrificial layer 30 can be deposited under the same vacuum environment conditions using the same deposition equipment to form the gate dielectric layer 40. For example, atomic layer deposition (ALD) can be used to form the gate dielectric layer 40 on the interface layer 31.

[0094] For example, the material of the gate dielectric layer 40 may include, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric coefficient greater than 3.9), ferroelectric material, antiferroelectric material, or combinations thereof. Exemplarily, high-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0095] In some embodiments, the thickness of the gate dielectric layer 40 ranges from 1 nm to 10 nm. For example, the thickness of the gate dielectric layer 40 ranges from 1 nm, 2 nm, 3 nm, 5 nm, 7 nm, or 10 nm.

[0096] Please see Figures 2 to 5In some embodiments, the channel layer 20, sacrificial layer 30, interface layer 31, and gate dielectric layer 40 are formed in the same vacuum environment. It is understood that a vacuum environment allows for more precise control of deposition rates and temperatures, thereby optimizing the thickness and quality of each layer. Under vacuum conditions, the deposition and growth process of materials is more uniform, enabling the formation of semiconductor structures with better interface quality, which is beneficial for improving interlayer adhesion and overall structural stability. Forming multiple layers in the same vacuum environment can reduce transfer and processing steps, thereby simplifying the process flow and improving production efficiency. Multilayer deposition under the same vacuum conditions ensures the consistency and repeatability of each device, reducing variability in the production process. Furthermore, the interface layer 31 and gate dielectric layer 40 formed in a vacuum typically have better electrical properties, such as lower leakage current and higher dielectric strength, which helps to improve the switching speed of the device and reduce power consumption.

[0097] Please see Figure 5 In step S90, an annealing process is performed on the structure obtained after forming the gate dielectric layer 40.

[0098] In some embodiments, the annealing temperature range of the annealing process is 300°C-700°C. For example, the annealing temperature range of the in-situ annealing process is 300°C, 400°C, 500°C, 600°C, or 700°C, etc.

[0099] In some embodiments, the annealing time ranges from 1 min to 60 min. For example, the annealing time range for in-situ annealing is 1 min, 10 min, 20 min, 30 min, or 60 min, etc.

[0100] In some embodiments, the annealing atmosphere of the annealing process is a gaseous atmosphere formed by oxygen, ozone, nitrogen, or an inert gas mixture containing oxygen.

[0101] In some embodiments, after step S90, a step of depositing a metal gate electrode (not shown) may be included to form a complete gate structure.

[0102] For example, the constituent materials of the metal gate electrode include, but are not limited to, one or more of conductive polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0103] In the semiconductor structure fabrication method of the above embodiment, the portion of the channel layer 20 near the sacrificial layer 30 contains lattice vacancies. During the formation of the interface layer 31 on the channel layer 20, lattice vacancies can be repaired based on the sacrificial layer 30 and the channel layer 20, thereby improving the interface quality of the interface layer 31. This reduces the impact of the interface state between the gate dielectric layer 40 and the channel layer 20 on the device, improving the device's electrical performance and reliability. Furthermore, the interface layer 31 can also serve as a passivation layer to protect the channel layer 20, suppressing reactions between the precursor and the channel layer 20 during the formation of the gate dielectric on the interface layer 31, thereby further improving the device's electrical performance and reliability.

[0104] According to some embodiments, a semiconductor structure is provided.

[0105] As an example, the above-described semiconductor structure can be used to construct a semiconductor device with a gate structure. For instance, the above-described semiconductor structure can be used to construct a DRAM device. The DRAM may include a transistor structure and a capacitor or equivalent capacitor connected to the transistor structure. The capacitor or equivalent capacitor is used to store data, and the transistor structure is used to read data from or write data to the equivalent capacitor. It is understood that the semiconductor structure provided in the embodiments of this disclosure can be used as a component of the transistor structure and equivalent capacitor in a DRAM, such as a 1T1C structure, a 2T0C structure, etc., but is not limited thereto. The semiconductor structure provided in the embodiments of this disclosure can also be used as other structures, such as planar semiconductor devices, FinFET devices, or nanowire devices.

[0106] Please see Figure 5 The semiconductor structure includes a substrate 10 and, from bottom to top, a channel layer 20, an interface layer 31, and a gate dielectric layer 40 located on the substrate 10; wherein, the interface layer 31 is a lattice vacancy repair layer.

[0107] In the semiconductor structure of the above embodiment, the interface layer 31 serves as a lattice vacancy repair layer, and its physicochemical stability is greater than that of the gate dielectric layer 40, thereby improving the quality of the interface between the channel layer 20 and the gate dielectric layer 40. This enhances the electrical performance and reliability of the device. Furthermore, the interface layer 31 can also serve as a passivation layer to protect the channel layer 20, suppressing reactions between the precursor and the channel layer 20 during the formation of the gate dielectric on the interface layer 31, further improving the electrical performance and reliability of the device.

[0108] For example, in an embodiment where the channel layer 20 is made of an oxide semiconductor material, the lattice vacancies are oxygen vacancies, that is, the interface layer 31 serves as an oxygen vacancy repair layer.

[0109] In some embodiments, the semiconductor structure further includes a metal gate electrode (not shown) located on the surface of the gate dielectric layer 40 away from the channel layer 20 to form a complete gate structure as a transistor of the semiconductor device.

[0110] For example, the substrate 10 may include at least one active pillar, and a gate dielectric layer 40 may be disposed around the active pillar. A metal gate electrode may be disposed around the gate dielectric layer 40 to form a semiconductor structure with a vertical channel as one possible implementation. This further increases the contact area between the metal gate electrode and the active pillar, thereby further improving gate control capability. Furthermore, the vertical structure also helps to save structural size, further increasing the distribution density of the semiconductor structure, and thus further increasing the storage density of the device.

[0111] In other embodiments, the channel layer 20 may be disposed around the metal gate electrode. As a possible implementation, this can help save structural size, increase the distribution density of the semiconductor structure, and thus increase the storage density of the device. For example, the active pillars are perpendicular to the thickness direction of the substrate 10 to form a vertical semiconductor structure, which is one possible implementation, thereby further reducing the size of the semiconductor cell.

[0112] According to some embodiments, another aspect of this disclosure provides a memory including the semiconductor structure described above.

[0113] In some embodiments, a memory is provided, including the semiconductor structure described above, or a semiconductor structure formed by the method described above for fabricating the semiconductor structure. Because it employs a semiconductor structure with better performance and reliability, the memory of this embodiment has superior performance and higher reliability.

[0114] This application also provides an electronic device that includes the memory described above. Because it uses a memory with better performance and reliability, the electronic device of this embodiment has superior performance and higher reliability.

[0115] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0116] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0117] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above embodiments are merely illustrative of several implementation methods of this disclosure, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided, and a trench layer is formed on the substrate; A sacrificial layer of predetermined thickness is formed on the channel layer; the portion of the channel layer near the sacrificial layer contains lattice vacancies; The lattice vacancies are repaired based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer; A gate dielectric layer is formed on the interface layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The lattice vacancies include oxygen vacancies; the repair of the lattice vacancies based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer includes: An in-situ annealing process is performed on the structure obtained after the formation of the sacrificial layer, so that the contact interface between the sacrificial layer and the channel layer reacts to form the interface layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The in-situ annealing process includes at least one of the following features: The annealing temperature range of the in-situ annealing process is 300℃-700℃; The annealing time range for the in-situ annealing process is 1 min to 60 min. The annealing atmosphere of the in-situ annealing process is a gaseous atmosphere formed by oxygen, ozone, or an inert mixture containing oxygen.

4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The range of the preset thickness is:

5. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The sacrificial layer material includes oxides.

6. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The channel layer, the sacrificial layer, the interface layer, and the gate dielectric layer are formed in the same vacuum environment.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sacrificial layer and the gate dielectric layer may be made of the same or different materials.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming a gate dielectric layer on the interface layer, the method further includes: An annealing process is performed on the resulting structure after forming the gate dielectric layer; wherein the annealing process includes at least one of the following features: The annealing temperature range of the annealing process is 300℃-700℃; The annealing time range for the annealing process is 1 min to 60 min. The annealing atmosphere of the annealing process is a gaseous atmosphere formed by oxygen, ozone, nitrogen, or an inert mixture containing oxygen.

9. A semiconductor structure, characterized in that, It includes a substrate and, from bottom to top, a channel layer, an interface layer, and a gate dielectric layer located on the substrate; wherein the interface layer is a lattice vacancy repair layer.

10. A memory, characterized in that, It includes the semiconductor structure as described in claim 9, or the semiconductor structure formed by the preparation method of the semiconductor structure as described in any one of claims 1 to 8.

11. An electronic device, characterized in that, Includes the memory as described in claim 10.

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