Mother substrate for display device

Abstract

According to one embodiment, a mother substrate for a display device is provided with: a display region on which an image is displayed; the remaining white area is used for cutting out the outer side of a cutting line of the display area; a display element disposed in the display area; a first partition wall disposed in the remaining white region and including a plurality of first segments and a plurality of second segments; and a first sealing layer that is formed of an inorganic insulating material, is disposed above the display element and the first section, and is not disposed above the second section. The second section has a planar shape different from that of the first section.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2024-197539, filed on November 12, 2024, and Japanese Patent Application No. 2025-115665, filed on July 9, 2025, the contents of which are incorporated herein by reference in their entirety. Technical Field Embodiments of the present invention relate to a mother substrate for a display device. Background Technology

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. In such display devices, technologies to improve yield are needed. Summary of the Invention Generally, according to an embodiment, a mother substrate for a display device includes: a display area for displaying an image; a blank area for cutting out the outer side of the cutting line of the display area; a display element disposed in the display area; a first partition wall disposed in the blank area, comprising a plurality of first segments and a plurality of second segments; and a first sealing layer formed of an inorganic insulating material, disposed above the display element and the first segments, but not above the second segments. The second segments have a planar shape different from the first segments.

[0003] According to another embodiment, a mother substrate for a display device includes: a display area for displaying an image; a blank area for cutting out the outer side of a cutting line of the display area; an inorganic insulating layer disposed in the display area and the blank area; a display element disposed in the display area; a first partition wall including a plurality of first segments and a plurality of second segments, disposed above the inorganic insulating layer in the blank area; a first sealing layer formed of an inorganic insulating material, disposed above the display element and the first segments, but not above the second segments; and a resin layer disposed above the first sealing layer in the blank area.

[0004] Based on this structure, a mother substrate for display devices can be provided that can improve yield. Attached Figure Description

[0005] Figure 1 This is a diagram showing a structural example of the display device according to the first embodiment.

[0006] Figure 2 This is a schematic top view of an example of the layout of subpixels.

[0007] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel along line III-III.

[0008] Figure 4 This is a schematic top view of the mother substrate of the first embodiment.

[0009] Figure 5 This is a schematic top view of a portion of the mother substrate.

[0010] Figure 6 It is a rough top view showing the island-shaped part and its vicinity.

[0011] Figure 7 It means Figure 6 A simplified enlarged view of part VII.

[0012] Figure 8 It is along Figure 7 A schematic cross-sectional view of line VIII-VIII in the diagram.

[0013] Figure 9 This is a flowchart illustrating an example of a method for manufacturing a display device.

[0014] Figure 10A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0015] Figure 10B It means Figure 10A A rough cross-sectional view of the subsequent processes.

[0016] Figure 10C It means Figure 10B A rough cross-sectional view of the subsequent processes.

[0017] Figure 10D It means Figure 10C A rough cross-sectional view of the subsequent processes.

[0018] Figure 10E It means Figure 10D A rough cross-sectional view of the subsequent processes.

[0019] Figure 10F It means Figure 10E A rough cross-sectional view of the subsequent processes.

[0020] Figure 10G It means Figure 10F A rough cross-sectional view of the subsequent processes.

[0021] Figure 10H It means Figure 10G A rough cross-sectional view of the subsequent processes.

[0022] Figure 10I It means Figure 10H A rough cross-sectional view of the subsequent processes.

[0023] Figure 10J It means Figure 10IA rough cross-sectional view of the subsequent processes.

[0024] Figure 11A It is a schematic cross-sectional view showing the structure of the blank area during the manufacturing process of a display device.

[0025] Figure 11B It means Figure 11A A rough cross-sectional view of the subsequent processes.

[0026] Figure 11C It means Figure 11B A rough cross-sectional view of the subsequent processes.

[0027] Figure 11D It means Figure 11C A rough cross-sectional view of the subsequent processes.

[0028] Figure 12 This is a schematic enlarged view showing the display device of the second embodiment.

[0029] Figure 13 It is along Figure 12 A schematic cross-sectional view of line XIII-XIII in the diagram.

[0030] Figure 14 This is a schematic enlarged view showing the display device of the third embodiment.

[0031] Figure 15 It is along Figure 14 A schematic cross-sectional view of the XV-XV line in the diagram. Detailed Implementation

[0032] Hereinafter, various embodiments will be described with reference to the accompanying drawings. Furthermore, the disclosed content is merely an example, and appropriate modifications that maintain the spirit of the invention and are readily conceived by those skilled in the art are of course included within the scope of this invention. Additionally, regarding the drawings, to make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual embodiment; however, this is merely an example and does not limit the interpretation of the invention. Furthermore, in this specification and the various drawings, the same reference numerals are sometimes used for components that perform the same or similar functions as those described in previously presented figures, and repeated detailed descriptions are appropriately omitted. It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are shown as needed and for ease of understanding. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The view of various elements parallel to the third direction Z is called a top view. The display device in each embodiment is an organic electroluminescent display device with organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0033] [First Embodiment]

[0034] Figure 1 This diagram illustrates a structural example of the display device DSP according to this embodiment. The display device DSP includes a display panel PNL comprising an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0035] In this embodiment, the substrate 10 and the display area DA, viewed from above, are circular. Here, "circular" is not limited to a perfect circle, but includes shapes such as a circle with a missing portion, an ellipse, or an oblong shape. Furthermore, the shape of the substrate 10 and the display area DA, viewed from above, is not limited to a circle; it can also be other shapes such as a rectangle, a square, or an ellipse.

[0036] exist Figure 1 In this example, the annular partition structure DS is disposed in the peripheral region SA. The partition structure DS surrounds the display region DA. The shape of the partition structure DS when viewed from above is, for example, circular, but is not limited to this example. The partition structure DS can, for example, be composed of an organic insulating layer 12 described later (see reference). Figure 3 )form.

[0037] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of sub-pixels SP displaying different colors. In this embodiment, it is envisioned that the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. For example, the first color is blue, the second color is green, and the third color is red, but this is not limited to this example. The pixel PX may also include sub-pixels SP of other colors such as white, in addition to or in place of any one of the sub-pixels SP1, SP2, and SP3.

[0038] The display device DSP also includes a terminal section T disposed in the peripheral area SA. A flexible circuit board for supplying voltage or signals for driving the display device DSP is connected to the terminal section T, for example.

[0039] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements composed of thin-film transistors.

[0040] The display area DA is equipped with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply image signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. Figure 1 In the example, the scan line GL and the power line PL extend along the first direction X, and the signal line SL extends along the second direction Y.

[0041] The gate of pixel switch 2 is connected to scan line GL. One of the source and drain of pixel switch 2 is connected to signal line SL, and the other is connected to the gate of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source and drain is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0042] It should be noted that the structure of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 can also have more thin-film transistors and capacitors.

[0043] Figure 2 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. Figure 2 In the example, subpixels SP2 and SP3 are arranged along the first direction X with subpixel SP1. Furthermore, subpixels SP2 and SP3 are arranged along the second direction Y.

[0044] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of sub-pixels SP2 and SP3 alternately arranged along the second direction Y, and multiple columns of sub-pixels SP1 repeatedly arranged along the second direction Y. These columns are arranged alternately along the first direction X. It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to this. Figure 2 Examples.

[0045] A rib layer 5 is disposed in the display area DA. In this embodiment, the rib layer 5 is an example of an inorganic insulating layer. The rib layer 5 has pixel openings AP1, AP2, and AP3 on the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among subpixels SP1, SP2, and SP3, subpixel SP1 has the largest aperture ratio, and subpixel SP3 has the smallest aperture ratio. However, the sizes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0046] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0047] The portion of the lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 overlapping with the pixel opening AP1 constitutes the display element DE1 of sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 overlapping with the pixel opening AP2 constitutes the display element DE2 of sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 overlapping with the pixel opening AP3 constitutes the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may also include a capping layer described later. Rib layer 5 surrounds these display elements DE1, DE2, and DE3 respectively.

[0048] A conductive partition 6 (second partition) is disposed above the rib layer 5. The partition 6 serves as wiring to supply a common voltage to the upward electrodes UE1, UE2, and UE3. The partition 6 overlaps the rib layer 5 in general and has the same planar shape as the rib layer 5.

[0049] Specifically, partition 6 has partition opening 601A on sub-pixel SP1, partition opening 602A on sub-pixel SP2, and partition opening 603A on sub-pixel SP3. Partition openings 601A, 602A, and 603A completely overlap with pixel openings AP1, AP2, and AP3, respectively. Furthermore, partition openings 601A, 602A, and 603A completely overlap with display elements DE1, DE2, and DE3, respectively. That is, partition 6 surrounds display elements DE1, DE2, and DE3.

[0050] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel PNL with line III-III. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line GL, signal line SL, and power line PL. Circuit layer 11 is covered by organic insulating layer 12. Organic insulating layer 12 functions as a planarization film to flatten the unevenness created by circuit layer 11.

[0051] Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by rib layer 5. Although not in Figure 3 The cross-section shows that the lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided on the organic insulating layer 12.

[0052] The partition 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. In this embodiment, the lower portion 61 of the partition 6 corresponds to the second lower portion, and the upper portion 62 of the partition 6 corresponds to the second upper portion.

[0053] The upper part 62 has a wider width than the lower part 61. As a result, the two ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of the partition 6 is called an overhang.

[0054] exist Figure 3 In this example, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Additionally, in Figure 3 In the example, the two ends of the bottom layer 63 protrude from the sides of the shaft layer 64.

[0055] In addition, Figure 3 In the example, the upper part 62 has a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this; the first top layer 65 and the second top layer 66 can also have the same width.

[0056] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and is opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the side of the lower part 61 of partition 6.

[0057] Display element DE1 includes a capping layer CP1 disposed on the upper electrode UE1. Display element DE2 includes a capping layer CP2 disposed on the upper electrode UE2. Display element DE3 includes a capping layer CP3 disposed on the upper electrode UE3. The capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers for improving the light extraction efficiency emitted by the organic layers OR1, OR2, and OR3.

[0058] In the following description, the multilayer comprising organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer comprising organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer comprising organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0059] Sealing layers SE11, SE12, and SE13 are respectively disposed on sub-pixels SP1, SP2, and SP3. Sealing layer SE11 continuously covers the laminated film FL1 and the partition wall 6 around sub-pixel SP1. Sealing layer SE12 continuously covers the laminated film FL2 and the partition wall 6 around sub-pixel SP2. Sealing layer SE13 continuously covers the laminated film FL3 and the partition wall 6 around sub-pixel SP3.

[0060] exist Figure 3 In the example, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition 6. Additionally, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition 6. However, any two of the sealing layers SE11, SE12, and SE13 can also be in contact above the partition 6.

[0061] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. Laminated films FL1, FL2, FL3 may also be disposed on at least a portion of these gaps.

[0062] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, and a portion of them also involves the surrounding area SA.

[0063] exist Figure 3 In this example, a touch panel electrode TP is disposed on the sealing layer SE2. The touch panel electrode TP is covered by a resin layer RS2. The touch panel electrode TP can be formed from metallic wiring. This wiring can also be opposite to the partition wall 6 in the third direction Z. Furthermore, this wiring can also have the same planar shape as the partition wall 6.

[0064] Polarizing filters, protective films, or glass covers can also be further disposed above the resin layer RS2. Such cover components can also be bonded to the resin layer RS2 via adhesive layers such as OCA (Optical Clear Adhesive).

[0065] The organic insulating layer 12 is formed of organic insulating materials such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed, for example, of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0066] The lower electrodes LE1, LE2, and LE3, for example, have a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0067] The upper electrodes UE1, UE2, and UE3 are formed, for example, from metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0068] Organic layers OR1, OR2, and OR3 are composed of multiple thin films, including a light-emitting layer. In one example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked along the third direction Z. However, organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure including multiple light-emitting layers.

[0069] The capping layers CP1, CP2, and CP3, for example, have a stacked structure with multiple overlapping transparent layers. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0070] The bottom layer 63 and the axial layer 64 of the partition 6 are formed of metallic materials. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. It should be noted that the axial layer 64 can also be formed of an insulating material.

[0071] The first top layer 65 of the partition 6 is formed, for example, of a metallic material. The second top layer 66 of the partition 6 is formed, for example, of a conductive oxide. As the metallic material forming the first top layer 65, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used, for example. As the conductive oxide forming the second top layer 66, ITO or IZO can be used, for example. It should be noted that the upper part 62 may also have three or more layers, or it may be formed from a single layer. Furthermore, the upper part 62 may also include a layer formed of an insulating material.

[0072] A common voltage is supplied to the adjacent 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. Pixel voltages corresponding to the image signals of signal line SL are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of sub-pixels SP1, SP2, and SP3, respectively.

[0073] Organic layers OR1, OR2, and OR3 emit light according to the applied voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the wavelength range of the first color. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the wavelength range of the second color. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the wavelength range of the third color.

[0074] When manufacturing a display device DSP, a large mother substrate is made, comprising multiple regions, each corresponding to a display panel PNL. The structure applicable to this mother substrate will be described below.

[0075] Figure 4 This is a schematic top view of the mother substrate MB (mother substrate for display device) in this embodiment. The mother substrate MB is, for example, a quadrilateral as shown in the figure, but it can also be other shapes such as a circle.

[0076] The mother substrate MB has multiple panel sections PP arranged in a matrix. Figure 4 In this example, multiple panel portions PP are arranged continuously along the first direction X and the second direction Y. However, the arrangement of multiple panel portions PP on the mother substrate MB is not limited to this example.

[0077] Figure 5 This is a schematic top view of a portion of the motherboard (MB). Figure 5 If you pay attention to Figure 4 One of the panel portions PP shown.

[0078] The top view of the panel PP Figure 5 In the example, it is a square. It should be noted that the shape of the panel portion PP when viewed from above can also be a rectangle that is longer in the first direction X, or a rectangle that is longer in the second direction Y. In addition, the shape of the panel portion PP when viewed from above can also be a shape that includes multiple straight or curved portions.

[0079] The shape of each panel portion PP corresponds to the cutting line CL1 used to cut each panel portion PP from the mother substrate MB. The cutting line CL1 is formed in a grid pattern. When focusing on a single panel portion PP, the cutting line CL1 is formed in a quadrilateral shape.

[0080] Additionally, a cutting line CL2 is formed on the panel portion PP. The cutting line CL2 is equivalent to... Figure 1 The shape of the display panel PNL is shown. In other words, the cutting line CL2 is formed as a circle. The cutting line CL2 is equivalent to the cutting line used to cut the display area DA and a portion of the surrounding area SA from the panel portion PP.

[0081] The panel portion PP has the aforementioned display area DA and peripheral area SA. The peripheral area SA includes a blank area FA outside the cutting line CL2. The blank area FA, for example, corresponds to the area between cutting lines CL1 and CL2. Cutting line CL1 corresponds to the cutting line used to cut the display area DA and the blank area FA from the mother substrate MB.

[0082] The panel portion PP is divided into a portion including the display area DA and a portion including the blank area FA by a cutting line CL2. Multiple inspection pads (not shown) for checking the operation of the display panel PNL are arranged between the cutting lines CL1 and CL2.

[0083] In this embodiment, a partition 7 (first partition) is disposed in the surrounding area SA, including the blank area FA. Figure 5 In this design, a dotted pattern is added to the area where the partition 7 can be configured. The partition 7 can be configured in the area between the display area DA and the cutting line CL2, the blank area FA, etc. However, the partition 7 may not be configured in at least one of these areas. In addition, the configuration position and planar shape of the partition 7 in these areas can be appropriately determined.

[0084] From the viewpoint of efficiently cutting the panel portion PP, it is preferable not to provide the partition 7 on the cutting line CL1. Similarly, it is preferable not to provide the partition 7 on the cutting line CL2.

[0085] The blank area FA has multiple island-shaped IPs. Specifically, the multiple island-shaped IPs are arranged around the cutting line CL2 when viewed from above. More specifically, the multiple island-shaped IPs are arranged between the cutting lines CL1 and CL2 when viewed from above. In addition, the multiple island-shaped IPs are arranged separately from the cutting line CL2.

[0086] exist Figure 5 In the example, the island-shaped portions IP are respectively disposed at the corner CN of the cutting line CL1. The corner CN is formed by a straight portion extending along the first direction X and a straight portion extending along the second direction Y in the cutting line CL1. Figure 5 In the middle, each of the island-shaped IPs is marked with a diagonal line pattern.

[0087] In this embodiment, four island-shaped IPs are configured relative to one panel PP. It should be noted that the number and position of the island-shaped IPs configured relative to one panel PP can be appropriately changed.

[0088] The island portion IP protrudes further in the third direction Z in the blank area FA compared to the portion outside the island portion IP. In other words, the island portion IP has a greater thickness in the blank area FA than the portion outside the island portion IP. The island portion IP is formed by stacking multiple layers (e.g., sealing layers SE1x, SE2 and resin layer RS3, described later) above the partition wall 7.

[0089] The island-shaped IPs, for example, each have the same shape centered on the display area DA. Furthermore, the shape of the island-shaped IPs in a top-down view is not limited to... Figure 5 Examples. The shape of the island IP can also be different. Here, if we focus on an island IP ( Figure 5 The shape of the island IP1 in the top view is described.

[0090] The island-shaped portion IP1 has edges M1, M2, and M3. In other words, the island-shaped portion IP1 has a side surface including edges M1, M2, and M3. This side surface extends upward from the substrate 10. Edge M1 extends along a first direction X. Edge M2 extends along a second direction Y. The length of edge M1 is, for example, approximately equal to the length of edge M2.

[0091] Edge M3 extends in a direction different from the first direction X and the second direction Y. Specifically, edge M3 is formed along the cutting line CL2. Figure 5In the example, edge M3 can be formed as a curve or as a straight line. These edges M1, M2, and M3 are connected by shorter edges SM that are shorter than edges M1, M2, and M3, respectively. It should be noted that edges M1, M2, and M3 can also be directly connected.

[0092] If you pay attention here Figure 5 The island-shaped part IP1 and its vicinity illustrate the composition of the blank area FA. Figure 6 This is a schematic top view showing the island-shaped section IP1 and its vicinity. As mentioned above, a partition 7 is arranged in the blank area FA.

[0093] The adjacent section 7 has multiple segments 71 and 72. In this embodiment, segment 71 corresponds to the first segment, and segment 72 corresponds to the second segment. In the blank area FA, segment 71 is configured in the island IP, and segment 72 is configured outside the island IP.

[0094] Here, the area within the blank area FA designated for configuring the island-shaped IP is defined as area A1, and the area surrounding the island-shaped IP is defined as area A2. In this embodiment, area A1 corresponds to the first area, and area A2 corresponds to the second area. The blank area FA may, for example, have multiple areas A1 and areas A2. Figure 6 In this embodiment, region A1 is marked with a grid pattern, and region A2 is marked with a diagonal line pattern. Region A1 corresponds to the region with segment 71, and region A2 corresponds to the region with segment 72.

[0095] Area A2, for example Figure 6 The area shown is enclosed as region A1. It should be noted that segment 72 can also be configured in the peripheral region SA between the cutting line CL2 and the display area DA.

[0096] Figure 7 It means Figure 6 A schematic enlarged view of part VII. As described above, partition 7 has multiple segments 71 disposed in region A1 and multiple segments 72 disposed in region A2. The segments 71 and 72 are arranged at intervals in the first direction X and the second direction Y.

[0097] Here, the planar shapes of sections 71 and 72 are described.

[0098] Section 72 has a different planar shape than section 71. Sections 71 and 72 are quadrilateral in shape. Here, quadrilateral shape includes not only square shape, but also rectangular shape, etc. In addition, the corners of sections 71 and 72 are not limited to right angles, but can also be R-shaped.

[0099] The area of ​​segment 71 may be equal to the area of ​​segment 72. The areas of segments 71 and 72 correspond to the size of the shape when viewed from above. It should be noted that the area of ​​segment 71 may also be different from the area of ​​segment 72.

[0100] Section 71 has the same planar shape. Section 72 has the same planar shape. Sections 71 and 72 are as follows: Figure 7 As shown below, it has wall portions 71W and 72W respectively. In this embodiment, wall portion 71W corresponds to the first wall portion, and wall portion 72W corresponds to the second wall portion. Wall portions 71W and 72W respectively form the closed regions described later.

[0101] The wall portion 71W has a frame-shaped outer wall 710 and an inner wall 71X extending from the outer wall 710 in a direction opposite to the first direction X. The inner wall 71X does not partition the interior of the outer wall 710. The segment 71 has a partition opening 71A defined by the outer wall 710 and the inner wall 71X. The area inside the partition opening 71A corresponds to a closed region CA10 (first closed region). In other words, the segment 71 has a closed region CA10.

[0102] The planar shape of the partition opening 71A (closed region CA10) is U-shaped. Additionally, in Figure 7 In the example, a protrusion 71a is formed at the end of the inner wall 71X, protruding in the second direction Y and in the direction opposite to the second direction Y. A slit 71S is formed between the end of the inner wall 71X (protrusion 71a) and the outer wall 710. It should be noted that the protrusion 71a may not be formed.

[0103] The wall portion 72W has a frame-shaped outer wall 720, an inner wall 72X extending from the outer wall 720 in a direction opposite to the first direction X, and an inner wall 72Y extending in the second direction Y. The inner wall 72Y partitions the interior of the outer wall 710. The inner wall 72X extends from the outer wall 720 to the inner wall 72Y in the second direction Y.

[0104] Segment 72 has partition openings 72A, 72B, and 72C defined by the outer wall 720 and the inner walls 72X and 72Y. The regions inside the partition openings 72A, 72B, and 72C correspond to closed regions CA21, CA22, and CA23 (the second closed region). In other words, segment 72 has closed regions CA21, CA22, and CA23.

[0105] The planar shape of the adjacent openings 72A, 72B, 72C (closed regions CA21, CA22, CA23) and Figure 2 The partition openings 601A, 602A, and 603A shown have the same planar shape. The partition openings 72A, 72B, and 72C have, for example, quadrilateral shapes.

[0106] exist Figure 7 In the example, partition openings 72B and 72C are arranged with partition opening 72A in the first direction X. Furthermore, partition openings 72B and 72C are arranged in the second direction Y. Additionally, partition openings 72B and 72C are smaller than partition opening 71A. It should be noted that the shape or relative positional relationship of partition openings 72A, 72B, and 72C is not limited to... Figure 7 Examples.

[0107] Compared to segment 71, the planar shapes of the closed regions CA21, CA22, and CA23 in segment 72 are different from the planar shape of the closed region CA10 in segment 71. Segment 72 has more closed regions CA21, CA22, and CA23 than segment 71 has closed region CA10. In this embodiment, segment 71 has one closed region, and segment 72 has multiple (e.g., three) closed regions.

[0108] The area of ​​closed region CA10 in segment 71 is larger than the areas of closed regions CA21, CA22, and CA23 in segment 72. Alternatively, the ratio of the area of ​​closed region CA10 to the area of ​​segment 71 is larger than the ratio of the combined area of ​​closed regions CA21, CA22, and CA23 to the area of ​​segment 72.

[0109] The area of ​​the wall portion 72W in segment 72 is larger than the area of ​​the wall portion 71W in segment 71. In other viewpoints, the ratio of the area of ​​wall portion 71W to the area of ​​segment 71 is smaller than the ratio of the area of ​​wall portion 72W to the area of ​​segment 72.

[0110] Figure 8 It is along Figure 7 A schematic cross-sectional view of line VIII-VIII in the diagram. Figure 8 In the middle, observe the partition 7 from the direction opposite to the first direction X.

[0111] The aforementioned organic insulating layer 12 and rib layer 5 are also formed in the peripheral region SA, including the blank area FA. Figure 8 In the text, elements located below the organic insulating layer 12 are omitted.

[0112] The partition walls 7 (segments 71 and 72) are disposed on the rib layer 5. Segments 71 and 72 have the same cross-sectional structure. Segments 71 and 72 are the same as the partition wall 6, including a lower part 61 and an upper part 62. In this embodiment, the lower part 61 of the partition wall 7 corresponds to the first lower part, and the upper part 62 of the partition wall 7 corresponds to the first upper part.

[0113] The upper part 62 has a wider width than the lower part 61. The lower part 61 of the partition 7 is the same as that of the partition 6, including a bottom layer 63 and a shaft layer 64. The upper part 62 of the partition 7 is the same as that of the partition 6, including a first top layer 65 and a second top layer 66.

[0114] The bottom layer 63, the axial layer 64, the first top layer 65, and the second top layer 66 of the partition 7 are all formed of the same material as the bottom layer 63, the axial layer 64, the first top layer 65, and the second top layer 66 of the partition 6.

[0115] The laminated membrane FLx is disposed in region A1 (island portion IP) in the blank area FA, but not in region A2. The laminated membrane FLx is disposed in region A1 on the wall portion 71W of segment 71, on the rib layer 5 of the closed region CA10 of segment 71, and on the rib layer 5 between adjacent segments 71.

[0116] The laminated membrane FLx is composed of and Figure 3 The laminated films FL1, FL2, and FL3 shown are formed using the same process and the same materials. In other words, the laminated film FLx is composed of the same layers as any one of the laminated films FL1, FL2, and FL3. For example, the laminated film FLx is formed using the same process and the same materials as the laminated film FL3. Therefore, the capping layer CP3 is also disposed in the blank area FA.

[0117] The sealing layer SE1x is disposed in region A1 (island portion IP) within the blank area FA, but not in region A2. For example, the end of the sealing layer SE1x corresponds to the end of region A1. The sealing layer SE1x is disposed on top of the laminated film FLx. The laminated film FLx is disposed between segment 71 and the sealing layer SE1x.

[0118] The sealing layer SE1x continuously covers the segmented portions of the laminated film FLx and the partition wall 7. In the case of segment 71, the sealing layer SE1x contacts the lower portion 61 and the upper portion 62 of segment 71. Therefore, segment 71 is not exposed from the sealing layer SE1x. Conversely, the sealing layer SE1x is not positioned above segment 72.

[0119] SE1x sealing layer is composed of and Figure 3 The sealing layers SE11, SE12, and SE13 shown are formed using the same process and the same materials. Sealing layer SE1x is formed, for example, using the same process and the same materials as sealing layer SE13. In this embodiment, sealing layers SE11, SE12, SE13, and SE1x correspond to the first sealing layer.

[0120] Resin layer RS3 is disposed in region A1 (island portion IP) within the blank area FA, but not in region A2. Resin layer RS3 is disposed on top of the sealing layer SE1x. Resin layer RS3 utilizes the resin layer RS1 (of the display area DA) Figure 3(As shown) It is formed using the same process and the same materials. The island portion IP includes segment 71, laminated film FLx, sealing layer SE1x, resin layer RS3, and sealing layer SE2.

[0121] The thickness of resin layer RS3 is, for example, greater than that of resin layer RS1 ( Figure 3 The thickness of the layer shown is small. Furthermore, the island portion IP (resin layer RS3) is separated from the resin layer RS1. In other words, resin layer RS3 is isolated from resin layer RS1.

[0122] If we focus on the end S1E of the sealing layer SE1x, the end R3E of the resin layer RS3 is located above the sealing layer SE1x. Here, the end includes the end and the area nearby. The end R3E overlaps with the end S1E. In other words, the resin layer RS3 does not protrude further than the end S1E. In addition, the resin layer RS3 is not disposed above section 72.

[0123] It should be noted that the position of the end R3E of resin layer RS3 is not limited to... Figure 8 Examples. For example, the end R3E can also be... Figure 8 The example is located inside the island-shaped portion IP1. Additionally, the end R3E is located above section 71 of the partition 7, but it may not be located above section 71.

[0124] Sealing layer SE2 is disposed in regions A1 and A2 respectively. In this embodiment, sealing layer SE2 is equivalent to a second sealing layer. In region A1 of interest, sealing layer SE1x and resin layer RS3 are covered by sealing layer SE2. Section 71 is not in contact with sealing layer SE2. In region A2 of interest, rib layer 5 and section 72 are covered by sealing layer SE2.

[0125] Next, an example of a manufacturing method for a display device DSP will be described. Figure 9 This is a flowchart illustrating an example of a manufacturing method for a display device DSP. Figures 10A to 10J This is a schematic cross-sectional view showing the manufacturing process of the display device's DSP. Figures 10A to 10J In this paper, the main focus is on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0126] When forming the panel portion PP, firstly, a substrate 10 of the mother substrate MB is prepared, and a circuit layer 11 and an organic insulating layer 12 are formed thereon. Figure 9 The process PR1). Secondly, as Figure 10A As shown, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Figure 9 Process PR2).

[0127] Next, as Figure 10BAs shown, a rib layer 5 is formed on the entire mother substrate MB to cover the lower electrodes LE1, LE2, and LE3. Figure 9 (Process PR3). At this point in time, pixel openings AP1, AP2, and AP3 have not yet been formed on rib layer 5. Rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0128] After the rib layer 5 is formed, the process for forming the partition wall 6 is carried out. Figure 9 (Process PR4). In process PR4, such as Figure 10C As shown, a first layer L1 for forming a bottom layer 63, a second layer L2 for forming a shaft layer 64, a third layer L3 for forming a first top layer 65, and a fourth layer L4 for forming a second top layer 66 are sequentially formed on the entire mother substrate MB. Further, a photoresist R1 is disposed on the fourth layer L4. The photoresist R1 is patterned into the shape of a partition 6. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed, for example, by sputtering.

[0129] Subsequently, resist R1 is used as a mask to pattern the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning can include: wet etching to remove the portion of the fourth layer L4 exposed from the resist R1; dry etching to remove the portions of the first layer L1, the second layer L2, and the third layer L3 exposed from the resist R1; and wet etching to reduce the width of the second layer L2.

[0130] After process PR4, such as Figure 10D As shown, a partition 6 is formed in the display area DA. After the partition 6 is formed, the resist R1 is removed (stripped). In the wet etching process described above to reduce the width of the second layer L2, the second top layer 66 (the fourth layer L4) may also be slightly etched. In the case of this etch, the width of the second top layer 66 becomes smaller than the width of the first top layer 65.

[0131] Next, the process of setting pixel apertures AP1, AP2, and AP3 is performed. Figure 9 Process PR5). In process PR5, such as Figure 10E As shown, a resist R2 is formed covering the partition 6. Further, the resist R2 is used as a mask to perform dry etching on the rib layer 5. Thus, as... Figure 10F As shown, pixel openings AP1, AP2, and AP3 are formed on the rib layer 5 to expose the lower electrodes LE1, LE2, and LE3. After the above dry etching, the resist R2 is removed (stripped).

[0132] After process PR5, a process is performed to remove the rib layer 5 on the inspection pads located in the blank area FA. Figure 9 Process PR6). In process PR6, the resist at the opening of the inspection pad is applied to the rib layer 5, and the rib layer 5 is dry etched.

[0133] After process PR6, a process for forming display element DE1 is performed. Figure 9 Process PR7). When forming the display element DE1, firstly, as... Figure 10G As shown, a laminated film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through a pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed, for example, by vapor deposition. In addition, the sealing layer SE11 can be formed, for example, by CVD.

[0134] The laminate FL1 and the sealing layer SE11 are not formed only on the display area DA of each panel portion PP, but are formed on the entire mother substrate MB including the peripheral area SA. The laminate FL1 is divided into multiple parts by the hanging partitions 6. The sealing layer SE11 continuously covers each part of the laminate FL1 after the partitions and the partitions 6.

[0135] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as... Figure 10G As shown, resist R3 is disposed on the sealing layer SE11. Resist R3 covers a portion of the sub-pixel SP1 and its surrounding partition 6.

[0136] Next, an etching process using resist R3 as a mask is performed. Thus, as... Figure 10H As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R3 are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the rest are removed. Thus, the display element DE1 is formed in the sub-pixel SP1. For example, the laminated film FL1 and the sealing layer SE11 are removed in the peripheral region SA by this etching process. This etching process can include wet etching and dry etching sequentially performed on the sealing layer SE11, the capping layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R3 is removed (stripped off).

[0137] After process PR7, a process for forming display element DE2 is performed. Figure 8The process PR8). Display element DE2 can be formed using the same steps as display element DE1. That is, when forming display element DE2, a laminated film FL2 and a sealing layer SE12 are formed on the entire mother substrate MB. Figure 3 As shown, the laminated film FL2 includes an organic layer OR2 that is in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 that covers the organic layer OR2, and a capping layer CP2 that covers the upper electrode UE2.

[0138] The organic layer OR2, the upper electrode UE2, and the capping layer CP2 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE12 can be formed, for example, by CVD. The laminated film FL2 is divided into multiple sections by suspended partitions 6. The sealing layer SE12 continuously covers each section of the laminated film FL2 after the partitions and the partitions 6. By patterning such a laminated film FL2 and sealing layer SE2, as... Figure 10I As shown, a display element DE2 is formed in sub-pixel SP2. For example, the laminated film FL2 and the sealing layer SE12 are removed in the peripheral region SA by etching during this patterning process.

[0139] After process PR8, a process for forming display element DE3 is performed. Figure 9 The process PR9). Display element DE3 can be formed using the same steps as display elements DE1 and DE2. That is, when forming display element DE3, a laminated film FL3 and a sealing layer SE13 are formed on the entire mother substrate MB. Figure 3 As shown, the laminated film FL3 includes an organic layer OR3 that is in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a capping layer CP3 covering the upper electrode UE3.

[0140] The organic layer OR3, the upper electrode UE3, and the capping layer CP3 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE13 can be formed, for example, by CVD. The laminated film FL3 is divided into multiple portions by suspended partitions 6. The sealing layer SE13 continuously covers each portion of the laminated film FL3 and the partitions 6. By patterning such a laminated film FL3 and the sealing layer SE13, as... Figure 10J As shown, a display element DE3 is formed in sub-pixel SP3. For example, a portion of the laminated film FL3 and the sealing layer SE13 are removed in the peripheral region SA by etching during this patterning process.

[0141] However, in the blank area FA where multiple island-shaped portions IP are formed, the laminated film FL3 and the sealing layer SE13 remain unremoved by etching. These remaining laminated films FL3 and sealing layers SE13 are respectively equivalent to Figure 8 The laminated film FLx and the sealing layer SE1x are shown.

[0142] It should be noted that this scenario assumes that display elements DE1, DE2, and DE3 are formed in this order, but display elements DE1, DE2, and DE3 can also be formed in other orders.

[0143] Figures 11A to 11D This is a schematic cross-sectional view showing the structure of the blank area FA during the manufacturing process of the display device DSP.

[0144] In process PR4, the partition 7 (sections 71 and 72) of the remaining blank area FA is formed together with partition 6. After process PR4, as... Figure 11A As shown, there are suspended sections 71 and 72 with a lower part 61 and an upper part 62, respectively. The bottom layer 63, the shaft layer 64, the first top layer 65 and the second top layer 66 of the sections 71 and 72 are respectively obtained by processing the first layer L1, the second layer L2, the third layer L3 and the fourth layer L4 mentioned above.

[0145] Moreover, after process PR9, such as Figure 11B As shown, a laminated film FLx and a sealing layer SE1x are formed in region A1 (island portion IP). If used... Figure 8 As explained, the laminated film FLx is formed on the wall portion 71W of segment 71, the closed region CA10 of segment 71, and between adjacent segments 71. In contrast, the laminated film FLx and the sealing layer SE1x are not formed in region A2. In this way, by patterning the laminated film FL3 and the sealing layer SE13, the laminated film FLx and the sealing layer SE1x are formed in the blank region FA.

[0146] The laminated membrane FLx is thus finely segmented by segment 71. This prevents the laminated membrane FLx after the segmentation and the sealing layer SE1x covering them from peeling off from the substrate.

[0147] After step PR9, a step for forming resin layer RS1 is performed. Figure 8 Process PR10). The resin layer RS1 can be formed on the separator structure DS (e.g., by inkjet printing) for example. Figure 1 The inner side (as shown). The partition structure DS serves to block the resin layer RS1 before curing. Process PR10 includes multiple (e.g., three) coating processes.

[0148] In addition, Figure 9 In process PR10, such as Figure 11C As shown, a resin layer RS3 is formed on the sealing layer SE1x of the island portion IP. The resin layer RS3 is formed in the blank area FA (between cutting line CL1 and cutting line CL2). Specifically, the resin layer RS3 is formed at the corner CN of cutting line CL1 (e.g., Figure 5 (As shown).

[0149] More specifically, resin layer RS3 is formed in region A1. This resin layer RS3 is thinner than resin layer RS1. Specifically, resin layer RS3 is formed from fewer layers than resin layer RS1. In contrast, resin layer RS3 is not formed in region A2.

[0150] like Figure 11B As shown, droplets D are ejected from nozzle NZ toward the sealing layer SE1x to form resin layer RS3. Figure 11B The image shows the process of spraying droplets D toward the mother substrate MB during the formation of the resin layer RS3 using an inkjet method in the aforementioned process PR10.

[0151] The outer end of the ejected droplet D's range is located at the position overlapping with the sealing layer SE1x. Figure 6 as well as Figure 7 In the image, the outer end of the range of the ejected droplet D is shown as the inkjet pattern PT. The droplet D is ejected towards the inside of the inkjet pattern PT.

[0152] like Figure 6 As shown, if we focus on an island-shaped IP, the area of ​​the inkjet pattern PT is smaller than the area of ​​the island-shaped IP (region A1). Additionally, as... Figure 7 As shown, multiple segments 71 are arranged around the inkjet pattern PT.

[0153] For example, in the second direction Y, at least one segment 71 is disposed between the outermost segment 71 and segment 72 that overlap with the inkjet pattern PT. Similarly, in the first direction X, at least one segment 71 is disposed between the outermost segment 71 and segment 72 that overlap with the inkjet pattern PT. The distance between the inkjet pattern PT and the end of the sealing layer SE1x ( Figure 7 The distance shown (D1) is, for example, approximately 100 μm.

[0154] The droplets D ejected from nozzle NZ diffuse over the sealing layer SE1x, forming a resin layer RS3. At this point, the surface tension near the end S1E is used to suppress the diffusion of the resin layer RS3. Therefore, the sealing layer SE1x becomes larger than the inkjet pattern PT and is less likely to overflow from its upper surface.

[0155] In this way, by spraying droplets D onto the sealing layer SE1x, the resin layer RS3 can be positioned at the desired location. In other words, the sealing layer SE1x has the function of positioning the resin layer RS3. Figure 7 In the diagram, the areas where the resin layer RS3 is formed are marked with dotted patterns.

[0156] After process PR10, for example, a sealing layer SE2 is formed on the mother substrate MB by CVD. Figure 9 (Process PR11). The sealing layer SE1x and resin layer RS3 of the island IP are as follows. Figure 11D The area shown is covered by the sealing layer SE2. Additionally, section 72 of region A2 and rib layer 5 are also covered by the sealing layer SE2.

[0157] Therefore, as Figure 5 As shown, island-shaped portions (IPs) are formed in the blank area FA. By forming island-shaped portions (IPs) in the blank area FA, variations in the thickness of the resist applied in processes described later can be suppressed. Specifically, by arranging island-shaped portions (IPs) in the blank area FA, the velocity difference of the resist flowing in the panel portion (PP) can be reduced, thus suppressing uneven resist application. As a result, the resist reliably functions as a mask, thus preventing the layer disposed beneath the resist from being removed, and reducing the likelihood of defects in the manufactured display device DSP.

[0158] After process PR11, a process is performed to remove the rib layer 5 and the sealing layer SE2 covering the terminal portion T. Figure 9 Process PR12). Further, a process for removing the sealing layer SE2 around the terminal portion T is performed ( Figure 9 Process PR13).

[0159] After process PR13, touch panel electrodes TP are formed on the sealing layer SE2. Figure 9 The process PR14 involves, firstly, forming a conductive layer on the mother substrate MB for fabricating touch panel electrodes TP. Next, a resist of the shape corresponding to the touch panel electrodes TP is applied, and this resist is used as a mask to etch the conductive layer. After etching, the resist is removed (stripped off).

[0160] After process PR14, resin layer RS2 is formed. Figure 9 (Process PR15). The resin layer RS2 can be formed, for example, on the inside of the separator structure DS by inkjet printing. The separator structure DS functions to block the resin layer RS2 before it cures.

[0161] The resin layer RS2 can also be formed by a photolithography process. In this case, firstly, a photosensitive resin for processing into the resin layer RS2 is formed on the entire mother substrate MB. Then, through a process of pre-baking, exposing, developing, and firing the photosensitive resin, the resin layer RS2 is formed on each panel PP.

[0162] After process PR15, each panel portion PP is cut from the mother substrate MB along the cutting line CL1. Figure 9Process PR16). Further, the remaining white area FA is cut off along the cutting line CL2. Figure 9 (Process PR17). Thus, the display panel PNL is completed.

[0163] As in this embodiment, when a resin layer RS3 is formed in the blank area FA, as described above, by spraying droplets D onto the pre-positioned sealing layer SE1x and using the sealing layer SE1x to suppress the diffusion of droplets D, the resin layer RS3 can be positioned at the desired location.

[0164] Depending on the shape of the closed area (septum opening) of the partition below the sealing layer SE1x, air or other particles may remain in the closed area when the droplet D is ejected, resulting in areas where the droplet D does not flow in sufficiently in the island-shaped part IP. This can cause areas (coating peeling areas) where the resin layer RS3 is not formed to appear in part of the island-shaped part IP.

[0165] In this embodiment, a segment 71 with a partition 7 is configured in the island-shaped portion IP. Specifically, segment 71 has a closed region CA10 that is not partitioned. Compared to segment 72, the area of ​​the closed region CA10 is larger than the closed regions CA21, CA22, and CA23 of segment 72.

[0166] Therefore, as the ejected droplet D flows through, air easily escapes from the closed region CA10, allowing the droplet D to diffuse sufficiently across CA10. Specifically, since the closed region CA10 is not isolated, if the droplet D enters CA10, it can flow into the entire closed region CA10. As a result, in the island-shaped portion IP, it is less likely to occur in areas where the resin layer RS3 is not formed, and the resin layer RS3 can be formed throughout the entire island-shaped portion IP.

[0167] It should be noted that if segment 71 is also configured in the area outside the island IP (area A2), other problems will arise. That is, since the closed area CA10 of segment 71 is large, if the sealing layer SE2 is configured on top of segment 71 in area A2, the tightness of the seal with the sealing layer SE2 cannot be fully determined, which may become a reason for the sealing layer SE2 to peel off.

[0168] In this respect, in this embodiment, a section 72 of partition 7 is provided in the area outside the island portion IP (area A2). Specifically, the section 72 has partition openings 72A, 72B, and 72C that are divided into multiple partition openings.

[0169] Therefore, by configuring the sealing layer SE2 to flow into the partition wall openings 72A, 72B, and 72C respectively, the adhesion to the substrate is improved, and the peeling of the sealing layer SE2 is suppressed. It should be noted that region A2 is the region without resin layer RS3, therefore, the areas of closed regions CA21, CA22, and CA23 can be smaller than the area of ​​closed region CA10.

[0170] In this way, in the blank area FA, a region A1 (the region with segment 71) for suppressing the formation of areas where the resin layer RS3 is not formed, and a region A2 (the region with segment 72) for suppressing the peeling of the sealing layer SE2 are formed. As a result, by reliably forming the resin layer RS3 and the sealing layer SE2 in the blank area FA, the yield of the display device DSP can be improved.

[0171] In this embodiment, the sections 71 and 72 of the partition 7 are appropriately configured according to the position, shape and size of the island-shaped part IP of the FAD in the blank area, thereby improving the yield of the display device DSP.

[0172] In this embodiment, the sealing layer SE1x is disposed on the island portion IP in the blank area FA. In other words, the area where the sealing layer SE1x is disposed is reduced. In this way, by reducing the area where the sealing layer SE1x is disposed, it becomes easier to suppress the peeling of the sealing layer SE1x.

[0173] Next, other embodiments will be described. It should be noted that in the other embodiments described below, the same reference numerals are used for the same components as in the first embodiment, and detailed descriptions are sometimes omitted or simplified. Regarding the configuration of the display device DSP, which is not specifically mentioned, the same configuration as in the first embodiment can be applied.

[0174] [Second Implementation]

[0175] Figure 12 This is a schematic enlarged view showing a portion of the display device DSP according to this embodiment. Figure 12 The above is shown in the figure. Figure 7 The same location. In this embodiment, the configuration of the island-shaped portion IP differs from that in the first embodiment. In Figure 12 In the diagram, dotted patterns are marked on the areas where the sealing layer SE1x is formed. The planar shapes of segments 71 and 72 are the same as in the first embodiment. Segments 71 and 72 are arranged at intervals in the first direction X and the second direction Y.

[0176] The adjacent section 7 also has multiple segments 73 (the third segment). In this embodiment, segments 71, 72, and 73 are configured in the island-shaped portion IP. In other words, region A1 corresponds to the region configured with segments 71, 72, and 73, and region A2 corresponds to the region configured with segment 72. Segment 73 is... Figure 9 It is formed together with sections 71 and 72 in process PR4.

[0177] Multiple segments 73 are disposed between multiple segments 71 and multiple segments 72. The multiple segments 73 are configured, for example, to surround multiple segments 71. Gaps are formed between adjacent segments 73 in the first direction X and between adjacent segments 73 in the second direction Y.

[0178] Segment 73 has a different planar shape than segments 71 and 72. The plurality of segments 73 includes straight segments 731 and curved segments 732. The straight segments 731 include segments having a long side in the first direction X and segments having a long side in the second direction Y. The shapes of these segments are not limited to the examples described above and may also include segments including, for example, curved portions.

[0179] The interval between segment 71 and segment 73, and the interval between segment 73 and segment 72, are greater than the interval between adjacent segments 71 and between adjacent segments 72.

[0180] Multiple sections 73 in Figure 12 The example shown is the central portion between segment 71 and segment 72, but it is not limited to this example. When the interval between segment 71 and segment 72 is approximately 100 μm, the interval between segment 71 and segment 73, and the interval between segment 73 and segment 72, are formed, for example, to be 30 μm or more.

[0181] Figure 13 It is along Figure 12 A schematic cross-sectional view of line XIII-XIII in the diagram. Figure 13 In the middle, observe the adjacent wall 7 in the direction opposite to the first direction X.

[0182] Similar to the first embodiment, the organic insulating layer 12 and the rib layer 5 are also formed in the peripheral region SA, including the blank region FA. Figure 13 In the text, elements below the organic insulating layer 12 are omitted.

[0183] Partitions 7 (segments 71, 72, and 73) are disposed above rib layer 5. Segment 73 is identical to partition 6, comprising a lower portion 61 and an upper portion 62. The upper portion 62 of segment 73 has a wider width than the lower portion 61. The lower portion 61 of segment 73 is identical to partition 6, comprising a bottom layer 63 and an axial layer 64. The upper portion 62 of segment 73 is identical to partition 6, comprising a first top layer 65 and a second top layer 66.

[0184] The bottom layer 63, the axial layer 64, the first top layer 65, and the second top layer 66 of section 73 are formed of the same material as the bottom layer 63, the axial layer 64, the first top layer 65, and the second top layer 66 of the adjacent 6.

[0185] The sealing layer SE1x is disposed in region A1 (island portion IP) within the blank area FA, but not in region A2. Specifically, the sealing layer SE1x is configured to cover segments 71 and 72. Conversely, the sealing layer SE1x is not disposed above segment 73. In other words, segment 73 is not covered by the sealing layer SE1x. In this embodiment, for example, the end of the sealing layer SE1x covering segment 72 corresponds to the end of region A1.

[0186] Furthermore, a dam DM1 is formed between the sealing layer SE1x of covered section 71 and the sealing layer SE1x of covered section 72. Section 73 is located inside the dam DM1. Dam DM1 includes the area between section 71 and section 73, and the area between section 73 and section 72.

[0187] If we focus on the laminated membrane FLx, the laminated membrane FLx is disposed between sections 71 and 72 and the sealing layer SE1x. In contrast, the laminated membrane FLx is not disposed on section 73.

[0188] The resin layer RS3 is disposed in region A1 (island portion IP) in the blank area FA, but not in region A2. Specifically, the resin layer RS3 is disposed on top of the sealing layer SE1x disposed above section 71.

[0189] Furthermore, resin layer RS3 is also disposed above section 73. Specifically, resin layer RS3 is configured to cover section 73. In contrast, resin layer RS3 is not disposed above the sealing layer SE1x disposed above section 72. In other words, the sealing layer SE1x disposed above section 72 is in contact with sealing layer SE2.

[0190] Resin layer RS3 utilizes resin layer RS1 in display area DA ( Figure 3 (As shown) The same process and the same materials are used to form it. The range of materials coated to form the resin layer RS3 is, for example, the same as in the first embodiment.

[0191] Dam DM1 serves to block the uncured resin layer RS3. Therefore, even in the event of coating misalignment during the manufacturing process, the uncured resin layer RS3 is also blocked by dam DM1. The island portion IP includes sections 71, 72, 73, the laminated film FLx, the sealing layer SE1x, the resin layer RS3, and the sealing layer SE2.

[0192] In this embodiment, the same effects as in the first embodiment can be obtained. In this embodiment, a dam DM1 is formed in the island portion IP. As a result, since the resin layer RS3 before curing is blocked by the dam DM1, it is easy to form the resin layer RS3 within the desired range. Moreover, by configuring the dam DM1 in the section 73, it is possible to prevent the area where the dam DM1 is formed from becoming the starting point of film peeling.

[0193] It should be noted that, in Figure 13 In the example shown, dam DM1 is filled with resin layer RS3, but dam DM1 may also not be filled with resin layer RS3.

[0194] [Third Implementation]

[0195] Figure 14 This is a schematic enlarged view showing a portion of the display device DSP according to this embodiment. In this embodiment, the point covered by the sealing layer SE1x in section 73 differs from that in the second embodiment.

[0196] In this embodiment, the plurality of segments 73 covered by the sealing layer SE1x are configured to surround the plurality of segments 71. The sealing layer SE1x continuously covers the plurality of segments 73. Specifically, the sealing layer SE1x is located in the gaps between adjacent segments 73. It should be noted that the plurality of segments 73 are configured in the same way as in the second embodiment, but are not limited to this example.

[0197] Figure 15 It is along Figure 14 A schematic cross-sectional view of the XV-XV line. As described above, the sealing layer SE1x is disposed above section 73. In other views, at least a portion of the sealing layer SE1x is disposed between section 73 and resin layer RS3.

[0198] This further enhances the function of the resin layer RS3 before the dam DM1 is cured. Specifically, by configuring a sealing layer SE1x above section 73, the height H3 becomes greater than the height H2 ( Figure 13 (As shown) The height H3 is equivalent to the distance along the third direction Z from the upper surface of rib 5 to the upper surface of the sealing layer SE1x of the covering section 73, and the height H2 is equivalent to the distance along the third direction Z from the upper surface of rib 5 to the upper surface of the second top layer 66 of section 73. By increasing the height H3, the resin layer RS3 before curing is less likely to cross the sealing layer SE1x of the covering section 73.

[0199] In this embodiment, the same effects as in the second embodiment can be obtained. In this embodiment, section 73 is covered by the sealing layer SE1x. As a result, since the resin layer RS3 before curing is less likely to extend beyond the sealing layer SE1x covering section 73, it is easier to form the resin layer RS3 within the desired range compared to the second embodiment.

[0200] It should be noted that, in Figure 15 In the example shown, the dam DM1 is filled with resin layer RS3, but the dam DM1 may also not be filled with resin layer RS3.

[0201] According to the above embodiments, the yield of the display device DSP can be improved.

[0202] In this embodiment, an example is disclosed in which the blank area FA includes area A1 and area A2, but the blank area FA may also include other areas.

[0203] Furthermore, in the above embodiments, examples were disclosed where the island-shaped IP was arranged at the four corners of the blank area FA of the panel portion PP, but the arrangement of the island-shaped IP is not limited to this example. The island-shaped IP may be arranged outside the four corners of the blank area FA, or it may be arranged at both the four corners and the areas outside the four corners.

[0204] Furthermore, in the above embodiments, examples were disclosed where the thickness of resin layer RS3 was smaller than the thickness of resin layer RS1, but the thickness of resin layer RS3 could also be the same as the thickness of resin layer RS1.

[0205] Furthermore, the differences in the planar shape of these sections 71 and 72 in the above embodiments, and the situation where the resin layer RS3 is undesirably diffused compared to the sealing layer SE1x, can be visually confirmed.

[0206] Based on the display device, mother substrate, and manufacturing method described above as embodiments of the present invention, all display devices, mother substrates, and manufacturing methods that can be implemented by those skilled in the art with appropriate design modifications, as long as they contain the essence of the present invention, also fall within the scope of the present invention.

[0207] Within the scope of the present invention, various modifications will be conceived by those skilled in the art, and these modifications can also be understood to fall within the scope of the present invention. For example, any addition, deletion, or design change of constituent elements, or addition, omission, or change of processes or conditions made by those skilled in the art to the above embodiments, as long as they possess the essence of the present invention, are also included within the scope of the present invention.

[0208] Furthermore, regarding other effects brought about by the solutions described in the above embodiments, effects known from the description in this specification or effects that can be appropriately conceived by those skilled in the art can of course be understood as being brought about by the present invention.

Claims

1. A mother substrate for a display device, characterized in that, have: The display area for the image; The blank area outside the cutting line used to cut out the display area; Display elements configured in the display area; The first partition wall, comprising a plurality of first sections and a plurality of second sections, is configured in the blank area; as well as A first sealing layer, formed of an inorganic insulating material, is disposed above the display element and the first segment, but not above the second segment. The second segment has a different planar shape than the first segment.

2. The mother substrate for a display device according to claim 1, characterized in that, The first segment has the same planar shape. The second section has the same planar shape.

3. The mother substrate for a display device according to claim 2, characterized in that, The first section has a first closed region when viewed from above. The second section is a second closed region with a different planar shape than the first closed region when viewed from above.

4. The mother substrate for a display device according to claim 3, characterized in that, The second section has a larger second closed area when viewed from above than the first closed area of ​​the first section.

5. The mother substrate for a display device according to claim 4, characterized in that, The first section has a first closed region when viewed from above. The second section has multiple second closed regions when viewed from above.

6. The mother substrate for a display device according to claim 3, characterized in that, The area of ​​the first closed region is larger than the area of ​​the second closed region.

7. The mother substrate for a display device according to claim 3, characterized in that, The first section has a first wall portion that forms the first closed region. The second section has a second wall portion that forms the second closed region. The area of ​​the second wall portion is larger than the area of ​​the first wall portion.

8. The mother substrate for a display device according to any one of claims 1 to 7, characterized in that, The blank area has: The first region is configured with the first segment; and The second region is configured with the second segment.

9. The mother substrate for a display device according to claim 8, characterized in that, The blank area has multiple first areas. The second region surrounds the first region.

10. A mother substrate for a display device, characterized in that, have: The display area for the image; The blank area outside the cutting line used to cut out the display area; An inorganic insulating layer is disposed in the display area and the blank area; Display elements configured in the display area; A first partition wall comprising multiple first sections and multiple second sections is disposed above the inorganic insulating layer in the remaining blank area; The first sealing layer, which is formed of inorganic insulating material, is disposed above the display element and the first segment, but not above the second segment; as well as A resin layer is disposed on top of the first sealing layer in the blank area.

11. The mother substrate for a display device according to claim 10, characterized in that, The end of the resin layer is located above the first sealing layer.

12. The mother substrate for a display device according to claim 11, characterized in that, The end of the resin layer overlaps with the end of the first sealing layer.

13. The mother substrate for a display device according to claim 11, characterized in that, The resin layer is not disposed above the second section.

14. The mother substrate for a display device according to claim 11, characterized in that, The first segment and the second segment each have: The first lower portion disposed above the inorganic insulating layer; and A first upper part is disposed above the first lower part and protrudes from the side of the first lower part.

15. The mother substrate for a display device according to claim 14, characterized in that, It also includes a second partition, which is disposed in the display area and surrounds the display element. The second partition wall has: The second lower portion disposed above the inorganic insulating layer; and A second upper part is disposed above the second lower part and protrudes from the side of the second lower part.

16. The mother substrate for a display device according to claim 11, characterized in that, It also includes a laminated film, which comprises an organic layer contained in the display element and an upper electrode. The laminated film is disposed between the first section and the first sealing layer.

17. The mother substrate for a display device according to claim 16, characterized in that, The laminated film is disposed in the closed region of the first section.

18. The mother substrate for a display device according to claim 17, characterized in that, The laminated film is disposed between adjacent first segments.

19. The mother substrate for a display device according to claim 18, characterized in that, The laminated film also includes a capping layer disposed above the upper electrode. The cover layer is disposed in the remaining blank area.

20. The mother substrate for a display device according to any one of claims 10 to 19, characterized in that, It also includes a second sealing layer, which is formed of an inorganic insulating material and covers the resin layer and the second segment.

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