Display device

Abstract

A display device is disclosed. The display device includes a substrate including a display area and a non-display area outside the display area; a sensor portion disposed in the display area; a plurality of first transistors disposed in the display area on the substrate and configured to include an oxide semiconductor layer; and a hydrogen trapping pattern in the sensor portion and disposed adjacent to the oxide semiconductor layer of the first transistor.

Description

Technical Field

[0001] This disclosure relates to an apparatus, specifically, but not limited to, a display apparatus, and more specifically, to a light-emitting display apparatus capable of improving the sensitivity of a sensor portion and the reliability of internal components. Background Technology

[0002] Display devices that display images, such as televisions, monitors, smartphones, tablets, and laptops, are used in various ways and forms.

[0003] The display device includes multiple pixels to display images and has transistors to control the operation of each pixel.

[0004] In display devices, light-emitting display devices with light-emitting devices in the display panel without a separate light source are considered competitive applications for the sake of compactness and clear color display.

[0005] The light-emitting device includes an anode and a cathode facing each other as electrodes, and a light-emitting layer between the anode and the cathode, and may include a common layer for transporting holes and electrons to the light-emitting layer.

[0006] Furthermore, recent display devices are considering structures that include sensor components for various purposes, and various studies and developments are underway on them.

[0007] The descriptions provided in the Related Art section should not be assumed to be prior art simply because they are mentioned or related to in that section. The discussion in the Related Art section may contain information describing one or more aspects of the subject art, and the descriptions in that section do not limit the scope of this disclosure. Summary of the Invention

[0008] The purpose of this disclosure is to provide a light-emitting display device with improved sensitivity of the sensor portion.

[0009] Another object of this disclosure is to provide a light-emitting display device that can improve the reliability of transistors.

[0010] Another object of this disclosure is to provide a display device that further includes a configuration capable of preventing or reducing the effects of hydrogen or the like generated by an array structure such as adjacent thin-film transistors in a transmission region without a metallic structure, thereby improving the reliability of the transmission region and increasing the transmittance in the transmission region.

[0011] Another object of this disclosure is to provide a display device with improved reliability by further providing a hydrogen trapping pattern that can prevent or reduce the operational degradation of components caused by hydrogen generated during the process due to movement between insulating films.

[0012] Another object of this disclosure is to provide a display device in which a hydrogen trapping pattern can be formed without providing an additional layer. This hydrogen trapping pattern can reduce the component failure rate due to the flow of hydrogen that may affect the operation of the component, thereby reducing the amount of materials (e.g., gases, etchants, etc.) used in the manufacturing process for the display device, thereby reducing the generation of greenhouse gases during the manufacturing process.

[0013] Embodiments of this disclosure provide a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a sensor portion disposed in the display area; a plurality of first transistors disposed in the display area on the substrate and configured to include an oxide semiconductor layer; and a hydrogen capture pattern located on the sensor portion and disposed adjacent to the oxide semiconductor layer of the first transistors.

[0014] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0015] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0016] Figure 1 This is a plan view showing a display device according to an embodiment of the present disclosure;

[0017] Figure 2 It is shown Figure 1 A magnified view of region A1;

[0018] Figure 3 yes Figure 1 The circuit diagram of the first and second sub-pixels;

[0019] Figure 4 It is along Figure 2 A cross-sectional view taken from line I-I';

[0020] Figure 5 This is a graph showing the wavelength-dependent transmittance of the hydrogen capture pattern included in the embodiments of this disclosure;

[0021] Figure 6 This is a cross-sectional view showing a transistor and hydrogen capture pattern disposed in a region of an infrared sensor according to an embodiment of the present disclosure;

[0022] Figure 7It is a graph showing the IV characteristics of transistors in the display areas of the sensor and non-sensor portions of a display device without a hydrogen capture pattern;

[0023] Figure 8 It is a graph showing the IV characteristics of a transistor in the transmission region of a display device having a hydrogen capture pattern in the transmission region according to an embodiment of the present disclosure.

[0024] Figure 9 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure; and

[0025] Figures 10 to 12 This is a cross-sectional view of the transmission region according to various embodiments of the present disclosure. Detailed Implementation

[0026] In the following, a detailed description of preferred embodiments of the present disclosure will be given with reference to the accompanying drawings.

[0027] Reference will now be made in detail to preferred embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. In the following description of the present disclosure, detailed descriptions of known functions and configurations incorporated herein will be omitted where such descriptions might obscure the subject matter of the disclosure. Furthermore, the names of elements used in the following description are chosen for clarity of description and may differ from the names of elements in actual products.

[0028] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to illustrate various exemplary embodiments of this disclosure are given by way of example only. This disclosure is not limited to the illustrations in the accompanying drawings.

[0029] In this specification, where terms such as “comprising,” “having,” or “including” are used, one or more components may be added unless a term such as “only” is used. As used herein, the term “and / or” includes a single associated listed item as well as any and all combinations of two or more associated listed items.

[0030] When a phrase such as "at least one of..." precedes a list of elements, it may modify the entire list of elements, but may not modify any individual element in the list. The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third elements" means combinations of all three listed elements, combinations of any two of the three elements, and the individual elements, the first element, the second element, and the third element.

[0031] The terminology used herein is for the purpose of describing a particular aspect and is not intended to limit this disclosure. As used herein, the terms “a” and “an” used to describe elements in the singular form are intended to include multiple elements. Unless the context clearly indicates otherwise, elements described in the singular form are intended to include multiple elements, and vice versa.

[0032] When interpreting a component or value, the component or value should be interpreted as including a range of errors or tolerances, even if no explicit description of such range of errors or tolerances is provided.

[0033] In describing the various exemplary embodiments of this disclosure, when using terms such as "on," "above," "below," and "next to" to describe the positional relationship between two elements, at least one intermediate element may exist between the two elements unless "adjacent," "direct," or "near" is used. It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, that element or layer may be directly connected to or coupled to the other element or layer, or one or more intermediate elements or layers may exist.

[0034] In describing various exemplary embodiments of this disclosure, when using terms such as “after,” “following,” “next,” and “before” to describe the temporal relationship between two events, another event may occur between them unless more restrictive terms such as “exactly,” “immediately,” or “directly” are used.

[0035] In describing the various exemplary embodiments of this disclosure, terms such as “first” and “second” may be used to describe various components. These terms are intended to distinguish identical or similar components from one another and do not limit the components. Therefore, throughout the specification, unless otherwise specifically mentioned, a “first” component may be the same as a “second” component within the technical concept of this disclosure.

[0036] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may interoperate with each other in various ways and be technically driven. The embodiments of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0037] The advantages and features of this disclosure, and its implementation methods, will be set forth through the following exemplary embodiments described in conjunction with the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete, assisting those skilled in the art in fully understanding its scope.

[0038] Any implementation described herein as an "example" is not necessarily to be construed as superior to or better than other implementations.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant artistic context, and should not be interpreted in an idealized or overly formal manner unless explicitly defined herein. For example, the terms “component” or “unit” may be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein as would be understood by one of skill in the art.

[0040] Instead, these implementations are provided to make this disclosure thorough and complete, so as to help those skilled in the art to fully understand the scope of this disclosure.

[0041] Figure 1 This is a plan view showing a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 An enlarged view of sensor section A1. Figure 3 yes Figure 1 The circuit diagram of the first and second sub-pixels. Figure 4 It is along Figure 2 The cross-sectional view taken from line I-I'. Figure 5 This is a graph showing the wavelength-dependent transmittance of the hydrogen capture pattern included in the embodiments of this disclosure. Figure 2 Includes a magnified view of part of the MA.

[0042] like Figure 1 As shown, the display device 1000 according to an embodiment of the present disclosure includes a display panel DP, and the display panel DP may include a substrate 110. Figure 4 The drive portion is connected to a substrate 110, which includes a display area AA and a non-display area NA surrounding the display area AA. The drive portion may be integrated with an array configuration disposed in the display area AA on the substrate 110, or it may be connected to the substrate 110 using a COG (chip-on-glass) method, or it may include a printed circuit board connected to the substrate 110 via a film or connector using a COF (chip-on-film) method.

[0043] The display area AA is the area where the image is displayed. Multiple subpixels SP are set in the display area AA of the display panel DP, and the image can be displayed using the subpixels SP. In this specification, the display area AA may be referred to as the "valid area", and the non-display area NA may be referred to as the "invalid area".

[0044] The display device 1000 may include a display panel DP and a housing (not shown) housing the sides and bottom of the display panel DP. The non-display area NA of the display panel DP may be hidden by the housing or covered by a separate printed film. A printed circuit film and / or a battery may be included between the bottom of the display panel DP and the housing.

[0045] The display panel DP includes a substrate 110 and an array structure on the substrate 110. The substrate 110 can be formed of a flexible plastic material, and therefore can have flexible properties. For example, the substrate 110 may include a first organic film and a second organic film overlapping each other, with an inorganic interlayer insulating film disposed between the first organic film and the second organic film. The first organic film and the second organic film may include, for example, polyimide. In addition to polyimide, the first organic film and the second organic film may also include different organic films. As another example, the substrate 110 may include a thin glass material with flexibility.

[0046] The substrate 110 may include a first organic film and a second organic film, either of which is a PET (polyethylene terephthalate) film, and the remaining one of the first organic film and the second organic film is a polyimide film. When the first organic film and the second organic film of the substrate 110 are made of different organic materials, an adhesive film such as a pressure-sensitive adhesive (PSA) film may be included between them.

[0047] The substrate 110 is used to support and protect the components of the display device 1000 disposed thereon. The substrate 110 may include a display area AA for displaying images and a non-display area NA other than the display area AA.

[0048] The area with sub-pixels SP, such as first sub-pixel SP1 and second sub-pixel SP2, can be the display area AA (valid area), and the area other than the display area AA can be the non-display area NA.

[0049] The non-display area NA can be located outside the display area AA. The non-display area NA can also be located in the edge region surrounding the display area AA containing the displayed image. At least one driving portion configured to drive the sub-pixel SP can be located in the non-display area NA. The driving portion can include a gate-in-panel (GIP). The gate-in-panel GIP can be connected to multiple gate lines GL of the active area AA and can be configured to sequentially provide gate voltage signals to the gate lines GL. The gate-in-panel GIP can also include transistors in the same stack as the transistors disposed in the sub-pixel SP.

[0050] In the non-display area NA, various additional components can be further configured to drive sub-pixels SP in the display area AA, such as the first sub-pixel SP1 and the second sub-pixel SP2.

[0051] The display device 1000 according to embodiments of the present disclosure may include a display area AA, such as Figure 1 As shown, the display area AA includes a first area AA1 and a second area AA2. The first area AA1 includes multiple sensor parts A1 and A2, while the second area AA2 does not have any sensor parts. Therefore, the display area AA can be used to sense various functions and can also be used for display functions.

[0052] The second region AA2, which does not have a sensor portion, includes multiple first sub-pixels SP1. The first region AA1, which has a sensor portion, includes multiple second sub-pixels SP2 and a transmissive region TA. In the first region AA1 with the transmissive region TA, no light-shielding material or the like is provided in the area where the transmissive region TA is located. The density of the first sub-pixels SP1 in the second region AA2, which does not have a sensor portion, can be greater than the density of the second sub-pixels SP2 in the first region AA1, which includes sensor portions A1 and A2. The resolution of the first region AA1, which includes sensor portions A1 and A2, can be lower than the resolution of the second region AA2.

[0053] Each of sensor sections A1 and A2 may include a transmission region TA to increase sensitivity to light of various wavelengths. Sensor sections A1 and A2 are configured for various purposes and may include, for example, infrared sensors, ambient light detection sensors, fingerprint recognition sensors, cameras, biometric sensors, etc. Although in Figure 1 Two sensor sections are shown, but embodiments of this disclosure are not limited thereto. In modifications to embodiments of this disclosure, three or more sensor sections may be provided.

[0054] Sensor sections A1 and A2 are used to sense light from the top of substrate 110, and the sensing accuracy can vary depending on the amount of light received. Therefore, the areas where sensor sections A1 and A2 are located do not overlap with the light-shielding metal, allowing external light to be collected by each sensor without obstruction. Sensor sections A1 and A2 are located in display area AA and, in addition to sensing operations, also have display functions; therefore, they can include multiple second sub-pixels SP2, such as... Figure 2As shown. Wiring such as gating lines, data lines, and power supply lines for driving the second sub-pixel SP2 included in sensor sections A1 and A2 can be arranged to bypass the outer periphery of sensor sections A1 and A2. To obtain a sufficient amount of received light in sensor sections A1 and A2 via external light sensing, the area where the second sub-pixel SP2 is not located can be designated as a transmission region TA. The transmission region TA may not have a light-shielding metal. Thus, the second sub-pixel SP2 included in sensor sections A1 and A2 is locally located within sensor sections A1 and A2, and the second sub-pixel SP2 can be directly connected to gating lines, data lines, power supply lines, etc., in areas other than the transmission region TA.

[0055] In sensor sections A1 and A2, multiple second sub-pixels SP2 can be locally arranged to form a group. The group of second sub-pixels SP2 in sensor sections A1 and A2 functions as the light-emitting portion setting area PG in sensor sections A1 and A2. The light-emitting portion setting area PG can be configured not to overlap with the transmission area TA.

[0056] Multiple light-emitting areas PG can be spaced apart from each other in sensor sections A1 and A2. For example... Figure 2 As shown, the transmission region TA can be disposed between the light-emitting portion setting regions PG. In some cases, when the light-emitting portion setting region PG is disposed outside the four sides of a square at the center, an alignment key can be provided in the square inside the light-emitting portion setting region PG to align the positions of sensor portions A1 and A2 in a specific portion of the display area AA of the display panel DP. In embodiments of this disclosure, in addition to a rectangle, the shape of the light-emitting portion setting region PG or the arrangement shape of the hydrogen capture pattern 280 can be other shapes, such as circles, semicircles, polygons, or other shapes, but are not limited thereto.

[0057] The display device 1000 according to an embodiment of the present disclosure further includes a hydrogen capture pattern 280 in a transmission region TA. The hydrogen capture pattern 280 disposed in the transmission region TA of sensor portions A1 and A2 may have a transmittance dependent on the wavelength of light detected by sensor portions A1 and A2. For example, when the first sensor portion A1 is provided with an infrared sensor, the hydrogen capture pattern 280 may be made of a material with high transmittance in the infrared wavelength range. For example, when the second sensor portion A2 is provided with a camera, the hydrogen capture pattern 280 may be made of a material with high transmittance in the visible spectrum. In some cases, the ultraviolet sensor configured to sense ultraviolet light in the display region AA may be additionally configured with a different structure than that of the first sensor portion A1 and the second sensor portion A2. Sensor portions A1 and A2 may be disposed below the substrate 110, but the present disclosure is not limited thereto. Sensor portions A1 and A2 can be formed by inserting them into the substrate 110, and the structure of the sub-pixels formed on the substrate 110 further includes the functionality of sensor portions A1 and A2.

[0058] Multiple hydrogen trapping patterns 280 can be disposed in the transmission region TA. The hydrogen trapping patterns 280 are used to block hydrogen generated or flowing in the lower insulating film, and the hydrogen blocking function can be enhanced by making the width a of each hydrogen trapping pattern 280 greater than the interval s between the hydrogen trapping patterns 280.

[0059] The inventors of this disclosure have determined that when the hydrogen capture pattern 280 is made of indium zinc oxide in indium oxide, as Figure 5 As shown, the transmittance is over 99% in the infrared wavelength range, specifically at a wavelength of approximately 900 nm. The hydrogen trapping pattern 280 can be used to trap hydrogen generated in the array, thereby stabilizing the function of transistors in adjacent sub-pixels and maintaining light transmittance in the sensor portion or transmission region TA.

[0060] In addition, such as Figure 4As shown, hydrogen may be generated during the formation of insulating films 120, such as the first to tenth insulating films 122, 123, 124, 125, 126, 127, 128, 129, 130, and 131, on the substrate 110, or during the hydrogenation or heat treatment process of the first active layer 151 after film formation. Since the insulating films 120 (such as the first to tenth insulating films 122, 123, 124, 125, 126, 127, 128, 129, 130, and 131) are formed individually, the hydrogen retained in the insulating films does not flow significantly when hydrogen is included in the insulating films in the deposition chamber during the formation of each insulating film. To increase carrier mobility in the polycrystalline silicon semiconductor layer, the first active layer 151 can be hydrogenated by heat treatment to fill the voids in the first active layer 151 with the remaining hydrogen in the third to fifth insulating films 124, 125, and 126 adjacent to the upper side of the first active layer 151 and the second insulating film 123 adjacent to the lower side of the first active layer 151. For this purpose, the second to fifth insulating films 123, 124, 125, and 126 may comprise silicon nitride films with high hydrogen content.

[0061] Silicon nitride films have excellent barrier properties, but contain more hydrogen than silicon oxide films. Therefore, during the thermal processing required to manufacture the first oxide transistor OT1 and the second oxide transistor OT2, hydrogen retained in the second to fifth insulating films 123, 124, 125, and 126 located below the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2 can flow upward and escape.

[0062] The flow of hydrogen is random. In particular, the transmission region TA does not have a light-shielding metal. Since no light-shielding metal is provided on each of the first to tenth insulating films 122, 123, 124, 125, 126, 127, 128, 129, 130, 131 located on the substrate 110, hydrogen passing through the second to fifth insulating films 123, 124, 125, 126 of the polycrystalline transistor LT can flow radially and can be strongly applied to the transmission region TA.

[0063] The display device according to an embodiment of the present disclosure is configured such that an insulating film 120 disposed on a substrate is divided into a first insulating film group 120A located at a lower position and a second insulating film group 120B located at an upper position based on a second active layer 182 and a third active layer 181 made of an oxide semiconductor layer, and a hydrogen trapping pattern 280 is disposed between the first insulating film group 120A and the second insulating film group 120B in a transmission region TA. When the hydrogen trapping pattern 280 is located on the first insulating film group 120A, hydrogen retained in the first insulating film group 120A and flowing upward can be trapped by the hydrogen trapping pattern 280 with good hydrogen trapping capability, and abnormal operation of the first oxide transistor OT1 and the second oxide transistor OT2 in response to hydrogen can be prevented or reduced.

[0064] Additionally, the second light-shielding pattern 162 of the first oxide transistor OT1 and the third light-shielding pattern 173 of the second oxide transistor OT2 may include a metal such as titanium, which has hydrogen-capturing properties, thereby preventing hydrogen from transferring from the first insulating film group 120A to the second active layer 182 and the third active layer 181 in the vertical direction.

[0065] The seventh insulating film 128, or the sixth insulating film 127 and the seventh insulating film 128, which are in direct contact with the underside of the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2, may include a silicon oxide film having a lower hydrogen content than the silicon nitride film, so as to be able to interlayer block hydrogen generated from the first to fifth insulating films 122, 123, 124, 125, 126 of the polycrystalline transistor LT.

[0066] Because the transistor density in the transmission region TA is low or zero, a large number of channels through which hydrogen can move can be formed. In embodiments of this disclosure, a hydrogen trapping pattern 280 can be disposed in the transmission region TA, so that hydrogen generated from the polycrystalline transistor LT can be trapped by the hydrogen trapping pattern 280 in the transmission region TA, thereby blocking the flow of hydrogen and preventing or reducing the transfer of hydrogen to the oxide transistors OT1 and OT2.

[0067] The first region AA1, where sensor portions A1 and A2 are located, includes a transmissive region TA that does not have light-shielding metal or a second sub-pixel SP2, and therefore has a lower transistor density than the second region AA2, where the first sub-pixel SP1 is densely arranged.

[0068] The second sub-pixel SP2 of the first region AA1, which includes sensor portions A1 and A2, and the first sub-pixel SP1 of the second region AA2, which does not have a sensor portion, may include the same circuit configuration, for example, as Figure 3As shown in the diagram. In some cases, the first region AA1 of sensor portions A1 and A2 and the second region AA2 without sensor portions can compensate for the brightness of the region including the transmission region TA by utilizing a small number of transistors with a relatively low arrangement density in sensor portions A1 and A2, depending on the difference in transistor arrangement density. For example, the size of the light-emitting device or the size of the transistor in at least one second sub-pixel SP2 in the first region AA1 can be increased. Alternatively, even when the transistors in the second sub-pixel SP2 of the first region AA1 including sensor portions A1 and A2 and the first sub-pixel SP1 in the second region AA2 without sensor portions can have the same layer structure, the width / length or carrier mobility of at least one active layer can be changed. However, embodiments of this disclosure are not limited thereto.

[0069] The hydrogen trapping pattern 280 included in the transmission region TA can be disposed adjacent to the second sub-pixel SP2, which has a low setting density, in the sensor portions A1 and A2, thereby preventing or reducing hydrogen inflow to the second sub-pixel SP2 side and reaching the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2. When the hydrogen trapping pattern 280 has a higher hydrogen trapping capability than the second active layer 182 and the third active layer 181, the hydrogen trapping pattern 280 further enhances the hydrogen blocking effect on the second active layer 182 and the third active layer 181.

[0070] The embodiments disclosed herein are not limited to the configuration where the transmission region TA is disposed in the sensor portions A1 and A2. For example, the transmission region TA may be disposed in a second region AA2 that does not have a sensor portion, and a hydrogen trapping pattern 280 may also be disposed in this transmission region TA. In short, a hydrogen trapping pattern 280 with high transmittance can be disposed in the transmission region TA of the transparent display device. Thus, the hydrogen trapping pattern 280 disposed in the transmission region TA of the transparent display device can be made of a material with high transmittance in the visible spectrum (e.g., at wavelengths of 400 nm to 700 nm). For example, when the hydrogen trapping pattern 280 is made of indium oxide, such as Figure 5 As shown, the hydrogen capture pattern 280 can have a transmittance of approximately 85% or more.

[0071] Examples of indium oxides used for the hydrogen capture pattern 280 include indium oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide. However, in embodiments of this disclosure, the material used for the hydrogen capture pattern 280 may not be limited to indium oxides. The material used for the hydrogen capture pattern 280 may be varied depending on the wavelength of the light received or sensed by the sensor portions A1 and A2. When the sensor portions have light-receiving characteristics for any wavelength of infrared, visible, and ultraviolet light, materials that selectively transmit light of the corresponding wavelength may be used.

[0072] Furthermore, the hydrogen capture pattern 280 disposed in the transmission region TA can be configured to be adjacent on a plane to the second active layer 182 of the first oxide transistor OT1 or the third active layer 181 of the second oxide transistor OT2 disposed in the second sub-pixel SP2 in the transmission region TA of the sensor portions A1 and A2. In embodiments of this disclosure, the hydrogen capture pattern 280 may be located on the same plane as or coplanar with the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2.

[0073] The sub-pixels SP in the effective area AA, including the first sub-pixel SP1 and the second sub-pixel SP2, may include, for example, a first transistor T1, a second transistor T2, a storage capacitor Cst, a compensation circuit CC, and a light-emitting device ED, such as... Figure 3 As shown in the image.

[0074] For example, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor.

[0075] The first electrode (e.g., drain electrode) of the first transistor T1 is electrically connected to the data line DL, and the second electrode (e.g., source electrode) of the first transistor T1 is electrically connected to the first node N1. The gate electrode of the first transistor T1 is electrically connected to the gating line GL. The first transistor T1 is used to transmit a data signal provided via the data line DL to the first node N1 in response to a scan signal provided via the gating line GL.

[0076] The storage capacitor Cst is electrically connected to the first node N1 and is charged by the voltage applied to the first node N1.

[0077] The first electrode (e.g., the drain electrode) of the second transistor T2 receives a high-potential drive voltage EVDD, and the second electrode (e.g., the source electrode) of the second transistor T2 is electrically connected to the first electrode (e.g., the anode electrode) of the light-emitting device ED. The second transistor T2 can be used to control the amount of drive current flowing to the light-emitting device ED in response to the voltage applied to the gate electrode.

[0078] The semiconductor layer of the first transistor T1 and / or the second transistor T2 may include silicon such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polycrystalline silicon (poly-Si), or may include oxides such as IGZO (indium gallium zinc oxide), but this disclosure is not limited thereto. At least one of the first transistor T1 and the second transistor T2 may include an oxide semiconductor layer, thereby enabling formation at low temperatures compared to using other materials, maintaining amorphous properties, and exhibiting high carrier mobility.

[0079] An LED (Emitting Diode) is used to output light corresponding to a driving current. An LED can output light corresponding to any color selected from red, green, blue, and white.

[0080] A light-emitting device (ED) may include an anode, a light-emitting layer disposed on the anode, and a cathode configured to be connected to a low-potential driving voltage (EVSS) or a common voltage. The light-emitting layer may be configured to emit light of the same color, such as white light, for each pixel, or to emit light of different colors, such as red, green, or blue light, for each sub-pixel (SP).

[0081] The light-emitting device (ED) can be a top-emitting diode or a bottom-emitting diode.

[0082] A compensation circuit CC can be disposed in sub-pixel SP to compensate for the threshold voltage of the second transistor T2, etc. The compensation circuit CC can be composed of one or more transistors. The compensation circuit CC may include one or more transistors and capacitors, and can be configured in various ways depending on the compensation method. Sub-pixels including the compensation circuit CC may include circuits with various structures having different numbers of transistors and / or capacitors, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0083] Figure 4 The second sub-pixel SP2 is shown, comprising both polycrystalline transistor LT and oxide transistors OT1 and OT2. Figure 4 The sub-pixel represents the second sub-pixel SP2 adjacent to the transmission region TA. The first sub-pixel SP1 in the second region AA2 (where sensor portions A1 and A2 are not located) can also have the same... Figure 4 The second sub-pixel SP2 has the same construction.

[0084] like Figure 4 As shown, the polycrystalline transistor LT may include a first active layer 151 made of polycrystalline silicon on a substrate 110, a first gate electrode 161 overlapping the first active layer 151, and a first source / drain electrode 171 spaced apart from the first gate electrode 161 and disposed above the first active layer 151.

[0085] The first light-shielding pattern 141 may be disposed below the first active layer 151 of the polycrystalline transistor LT to prevent or reduce light incident on the first active layer 151 due to light on the underside of the substrate 110.

[0086] Figure 4The polytransistor LT illustrated shows, for example, a state where the first gate electrode 161 and the first light-shielding pattern 141 are electrically connected by the first connection electrode 172. When the first light-shielding pattern 141 and the first gate electrode 161 are electrically connected, fast operation can be easily achieved, and the on-current can be increased by dual-gate drive. However, the shape of the polytransistor LT in the display device 1000 according to embodiments of the present disclosure is not limited to this. Another source / drain electrode may be connected to the first active layer 151. The first source / drain electrode 171 and the other source / drain electrode may be symmetrically positioned about the first active layer 151.

[0087] A first insulating film 122, which serves as a buffer layer, can be provided between the substrate 110 and the first light-shielding pattern 141 to prevent or reduce the transfer of impurities included in the substrate 110 or impurities introduced from the lower side through the substrate 110 to the upper array.

[0088] The first oxide transistor OT1 and the second oxide transistor OT2 may be located at least above the first active layer 151 of the polycrystalline transistor LT. This is to form the oxide transistors OT1 and OT2 after crystallization is completed, so as to prevent or reduce the heat generated during crystallization from affecting the oxide transistors OT1 and OT2 when heat treatment is performed at a temperature higher than or equal to the specific temperature used for crystallization after the first active layer 151 of the polycrystalline transistor LT is formed in an amorphous state on the substrate 110.

[0089] The first oxide transistor OT1 and the second oxide transistor OT2 disposed in the second sub-pixel SP2 can have different structures depending on their characteristics. The first oxide transistor OT1 may include a second active layer 182 made of oxide semiconductor, a second gate electrode 191 overlapping the second active layer 182, and a second source / drain electrode 202 and a third source / drain electrode 203 spaced apart from the second gate electrode 191 and disposed on both sides of the second active layer 182. The second oxide transistor OT2 may include a third active layer 181 made of oxide semiconductor, a third gate electrode 192 overlapping the third active layer 181, and a fourth source / drain electrode 204 and a fifth source / drain electrode 205 spaced apart from the third gate electrode 192 and disposed on both sides of the third active layer 181. By adjusting the distance from the second light-shielding pattern 162 and the third light-shielding pattern 173 disposed below the second active layer 182 and the third active layer 181, and / or the connection between the third light-shielding pattern 173 and the fifth source / drain electrode 205, the first oxide transistor OT1 and the second oxide transistor OT2 can have different characteristics.

[0090] In some cases, the first oxide transistor OT1 can be used to increase the conduction current by connecting the second gate electrode 191 and the second light-shielding pattern 162, and can have high speed characteristics.

[0091] The second light-shielding pattern 162 of the first oxide transistor OT1 can be on the same layer as the first gate electrode 161 of the polycrystalline transistor LT, and the third light-shielding pattern 173 of the second oxide transistor OT2 can be on the same layer as the first source / drain electrode 171 and the first connection electrode 172 of the polycrystalline transistor LT.

[0092] According to embodiments of this disclosure, the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2 can have different carrier mobilities. For example, the second active layer 182 can have a higher carrier mobility than the third active layer 181. To change the carrier mobility, the second active layer 182 may further include an oxide semiconductor layer compared to the third active layer 181.

[0093] Refer to the attached figures (including) Figure 2 The first sensor portion A1 may include a transmissive region TA and a light-emitting portion setting region PG. In embodiments of this disclosure, the area of ​​the transmissive region TA may differ from the area of ​​the light-emitting portion setting region PG. For example, the area of ​​the transmissive region TA may be larger than the area of ​​the light-emitting portion setting region PG, but is not limited thereto. Furthermore, the area of ​​the transmissive region TA may differ from the area of ​​the hydrogen capture pattern 280. For example, the area of ​​the transmissive region TA may be larger than the area of ​​the hydrogen capture pattern 280, but is not limited thereto. That is, the total area of ​​the hydrogen capture pattern 280 may be smaller than the area of ​​the transmissive region TA. Furthermore, the total area of ​​the hydrogen capture pattern 280 may be larger than the size of the light-emitting portion setting region PG.

[0094] In embodiments of this disclosure, the size of a segment of the hydrogen capture pattern 280 may differ from the area size of at least one of the first active layer 151, the second active layer 182, and the third active layer 181. For example, some or all segments of the hydrogen capture pattern 280 may be larger than, or smaller than, the area size of at least one of the first active layer 151, the second active layer 182, and the third active layer 181. In other embodiments of this disclosure, some segments of a portion of the hydrogen capture pattern 280 may be larger than the area size of at least one of the first active layer 151, the second active layer 182, and the third active layer 181, and some segments of the hydrogen capture pattern 280 may be smaller than the area size of at least one of the first active layer 151, the second active layer 182, and the third active layer 181.

[0095] In embodiments of this disclosure, the segments of the hydrogen capture pattern 280 may have different sizes or areas. For example, some segments of the hydrogen capture pattern 280 may be larger or smaller than other segments of the hydrogen capture pattern 280. In embodiments of this disclosure, segments of different sizes of the hydrogen capture pattern 280 may be set based on the specific pattern in the transmission region TA. For example, larger segments of the hydrogen capture pattern 280 may be set closer to the light-emitting portion setting region PG or the second sub-pixel SP2, and vice versa. In other embodiments of this disclosure, smaller segments of the hydrogen capture pattern 280 may be located between larger segments of adjacent hydrogen capture patterns 280, but are not limited thereto. Furthermore, the second sub-pixel SP2 may be located within the light-emitting portion setting region PG. In embodiments of this disclosure, the hydrogen capture pattern 280 may surround the light-emitting portion setting region PG in the first sensor portion A1, or the light-emitting portion setting region PG may surround the hydrogen capture pattern 280, or both.

[0096] Furthermore, the segments of the hydrogen capture pattern 280 can have different thicknesses, or the thickness within the same segment can be varied to have different thicknesses. For example, the thickness of a smaller segment of the hydrogen capture pattern 280 can be greater than the thickness of a larger segment, and vice versa. When the segments of the hydrogen capture pattern 280 have different thicknesses, the thicker portions can be located at the periphery, while the thinner portions can be located in the middle of the segment, and vice versa, but this is not a limitation.

[0097] In embodiments of this disclosure, the individual segments of the hydrogen capture pattern 280 may have different hydrogen capture capabilities based on, for example, but not limited to, different densities or constituent materials.

[0098] In embodiments of this disclosure, the pattern or arrangement of the segments of the hydrogen capture pattern 280 can vary. For example, the segments of the hydrogen capture pattern 280 do not necessarily have to be arranged in a matrix pattern, but can be arranged in, for example, but not limited to, a circular pattern or other patterns.

[0099] The polysilicon transistor LT and the first oxide transistor OT1 can be Figure 3 The first transistor T1 shown is either a switching transistor capable of fast operation. The polycrystalline transistor LT and the first oxide transistor OT1 can receive an EM signal from the light-emitting control line or a scan signal from the gating line GL. The second oxide transistor OT2, having a third active layer 181 with a lower carrier mobility than the second active layer 182, can obtain a range of gating voltage (Vgs) variation from the off state to the on state in the IV curve and contributes to grayscale representation; therefore, it can be used as a driving transistor configured to provide drive current to the light-emitting device ED. Figure 3 In the sub-pixel SP, the second oxide transistor OT2 can be used as the second transistor T2.

[0100] exist Figure 4 In the diagram, the fifth source / drain electrode 205, connected to the third active layer 181 of the second oxide transistor OT2, is shown connected to a third light-shielding pattern 173, which extends further from one side than the third active layer 181 and is located lower than the third active layer 181. This stabilizes the potential of the third light-shielding pattern 173 and prevents or reduces the effects of parasitic capacitance in the third active layer 181. This configuration is exemplary, and in some cases, the third active layer 181 and the third light-shielding pattern 173 can be electrically isolated from each other.

[0101] like Figure 4 As shown, the hydrogen trapping pattern 280 disposed in the transmission region TA can be on the same layer as the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2. However, the embodiments of this disclosure are not limited thereto. For example, the hydrogen trapping pattern 280 in the transmission region TA can be located on a different layer than the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2, for example, a layer above or below the layer having the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2.

[0102] Thus, the hydrogen trapping pattern 280 may comprise the same material as the oxide semiconductor layers of the second active layer 182 and the third active layer 181. However, the display device according to embodiments of this disclosure is not limited thereto. The material of the hydrogen trapping pattern 280 may be replaced by any material that has hydrogen trapping functionality but does not impair the light receiving sensitivity of sensor portions A1, A2 or the transmittance of the transmission region TA. In some cases, the hydrogen trapping pattern 280 may comprise a material having a higher hydrogen trapping capability than the second active layer 182 and the third active layer 181. The hydrogen trapping pattern 280 may be formed by changing the composition ratio of the oxide semiconductor or adjusting the thickness during the formation of the second active layer 182 and the third active layer 181, thereby increasing the transmittance of light at a specific wavelength.

[0103] The transmission region TA where the hydrogen capture pattern 280 is located is a region without any light-shielding metal. When hydrogen generated from the array in the adjacent sub-pixel SP1 flows upward, the hydrogen is captured by the hydrogen capture pattern 280, which has excellent hydrogen capture capability, thereby preventing or reducing the operational degradation of the oxide transistors OT1 and OT2, including the oxide semiconductors around or on the hydrogen capture pattern 280.

[0104] The polycrystalline transistor LT, the first oxide transistor OT1, and the second oxide transistor OT2 include an insulating film to insulate the first light-shielding pattern 141, the second light-shielding pattern 162, the third light-shielding pattern 173 from the first active layer 151, the second active layer 182, the third active layer 181; the first active layer 151, the second active layer 182, the third active layer 181 from the first gate electrode 161, the second gate electrode 191, the third gate electrode 192; and the first gate electrode 161, the second gate electrode 191, the third gate electrode 192 from the first source / drain electrode 171 to the fifth source / drain electrode 202, 203, 204, 205.

[0105] Reference Figure 4 The layer structure of the display device is described below.

[0106] Multiple insulating films 120 (such as the first to tenth insulating films 122, 123, 124, 125, 126, 127, 128, 129, 130, 131) can be stacked on the display area AA and non-display area NA of the substrate 110, so that the active layers 151, 182, 181 and electrodes 161, 191, 192, 171, 172, 202, 203, 204, 205 constituting transistors LT, OT1, OT2 can be insulated from each other.

[0107] A first insulating film 122 is disposed on the display area AA and the non-display area NA on the substrate 110. The first insulating film 122 may be referred to as a buffer film and may have the same function as buffer films known in the art. The first insulating film 122 may be disposed on the substrate 110 to protect the structure located on the substrate 110 from the influence of moisture that permeates through the substrate 110 and to planarize the surface of the substrate 110.

[0108] The first insulating film 122 may be disposed up to the edge of the substrate 110 to prevent or reduce the penetration of moisture from the edge of the substrate 110. The first insulating film 122 may be a single inorganic film or may be composed of multiple inorganic films stacked alternately.

[0109] For example, the first insulating film 122 may include at least one inorganic film of silicon oxide film (SiOx), silicon nitride film (SiNx) or silicon oxynitride film (SiOxNy), or may include a multilayer film in which the above-mentioned inorganic films are stacked.

[0110] The first light-shielding pattern 141 may be disposed on the first insulating film 122. For example, the first light-shielding pattern 141 may be made of a conductive metal material, and the conductive metal material may include at least one selected from aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The conductive metal material may be provided in a single-layer or multi-layer structure.

[0111] The second insulating film 123 may be disposed on the first light-shielding pattern 141 and the first insulating film 122. The second insulating film 123 may be used as, for example, a second buffer layer. The second insulating film 123 may include an inorganic film, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer film composed thereof.

[0112] A first active layer 151 made of polycrystalline silicon can be disposed on the second insulating film 123. The first active layer 151 can be polycrystalline by depositing amorphous silicon on the second insulating film 123 and then crystallizing it.

[0113] A third insulating film 124 may be disposed on the first active layer 151 and the second insulating film 123. The third insulating film 124 may be used as the gate insulating film of a polycrystalline transistor LT. The third insulating film 124 may include an inorganic material. The inorganic material may include, for example, a silicon nitride film (SiNx).

[0114] The first gate electrode 161 and the second light-shielding pattern 162 can be disposed on the third insulating film 124. The first gate electrode 161 and the second light-shielding pattern 162 can be formed of, for example, a conductive metal material. Specifically, the conductive metal material can include at least one selected from aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The conductive metal material can be provided in a single-layer or multi-layer structure.

[0115] The fourth insulating film 125 and the fifth insulating film 126 can be disposed on the third insulating film 124. The fourth insulating film 125 and the fifth insulating film 126 can be made of inorganic insulating materials. For example, the fourth insulating film 125 can be a silicon nitride film, and the fifth insulating film 126 can be a silicon oxide film. The fourth insulating film 125 and the fifth insulating film 126 can also be used as interlayer insulating films for polycrystalline transistors (LTs).

[0116] The first source / drain electrode 171 and the first connection electrode 172 may be formed on the fifth insulating film 126 using a conductive metal material. Specifically, the conductive metal material may include at least one selected from aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The conductive metal material may be provided in a single-layer or multi-layer structure.

[0117] The first source / drain electrode 171 can be connected to the first active layer 151 through contact holes 171a formed in the fifth insulating film 126, the fourth insulating film 125 and the third insulating film 124.

[0118] For example, the first connecting electrode 172 can be connected to the first gate electrode 161 through contact holes 172a formed in the fifth insulating film 126 and the fourth insulating film 125, and can be connected to the first light-shielding pattern 141 through contact holes 172b formed in the fifth insulating film 126, the fourth insulating film 125, the third insulating film 124 and the second insulating film 123.

[0119] The third light-shielding pattern 173 can be disposed on the fifth insulating film 126 using the same material as the first source / drain electrode 171 and the first connecting electrode 172.

[0120] The sixth insulating film 127 and the seventh insulating film 128 may be disposed on the fifth insulating film 126. The sixth insulating film 127 and the seventh insulating film 128, comprising inorganic insulating materials, can be used to protect the polycrystalline transistor LT and achieve surface planarization of the first oxide transistor OT1 and the second oxide transistor OT2, and can also serve as buffer films. For example, to prevent or reduce the impact of hydrogen flow caused by the insulating film included in the polycrystalline transistor LT on the first oxide transistor OT1 and the second oxide transistor OT2, at least the seventh insulating film 128 (which is in contact with the lower surface of the second active layer 182 of the first oxide transistor OT1 and the third active layer 181 of the second oxide transistor OT2) may be a silicon oxide film. The sixth insulating film 127 may be a silicon oxide film or a silicon nitride film.

[0121] The second active layer 182 and the third active layer 181 are formed on the seventh insulating film 128 using an oxide semiconductor. This oxide semiconductor can be formed by a combination of at least one metal selected from the group consisting of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) with an oxide. In some cases, the oxide semiconductor material may further include a metal with high conductivity, such as iron (Fe), thereby increasing carrier mobility.

[0122] More specifically, examples of oxide semiconductor materials constituting the second active layer 182 and the third active layer 181 include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), iron indium zinc oxide (FIZO), etc.

[0123] Additionally, a hydrogen-capturing pattern 280 is disposed on the seventh insulating film 128 corresponding to the transmission region TA. The hydrogen-capturing pattern 280 selectively transmits light received or sensed by the transmission region TA or sensor portions A1, A2, and can be made of, for example, indium oxide. The hydrogen-capturing pattern 280 may include a material having a higher hydrogen-capturing capability than the oxide semiconductor forming the second active layer 182 and the third active layer 181, to further prevent or reduce hydrogen transfer to the second active layer 182 and the third active layer 181 disposed at the second sub-pixel SP2 adjacent to the transmission region TA.

[0124] An eighth insulating film 129 is disposed on the hydrogen capture pattern 280, the second active layer 182, and the third active layer 181. The eighth insulating film 129 can be used as the gate insulating film for the first oxide transistor OT1 and the second oxide transistor OT2. The eighth insulating film 129 comprises an inorganic insulating material. The eighth insulating film 129 can be a silicon oxide film to minimize or reduce the impact of hydrogen on the second active layer 182 and the third active layer 181.

[0125] As illustrated, the eighth insulating film 129 can be formed to cover the hydrogen trapping pattern 280 and the upper and side surfaces of the second active layer 182 and the third active layer 181 made of oxide semiconductor. The eighth insulating film 129 can be formed by extending to the side surfaces throughout the entire display area AA and the non-display area NA. In some cases, the eighth insulating film 129 can be disposed only between the channel regions of the second active layer 182 and the third active layer 181 and the subsequently formed second gate electrode 191 and third gate electrode 192.

[0126] The eighth insulating film 129 can be configured as a multilayer structure. When the eighth insulating film 129 has a multilayer structure, the insulating film in contact with the second active layer 182 and the third active layer 181 can be an inorganic insulating film with a low hydrogen content.

[0127] The second gate electrode 191 and the third gate electrode 192, which overlap with the corresponding portions of the second active layer 182 and the third active layer 181, can be disposed on the eighth insulating film 129.

[0128] The second gate electrode 191 and the third gate electrode 192 can be formed of a conductive metal material. Specifically, the conductive metal material may include at least one selected from aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The second gate electrode 191 and the third gate electrode 192 may have a multilayer film structure comprising at least two conductive metal materials. The conductive metal materials may be provided in a single-layer or multilayer structure.

[0129] When the second gate electrode 191 and the third gate electrode 192 are used as mask impurities to dope the second active layer 182 and the third active layer 181, the channel of the second gate electrode 191 and the third gate electrode 192 can be the region overlapping with the second gate electrode 191 and the third gate electrode 192. The region of the second active layer 182 and the third active layer 181 that overlaps with the second gate electrode 191 and the third gate electrode 192 is not doped with impurities and serves as the channel of the oxide semiconductor layer.

[0130] Then, the doped regions in the second active layer 182 and the third active layer 181 can be connected to the mutually spaced second source / drain electrodes 202 and 203, as well as the fourth source / drain electrode 204 and the fifth source / drain electrode 205, and can be used as conductive power drain regions.

[0131] The ninth insulating film 130 and the tenth insulating film 131 can be sequentially formed on the second gate electrode 191, the third gate electrode 192, and the eighth insulating film 129.

[0132] The ninth insulating film 130 and the tenth insulating film 131 may be inorganic insulating films. For example, the ninth insulating film 130 and the tenth insulating film 131 may include at least one inorganic material selected from silicon oxide film (SiOx), silicon nitride film (SiNx), and silicon oxynitride film (SiOxNy).

[0133] A second connection electrode 201 can be formed on the tenth insulating film 131 using a conductive metal material to protect and cover the first source / drain electrode 171. Specifically, the conductive metal material may include at least one selected from aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The conductive metal material may be provided in a single-layer or multi-layer structure.

[0134] The second connection electrode 201 can be connected to the first source / drain electrode 171 through contact holes formed in the tenth insulating film 131, the ninth insulating film 130, the eighth insulating film 129, the seventh insulating film 128, and the sixth insulating film 127, and can have both conductive and protective functions for the first source / drain electrode 171. Furthermore, the second connection electrode 201 can be located around the transmission region TA and can be used to block impurities such as hydrogen retained in the sixth to tenth insulating films 127, 128, 129, 130, and 131 at the second sub-pixel SP2 from transferring to the insulating film on the adjacent side.

[0135] The second source / drain electrode 202 and the third source / drain electrode 203 are connected to the second active layer 182 through contact holes formed in the tenth insulating film 131, the ninth insulating film 130 and the eighth insulating film 129.

[0136] The fourth source / drain electrode 204 and the fifth source / drain electrode 205 are connected to the third active layer 181 through contact holes formed in the tenth insulating film 131, the ninth insulating film 130, and the eighth insulating film 129. The fifth source / drain electrode 205 may extend further outward than the third active layer 181 and can be connected to the third light-shielding pattern 173 located at a position lower than the third active layer 181 through contact holes formed in the tenth insulating film 131, the ninth insulating film 130, the eighth insulating film 129, the seventh insulating film 128, and the sixth insulating film 127.

[0137] Referring to the attached figures and experiments, the principle of the hydrogen capture pattern 280 in the transmission region TA is described as follows.

[0138] Figure 6 This is a cross-sectional view showing a transistor and hydrogen capture pattern disposed in a region of an infrared sensor IRS according to an embodiment of the present disclosure.

[0139] Figure 6 The diagram shows a sensor portion of an infrared sensor (IRS) disposed beneath a substrate 110. A first insulating film group 120A is disposed between the substrate 110 and a second active layer 182 made of an oxide semiconductor material, and a second insulating film group 120B is disposed on the second active layer 182. The first insulating film group 120A may include components located on a polycrystalline transistor (LT). Figure 4 The lower insulating film 1200A below the first source / drain electrode 171 and the upper insulating film 1200B located on the first source / drain electrode 171.

[0140] The lower insulating film 1200A includes a silicon nitride film, and through heat treatment in the hydrogenation process, the pores in the first active layer 151 made of polycrystalline silicon can be filled by hydrogen included in the lower insulating film 1200A.

[0141] Furthermore, unlike polycrystalline silicon, the second active layer 182 or the third active layer 181, which controls carrier mobility through pores in the oxide semiconductor, can be used to prevent or reduce the influence of hydrogen (H) from the contacting insulating film by making the upper insulating film 1200B of the first insulating film group 120A a silicon oxide film, maintain internal pores, and prevent or reduce changes in electrical properties.

[0142] Furthermore, the second insulating film group 120B may include an interlayer insulating film 1200C and an eighth insulating film 129 closest to the second active layer 182 made of oxide semiconductor material. The eighth insulating film 129 is in direct contact with the second active layer 182 and can be used as a gate insulating film, and may be made of a silicon oxide film having low hydrogen transfer capability to the second active layer 182.

[0143] like Figure 6 As shown, a hydrogen trapping pattern 280, made of indium oxide or the like with excellent infrared transmittance, is disposed around the second active layer 182 of the oxide transistor OT. When hydrogen H retained in the first insulating film group 120A between the substrate 110 and the second active layer 182 flows upward during a process such as heat treatment of the oxide transistor OT, the hydrogen H can be trapped by the hydrogen trapping pattern 280 around the oxide transistor OT. In addition, when the hydrogen trapping pattern 280 has a higher hydrogen trapping capability than the second active layer 182, it is possible to prevent or reduce changes in the characteristics of the oxide transistor OT including the second active layer 182 due to the dense application of hydrogen H to the second active layer 182.

[0144] In addition, the hydrogen capture pattern 280 has an infrared transmittance of about 99% and can capture hydrogen without reducing the infrared sensitivity of the infrared sensor IRS.

[0145] Figure 7 It is a graph showing the IV characteristics of transistors in the effective regions of the sensor and non-sensor portions of a display device without a hydrogen capture pattern. Figure 8 This is a graph showing the IV characteristics of a transistor in the transmission region of a display device having a hydrogen capture pattern in the transmission region according to an embodiment of the present disclosure.

[0146] like Figure 7 As shown, in Figure 1 In the display device, when the sensor portion does not have a hydrogen capture pattern, the effective area outside the sensor portion includes densely arranged sub-pixels SP1 without a transmission area, and the oxide transistor SP1 TR in the transistor in the effective area outside the sensor portion includes an active layer made of oxide semiconductor material, which to some extent blocks hydrogen from the interlayer insulating film of the lower polycrystalline transistor, so that the current change dependent on the gate voltage change has on / off characteristics.

[0147] On the other hand, Figure 1 In the display device, when the sensor portion does not have a hydrogen capture pattern, the effective area in the sensor portion does not include the sub-pixel SP2 disposed in the transmission area. Therefore, the arrangement density of the transistor SP2 TR in the sensor portion is low, and the active layer of the oxide transistor in the sensor portion, made of oxide semiconductor material, is sparsely arranged. This causes hydrogen passing through the first insulating film group 120A to be strongly applied to the transistor SP2 TR in the sensor portion, resulting in the active layer made of oxide semiconductor material losing its internal channel characteristics and becoming conductive, similar to... Figure 7 The transistor SP2 TR in the sensor section.

[0148] like Figures 1 to 4 As shown, the display device according to an embodiment of the present disclosure includes a hydrogen trapping pattern 280 disposed in the transmission region, thereby preventing hydrogen from flowing into the oxide semiconductor layer of transistors disposed at a low density around the transmission region in the sensor portion, so that the transistors in the sensor portion can stably maintain on / off characteristics dependent on changes in the gate voltage, such as... Figure 8 As shown in the image.

[0149] Figure 9 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0150] like Figure 9 As shown, with Figure 4 Compared to the structure of the display device described in the previous section, the display device 1000 according to the embodiments of the present disclosure is configured to further include a light-emitting device 300 connected to a second oxide transistor OT. Figure 3 (ED in the text).

[0151] Describe any additional configurations besides the same configurations described above.

[0152] like Figure 9 As shown, the planarization film 135 can be disposed above transistors LT, OT1, and OT2. The planarization film 135 can be disposed on the second connection electrode 201 and the second source / drain electrodes to the fifth source / drain electrodes 202, 203, 204, and 205 to achieve surface planarization.

[0153] The planarization film 135 may include an organic material. This organic material may include at least one selected from acrylic resins, phenolic resins, polyimide resins, unsaturated polyester resins, polyamide resins, benzocyclobutene resins, polyphenylene sulfide resins, and polyphenylene sulfide resins.

[0154] The planarization film 135 can have a single-layer or multi-layer structure. When the planarization film 135 has a multi-layer structure, some layers of the planarization film are also provided with connecting electrodes, and the fourth source / drain electrode 204 located at the bottom and the first electrode 310 of the light-emitting device ED can be connected.

[0155] Light-emitting device 300 ( Figure 3 The ED can be set on the planarization film 135.

[0156] The first electrode 310 is further disposed on the planarization film 135 and can be connected to one of the second to fifth source / drain electrodes 202, 203, 204, 205 through the contact holes in the planarization film 135.

[0157] The first electrode 310 may be an anode. The first electrode 310 may include, for example, a reflective electrode, and may be used to block light incident on transistors LT, OT1, and OT2 below the light-emitting device 300. The first electrode 310 may have, for example, a stacked structure of a first transparent electrode, a reflective electrode, and a second transparent electrode. The second transparent electrode, serving as the uppermost electrode of the first electrode 310, may be used to lower the hole injection barrier at the interface with the intermediate layer 320, which serves as a dielectric. Here, the first and second transparent electrodes may be transparent oxide electrodes made of ITO, IZO, etc. The reflective electrode may include silver, a silver alloy such as APC (Ag-Pd-Cu), aluminum, or an aluminum alloy.

[0158] The embankment 350 is disposed at the edge of the first electrode 310, and the opening area of ​​the embankment 350 in at least the second sub-pixel SP2 and the first sub-pixel SP1 can be used as a light-emitting part.

[0159] Furthermore, the barrier 350 may include a light-shielding barrier, or may include a transparent barrier and a light-shielding barrier, through which the light-shielding barrier blocks light passing through the second sub-pixel SP2 in the sensor portion from entering the transmission area of ​​the adjacent sensor portion.

[0160] The light-emitting device 300 (ED) includes a first electrode 310, an intermediate layer 320, and a second electrode 330. After the embankment 350 that opens the light-emitting portion is provided at the edge of the first electrode 310, the intermediate layer 320 and the second electrode 330 can be provided sequentially.

[0161] For process integrity, the intermediate layer 320 and the second electrode 330 can be disposed not only in the second sub-pixel SP2 and the first sub-pixel SP1, but also in the transmissive region TA. However, the display device according to the embodiments of this disclosure is not limited thereto. Other arrangements of the transmissive region TA will be described later.

[0162] Intermediate layer 320 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Intermediate layer 320 may be provided as a plurality of stacks including the hole transport layer, the light-emitting layer, and the electron transport layer, and may also be formed in a series structure, including charge generation layers located between the stacks. The charge generation layers may include, for example, n-type charge generation layers and p-type charge generation layers.

[0163] The second electrode 330 can be a cathode. The second electrode 330 can be provided by forming a transparent electrode made of ITO, IZO, etc., or a reflective transparent electrode made of silver, silver alloys, magnesium, magnesium alloys, ytterbium (Yb), or ytterbium alloys with a low thickness. In another embodiment, the second electrode 330 can be formed in the transmission region TA with a low thickness or by partial removal to increase the transmittance in the transmission region TA.

[0164] One of the first electrode 310 and the second electrode 330 can be an anode, and the other can be a cathode.

[0165] A capping layer (not shown) may be further formed on the second electrode 330 to protect the second electrode 330 of the light-emitting device 300 and increase the upward light extraction efficiency.

[0166] The encapsulation layer 400 can be disposed on the second electrode 330 to prevent or reduce moisture penetration into the internal structure and protect the internal structure from the influence of external air.

[0167] For example, the encapsulation layer 400 may be configured such that inorganic and organic films are stacked. However, this disclosure is not limited thereto, and the encapsulation layer 400 may include an encapsulation substrate made of glass or the like. The encapsulation substrate may also include an adhesive layer disposed between the encapsulation substrate and the facing light-emitting device 300.

[0168] exist Figure 9 In the display device, an intermediate layer 320 and a second electrode 330 disposed in adjacent sub-pixels SP2 are shown in a state extending to the transmissive region TA. This allows for the integration of the intermediate layer 320 and second electrode 330 of other first sub-pixels SP1 and second sub-pixels SP2, as well as the transmissive region TA, thereby achieving process optimization.

[0169] The different settings for the transmission region (TA) are described below.

[0170] Figures 10 to 12 This is a cross-sectional view of the transmission region according to various embodiments of the present disclosure.

[0171] like Figure 10As shown, in the display device according to an embodiment of the present disclosure, the transmissive region TA can be configured such that the planarization film 135 is disposed on the insulating film 120 made of an inorganic insulating film material, and the encapsulation layer 400 is disposed directly on the planarization film 135 in the absence of a light-emitting device 300.

[0172] like Figure 11 As shown, in order to further increase the transmittance of the transmission region TA in the display device according to the embodiments of the present disclosure, in the absence of a planarization film 135 and a light-emitting device 300 on the insulating film 120 made of inorganic insulating film material, the encapsulation layer 400 can be directly disposed on the insulating film 120.

[0173] like Figure 12 As shown, with Figure 9 Compared to the display device described in the previous section, the display device according to the embodiments of this disclosure has a partial overlap between the hydrogen capture pattern 280 and the first active layer 151 made of polysilicon. When there is an overlap between the first active layer 151 and the hydrogen capture pattern 280, hydrogen flowing upward through the first active layer 151 or the first insulating film group 120A adjacent to the first active layer 151 can be more easily captured by the hydrogen capture pattern 280.

[0174] Furthermore, although the stability of the oxide transistor located at the upper position among the transistors mainly disposed in the sub-pixels in the display device according to the embodiments of the present disclosure has been described above, the embodiments of the present disclosure are not limited thereto.

[0175] For example, for transistors located in the non-display area NA (such as in-panel gates), when polycrystalline transistors LT and oxide transistors OT1 and OT2 are used as follows: Figure 4 When arranged together as shown, a hydrogen trapping pattern can be further formed around the oxide semiconductor layer of oxide transistors OT1 and OT2 to prevent or reduce the influence of hydrogen flowing in the first insulating film group 120A included in the polycrystalline transistor LT located below on the characteristics of oxide transistors OT1 and OT2 located above.

[0176] The display device according to embodiments of this disclosure can have a hydrogen trapping pattern corresponding to the sensor portion, thereby blocking the influence of hydrogen generated below or around the transistors in areas where transistors are arranged in low density. Therefore, it is possible to prevent or reduce the degradation of transistors located in the sensor portion due to hydrogen, thereby stably maintaining IV characteristics and preventing or reducing changes in switching characteristics and threshold voltage.

[0177] Furthermore, in the display device according to the embodiments of the present disclosure, the hydrogen trapping pattern is on the same layer as the active layer including the oxide semiconductor layer, such that the hydrogen trapping pattern can prevent or reduce the generation of gases such as hydrogen around the low-density active layer during heat treatment or the array structure including the polysilicon layer located below.

[0178] In the display device according to embodiments of the present disclosure, the hydrogen trapping pattern is formed of an indium-containing oxide material to increase infrared transmittance and hydrogen trapping function, thereby increasing the infrared sensitivity of the sensor portion and improving the sensing function. Furthermore, the hydrogen trapping pattern is disposed at a position higher than the active layer including a polycrystalline silicon layer with a high hydrogen content and at least one insulating layer on the active layer including the polycrystalline silicon layer, such that hydrogen generated from the transistor including the polycrystalline silicon layer can prevent or reduce its impact on the transistor including the oxide semiconductor layer.

[0179] A display device according to one embodiment of the present disclosure may include: a substrate including a display area and a non-display area surrounding the display area; a sensor portion having a transmissive area in the display area; a plurality of first transistors disposed on the substrate in the display area and including an oxide semiconductor layer; and a hydrogen trapping pattern located in the transmissive area and configured to be adjacent in a plane to the oxide semiconductor layer of at least one of the plurality of first transistors.

[0180] In a display device according to one embodiment of the present disclosure, the hydrogen capture pattern may include a conductive oxide.

[0181] In a display device according to one embodiment of the present disclosure, the hydrogen capture pattern may include a conductive oxide containing indium.

[0182] In a display device according to one embodiment of the present disclosure, the hydrogen capture pattern may include a material that is transmissive in the infrared wavelength range.

[0183] In a display device according to one embodiment of the present disclosure, the hydrogen capture pattern may be in the same layer as the oxide semiconductor layer of the plurality of first transistors.

[0184] In a display device according to one embodiment of the present disclosure, the hydrogen capture pattern may have a higher hydrogen capture capability than the oxide semiconductor layer of the plurality of first transistors.

[0185] In a display device according to one embodiment of the present disclosure, the sensor portion may be located below the substrate, and the hydrogen capture pattern overlaps with the sensor portion.

[0186] The display device according to one embodiment of the present disclosure may further include a polycrystalline silicon layer located between the substrate and the oxide semiconductor layer. At least one inorganic insulating film may be disposed between the oxide semiconductor layer and the polycrystalline silicon layer.

[0187] In a display device according to one embodiment of the present disclosure, at least a portion of the polysilicon layer may overlap with a hydrogen capture pattern.

[0188] In a display device according to one embodiment of the present disclosure, the oxide semiconductor layers of a plurality of first transistors may include a first active layer and a second active layer having different carrier mobilities in different regions.

[0189] A display device according to one embodiment of the present disclosure may further include a second transistor corresponding to the display area, the second transistor including a polysilicon layer located between the substrate and the oxide semiconductor layers of the plurality of first transistors.

[0190] In a display device according to one embodiment of the present disclosure, the display area may include a first area where the sensor portion is disposed and a second area where the sensor portion is not disposed. The first area of ​​the substrate may include a transmissive area and a plurality of first light-emitting portions, and the second area of ​​the substrate may include a plurality of second light-emitting portions. Furthermore, in the first area, the electrodes of the first transistor and the second transistor may not overlap with the transmissive area.

[0191] In a display device according to one embodiment of the present disclosure, in a first region, a hydrogen capture pattern may be disposed between the oxide semiconductor layers of adjacent first transistors.

[0192] In a display device according to one embodiment of the present disclosure, the density of the first transistors in the first region may be less than the density of the transistors including the oxide semiconductor layer in the second region.

[0193] In a display device according to one embodiment of the present disclosure, each of the first light-emitting portion and the second light-emitting portion may be connected to any one of the first transistors.

[0194] In a display device according to one embodiment of the present disclosure, the hydrogen capture pattern can be divided into multiple segments in the transmission area, and the width of each segment in the divided hydrogen capture pattern segment is greater than the interval between adjacent hydrogen capture pattern segments.

[0195] A display device according to one embodiment of the present disclosure may further include: a second transistor comprising a polysilicon layer located in the non-display area of ​​the substrate, the polysilicon layer being located between the substrate and the oxide semiconductor layer of at least one of the plurality of first transistors; and a third transistor comprising an active layer disposed on the same layer as the oxide semiconductor layer of the at least one of the plurality of first transistors.

[0196] In a display device according to one embodiment of the present disclosure, the carrier mobility of the oxide semiconductor layer of the first transistor may be different from the carrier mobility of the active layer of the third transistor.

[0197] The display device according to one embodiment of this disclosure may further include a planarization film above the first transistor and the hydrogen capture pattern. Each of the first light-emitting portion and the second light-emitting portion may include a light-emitting device on the planarization film, the light-emitting device including an anode, an intermediate layer, and a cathode. Any of the first transistors and the anode may be connected through contact holes in the planarization film.

[0198] A display device according to one embodiment of the present disclosure may include a display area and a non-display area located outside the display area; a sensor portion located in the display area and having a transmissive area and a light-emitting portion setting area; at least one transistor disposed in the light-emitting portion setting area and including an oxide semiconductor layer; and a hydrogen capture pattern located in the transmissive area and configured not to overlap with the oxide semiconductor layer.

[0199] In a display device according to one embodiment of the present disclosure, the infrared transmittance in the hydrogen capture pattern may be approximately 99%.

[0200] As can be seen from the above, the display device according to the embodiments of this disclosure has the following effects.

[0201] First, the display device according to the embodiments of this disclosure has a hydrogen trapping pattern corresponding to the sensor portion, blocking the influence of hydrogen generated below or around the transistors in the area where transistors are arranged in a low density. Accordingly, it is possible to prevent or reduce the degradation of the transistors located in the sensor portion due to hydrogen, thereby enabling stable maintenance of IV characteristics, and preventing or reducing variations in switching characteristics and threshold voltage.

[0202] Second, the hydrogen trapping pattern is on the same layer as the active layer, which includes an oxide semiconductor layer, so that the hydrogen trapping pattern can prevent or reduce the generation of gases such as hydrogen around the low-density active layer during heat treatment or other processes in the array structure including the polysilicon layer located below.

[0203] Third, the hydrogen trapping pattern is formed from an indium-containing oxide material, which increases infrared transmittance and hydrogen trapping function, thereby increasing the infrared sensitivity of the sensor and improving the sensing function.

[0204] Fourth, the hydrogen trapping pattern is positioned above the active layer including the polysilicon layer with a high hydrogen content and at least one insulating layer on the active layer including the polysilicon layer, thereby preventing or reducing the impact of hydrogen generated from the transistor including the polysilicon layer on the transistor including the oxide semiconductor layer.

[0205] Fifth, by placing the hydrogen trapping pattern on the same layer as the oxide semiconductor in regions with different transistor densities, the influence of the lower array in regions with different transistor densities can be made uniform, thereby controlling the abnormal characteristics of transistors in each region.

[0206] Sixth, the display device according to the embodiments of this disclosure can be formed by the same process as the formation of oxide semiconductors without the need to add additional materials, thereby enabling the use of a single material.

[0207] Furthermore, in the display device according to the embodiments of this disclosure, the number of processes required for additional materials can be reduced, the energy consumed in producing additional materials can be reduced, and the generation of greenhouse gases during the manufacturing process can be reduced through process optimization, thereby achieving ESG (Environmental, Social, and Governance) objectives.

[0208] From the above description, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of this disclosure. Therefore, the scope of this disclosure should not be limited to the above detailed description, but should be defined by the scope of the claims.

[0209] This application claims the benefit of Korean Patent Application No. 10-2024-0159598, filed on November 11, 2024, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: A substrate, the substrate including a display area and a non-display area outside the display area; The sensor portion has a transmissive area at the display area; A plurality of first transistors are disposed in the display area on the substrate, and each of the plurality of first transistors includes an oxide semiconductor layer; as well as A hydrogen trapping pattern, the hydrogen trapping pattern being located in the transmission region and being configured to be adjacent in a plane to the oxide semiconductor layer of at least one of the plurality of first transistors.

2. The display device according to claim 1, wherein, The hydrogen capture pattern includes conductive oxides.

3. The display device according to claim 1, wherein, The hydrogen capture pattern comprises a conductive oxide containing indium.

4. The display device according to claim 1, wherein, The hydrogen-capturing pattern comprises a material that is light-transmitting in the infrared wavelength range.

5. The display device according to claim 1, wherein, The hydrogen capture pattern is located on the same layer as the oxide semiconductor layer of the plurality of first transistors.

6. The display device according to claim 1, wherein, The hydrogen capture pattern has a higher hydrogen capture capability than the oxide semiconductor layer of the plurality of first transistors.

7. The display device according to claim 1, further comprising a sensor located below the substrate. in, The hydrogen capture pattern overlaps with the sensor.

8. The display device according to claim 1, further comprising a polysilicon layer between the substrate and the oxide semiconductor layer, wherein, At least one inorganic insulating film is disposed between the oxide semiconductor layer and the polycrystalline silicon layer.

9. The display device according to claim 8, wherein, At least a portion of the polycrystalline silicon layer overlaps with the hydrogen capture pattern.

10. The display device according to claim 1, wherein, The oxide semiconductor layer of at least one of the plurality of first transistors includes a first active layer and a second active layer, the first active layer and the second active layer having different carrier mobilities.

11. The display device of claim 1, further comprising a second transistor corresponding to the display area, the second transistor comprising a polysilicon layer located between the substrate and the oxide semiconductor layers of the plurality of first transistors.

12. The display device according to claim 11, wherein, The display area includes a first area where the sensor portion is located and a second area where the sensor portion is not located. The first region of the substrate includes the transmission region and a plurality of first light-emitting portions. The second region of the substrate includes a plurality of second light-emitting portions, and In the first region, the electrodes of the plurality of first transistors and the electrodes of the second transistor do not overlap with the transmission region.

13. The display device according to claim 12, wherein, In the first region, the hydrogen capture pattern is disposed between the oxide semiconductor layers of adjacent first transistors of the plurality of first transistors.

14. The display device according to claim 12, wherein, The density of the plurality of first transistors in the first region is less than the density of transistors including the oxide semiconductor layer in the second region.

15. The display device according to claim 12, wherein, Each of the plurality of first light-emitting portions and the plurality of second light-emitting portions is connected to any one of the plurality of first transistors.

16. The display device of claim 12, further comprising a planarization film located above the plurality of first transistors and the hydrogen capture pattern. in, Each of the first light-emitting portion and the second light-emitting portion includes a light-emitting device located on the planarization film, the light-emitting device including an anode, an intermediate layer, and a cathode, and In this embodiment, any one of the plurality of first transistors is connected to the anode through a contact hole in the planarization film.

17. The display device according to claim 1, wherein, In the transmission region, the hydrogen capture pattern is divided into multiple segments, and the width of each segment is greater than the interval between adjacent segments.

18. The display device according to claim 1, further comprising: A second transistor comprising a polysilicon layer located in the non-display area of ​​the substrate, the polysilicon layer being located between the substrate and the oxide semiconductor layer of at least one of the plurality of first transistors; And a third transistor, the third transistor including an active layer disposed on the same layer as the oxide semiconductor layer of at least one of the plurality of first transistors.

19. The display device according to claim 18, wherein, The carrier mobility of the oxide semiconductor layer of at least one of the plurality of first transistors is different from the carrier mobility of the active layer of the third transistor.

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