Chip package with multiple HBM stacks

Abstract

Disclosed herein is a chip package that integrates a plurality of computing dies into a memory stack through a single interposer die. The interposer die includes a memory controller circuit that allows a plurality of computing dies to access the memory stack in an efficient manner.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to chip packages having memory stacks, and more specifically to chip packages that interface one or more compute die stacks with multiple memory stacks within a single chip package. Background Technology

[0002] Electronic devices (such as tablets, computers, copiers, digital cameras, smartphones, control systems, ATMs, data centers, artificial intelligence systems, and machine learning systems) typically employ electronic and / or photonic components, which utilize chip packaging to increase functionality and component density. Conventional chip packaging schemes typically utilize a packaging substrate, usually combined with a through-silicon via (TSV) interposer substrate and / or other substrates such as fan-out and / or silicon bridging and / or substrates with glass and / or Si and / or organic cores, to allow multiple integrated circuit (IC) dies to be mounted onto a single packaging substrate. The IC dies are mounted to the top surface of the packaging substrate, while the bottom surface of the packaging substrate is mounted to a printed circuit board (PCB).

[0003] In many applications, memory dies are integrated into chip packages to reduce the distance between the memory dies and compute dies within the chip package. This reduced distance lowers power consumption and improves device performance. One type of chip package containing both a stack of memory dies and at least one connected compute die is called a high-bandwidth memory (HBM). An HBM stack typically includes I / O buffer dies on which memory dies are stacked. The I / O buffer dies also include a memory controller. However, most conventional chip packages with HBM die stacks typically contain compute dies with complex wiring between each compute die and the I / O buffer and the memory die with the specific HBM die stack, often requiring routing across the package substrate. This complex wiring introduces scheduling complexity, which slows down device performance. Furthermore, complex wiring often requires larger, more expensive interposers and package substrates to accommodate the increased number of wiring traces without generating excessive unwanted noise. Larger interposers and package substrates increase manufacturing complexity and cost, and result in slower performance, all of which are undesirable.

[0004] Therefore, there is a need for improved chip packaging that interfaces multiple compute dies with memory stacks within a single chip package. Summary of the Invention

[0005] This paper discloses a chip package that integrates multiple compute dies into a memory stack via a single interposer die. The interposer die includes memory controller circuitry that allows the multiple compute dies to access the memory stack in an efficient, scalable, robust, and cost-effective manner.

[0006] In one example, a chip package is provided that includes a substrate, an integrated circuit (IC) interposer die, a compute die stack, and a memory stack. The IC interposer die and the memory stack are mounted on the substrate. The compute die stack is mounted on the IC interposer die. The mounted memory stack is electrically coupled to the compute die stack through the IC interposer die.

[0007] In another example, the compute die stack also includes at least a first compute die and a second compute die. Both the first and second compute dies may include a central processing unit (CPU) core. Alternatively, both the first and second compute dies may include an acceleration compute core. In other examples, one of the first and second compute dies may include a CPU core, while the other may include an acceleration compute core.

[0008] In some examples, the compute die stack may include a carrier die disposed on one or more compute dies. The carrier die may be circuitless, such as lacking any functional integrated circuits. The carrier die may be fused-bonded to one or more compute dies within the compute die stack. The fusion bonding may utilize an oxide layer. In some examples, the chip package may include a molding compound disposed between the memory stack and the carrier die of the compute die stack. In some examples, a metal layer may be formed to contact the top surface of the molding compound disposed between the memory stack and the carrier die of the compute die stack, the top surface of the memory stack, and the top surface of the carrier die. In some examples, the chip package may include a cap disposed on the memory stack and the carrier die. A thermal interface material may be configured to contact both the metal layer and the cap. The thermal interface material may be a liquid metal or a phase change material. An example of a suitable liquid metal is indium.

[0009] In some examples, the substrate on which the IC interposer die is mounted is an interposer layer, and the interposer layer is mounted on a package substrate.

[0010] Surface mount components can be disposed on the package substrate and electrically connected to the IC interposer die through the package substrate and the interposer.

[0011] In some examples, the chip package includes at least one integrated passive device (IPD) mounted to the substrate and electrically connected to the IC interposer die via the substrate. The IPD may be a deep trench capacitor, inductor, resistor, or other passive circuit element.

[0012] A molding compound may be disposed between the memory stack, the IPD, and the carrier die. A metal layer may be formed to contact the top surface of the molding compound, the top surface of the memory stack, the top surface of the IPD, and the top surface of the carrier die. A cap may be disposed on the memory stack, the IPD, and the carrier die, and a thermal interface material may be configured to contact both the metal layer and the cap.

[0013] In some examples, the compute die stack includes a first compute die, a second compute die, a carrier die disposed on the first and second compute dies, and a dummy die disposed between the IC interposer die and the carrier die. The dummy die may not contain circuitry. The dummy die may be a silicon block. The dummy die may be fused-bonded to at least two of the first compute die, the second compute die, the IC interposer die, and the carrier die. The dummy die may be fused-bonded to the IC interposer die between a first edge of the second compute die and a second edge of the IC interposer die, the first compute die being disposed between a second edge of the second compute die and the IC interposer die, and the first compute die, the second compute die, and the dummy die being disposed between the first and second edges of the IC interposer die.

[0014] The compute dies in the compute die stack can be mixed-bonded to one or both of the IC interposer die and another compute die in the compute die stack.

[0015] The IC interposer die may include memory controller circuitry and cache memory circuitry. The memory controller circuitry is coupled to both the compute dies in the compute die stack and the IC interposer die, without routing signals through the substrate. The cache memory circuitry is also coupled to both the first compute die and the second compute die, without routing signals through the substrate. The interposer die may further include: on-chip network (NOC) circuitry; peripheral component interconnect (PCIe) circuitry; memory physical layer (PHY) circuitry configured to communicate with the memory stack; die-to-die PHY configured to communicate with at least one of the first compute die and the second compute die; and I / O PHY configured to communicate with devices remote from the chip package.

[0016] The chip package can be configured to include: solder balls for connection to a printed circuit board; or exposed contact pads for mating with a socket (which is typically mounted to a printed circuit board).

[0017] In yet another example, a chip package includes a substrate, a first integrated circuit (IC) interposer die, a first compute die stack, a first memory stack, and a cover. The first IC interposer die and the first memory stack are mounted on the substrate. The first IC interposer die includes memory controller circuitry. The first compute die stack is mounted on the first IC interposer die. The first compute die stack includes at least a first compute die and a second compute die, both of which are communicatively coupled to the memory controller circuitry. The first memory stack is mounted on the substrate and electrically coupled to the memory controller circuitry via the substrate. The cover is disposed over the first memory stack and the first compute die stack. A thermal interface material is configured to contact both the first compute die stack and the cover.

[0018] In one example, the chip package includes a second compute die stack mounted on the first IC interposer die. The second compute die stack includes a plurality of compute dies communicatively coupled to the memory controller circuitry.

[0019] In one example, the chip package includes a second memory stack mounted on the substrate and electrically coupled to the memory controller circuitry via the substrate.

[0020] In one example, the chip package includes a second IC interposer die and a second memory stack, both mounted on the substrate. The chip package also includes the second memory stack. The second IC interposer die includes memory controller circuitry. The second compute die stack includes a plurality of compute dies communicatively coupled to the memory controller circuitry of the second IC interposer die. The second memory stack is electrically coupled to the memory controller circuitry of the second IC interposer die through the substrate. Attached Figure Description

[0021] To gain a more detailed understanding of the above-described features of the invention, a more specific description of the invention, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the invention and should therefore not be considered as limiting the scope of the invention, as the invention allows for other equivalent embodiments.

[0022] Figure 1This is a schematic cross-sectional view of an example of a chip package having a memory stack, a compute die stack, and an integrated circuit (IC) interposer die. The memory stack and IC interposer die are mounted on a common substrate, while the compute die stack is mounted on the IC interposer die. Figure 1 In the example, the compute die stack includes a first compute die stacked on an IC interposer die, and a second compute die stacked on the first compute die in a vertical orientation.

[0023] Figure 2 This is a schematic cross-sectional view of another example of a chip package having a memory stack, a compute die stack, and an integrated circuit (IC) interposer die. The memory stack and IC interposer die are mounted on a common substrate, while the compute die stack is mounted on the IC interposer die. Figure 1 In the example, the computation die stack includes at least two first computation dies stacked horizontally on the IC interposer die.

[0024] Figure 3 This is a schematic block diagram of an IC interposer die that interfaces with one or more memory stacks and one or more compute die stacks, which can be utilized in any chip package envisioned herein.

[0025] Figure 4 This is a schematic cross-sectional view of an example of a compute die stack mounted to an IC interposer die, which can be utilized in any chip package envisioned herein.

[0026] Figure 5 This is a schematic cross-sectional view of another example of a computed die stack mounted to an IC interposer die, which can be utilized in any chip package envisioned herein.

[0027] Figure 6 This is a schematic cross-sectional view of yet another example of a computed die stack mounted to an IC interposer die, which can be utilized in any chip package envisioned herein.

[0028] Figure 7 This is a schematic plan view of a portion of a chip package, illustrating the relative exemplary positioning of the memory stack, the compute die stack, and the integrated circuit (IC) interposer die.

[0029] Figure 8 This is a schematic plan view of part of another chip package, illustrating the relative exemplary positioning of the memory stack, the compute die stack, and the integrated circuit (IC) interposer die. Figure 8 An exemplary chip package includes at least one integrated passive device (IPD) coupled to a common substrate in proximity to the memory stack.

[0030] Figure 9 and Figure 10 This is a partial cross-sectional view of an exemplary hybrid bonding interface between a computation die and an integrated circuit (IC) interposer die in a computation die stack.

[0031] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one embodiment can be advantageously incorporated into other embodiments. Detailed Implementation

[0032] This paper discloses a chip package that integrates multiple compute dies into a memory stack via a single integrated circuit (IC) interposer die. The IC interposer die includes memory controller circuitry that allows multiple compute dies to access the memory stack more efficiently compared to conventional chip packages, resulting in scalable, robust, and cost-effective designs. In some examples, the compute dies within the chip stack utilize hybrid bonding to increase communication bandwidth between compute dies. The compute die stack can also be hybrid-bonded to the IC interposer die, further increasing communication bandwidth between the compute dies and the IC interposer die. Hybrid bonding of the compute die stack to the IC interposer die also avoids the need to route communication between the compute die stack and the memory controller, and the cache of the IC interposer die crosses the substrate, which also improves performance and reliability. The use of hybrid bonding allows for different interconnect configurations (i.e., bonding pad locations) on the IC interposer die without altering the IC interposer die itself. Therefore, different compute dies can be connected in the same locations within a single IC interposer die design, providing increased manufacturing flexibility at a reduced cost. For example, both a compute die configured as a central processing unit (CPU) and a compute die configured as a graphics processing unit (GPU) can be easily mounted onto the same IC interposer die by changing the configuration of the hybrid bonding layer. Furthermore, the modular arrangement of the IC interposer die, memory stack, and compute die makes chip packaging easily scalable. The number and positioning of the modular arrangement components in the chip package can be selected and arranged for various computing applications without requiring new die or interposer designs. Therefore, chip packaging provides increased application flexibility with reduced manufacturing costs.

[0033] In one example, a chip package is provided that includes a substrate, an integrated circuit (IC) interposer die, a compute die stack, and a memory stack. The IC interposer die and the memory stack are mounted on the substrate. The compute die stack is mounted on the IC interposer die. The mounted memory stack is electrically coupled to the compute die stack through the IC interposer die.

[0034] Now go to Figure 1A schematic cross-sectional view of an example chip package 100 is provided. The chip package 100 includes at least one integrated circuit (IC) interposer die 102, at least one compute die stack 104, and at least one memory stack 106. Although in this example, the chip package 100 includes... Figure 1 The diagram shows two IC interposer dies 102, but the chip package 100 may include one or more space-constrained IC interposer dies 102 to achieve the desired functionality. Similarly, Figure 1 The illustrated chip package 100 may include a memory stack 106 of up to a space-allowed number to achieve the desired functionality. Additionally, each IC interposer die 102 may include a computing die stack 104 IC of up to a space-allowed number to achieve the desired functionality.

[0035] The memory stack 106 and the IC interposer die 102 are mounted on a common substrate. The substrate may be a package substrate. Alternatively, such as... Figure 1 As shown, the substrate may be an interposer 108 mounted to a package substrate 112. The memory stack 106 and the IC interposer die 102 are electrically and mechanically coupled to the interposer 108 via interconnects 114. The interconnects 114 may be solder bumps, hybrid bonding, and may optionally or alternatively include redistribution layers or other types of wiring fan-outs. The interposer 108 includes interposer wiring 132 that connects the functional circuitry of the memory stack 106 and the IC interposer die 102. The interposer wiring 132 is also connected to package wiring 134 formed in the package substrate 112. Therefore, the package wiring 134 of the package substrate 112 is coupled to the functional circuitry of the memory stack 106 and the IC interposer die 102 via the interposer wiring 132.

[0036] The side of the package substrate 112 facing away from the IC interposer die 102 includes a plurality of exposed bonding pads. These exposed bonding pads can be configured to mate with corresponding pins of sockets mounted on a printed circuit board 116 to form an electronic device 150. Alternatively, as... Figure 1 As shown, solder balls 118 may be formed on exposed bonding pads of the package substrate 112 and used to mount the chip package 100 to the printed circuit board 116 to form an electronic device 150.

[0037] The package substrate 112 may include an optional reinforcement 120. The reinforcement 120 has an annular shape surrounding the memory stack 106 and the IC interposer die 102. The reinforcement 120 is attached to the top surface of the package substrate 112, thereby making the package substrate 112 and the final chip package 100 less prone to warping, thereby improving the reliability and performance of the chip package 100.

[0038] The memory stack 106 is typically mounted adjacent to the IC interposer die 102. Figure 1 In the example depicted, one or more memory stacks 106 are directly connected to adjacent IC interposer dies 102 via high-bandwidth wiring formed in interposer wiring 132 in interposer layer 108. Each memory stack in memory stacks 106 includes a plurality of stacked memory dies 144. Using the plane of interposer layer 108 as a horizontal reference, the memory dies 144 are stacked vertically. The memory dies 144 within each memory stack 106 may be interconnected via solder interconnects, via hybrid bonding, or other suitable techniques. The memory dies 144 within the common memory stack 106 may be volatile memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or other suitable volatile memory types. Optionally, one or more memory dies in the common memory stack 106 may be non-volatile memory, such as ferroelectric random access memory (FeRAM) and magnetoresistive random access memory (MRAM), or other suitable non-volatile memory types. The memory type of memory die 144 in one memory stack 106 may be the same as or different from the memory type of memory die 144 in another memory stack 106 adjacent to a common IC interposer die 102, or in another memory stack 106 located in another region of the chip package 100 and adjacent to a different IC interposer die 102 of the chip package 100.

[0039] In one example, the bottom memory die 144 of the memory die stack 106 is configured as a buffer die with I / O circuitry. In another example, the bottom memory die 144 of the memory die stack 106 is configured as a volatile or non-volatile memory die 144. The number of memory dies 144 within the common memory stack 106 can range from two to up to a desired number. In one example, the number of memory dies 144 within the common memory stack 106 is four to approximately sixteen. The number of memory dies 144 within different memory stacks 106 of the chip package 100 is typically the same. However, memory stacks 106 with different numbers of memory dies 144 can be utilized. When memory stacks 106 with different numbers of memory dies 144 are utilized, the memory stacks 106 can be configured to have the same height. For example, the height difference between stacks 106 can be compensated by using memory dies 144 with different thicknesses and / or by using one or more dummy dies on top of the memory stacks 106.

[0040] Compute stack 104 is mounted to IC interposer die 102 on the side opposite to interposer 108. Interposer die 102 and compute die stack 104 form interposer die / compute die stack assembly 160. One or more compute stacks 104 may be coupled to each IC interposer die 102. For example, two or more compute stacks 104 may be coupled to a single IC interposer die 102. Each compute stack 104 is electrically and mechanically coupled to IC interposer die 102 via interconnects such as solder bumps, hybrid bonding, or other suitable techniques. Figure 1 In the example depicted, the computation stack 104 is hybrid-bonded to the IC interposer die 102.

[0041] The computation stack 104 comprises multiple computation dies. Figure 1 In the example depicted, computation stack 104 includes a first computation die 140 and a second computation die 142. Computation stack 104 may include additional computation dies, not shown. Although in Figure 1 The first compute die 140 is shown vertically stacked on top of the second compute die 142, which is shown vertically stacked on top of the IC interposer die 102. However, the first compute die 140 and the second compute die 142 can be as follows: Figure 2 As shown, they are horizontally stacked side-by-side on the IC interposer die 102.

[0042] Continue to refer to Figure 1 The first compute die 140 and the second compute die 142 can be the same type of die or different types of processor dies. The first compute die 140 and / or the second compute die 142 can be the same type of processor die as another compute die included in the same compute stack or different types of processor die. The second compute die 142 is electrically and mechanically coupled to the IC interposer die 102 via interconnects (such as solder bumps, hybrid bonding, or other suitable techniques). Figure 1 In the example depicted, the second computing die 142 is hybrid-bonded to the IC interposer die 102. Similarly, the first computing die 140 is electrically and mechanically coupled to the second computing die 142 via interconnects such as solder bumps, hybrid bonding, or other suitable techniques. Figure 1 In the example depicted, the second compute die 142 is hybrid-bonded to the second compute die 142. As discussed above, hybrid bonding is expected to improve communication speed and allow for increased bandwidth. Furthermore, hybrid bonding allows compute dies with different bonding pad location configurations to be mounted on the same IC interposer die design because the bonding pads in the hybrid bonding layer can be easily repositioned without requiring different IC interposer dies.

[0043] In one example, the functional circuitry of both the first computing die 140 and the second computing die 142 includes a central processing unit (CPU) core. Therefore, each of the first computing die 140 and the second computing die 142 may be referred to as a CPU die or CPU chiplet. The functional circuitry of the first computing die 140 and the second computing die 142 may also include a system management unit (SMU). The SMU is circuitry configured to monitor thermal and power conditions and adjust power and cooling to keep dies 140 and 142 operating within specifications. The functional circuitry of the first computing die 140 and the second computing die 142 may also include Dynamic Function Exchange (DFX) controller IP circuitry. The DFX circuitry provides management of hardware or software-triggered events. For example, the DFX circuitry may pull partial bit streams from memory and deliver them to the Internal Configuration Access Port (ICAP). The DFX circuitry also assists with the customizable logic decoupling and startup events for each reconfigurable partition.

[0044] In another example, the functional circuitry of both the first computing die 140 and the second computing die 142 includes an acceleration computing core. Therefore, each of the first computing die 140 and the second computing die 142 may be referred to as an accelerator die or an accelerator chiplet. The first computing die 140 and the second computing die 142 may also be referred to as a graphics processing unit (GPU) die or a GPU chiplet. The acceleration computing core contained in the functional circuitry of the first computing die 140 and the second computing die 142 typically includes math engine circuitry. Math engine circuitry is typically designed for task-specific computations, such as those used in data center computing, high-performance computing, and AI / ML computations. Along with the acceleration computing core, the functional circuitry of the first computing die 140 and the second computing die 142 may also include SMU circuitry and DFX circuitry.

[0045] In other examples, the functional circuitry of the first compute die 140 and the second compute die 142 is different. For example, the first compute die 140 may include an accelerated compute core, while the second compute die 142 includes a CPU core. One or more compute dies, when present in the compute stack 104, may include a CPU core and / or an accelerated compute core.

[0046] The compute die stack 104 may additionally include a carrier die 138 disposed above compute dies 140, 142. The carrier die 138 is typically the top die in the compute die stack 104, positioned furthest from the IC interposer die 102. The carrier die 138 is typically a block of silicon material that provides good thermal transfer from the compute die stack 104. The carrier die 138 may be thicker than one or both of the compute dies 140, 142, thereby providing increased structural stiffness and increased resistance to warping within the compute die stack 104, making the connection between the compute dies 140, 142 more reliable and robust. The carrier die 138 may be free of circuitry, i.e., free of wiring, passive circuitry, and active circuitry. The carrier die 138 is adhered to one or both of the compute dies 140, 142. For example, the carrier die 138 is adhered to... Figure 1 The first computing die 140 in the chip package 100, while the carrier die 138 is adhered to Figure 2 Both computing dies 140 and 142 are included in the chip package 200. A carrier die 138 can be adhered to the computing die using any suitable adhesive or technique. In one example, the carrier die 138 is fused-bonded to the computing die. In such examples, an oxide layer is disposed between the carrier die 138 and the computing die to enhance the fused-bonding process. Fused bonding increases the structural stiffness of the computing die stack 104 and makes the connection between computing dies 140 and 142 more reliable and robust. Optionally, a single carrier die 138 may span more than one computing die stack 104.

[0047] The compute die stack 104 may additionally include a dummy die 136 disposed on or beside one or more of the compute dies 140, 142. The dummy die 136 is typically located between the carrier die 138 and the IC interposer die 102. The dummy die 136 may alternatively contact one of the carrier die 138 and the IC interposer die 102, and also contact one or both of the compute dies 140, 142. The dummy die 136 is typically a block of silicon material that provides good thermal transfer across the compute die stack 104. The dummy die 136 also provides mechanical stability across the width of the compute die stack 104. The dummy die 136 may be circuit-free, i.e., free of wiring, passive circuitry, and active circuitry. The dummy die 136 is adhered to the overlying die and the underlying die (i.e., both of the compute dies 140, 142, the IC interposer die 102, and the carrier die 138). For example, suppose the bare die 136 is adhered to Figure 1 The first computing die 140 and the IC interposer die 102 in the chip package 100, while the dummy die 136 is adhered to Figure 2Both the IC interposer die 102 and the carrier die 138 in the chip package 200. A dummy die 136 can be adhered to adjacent overlay and underlay dies using any suitable adhesive or technique. In one example, the dummy die 136 is fused-bonded to adjacent overlay and underlay dies. In such examples, an oxide layer is disposed between the dummy die 136 and each of the adjacent overlay and underlay dies to enhance the fused bonding process. Similar to the carrier die 138, the fused bonding of the dummy die 136 increases the structural stiffness of the computing die stack 104 and makes the connections between computing dies 140, 142 more reliable and robust. Optionally, more than one dummy die 136 may be used in a single computing die stack 104.

[0048] The chip package 100 also includes a molding compound 126 disposed between the memory stack 106 and the compute stack 104. The molding compound 126 provides structural rigidity to the chip package 100, thereby improving warpage resistance, while also protecting electrical components.

[0049] In one example, the top surfaces of the molded compound 126, the memory stack 106, and the compute stack 104 are exposed coplanarly. The exposed top surfaces may interface with a thermal management device (such as a heatsink, not shown) of the electronics 150, or be permitted to radiate heat into the environment. Figure 1 In the example depicted, the top surfaces of the molding compound 126, memory stack 106, and compute stack 104 are covered by a cap 122. The cap 122 is typically made of a material with good thermal conductivity, such as a metal. In one example, the cap 122 is a metal, such as copper, aluminum, or stainless steel. The cap 122 may optionally be plated with another metal, such as nickel. The cap 122 may optionally be coupled to the package substrate 112, for example, via fasteners or reinforcements 120 (via adhesive).

[0050] The top surfaces of the molding compound 126, memory stack 106, and compute stack 104 may be covered by a metal layer 128 to enhance heat transfer to the cover 122. The metal layer 128 may be copper, aluminum, nickel, or other suitable materials. A thermal interface material (TIM) 130 may be disposed between the metal layer 128 and the underside of the cover 122 and in contact with both the metal layer and the underside of the cover. The TIM 130 may be a liquid metal, phase change material, thermal grease, thermal pad, or other suitable heat transfer material. In one example, the TIM 130 is indium.

[0051] Continue to refer to Figure 1The package substrate 112 may also include surface mount components 124 coupled to the IC interposer die 102 via interposer wiring 132. Surface mount components 124 may be integrated passive devices (IPDs), such as capacitors, inductors, and resistors. In one example, surface mount component 124 is a capacitor. Alternatively, some or all of the surface mount components 124 may be positioned as IPDs at other locations within the chip package 100. For example, IPDs may be positioned within or attached to the interposer 108, within the package substrate 112, within a redistribution layer, or at other suitable locations within the chip package 100.

[0052] As briefly described above, Figure 2 This is a schematic cross-sectional view of another example of a chip package 200, which includes at least one integrated circuit (IC) interposer die 102, at least one compute die stack 204, and at least one memory stack 106. The interposer die 102 and the compute die stack 204 form an interposer die / compute die stack assembly 260. The chip package 200 is configured to... Figure 1 The chip package 100 shown is substantially the same, except that an interposer die / computing die stack assembly 260 replaces the interposer die / computing die stack assembly 160. The computing die stack 204 in the interposer die / computing die stack assembly 260 has computing dies 140, 142 arranged in a horizontal stacking orientation. Additionally, the computing die stack 204 may optionally include at least one dummy die 136 fused to the IC interposer die 102. Figure 2 In the example depicted, a dummy die 136 is disposed between the second computing die 142 and the first edge of the IC interposer die 102. A first computing die 140 is disposed between the second computing die 142 and the second edge of the IC interposer die 102. The first computing die 140, the second computing die 142, and the dummy die 136 are disposed between the first and second edges of the IC interposer die 102.

[0053] Figure 3 This is a schematic block diagram of an example of an IC interposer die 102 that interfaces with one or more memory stacks 106 and one or more compute die stacks 104, which can be utilized in any chip package (such as, but not limited to, chip packages 100, 200, 800, etc.) contemplated herein. The IC interposer die 102 may alternatively have other configurations. Figure 3The functional circuitry of the IC interposer die 102 shown includes a memory controller circuit 312 coupled to both the first compute die 140 and the second compute die 142, without routing signals through the package substrate 112 or the interposer 108. The functional circuitry of the IC interposer die 102 also includes a cache memory circuit 310. The cache memory circuit 310 is coupled to both the first compute die 140 and the second compute die 142, without routing signals through the package substrate 112 or the interposer 108. The cache memory circuit 310 provides a large common cache for the compute dies mounted in the compute stack 104 of the IC interposer die 102.

[0054] The functional circuitry of the IC interposer die 102 may further include: peripheral component interconnect (PCIe) circuitry 314; memory physical layer (PHY) circuitry 322 configured to communicate with memory stack 106; die-to-die PHY 324 configured to communicate with at least one or more compute stacks 106; and I / O PHY 320 configured to communicate via package substrate 112 with integrated circuit device 300 or printed circuit 116 remote from chip package 100. The I / O PHY 320 may also be configured to communicate with other IC interposers 102 and / or compute stacks 104 removed from the interposer die 102 residing therein. The I / O PHY 320 may also be configured to communicate with other memory stacks 106 residing in chip package 100.

[0055] The functional circuitry of IC interposer die 102 may also include functional block 316, which serializes and deserializes digital data used in high-speed chip-to-chip communication (e.g., serial-to-deserial circuitry). The functional circuitry of IC interposer die 102 may also include one or more other functional blocks 318 for performing other functions of the network on-chip (NOC).

[0056] Figure 4 This is a schematic cross-sectional view of an example of an interposer die / computation die stack assembly 426. The interposer die / computation die stack assembly 426 includes one or more computation die stacks 404. Figure 4 Two compute die stacks 404 are shown, but the number of compute die stacks 404 can be one or more that can reasonably be accommodated on the IC interposer die 102. The compute die stacks 404 may include those referenced above. Figure 1 and Figure 2 The optional dummy die 136 is described. The interposer die / computation die stack assembly 426 can be utilized in any chip package (such as, but not limited to, chip packages 100, 200, 800, etc.) envisioned herein.

[0057] exist Figure 4 In the example depicted, two compute dies 140, 142 are shown in each compute die stack 404. However, there may be no additional compute dies, or one or more additional compute dies may be present, positioned between the first compute die 140 and the carrier die 138.

[0058] Figure 5 This is a schematic cross-sectional view of an example of an interposer die / computation die stack component 526. The interposer die / computation die stack component 526 includes one or more computation die stacks 504. Figure 5 Two compute die stacks 504 are shown, but the number of compute die stacks 504 can be from one to a number that can reasonably be accommodated on the IC interposer die 102. The compute die stacks 504 may include those referenced above. Figure 1 and Figure 2 The optional dummy die 136 is described. The interposer die / computation die stack assembly 526 can be utilized in any chip package (such as, but not limited to, chip packages 100, 200, 800, etc.) envisioned herein.

[0059] exist Figure 5 In the example depicted, each compute die stack 504 includes a single compute die 140, 142. Each compute die 140, 142 is covered by a separate carrier die 138. Optionally, a single carrier die 138 may span across one or more of the die stacks 504.

[0060] Figure 6 This is a schematic cross-sectional view of an example of an interposer die / computation die stack assembly 626. The interposer die / computation die stack assembly 626 includes one or more computation die stacks 604. Figure 6 A single compute die stack 604 is shown, but the number of compute die stacks 604 can be one or more that can reasonably be accommodated on the IC interposer die 102. The compute die stack 604 may include those referenced above. Figure 1 and Figure 2 The optional dummy die 136 is described. The interposer die / computation die stack assembly 626 can be utilized in any chip package (such as, but not limited to, chip packages 100, 200, 800, etc.) envisioned herein.

[0061] exist Figure 6 In the example depicted, two compute dies 140 and 142 are shown in compute die stack 604. However, there may be no additional compute dies, or one or more additional compute dies disposed between the first compute die 140 and the carrier die 138.

[0062] Figure 7 This is a schematic plan view based on a portion of an example chip package 100, illustrating the exemplary relative positioning of a memory stack 106, a compute die stack 104, and an integrated circuit (IC) interposer die 102. Figure 7 In this process, cover 122, TIM 130, molding compound 126 and metal layer 128 have been removed to allow for a clearer view of memory stack 106, compute die stack 104 and integrated circuit (IC) interposer die 102.

[0063] As discussed above, chip package 100 may be configured with at least one memory stack 106, one compute die stack 104, and one integrated circuit (IC) interposer die 102. Chip package 100 may alternatively be configured with one or more memory stacks 106, one or more compute die stacks 104, and one or more IC interposer dies 102. The one or more memory stacks 106, one or more compute die stacks 104, and one or more IC interposer dies 102 may be arranged symmetrically or asymmetrically. For example, the IC interposer dies 102 may be arranged linearly or in a grid of rows and columns. In some examples, the IC interposer dies 102 may be arranged symmetrically about the bifurcation centerline of the interposer 108 using a 2×2, 3×3, 4×4, or other grid pattern. In other examples, an odd number of IC interposer dies 102 may be arranged in a grid pattern, wherein one location (i.e., node) of the grid does not contain an interposer die, and optionally, dummy silicon structures are present in the nodes of the grid where the interposer die has been omitted.

[0064] The compute die stack 104 may be positioned between the nearest edges of the interposer die 102 and the interposer layer 108. The compute die stack 104 may be arranged in one or more columns (e.g., 2 or 3 columns) between the nearest edges of the interposer die 102 and the interposer layer 108. The compute die stack 104 may be positioned on two sides of the interposer die 102, such as along opposite edges of the interposer layer 108. One, two, or more compute die stacks 104 may overlap with a single edge of each interposer die 102.

[0065] exist Figure 7 In the example depicted, the interposer dies 102 are arranged symmetrically about the bifurcation centerline of the interposer 108 in a 2×2 grid pattern. The interposer dies 102 may be uniformly spaced. Two compute die stacks 104 are positioned between the nearest edges of each interposer die 102 and the interposer 108. The compute die stacks 104 are arranged in a single column on opposite sides of the interposer dies 102 adjacent to the opposite edges of the interposer 108.

[0066] Figure 7The chip package 100 depicted also includes one or more rows of surface mount members 124 mounted on the package substrate 112. The surface mount members 124 are arranged on opposite sides of the interposer layer 108.

[0067] Figure 8 This is a schematic plan view of a portion of another chip package 800, illustrating the relative exemplary positioning of a memory stack 106, a compute die stack 104, and an integrated circuit (IC) interposer die 102. Figure 8 In this configuration, cover 122, TIM 130, molding compound 126, and metal layer 128 have been removed to allow for a clearer view of memory stack 106, compute die stack 104, and integrated circuit (IC) interposer die 102. Chip package 800 can be configured similarly to chip packages 100 and 200 discussed above, except that chip package 800 includes at least one integrated passive device (IPD) 802 coupled to or embedded in interposer 108, such that surface mount member 124 mounted on package substrate 112 is optional.

[0068] exist Figure 8 In the examples depicted, one or more IPDs 802 may be mounted to or fabricated within the interposer 108 adjacent to the memory stack 106. In some examples, multiple IPDs 802 may be disposed within or on the interposer 108 between two adjacent memory stacks 106. Alternatively, or in addition to mounting or forming IPDs within or on the interposer 108 adjacent to the memory stack 106, one or more IPDs 802 may be disposed within or on the interposer 108 between two adjacent IC interposer dies 102. The IPDs 802 are electrically connected to the circuitry of the IC interposer die 102 via wiring 132 of the interposer 108. The IPDs 802 may be capacitors, inductors, resistors, or other passive circuit elements. In one example, the IPD 802 is a deep trench capacitor. As part of the fabrication of the interposer 108, the IPDs 802 may be formed as solid-state circuitry.

[0069] Figure 9 and Figure 10This is a partial cross-sectional view of an exemplary hybrid bonding interface between compute dies 140 / 142 and integrated circuit (IC) interposer die 102 in compute die stack 104. After dies 102, 140, and 142 have been fabricated, a hybrid bonding interface is formed on the compute dies 140, 142 and the IC interposer die 102, allowing compute dies 140, 142 (or other dies) with different bonding pad layouts to be mounted onto the same IC interposer die 102. This allows a single IC interposer die design to be used with many different IC dies, thereby increasing design flexibility, reducing costs, and shortening time to market.

[0070] For example, first refer to Figure 9 In a partial cross-sectional view, computation die 140 in computation die stack 104 is illustrated as being hybrid-bonded to IC interposer die 102. Computation die 140 includes exposed bonding pads 910 having a first layout. The bonding pads 910 are coupled to functional circuitry 914 within computation die 140 via wiring 912.

[0071] A hybrid bonding layer 940 is formed on the surface of the compute die 140 facing the IC interposer die 102. The hybrid bonding layer 940 includes a plurality of dielectric layers 922 that separate conductive vias 924 and lines 926 forming wiring through the hybrid bonding layer 940. Suitable materials for the dielectric layers 922 include oxides, thermal oxides, SiO2, SiN, SiCN, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. The vias 924 and lines 926 can be copper or other suitable electrical conductors. At least one via 924 is coupled to a corresponding exposed bonding pad in an exposed bonding pad 910 formed on the bottom surface of the compute die 140. The wiring within the hybrid bonding layer 940 terminates at a hybrid bonding pad 928.

[0072] Similarly, the IC interposer die 102 includes exposed bonding pads 902 arranged in a pattern (e.g., layout). The bonding pads 902 are coupled to the die-to-die PHY 324 of the functional circuitry disposed within the IC interposer die 102 via wiring 904.

[0073] A hybrid bonding layer 920 is formed on the surface of the IC interposer die 102 facing the computing die 140. The hybrid bonding layer 920 includes a plurality of dielectric layers 922 that separate conductive vias 924 forming wiring through the hybrid bonding layer 940 from lines 926. At least one via 924 is coupled to a corresponding exposed bonding pad among exposed bonding pads 910 formed on the bottom surface of the IC interposer die 102. The wiring within the hybrid bonding layer 920 terminates at a hybrid bonding pad 928.

[0074] Hybrid bonding layers 920, 940 include: forming non-metal-to-non-metal bonds using fusion bonding, and forming metal-to-metal bonds across adjacent IC dies 102, 140. Pressure and heat can be used to form metal-to-metal bonds to form eutectic metal bonds. In one example, the hybrid bonding is formed by fusion bonding the dielectric material of layer 922 surrounding hybrid bonding pads 928 on each hybrid bonding layer 920, 940 to first hold the dies 102, 140 together, followed by fusing the metal materials of the hybrid bonding pads 928 of facing hybrid bonding layers 920, 940 to form an electrical interconnect between the functional circuitry 914 of the compute die 140 and the functional circuitry of the vertically adjacent IC interposer die 102.

[0075] The geometry of the wiring made of conductive vias 924 and lines 926 within the hybrid bonding layers 920 and 940 can be fabricated as needed. The flexible configuration of the wiring within the hybrid bonding layers 920 and 940 allows multiple IC dies with different bonding pad layouts to be mounted to the same IC interposer die 102 without the need to fabricate different IC interposer dies with different bonding pad positions.

[0076] For example, such as Figure 10 As shown, the IC interposer die 102 has the same characteristics as... Figure 9 The IC interposer die 102 shown has the same bonding pad 902 layout. However, the bonding pad 1010 layout of the computational die 142 differs from that of the bonding pad 910 of the computational die 140. To accommodate the difference in bonding pad layout between computational dies 140 and 142, and to allow the use of the same IC interposer die 102, different configurations of vias 924 and lines 926 are mixed between one or both of the bonding layers 1020 and 1040, even if the locations of the pads 910 and 1010 of the computational dies 140 and 142 are physically different, these vias and lines also allow the pads 928 of each layer 1020 and 1040 to mate. This allows the functional circuitry 1014 to be coupled to the bonding pad 1010 via the wiring 1012 of the computational die 142, to the die-to-die PHY 324 of the functional circuitry on the IC interposer die 102.

[0077] This document also describes a method for manufacturing a chip package, such as chip package 100 or other similarly constructed chip packages. The method begins by mounting a compute die stack 104 onto an IC interposer die 102. The compute die stack 104 includes at least a first compute die 140 and a second compute die 142. The compute stack 104 may include additional compute dies, dummy dies, etc., as described above. The compute stack 104 may be mounted to the IC interposer die 102 via solder joints, hybrid bonding, or other suitable techniques.

[0078] After the compute stack 104 has been mounted to the IC interposer die 102, the IC interposer die 102 is mounted to the substrate 112. The IC interposer die 102 may be mounted to the substrate 112 via solder joints, hybrid bonding, or other suitable techniques.

[0079] The memory stack 106 is mounted to the substrate 112 before, after, or simultaneously with the mounting of the IC interposer die 102 to the substrate 112. The memory stack 106 may be mounted to the substrate 112 via solder joints, hybrid bonding, or other suitable techniques.

[0080] Once the IC interposer die 102 and memory stack 106 have been mounted onto the substrate 112, a chip package 100 is formed. The chip package 100 can later be mounted onto a printed circuit board (PCB) and connected via the PCB to other chip packages or memory within a local device (such as a server) or coupled via a network to a remote electronic device (such as a data center).

[0081] Therefore, the chip package disclosed above arranges the memory stack as a unified memory device that is efficiently available through a single IC interposer die. This single IC interposer die includes multiple compute dies that utilize hybrid bonding and high-speed routing in the interposer to provide fast, high-bandwidth communication with multiple memory stacks. The modular arrangement of the IC interposer die, memory stack, and compute dies makes the chip package easily scalable and adaptable for configuration in a variety of computing applications without requiring new die or interposer designs. Thus, the chip package provides increased application flexibility with reduced manufacturing costs.

[0082] In addition to the examples described above, the disclosed techniques may also be expressed in the following non-limiting embodiments.

[0083] Example 1. A chip package, the chip package comprising: a substrate; an integrated circuit (IC) interposer die, the integrated circuit (IC) interposer die being mounted on the substrate; a computing die stack, the computing die stack being mounted on the IC interposer die; and a memory stack, the memory stack being mounted on the substrate and electrically coupled to the computing die stack through the IC interposer die.

[0084] Example 2. The chip package according to Example 1, wherein the computing die stack further includes at least a first computing die and a second computing die.

[0085] Example 3. The chip package according to Example 2, wherein the first computing die and the second computing die include a central processing unit (CPU) core.

[0086] Example 4. The chip package according to Example 2, wherein the first computing die includes an accelerated computing core, and the second computing die includes a central processing unit (CPU) core.

[0087] Example 5. The chip package according to Example 2, wherein the first computing die and the second computing die include an accelerated computing core.

[0088] Example 6. The chip package according to Example 1, wherein the computing die stack further includes: a carrier die, the carrier die being disposed on one or more computing dies.

[0089] Example 7. The chip package according to Example 6, wherein the carrier die does not contain circuitry.

[0090] Example 8. The chip package according to Example 7, wherein the carrier die is fused to one or more computing dies in the computing die with an oxide layer.

[0091] Example 9. The chip package according to Example 8 further includes: a molding compound disposed between the memory stack and the carrier die.

[0092] Example 10. The chip package according to Example 9 further includes: a metal layer formed to contact the top surface of the molding compound, the top surface of the memory stack and the top surface of the carrier die.

[0093] Example 11. The chip package according to Example 10 further includes: a cover disposed on the memory stack and the carrier die; and a thermal interface material configured to contact both the metal layer and the cover.

[0094] Example 12. The chip package according to Example 11, wherein the thermal interface material is a liquid metal or a phase change material.

[0095] Example 13. The chip package according to Example 1, wherein: the substrate is an interposer; and the interposer is mounted on the package substrate.

[0096] Example 14. The chip package according to Example 13 further includes: a surface mount component, the surface mount component being mounted to the package substrate and electrically connected to the IC interposer die through the package substrate and the interposer layer.

[0097] Example 15. The chip package according to Example 1 further includes: at least one integrated passive device (IPD), the at least one integrated passive device (IPD) being mounted to the substrate and electrically connected to the IC interposer die through the substrate.

[0098] Example 16. The chip package according to Example 15, wherein the IPD includes a deep trench capacitor.

[0099] Example 17. The chip package according to Example 16 further includes: a carrier die disposed on one or more computing dies; a molding compound disposed between the memory stack, the IPD and the carrier die; a metal layer formed to contact the top surface of the molding compound, the top surface of the memory stack, the top surface of the IPD and the top surface of the carrier die; a cap disposed on the memory stack, the IPD and the carrier die; and a thermal interface material configured to contact both the metal layer and the cap.

[0100] Example 18. According to the chip package of Example 1, the computing die stack further includes: a first computing die; a second computing die; a carrier die disposed on the first computing die and the second computing die; and a dummy die disposed between the IC interposer die and the carrier die.

[0101] Example 19. The chip package according to Example 18, wherein the dummy die does not contain circuitry.

[0102] Example 20. The chip package according to Example 18, wherein the dummy die is fused to at least two of the first computing die, the second computing die, the IC interposer die, and the carrier die.

[0103] Example 21. The chip package according to Example 18, wherein the dummy die is fused to the IC interposer die between the first edge of the second computing die and the first edge of the IC interposer die, the first computing die is disposed between the second computing die and the second edge of the IC interposer die, and the first computing die, the second computing die and the dummy die are disposed between the first edge and the second edge of the IC interposer die.

[0104] Example 22. The chip package according to Example 2, wherein the first computing die is co-bonded to one or both of the second computing die and the IC interposer die.

[0105] Example 23. The chip package according to Example 2, wherein the IC interposer die further includes: a memory controller circuit coupled to both the first computing die and the second computing die, without routing signals through the package substrate; and a cache memory circuit coupled to both the first computing die and the second computing die, without routing signals through the package substrate.

[0106] Example 24. The chip package according to Example 2, wherein the IC interposer die further includes: a network on-chip (NOC) circuit; a peripheral component interconnect (PCIe) circuit; a memory physical layer (PHY) circuit configured to communicate with the memory stack; a die-to-die PHY configured to communicate with at least one of the first computing die and the second computing die; and an I / O PHY configured to communicate with a device remote from the chip package.

[0107] Example 25. The chip package according to Example 9, wherein the top surface of the molding compound, the top surface of the memory stack, and the top surface of the carrier die are coplanar.

[0108] Example 26. The chip package according to Example 13 further includes: solder balls disposed on the bottom surface of the package substrate and electrically connected to the IC interposer die through wiring formed through the package substrate and the interposer layer.

[0109] Example 27. The chip package according to Example 13, the chip package further includes: contact pads exposed on the bottom surface of the package substrate and configured to mate with a socket.

[0110] Example 28. A chip package, the chip package comprising: a substrate; a first integrated circuit (IC) interposer die, the first IC interposer die being mounted on the substrate, the first IC interposer die including memory controller circuitry; a first compute die stack, the first compute die stack being mounted on the first IC interposer die, the first compute die stack including at least a first compute die and a second compute die, both the first compute die and the second compute die being communicatively coupled to the memory controller circuitry; a first memory stack, the first memory stack being mounted on the substrate and electrically coupled to the memory controller circuitry via the substrate; a cover, the cover being disposed over the first memory stack and the first compute die stack; and a thermal interface material, the thermal interface material being configured to contact both the first compute die stack and the cover.

[0111] Example 29. The chip package according to Example 28 further includes: a second computing die stack, the second computing die stack being mounted on the first IC interposer die, the second computing die stack including a plurality of computing dies communicatively coupled to the memory controller circuitry.

[0112] Example 30. The chip package according to Example 28 further includes: a second memory stack, the second memory stack being mounted on the substrate and electrically coupled to the memory controller circuit through the substrate.

[0113] Example 31. The chip package according to Example 28, the chip package further includes: a second IC interposer die, the second IC interposer die being mounted on the substrate, the second IC interposer die including a memory controller circuit; a second compute die stack, the second compute die stack being mounted on the second IC interposer die, the second compute die stack including a plurality of compute dies communicatively coupled to the memory controller circuit of the second IC interposer die; and a second memory stack, the second memory stack being mounted on the substrate and electrically coupled to the memory controller circuit of the second IC interposer die through the substrate.

[0114] Example 32. The chip package according to Example 28 further includes: a metal layer formed to contact the top surface of the first memory stack and the top surface of the first computing die stack.

[0115] Example 33. The chip package according to Example 32 further includes: a thermal interface material, the thermal interface material being configured to contact both the metal layer and the cover.

[0116] Example 34. The chip package according to Example 33, wherein the thermal interface material is a liquid metal or a phase change material.

[0117] Example 35. The chip package according to Example 32, the chip package further includes: a molding compound disposed between the first memory stack and the first computing die stack, wherein the metal layer is formed to contact the top surface of the molding compound.

[0118] Example 36. The chip package according to Example 35, wherein the thermal interface material is a liquid metal or a phase change material.

[0119] Example 37. The chip package according to Example 28, wherein the first computing die and the second computing die include a central processing unit (CPU) core.

[0120] Example 38. The chip package according to Example 28, wherein the first computing die includes an accelerated computing core, and the second computing die includes a central processing unit (CPU) core.

[0121] Example 39. The chip package according to Example 28, wherein the first computing die and the second computing die include an accelerated computing core.

[0122] Example 40. The chip package according to Example 28, wherein the first computing die stack terminates at a carrier die, the carrier die being configured to be closer to the cover than the first IC interposer die.

[0123] Example 41. The chip package according to Example 40, wherein the carrier die is a silicon block without circuitry.

[0124] Example 42. The chip package according to Example 41, wherein the carrier die is fused to at least one of the first computing die and the second computing die with an oxide layer.

[0125] Example 43. The chip package according to Example 28, wherein: the substrate is an interposer; and the interposer is mounted on the package substrate.

[0126] Example 44. The chip package according to Example 43 further includes: at least one integrated passive device (IPD), the at least one integrated passive device (IPD) being mounted to the interposer and electrically connected to the first IC interposer die through the substrate.

[0127] Example 45. The chip package according to Example 44, wherein the IPD includes a deep trench capacitor.

[0128] Example 46. The chip package according to Example 44 further includes: a molding compound disposed between the first memory stack, the IPD and the first die computing stack; a metal layer formed to contact the top surface of the molding compound, the top surface of the first memory stack, the top surface of the IPD and the top surface of the first die computing stack; and a thermal interface material configured to contact both the metal layer and the cap.

[0129] Example 47. The chip package according to Example 28, wherein the first computing die stack further includes: a carrier die disposed on the first computing die and the second computing die; and a dummy die disposed between the first IC interposer die and the carrier die.

[0130] Example 48. The chip package according to Example 47, wherein the dummy die does not contain circuitry.

[0131] Example 49. The chip package according to Example 48, wherein the dummy die is fused to at least two of the first computing die, the second computing die, the first IC interposer die, and the carrier die.

[0132] Example 50. The chip package according to Example 48, wherein the dummy die is fused to the first IC interposer die between the first edge of the second computing die and the first edge of the first IC interposer die, the first computing die is disposed between the second edge of the second computing die and the second edge of the first IC interposer die, and the first computing die, the second computing die and the dummy die are disposed between the first edge and the second edge of the first IC interposer die.

[0133] Example 51. The chip package according to Example 28, wherein the first computing die is co-bonded to one or both of the second computing die and the first IC interposer die.

[0134] Example 52. The chip package according to Example 28, wherein the first IC interposer die further includes: a cache memory circuit, the cache memory circuit being coupled to both the first computing die and the second computing die, without routing signals through the substrate.

[0135] Example 53. The chip package according to Example 52, wherein the IC interposer die further includes: a network on-chip (NOC) circuit; a peripheral component interconnect (PCIe) circuit; a memory physical layer (PHY) circuit configured to communicate with the first memory stack; a die-to-die PHY configured to communicate with at least one of the first computing die and the second computing die; and an I / O PHY configured to communicate with a device remote from the chip package.

[0136] Example 54. The chip package according to Example 28, wherein the top surface of the first memory stack and the top surface of the first compute die stack are exposed and coplanar.

[0137] Example 55. The chip package according to Example 43 further includes: solder balls disposed on the bottom surface of the package substrate and electrically connected to the first IC interposer die through wiring formed through the package substrate and the interposer layer.

[0138] Example 56. The chip package according to Example 43 further includes: contact pads exposed on the bottom surface of the package substrate and configured to mate with a socket.

[0139] Example 57. A method for manufacturing a chip package, the method comprising: mounting a computing die stack on an integrated circuit (IC) interposer die, the computing die stack including at least two computing IC dies; mounting the IC interposer die on a substrate; and mounting a memory stack on the substrate, the memory stack being electrically coupled to the computing die stack through the IC interposer die.

[0140] While the foregoing describes embodiments of the present invention, other and additional embodiments of the invention may be devised without departing from the basic scope of the invention, and the scope of the invention is defined by the appended claims.

Claims

1. A chip package, the chip package comprising: Substrate; An integrated circuit (IC) interposer die, the integrated circuit (IC) interposer die being mounted on the substrate; A compute die stack is mounted on the IC interposer die. and A memory stack, which is mounted on the substrate and electrically coupled to the computing die stack via the IC interposer die.

2. The chip package according to claim 1, wherein the computing die stack further comprises: At least the first and second computed bare wafers.

3. The chip package of claim 2, wherein the first computing die includes an accelerated computing core, and the second computing die includes a central processing unit (CPU) core.

4. The chip package according to claim 2, wherein the first computing die and the second computing die include an accelerated computing core.

5. The chip package according to claim 1, wherein the computing die stack further comprises: A molding compound disposed between the memory stack and the compute die stack; and A metal layer is formed to contact the top surface of the molded compound, the top surface of the memory stack, and the top surface of the computing die stack.

6. The chip package according to claim 1, wherein: The substrate is an intermediary layer; and The intermediate layer is mounted on the packaging substrate.

7. The chip package according to claim 2, wherein the IC interposer die further comprises: A memory controller circuit, which is coupled to both the first compute die and the second compute die, without routing signals through the package substrate; and A cache memory circuit coupled to both the first and second compute dies, without routing signals through the substrate.

8. A chip package, the chip package comprising: Substrate; A first integrated circuit (IC) interposer die, the first integrated circuit (IC) interposer die being mounted on the substrate, the first IC interposer die including memory controller circuitry; A first computing die stack is mounted on the first IC interposer die. The first computing die stack includes at least a first computing die and a second computing die, both of which are communicatively coupled to the memory controller circuitry. A first memory stack is mounted on the substrate and electrically coupled to the memory controller circuit via the substrate; A cover is disposed on top of the first memory stack and the first compute die stack; and A thermal interface material configured to contact both the first compute die stack and the cover.

9. The chip package according to claim 8, further comprising: A second compute die stack is mounted on the first IC interposer die and includes a plurality of compute dies communicatively coupled to the memory controller circuitry.

10. The chip package according to claim 8, wherein the chip package further comprises: A second memory stack is mounted on the substrate and electrically coupled to the memory controller circuitry via the substrate.

11. The chip package according to claim 8, wherein the chip package further comprises: A second IC interposer die is mounted on the substrate and includes memory controller circuitry. A second compute die stack is mounted on the second IC interposer die and includes a plurality of compute dies communicatively coupled to the memory controller circuitry of the second IC interposer die. and A second memory stack is mounted on the substrate and electrically coupled to the memory controller circuit of the second IC interposer die via the substrate.

12. The chip package of claim 2 or 8, wherein at least one or both of the first computing die and the second computing die comprise a central processing unit (CPU) core.

13. The chip package of claim 8, wherein at least one or both of the first computing die and the second computing die include an accelerated computing core.

14. The chip package of claim 8, wherein the first computing die stack further comprises: A carrier die, wherein the carrier die is disposed on a first computing die and a second computing die; and A dummy die without circuitry is disposed between the first IC interposer die and the carrier die, wherein the dummy die is fused to at least two of the first computing die, the second computing die, the first IC interposer die, and the carrier die.

15. The chip package according to claim 7 or 8, wherein the first IC interposer die further comprises: A cache memory circuit, coupled to both the first and second compute dies, without routing signals through the substrate, On-chip network (NOC) circuitry; High-speed PCIe (PCIe) circuitry for peripheral component interconnection; A memory physical layer (PHY) circuit, the memory physical layer (PHY) circuit being configured to communicate with the first memory stack; A die-to-die PHY configured to communicate with at least one of the first compute die and the second compute die; and I / O PHY, which is configured to communicate with devices located remotely from the chip package.

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