Display device

Abstract

The present invention provides a display device including pixels arranged in a display area, the display device including: a first conductive layer including a first voltage line; a second conductive layer disposed on the first conductive layer and including a first conductive pattern overlapping the first voltage line; a semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the first conductive pattern; a third conductive layer disposed on the semiconductor layer and including a second conductive pattern overlapping the first conductive pattern; and a fourth conductive layer disposed on the third conductive layer and including a data line and a third conductive pattern overlapping the second conductive pattern, in which the first voltage line includes a body portion extending in a first direction and a shield portion extending from the body portion in a second direction crossing the first direction to overlap the data line.

Description

Technical Field

[0001] The present invention relates to display devices, and more particularly, to display devices having improved display quality. Background Technology

[0002] Currently, the applications of display devices have diversified. Furthermore, display devices are becoming increasingly thinner and lighter, and therefore, their uses have expanded.

[0003] As display devices are being used for a variety of purposes, there are various ways to design the shape of display devices, and the functions that can be connected to or associated with display devices have increased. Summary of the Invention Technical issues

[0004] One or more embodiments include a display device with improved display quality. However, these issues are illustrative, and the scope of the embodiments described below is not limited thereto. Solution to the problem

[0005] According to one or more embodiments, a display device including pixels arranged in a display area includes: a first conductive layer including a first voltage line; a second conductive layer disposed on the first conductive layer and including a first conductive pattern overlapping the first voltage line; a semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the first conductive pattern; a third conductive layer disposed on the semiconductor layer and including a second conductive pattern overlapping the first conductive pattern; and a fourth conductive layer disposed on the third conductive layer and including a data line and a third conductive pattern overlapping the second conductive pattern, wherein the first voltage line includes a body portion extending in a first direction and a shielding portion extending from the body portion in a second direction to overlap the data line, the second direction intersecting the first direction.

[0006] In an embodiment, the third conductive layer may further include a first connection electrode, and the fourth conductive layer may further include a second connection electrode, wherein the shielding portion may be electrically connected to the first semiconductor pattern via the first connection electrode and the second connection electrode.

[0007] In an embodiment, the shielding portion may be spaced apart from the first semiconductor pattern in a plan view.

[0008] In an embodiment, the first conductive layer may further include a fourth conductive pattern that overlaps with the second conductive pattern, wherein the second conductive pattern may be electrically connected to the fourth conductive pattern, and the first conductive pattern may be electrically connected to the third conductive pattern.

[0009] In an embodiment, the data line may include a first data line, a second data line, and a third data line, and the shielding portion may include a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line, wherein the first shielding portion, the second shielding portion, and the third shielding portion may have the same area.

[0010] In an embodiment, the data line may include a first data line, a second data line, and a third data line, and the shielding portion may include a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line, wherein the area of ​​the first shielding portion may be different from the area of ​​the second shielding portion and the area of ​​the third shielding portion.

[0011] In one embodiment, a pixel may include a red pixel that emits red light, a blue pixel that emits blue light, and a green pixel that emits green light, wherein a first data line may be electrically connected to the red pixel.

[0012] In an embodiment, the first conductive layer may further include a second voltage line extending in the first direction, and the semiconductor layer may further include a second semiconductor pattern electrically connected between the data line and the second voltage line.

[0013] In an embodiment, the third conductive layer may further include a first gate line that overlaps with the first semiconductor pattern and is configured to transmit a first gate signal, and a second gate line that overlaps with the second semiconductor pattern and is configured to transmit a second gate signal. The pixel may operate during a non-emission period and an emission period during a frame period, wherein, during the non-emission period, the first gate signal may become an on voltage after the second gate signal becomes an on voltage, and the first gate signal may become an off voltage after the second gate signal becomes an off voltage.

[0014] In one embodiment, during the on-voltage period of the second gate signal, the reference voltage can be transmitted to the second conductive pattern via the second voltage line.

[0015] In an embodiment, the display device may further include: a fifth conductive layer disposed on the fourth conductive layer, and including a third voltage line extending in a second direction and overlapping with the data line.

[0016] In an embodiment, the display device may further include: a voltage supply line disposed in a peripheral region outside the display area and extending in a first direction, wherein a third voltage line may pass through the display area and be connected to the voltage supply line in the peripheral region.

[0017] In an embodiment, a pixel may include a display element, which includes a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode, wherein the voltage supplied to the third voltage line may be equal to the voltage supplied to the counter electrode.

[0018] In an embodiment, a pixel may include a display element, which includes a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode, wherein the voltage supplied to the third voltage line may be different from the voltage supplied to the counter electrode.

[0019] In an embodiment, the display device may further include: a fifth conductive layer disposed on the fourth conductive layer and including a fourth voltage line extending in a second direction; and a sixth conductive layer disposed on the fifth conductive layer and including a pixel electrode, an auxiliary electrode, and a fifth voltage line extending in the first direction and connecting adjacent auxiliary electrodes among the auxiliary electrodes.

[0020] In an embodiment, the display device may further include a pixel defining layer disposed on the sixth conductive layer and defining pixel openings and auxiliary openings, wherein each of the pixel openings may overlap with a corresponding one of the pixel electrodes, and each of the auxiliary openings may overlap with a corresponding one of the auxiliary electrodes that overlaps with the fourth voltage line.

[0021] According to one or more embodiments, a display device includes: a first pixel circuit electrically connected to a first light-emitting diode and a second pixel circuit electrically connected to a second light-emitting diode, wherein each of the first pixel circuit and the second pixel circuit includes: a first voltage line extending in a first direction; a data line disposed on the first voltage line and extending in a second direction intersecting the first direction; a capacitor including a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode; a first transistor electrically connected between the first voltage line and the capacitor; a second transistor electrically connected to the data line and the gate electrode of the first transistor; a third transistor electrically connected to the gate electrode of the first transistor and the second voltage line extending in the first direction; and a fourth transistor electrically connected between the first voltage line and the first transistor, wherein the first voltage line includes a body portion and a shielding portion extending from the body portion in the second direction to overlap with the data line.

[0022] In this embodiment, the area of ​​the shielding portion of the first pixel circuit may be smaller than the area of ​​the shielding portion of the second pixel circuit.

[0023] In one embodiment, the first light-emitting diode can emit red light.

[0024] In this embodiment, the first voltage line and the second voltage line can be disposed in the same layer.

[0025] In an embodiment, each frame period of the first pixel circuit and the second pixel circuit may include a non-transmission period and a transmission period, wherein the non-transmission period may include: a first period in which the third transistor and the fourth transistor are turned on before the write period in which the data signal is supplied from the data line; and a second period in which the fourth transistor remains turned on after the third transistor is turned off.

[0026] In an embodiment, each of the first light-emitting diode and the second light-emitting diode may include a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode, and the display device may further include: an auxiliary electrode located in the same layer as the pixel electrode; and a third voltage line connecting the auxiliary electrodes to each other and extending in a first direction.

[0027] In an embodiment, the display device may further include a fourth voltage line disposed between the data line and the pixel electrode and extending in a second direction, wherein, among the auxiliary electrodes, the auxiliary electrode overlapping the fourth voltage line may be electrically connected to the third voltage line.

[0028] In an embodiment, the auxiliary electrode that overlaps with the fourth voltage line can be in direct contact with the counter electrode.

[0029] In an embodiment, the display device may further include a fifth voltage line located in the same layer as the fourth voltage line and overlapping with the data line, wherein the fifth voltage line may be spaced apart from the third voltage line by at least one insulating layer.

[0030] Other aspects, features, and advantages, besides those described above, will become apparent from the detailed description of the present invention. Beneficial effects of the invention

[0031] As described above, a display device with improved display quality can be provided according to one or more of the above embodiments. However, the scope of the invention is not limited to the embodiments disclosed herein. Attached Figure Description

[0032] Figure 1 and Figure 2 This is a schematic diagram illustrating a display device according to an embodiment.

[0033] Figure 3 It is an equivalent circuit diagram of pixels included in a display device according to an embodiment.

[0034] Figure 4 This is for illustrative purposes based on the embodiments. Figure 3 The timing diagram of the signals for the operation of the pixels is shown in the figure.

[0035] Figure 5This is a circuit diagram schematically illustrating the connection relationship between a pixel and a second initialization voltage line according to an embodiment.

[0036] Figures 6 to 11 This is a schematic diagram illustrating the layer-by-layer layout of pixels according to an embodiment.

[0037] Figure 12 This is a schematic layout diagram illustrating the arrangement of pixel electrodes of a pixel according to an embodiment.

[0038] Figure 13a , Figure 13b and Figure 14 This is a schematic diagram illustrating the first voltage line and data line according to an embodiment.

[0039] Figure 15 This is a schematic diagram illustrating the arrangement of vertical voltage lines according to an embodiment.

[0040] Figure 16 This is a schematic layout diagram illustrating the arrangement of pixels and voltage lines according to an embodiment.

[0041] Figure 17a and Figure 17b This is a schematic cross-sectional view of pixels and voltage lines according to an embodiment.

[0042] Figure 18a and Figure 18b This is a schematic diagram illustrating the voltage lines according to an embodiment.

[0043] Figures 19a to 19d This is a cross-sectional view showing the structure of a display element according to an embodiment.

[0044] Figure 20a and Figure 20b This is a cross-sectional view showing the structure of a display element according to an embodiment.

[0045] Figure 21 This is a cross-sectional view showing the structure of the pixels of a display device according to an embodiment. Detailed Implementation

[0046] According to one or more embodiments, a display device including pixels arranged in a display area includes: a first conductive layer including a first voltage line; a second conductive layer disposed on the first conductive layer and including a first conductive pattern overlapping the first voltage line; a semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the first conductive pattern; a third conductive layer disposed on the semiconductor layer and including a second conductive pattern overlapping the first conductive pattern; and a fourth conductive layer disposed on the third conductive layer and including a data line and a third conductive pattern overlapping the second conductive pattern, wherein the first voltage line includes a body portion extending in a first direction and a shielding portion extending from the body portion in a second direction to overlap the data line, the second direction intersecting the first direction.

[0047] According to one or more embodiments, a display device includes: a first pixel circuit electrically connected to a first light-emitting diode and a second pixel circuit electrically connected to a second light-emitting diode, wherein each of the first pixel circuit and the second pixel circuit includes: a first voltage line extending in a first direction; a data line disposed on the first voltage line and extending in a second direction intersecting the first direction; a capacitor including a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode; a first transistor electrically connected between the first voltage line and the capacitor; a second transistor electrically connected to the data line and the gate electrode of the first transistor; a third transistor electrically connected to the gate electrode of the first transistor and the second voltage line extending in the first direction; and a fourth transistor electrically connected between the first voltage line and the first transistor, wherein the first voltage line includes a body portion and a shielding portion extending from the body portion in the second direction to overlap with the data line. The method of the present invention

[0048] Various modifications can be applied to this invention, and specific embodiments will be illustrated in the accompanying drawings and described in the detailed description section. The effects, features, and implementation methods of this invention will become clearer with reference to the following detailed description taken in conjunction with the accompanying drawings. However, this invention can be implemented in various forms and is not limited to the embodiments presented below.

[0049] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding components are indicated by the same reference numerals, and their redundant descriptions are omitted.

[0050] In this specification, it will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various components, regions, layers, and / or portions, these components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one component from another. Therefore, it will be understood that a "first" component, region, layer, or portion mentioned herein may be referred to as a "second" component, region, layer, or portion without departing from the technical scope of the invention.

[0051] In this specification, as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0052] In this specification, it will be further understood that the terms “comprising,” “including,” and / or “having” as used herein indicate the presence of a stated feature or component, but do not exclude the presence or addition of one or more other features or components.

[0053] In this specification, it will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, it can be formed directly or indirectly on that other layer, region, or component. That is, for example, an intermediary layer, region, or component may exist.

[0054] In this specification, "in a plan view" means the target portion viewed from above, and "in a cross-sectional view" means a vertically cut section of the target portion viewed from the side.

[0055] In this specification, the fact that the first component "overlaps" with the second component means that the first component is located above or below the second component and overlaps with at least a portion of the second component in the plan view. For ease of illustration, the dimensions of the components in the figures may be exaggerated. For example, the invention is not limited thereto because the dimensions and thicknesses of the components in the figures are arbitrarily illustrated for ease of illustration.

[0056] In this specification, the expression "A and / or B" may mean A, B, or A and B. Similarly, in this specification, the expression "at least one of A and B" may mean A, B, or A and B.

[0057] In this specification, when X and Y are connected, it can include cases where X and Y are functionally connected, cases where X and Y are directly connected, and cases where another component is between X and Y and thus X and Y are indirectly connected. Here, X and Y can be objects (e.g., devices, components, circuits, wires, electrodes, terminals, conductive films or layers, etc.). For example, when X and Y are electrically connected, it can include cases where X and Y are directly electrically connected and / or cases where another component is between X and Y and thus X and Y are indirectly electrically connected. For example, when X and Y are indirectly electrically connected, it can include cases where one or more components (e.g., switches, transistors, capacitors, inductors, resistors, diodes, etc.) capable of enabling the electrical connection between X and Y are connected between X and Y. Accordingly, the connection relationship is not limited to, for example, the connection relationships indicated in the drawings or detailed description, and may include connection relationships other than those indicated in the drawings or detailed description.

[0058] In this specification, the term "on" as used in association with the state of a component can refer to the active state of the component, and "off" can refer to the deactivated state of the component. The term "on" as used in association with a signal received by the component can refer to a signal used to activate the component, and "off" can refer to a signal used to deactivate the component. A component can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, and an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Accordingly, it should be understood that the "on" voltages of P-type transistors and N-type transistors are opposite (low to high) voltage levels.

[0059] In this specification, the x, y, and z directions are not limited to directions along the three axes of a Cartesian coordinate system and can be interpreted in a general sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and this disclosure, and shall not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0061] The display device according to the embodiments can be a device for displaying video or still images. The display device can be used as a display screen for various devices such as televisions, laptop computers, monitors, broadcast panels, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Furthermore, the display device according to the embodiments can be used in wearable devices such as smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs). Additionally, the display device according to the embodiments can be used as a central information display (CID) located on the instrument panel or center fascia or dashboard of a vehicle, an interior mirror display replacing the side mirrors of a vehicle, or a display mounted on the back of the front seats as a rear-seat entertainment device. Furthermore, the display device can be a flexible device.

[0062] Figure 1 and Figure 2 This is a schematic diagram illustrating a display device according to an embodiment.

[0063] In the embodiments and reference Figure 1 The display device 10 may include a display area DA for displaying an image and a peripheral area PA disposed around the display area DA. The display device 10 can provide a specific image by using light emitted from pixels disposed in the display area DA. The peripheral area PA is an area disposed around the display area DA and may be a non-display area in which no pixels are disposed. The display area DA may be completely surrounded by the peripheral area PA. In the peripheral area PA, various wirings configured to transmit electrical signals to be applied to the display area DA and pads to which printed circuit boards or driver integrated circuit (IC) chips are attached may be provided.

[0064] In the embodiments and reference Figure 2 The display device 10 may include a pixel portion 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0065] In this embodiment, the pixel portion 11 may be provided in the display area DA. In the peripheral area PA, various wires configured to transmit electrical signals to be applied to the display area DA, external circuitry electrically connected to the pixel circuitry, and pads to which a printed circuit board or driver IC chip is attached may be provided. For example, a gate drive circuit 13, a data drive circuit 15, a power supply circuit 17, and a controller 19 may be provided in the peripheral area PA.

[0066] In the embodiments and as Figure 2As shown, multiple gate lines GL, multiple data lines DL, and multiple pixels PX connected to the gate lines GL and data lines DL can be arranged in the display area DA. The multiple pixels PX can be arranged in various configurations, such as stripes, pentile patterns (diamond patterns), mosaic patterns, etc., to realize an image. Each pixel PX can include an organic light-emitting diode (OLED) as a display element (light-emitting device), and the OLED can be connected to a pixel circuit. The pixel circuit can include multiple transistors and at least one capacitor. The pixel PX can emit light, such as red, green, blue, or white light, through the OLED. Each pixel PX can be connected to at least one gate line GL corresponding to that pixel PX and one data line DL corresponding to that pixel PX among the multiple gate lines GL.

[0067] In this embodiment, each of the gate lines GL can extend in the x-direction (row direction) and can be connected to pixels PX arranged in the same row. Each of the gate lines GL can be configured to transmit a gate signal to the pixels PX arranged in the same row. Each of the data lines DL can extend in the y-direction (column direction) and can be connected to pixels PX arranged in the same column. Each of the data lines DL can be synchronized with the gate signal and can be configured to transmit a data signal to each of the pixels PX in the same column.

[0068] In one embodiment, the peripheral region PA can be a non-display area in which no pixels PX are arranged. In another embodiment, a portion of the peripheral region PA can be implemented as a display region DA. For example, multiple pixels PX can be arranged to overlap with the gate drive circuit 13 at at least one corner of the peripheral region PA. Accordingly, the dead zone can be reduced and the display region DA can be expanded.

[0069] In an embodiment, the gate driving circuit 13 can be connected to multiple gate lines GL, can generate gate signals in response to control signals GCS from the controller 19, and can sequentially supply the gate signals to the multiple gate lines GL. Each of the multiple gate lines GL can be connected to the gate of a transistor included in the pixel PX. The gate signal can be a gate control signal that controls the on and off states of the transistor whose gate is connected to the gate line GL. The gate signal can be a square wave signal including an on-state voltage that can turn on the transistor and an off-state voltage that can turn off the transistor. In an embodiment, the on-state voltage can be a high-level voltage (first-level voltage) or a low-level voltage (second-level voltage).

[0070] In an embodiment, Figure 2The illustration shows a pixel PX connected to a single gate line GL. However, this embodiment is merely an example, and the pixel PX can be connected to two or more gate lines, with the gate driving circuit 13 supplying two or more gate signals with different timings and applied turn-on voltages to the corresponding gate lines. For example, the pixel PX can be connected to first to third gate lines, as well as a first emitter control line and a second emitter control line, and the gate driving circuit 13 can apply a first gate signal GW, a second gate signal GI, a third gate signal GR, a first emitter control signal EM, and a second emitter control signal EMB to the first gate line, the second gate line, the third gate line, the first emitter control line, and the second emitter control signal EMB can be a gate control signal controlling the turn-on and turn-off of a transistor whose gate is connected to the first emitter control line.

[0071] In this embodiment, the data driving circuit 15 can be connected to multiple data lines DL and can supply a data signal Vdata to the data lines DL in response to a control signal DCS from the controller 19. The data signal Vdata supplied through the data lines DL can be supplied to the pixel PX to which the gate signal is supplied. The data driving circuit 15 can convert the input image data DATA with grayscale levels input from the controller 190 into a data signal Vdata in the form of voltage or current.

[0072] In this embodiment, the power supply circuit 17 can generate the voltage required to drive the pixel PX in response to a control signal PCS from the controller 19. The power supply circuit 17 can generate a first driving voltage ELVDD and a second driving voltage ELVSS, and can supply the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PX. The first driving voltage ELVDD can be a high-level voltage supplied to a first electrode (pixel electrode or anode) of the display element included in the pixel PX. The second driving voltage ELVSS can be a low-level voltage supplied to a second electrode (counter electrode or cathode) of the display element included in the pixel PX. The power supply circuit 17 can generate a reference voltage Vref and an initialization voltage Vaint, and can supply the reference voltage Vref and the initialization voltage Vaint to the pixel PX.

[0073] In this embodiment, the voltage level of the first driving voltage ELVDD can be higher than the voltage level of the second driving voltage ELVSS. The voltage level of the reference voltage Vref can be lower than the voltage level of the first driving voltage ELVDD. The voltage level of the initialization voltage Vaint can be the same as or higher than the voltage level of the second driving voltage ELVSS.

[0074] In this embodiment, the controller 19 can generate control signals GCS, DCS, and PCS based on signals input from an external source, and supply these control signals to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17, respectively. The control signal GCS output to the gate drive circuit 13 may include multiple clock signals and a gate start signal. The control signal DCS output to the data drive circuit 15 may include a source start signal and a clock signal.

[0075] In one embodiment, the display device 10 may include a display panel, and the display panel may include a substrate. In this embodiment, the fact that the substrate has a display area DA and a peripheral area PA indicates that the substrate has an area corresponding to the display area DA and an area corresponding to the peripheral area PA. Pixels PX may be arranged in the display area DA of the substrate. During the process of forming transistors constituting pixel circuits in the display area DA of the substrate, a portion or the entire gate drive circuit 13 may be directly formed in the peripheral area PA of the substrate. The data drive circuit 15, power supply circuit 17, and controller 19 may be formed as separate integrated circuit chips or as a single integrated circuit chip, and may be arranged on a flexible printed circuit board (FPCB) electrically connected to pads disposed on one side of the substrate. In another embodiment, the data drive circuit 15, power supply circuit 17, and controller 19 may be directly arranged on the substrate using a chip-on-glass (COG) method or a chip-on-plastic (COP) method.

[0076] In one embodiment, the plurality of transistors included in the pixel circuit may be N-type oxide thin-film transistors. In another embodiment, the plurality of transistors included in the pixel circuit may be P-type silicon thin-film transistors. In yet another embodiment, some of the transistors included in the pixel circuit may be N-type oxide thin-film transistors, and the others may be P-type silicon thin-film transistors.

[0077] In an embodiment, each of the N-type oxide thin-film transistors may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the active pattern (semiconductor layer) comprises oxide. However, this is an example, and the N-type oxide thin-film transistor is not limited thereto. For example, the active pattern (semiconductor layer) included in the N-type oxide thin-film transistor may comprise an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon) or an organic semiconductor. Each of the P-type silicon thin-film transistors may be a low-temperature polycrystalline silicon (LTPS) thin-film transistor in which the active pattern (semiconductor layer) comprises amorphous silicon, polycrystalline silicon, etc.

[0078] Figure 3 It is an equivalent circuit diagram including pixels in a display device according to an embodiment, and Figure 4This is for illustrative purposes based on the embodiments. Figure 3 The timing diagram of the signals for the operation of the pixels is shown in the figure.

[0079] In the embodiments and reference Figure 3 A pixel PX may include an organic light-emitting diode (OLED) as a display element and a pixel circuit PC connected to the OLED. The pixel circuit PC may include first transistors T1 to T6, a first capacitor C1, and a second capacitor C2. The first transistor T1 may be a driving transistor configured to output a driving current corresponding to a data signal, and the second transistors T2 to T6 may each be a switching transistor configured to transmit signals. The first terminal (first electrode) of each of the first transistors T1 to T6 may be a source or a drain, and the second terminal (second electrode) of each of the first transistors T1 to T6 may be a terminal different from the first terminal. For example, when the first terminal is a drain, the second terminal may be a source. The node to which the gate of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal (source) of the first transistor T1 is connected may be defined as a second node N2. The node to which the pixel electrode (anode) of the OLED is connected may be defined as a third node N3.

[0080] In this embodiment, pixel PX can be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a first transmit control line EML configured to transmit a first transmit control signal EM, a second transmit control line EMBL configured to transmit a second transmit control signal EMB, and a data line DL configured to transmit a data signal Vdata. Additionally, pixel PX can be connected to a drive voltage line PL configured to transmit a first drive voltage ELVDD, a reference voltage line VL1 configured to transmit a reference voltage Vref, and an initialization voltage line VL2 configured to transmit an initialization voltage Vaint.

[0081] In one embodiment, a first transistor T1 may be connected between a drive voltage line PL and a second node N2. The first transistor T1 may include a gate, a first terminal connected to the drive voltage line PL via a fifth transistor T5, and a second terminal connected to the second node N2. The first transistor T1 may include a first gate connected to the first node N1 and a second gate connected to the second node N2. The first and second gates may be arranged to face each other on different layers. For example, the first and second gates of the first transistor T1 may be positioned opposite each other with a semiconductor layer interposed therebetween. Because a first capacitor C1 is disposed between the first node N1 and the second node N2, the first transistor T1 may be disposed between the drive voltage line PL and the first capacitor C1. The first transistor T1 can receive a data signal Vdata according to the switching operation of the second transistor T2 and can control the amount of drive current Id flowing to the organic light-emitting diode (OLED).

[0082] In this embodiment, the second transistor T2 may be connected between the data line DL and the first node N1. The second transistor T2 may also be connected between the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 may be configured to be turned on by a first gate signal GW transmitted through the first gate line GWL, electrically connecting the data line DL to the first node N1, and transmitting the data signal Vdata transmitted through the data line DL to the first node N1.

[0083] In one embodiment, a third transistor T3 may be connected between the first node N1 and the reference voltage line VL1. The third transistor T3 may be connected between the reference voltage line VL1 and the first gate of the first transistor T1. The third transistor T3 may include a gate connected to a third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VL1. The third transistor T3 may be configured to be turned on by a third gate signal GR transmitted through the third gate line GRL, and may transmit a reference voltage Vref transmitted through the reference voltage line VL1 to the first node N1.

[0084] In one embodiment, a fourth transistor T4 may be connected between the first transistor T1 and the initialization voltage line VL2. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VL2. The fourth transistor T4 may be configured to be turned on by a second gate signal GI transmitted through the second gate line GIL, and may transmit the initialization voltage Vaint transmitted through the initialization voltage line VL2 to the third node N3.

[0085] In one embodiment, a fifth transistor T5 may be connected between the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the first transmit control line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 may be configured to be turned on or off according to a first transmit control signal EM transmitted via the first transmit control line EML.

[0086] In one embodiment, a sixth transistor T6 may be connected between the first transistor T1 and the third node N3. The sixth transistor T6 may include a gate connected to the second transmit control line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The sixth transistor T6 may be configured to be turned on or off according to a second transmit control signal EMB transmitted via the second transmit control line EMBL.

[0087] In an embodiment, when the fifth transistor T5 is turned on according to the first emission control signal EM received through the first emission control line EML and the sixth transistor T6 is turned on according to the second emission control signal EMB received through the second emission control line EMBL, the drive current Id can flow to the organic light-emitting diode OLED.

[0088] In this embodiment, a first capacitor C1 may be connected between a first node N1 and a second node N2. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the second node N2. The first capacitor C1 may be a storage capacitor and may store a voltage corresponding to the data signal Vdata and the threshold voltage of the first transistor T1.

[0089] In this embodiment, the second capacitor C2 can be connected between the driving voltage line PL and the second node N2. The first electrode of the second capacitor C2 can be connected to the driving voltage line PL, and the second electrode of the second capacitor C2 can be connected to the second node N2. The capacitance of the first capacitor C1 can be greater than the capacitance of the second capacitor C2.

[0090] In an embodiment, the organic light-emitting diode (OLED) may include a pixel electrode (anode) connected to a third node N3 and a counter electrode (cathode) facing the pixel electrode, and the counter electrode may be supplied with a second driving voltage ELVSS. The counter electrode may be a common electrode shared by multiple pixels PX.

[0091] In this embodiment, pixels PX can display the image within each frame period. (Reference) Figure 4A frame time period may include a transmission time period EP and a non-transmission time period NEP in which pixels PX do not emit light. The non-transmission time period NEP may include a first initialization time period P1, a compensation time period P2, a write time period P3, and a second initialization time period P4.

[0092] In this embodiment, the first gate signal GW, the second gate signal GI, the third gate signal GR, the first transmit control signal EM, and the second transmit control signal EMB may each have a high-level voltage for some time periods and a low-level voltage for some time periods. Here, the high-level voltage can be the turn-on voltage of a conducting transistor, and the low-level voltage can be the turn-off voltage of a cutting-off transistor.

[0093] In an embodiment, during a first initialization period P1, a second gate signal GI with an on-state voltage can be supplied to a second gate line GIL, and a third gate signal GR with an on-state voltage can be supplied to a third gate line GRL. The first initialization period P1 can be defined as the period during which the on-state voltage period of the second gate signal GI (i.e., the period during which the on-state voltage is maintained) overlaps with the on-state voltage period of the third gate signal GR. During the first initialization period P1, a second transmit control signal EMB can be supplied with an on-state voltage, and then inverted and supplied with a cutoff voltage. In other words, the second transmit control signal EMB can be at an on-state voltage, and then at a cutoff voltage that is the inverted voltage of the on-state voltage. Additionally, the first gate signal GW and the first transmit control signal EMB can each have a cutoff voltage.

[0094] In this embodiment, the fourth transistor T4 can be turned on by the second gate signal GI, and the third transistor T3 can be turned on by the third gate signal GR. During the first initialization period P1, the sixth transistor T6, which is in the on state, can be turned off by the second emitter control signal EMB. The first node N1 (i.e., the gate of the first transistor T1) can be initialized to the reference voltage Vref by the turned-on third transistor T3. The third node N3 (i.e., the pixel electrode of the organic light-emitting diode OLED) can be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4. The second node N2 can be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4 and the turned-on sixth transistor T6.

[0095] In this embodiment, during the compensation period P2, a third gate signal GR with an on-state voltage can be supplied to a third gate line GRL, and a first transmit control signal EM with an on-state voltage can be supplied to a first transmit control line EML. The compensation period P2 can be defined as the period during which the on-state voltage period of the third gate signal GR overlaps with the on-state voltage period of the first transmit control signal EM. Furthermore, the first gate signal GW, the second gate signal GI, and the second transmit control signal EMB can each have a cutoff voltage.

[0096] In this embodiment, the third transistor T3 can be turned on by the third gate signal GR, and the fifth transistor T5 can be turned on by the first emitter control signal EM. Accordingly, a reference voltage Vref can be supplied to the first node N1, and a first drive voltage ELVDD can be supplied to the first terminal of the first transistor T1, thus turning on the first transistor T1. When the voltage at the second terminal of the first transistor T1 (i.e., the second node N2) is lower than the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off. Furthermore, the voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the first capacitor C1, thus compensating for the threshold voltage (Vth) of the first transistor T1.

[0097] In this embodiment, the third gate signal GR can be maintained at an on-state voltage from the beginning of the first initialization period P1, and then reversed at the end of the compensation period P2 to be supplied as a cutoff voltage. The first transmit control signal EM can be maintained at an on-state voltage from the end of the compensation period P2 for a first time t1. After the end of the compensation period P2, when the third gate signal GR is at a cutoff voltage, the third transistor T3 can be turned off and the first node N1 can be electrically floated for the first time t1. Therefore, when the voltage of the first transmit control signal EM is reversed to a cutoff voltage, the gate-source voltage (Vgs) of the first transistor T1 can be maintained relatively constant, and the backlash caused by the cutoff of the fifth transistor T5 can be reduced. In this embodiment, the first time t1 can be four horizontal periods (4H).

[0098] In this embodiment, during the write phase P3, a first gate signal GW with an on-state voltage can be supplied to the first gate line GWL, and thus, the second transistor T2 can be turned on. In this case, the second gate signal GI, the third gate signal GR, the first transmit control signal EM, and the second transmit control signal EMB can each be at their off-state voltages, and the third to sixth transistors T3, T4, T5, and T6 can each be turned off. The second transistor T2 can transmit the data signal Vdata from the data line DL to the first node N1 (i.e., the gate of the first transistor T1). Accordingly, the voltage of the first node N1 can be changed from the reference voltage Vref to a voltage corresponding to the data signal Vdata.

[0099] In an embodiment, the first gate signal GW applied to the pixel circuit in the nth row may partially overlap with the first gate signal GW[n+1] applied to the pixel circuit in the next row (n+1th row). For example, the first gate signal GW applied to the pixel circuit in the nth row and the first gate signal GW[n+1] applied to the pixel circuit in the n+1th row may overlap each other at a second time t2, and the second time t2 may be at least two horizontal time periods (2H). By partially overlapping the first gate signals GW and GW[n+1], high-frequency driving of the display device 10 may be possible.

[0100] In this embodiment, during the second initialization period P4, a second gate signal GI with an on-state voltage can be supplied to the second gate line GIL. The second initialization period P4 can be defined as the on-state voltage period of the second gate signal GI after the write period P3. During the second initialization period P4, the second transmit control signal EMB can be at a cutoff voltage, and then at an on-state voltage that is the inversion of the cutoff voltage. Additionally, the first gate signal GW, the third gate signal GR, and the first transmit control signal EMB can each be at a cutoff voltage, and the second transistor T2, the third transistor T3, and the fifth transistor T5 can be turned off. The fourth transistor T4 can be turned on by the second gate signal GI, and the sixth transistor T6 can be turned on by the second transmit control signal EMB. The third node N3 (i.e., the pixel electrode of the organic light-emitting diode OLED) can be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4. The second node N2 can be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4 and the turned-on sixth transistor T6. By initializing the second node N2 before the transmit period EP, the variable refresh rate characteristics of the display device 10 can be improved.

[0101] In this embodiment, the second transmit control signal EMB can remain on even after the end of the second initialization period P4. Subsequently, during the transmit period EP, the first transmit control signal EM can be on, and the first gate signal GW, the second gate signal GI, and the third gate signal GR can each be off. The second transistor T2, the third transistor T3, and the fourth transistor T4 can be off by the first gate signal GW, the third gate signal GR, and the second gate signal GI, respectively, and the fifth transistor T5 and the sixth transistor T6 can be on by the first transmit control signal EM and the second transmit control signal EMB, respectively.

[0102] In an embodiment, the first transistor T1 can output a drive current Id with a magnitude corresponding to the gate-source voltage (Vgs) of the first transistor T1, and the organic light-emitting diode OLED can emit light with a brightness corresponding to the magnitude of the drive current Id.

[0103] Figure 5 This is a circuit diagram schematically illustrating the connection relationship between pixels and initialization voltage lines according to an embodiment.

[0104] In the embodiments and reference Figure 5 A pixel may include a first pixel PXr that emits light of a first color, a second pixel PXg that emits light of a second color, and a third pixel PXb that emits light of a third color. For example, the first pixel PXr may be a red pixel, the second pixel PXg may be a green pixel, and the third pixel PXb may be a blue pixel. In an embodiment, by taking into account the light-emitting characteristics of the first pixel PXr, the second pixel PXg, and the third pixel PXb, different initialization voltages Vaint can be supplied to the first pixel PXr, the second pixel PXg, and the third pixel PXb.

[0105] In the embodiments and as Figure 5 As shown, the first pixel PXr can be connected to the first initialization voltage line VL21, which is configured to supply the first initialization voltage Vaint1; the second pixel PXg can be connected to the second initialization voltage line VL22, which is configured to supply the second initialization voltage Vaint2; and the third pixel PXb can be connected to the third initialization voltage line VL23, which is configured to supply the third initialization voltage Vaint3. The first initialization voltage Vaint1, the second initialization voltage Vaint2, and the third initialization voltage Vaint3 can have different voltage levels.

[0106] In another embodiment, the first pixel PXr and the third pixel PXb can be connected to the first initialization voltage line VL21, and the second pixel PXg can be connected to the second initialization voltage line VL22. In yet another embodiment, the first pixel PXr and the second pixel PXg can be connected to the first initialization voltage line VL21, and the third pixel PXb can be connected to the second initialization voltage line VL22. In yet another embodiment, the first pixel PXr can be connected to the first initialization voltage line VL21, and the second pixel PXg and the third pixel PXb can be connected to the second initialization voltage line VL22.

[0107] In an embodiment, a second initialization voltage line VL22 connected to at least one of the first pixel PXr, the second pixel PXg, and the third pixel PXb can be provided individually, and different initialization voltages Vaint can be supplied, thereby improving the problems of low grayscale brightness variation and color variation caused by the differences in the characteristics of organic light-emitting diodes (OLEDs).

[0108] Figures 6 to 11 This is a schematic diagram illustrating the layer-by-layer layout of pixels according to an embodiment. Figure 6 This is a schematic illustration according to an embodiment. Figure 3 The diagram shows the layout of the transistors and capacitors in the pixel circuit. Figures 7 to 11 This is a schematic layout diagram of the components of the pixel circuit according to an embodiment, shown layer by layer.

[0109] In an embodiment, the display area DA of the substrate is the area where rows (pixel rows) and columns (pixel columns) intersect, and may include multiple circuit areas in which pixel circuits are arranged. In an embodiment, a unit circuit area may be defined as comprising two or more circuit areas adjacent to each other in the x-direction, and a unit pixel may be defined by pixels arranged in the circuit areas constituting the unit circuit area. For example, a unit circuit area may include a first circuit area PCA1, a second circuit area PCA2, and a third circuit area PCA3 arranged adjacent to each other in the x-direction, and a unit pixel may include a first pixel PXr, a second pixel PXg, and a third pixel PXb. The first circuit area PCA1 may be the area in which the pixel circuits of the first pixel PXr are arranged. The second circuit area PCA2 may be the area in which the pixel circuits of the second pixel PXg are arranged. The third circuit area PCA3 may be the area in which the pixel circuits of the third pixel PXb are arranged.

[0110] In the embodiments, the same elements may be arranged in each layer of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. Hereinafter, for ease of illustration and description, the same reference numerals will be assigned to components of the same pixel circuit PC, and the description will focus on the first circuit region PCA1. The description of the first circuit region PCA1 can be equally applied to the same components of the second circuit region PCA2 and the third circuit region PCA3.

[0111] In the embodiments and reference Figure 6 The pixel circuits arranged in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3 can each correspond to Figure 3 The pixel circuit PC of pixel PX is shown in the figure. Figures 7 to 11 Each is shown as either a conductive layer or a semiconductor layer. In this specification, the fact that certain components are "located in the same layer" means that these components are formed using the same manufacturing process, include the same materials, and have the same layer structure, film quality, electrical properties, etc. At least one insulating layer may be disposed between the conductive layer and the semiconductor layer. Reference will be made below. Figures 7 to 11 A description is provided. In the following text, a connecting electrode can be an electrode that transmits signals by electrically connecting wiring and conductive patterns arranged in different layers.

[0112] In this embodiment, the first conductive layer 1100 may be disposed on the substrate. For example... Figure 7 As shown, the first conductive layer 1100 may include a driving voltage line PL, a reference voltage line VL1, a repair line RPL, and a first conductive pattern 1110.

[0113] In one embodiment, the first conductive pattern 1110 may be island-shaped and may be arranged in each of the first circuit region PCA1 and the second circuit region PCA2. In another embodiment, the first conductive pattern 1110 may not be arranged in the third circuit region PCA3. The first conductive pattern 1110 may be the first capacitor electrode of the first capacitor C1 described above.

[0114] In an embodiment, the driving voltage line PL may extend in a first direction (x-direction) and may pass through a first circuit region PCA1, a second circuit region PCA2, and a third circuit region PCA3. A first driving voltage ELVDD may be applied to the driving voltage line PL. The driving voltage line PL may include a body portion 1121 extending in the first direction (x-direction) in each circuit region, an electrode portion 1123 protruding from the body portion 1121 in a second direction (y-direction), and a shielding portion SHP protruding from the body portion 1121 in the second direction (y-direction).

[0115] In an embodiment, the width of the main body portion 1121 of the drive voltage line PL in the second direction (y direction) may be different in each circuit region. For example, the width of the main body portion 1121 in the first circuit region PCA1 may be smaller than the width of the main body portion 1121 in the second circuit region PCA2, and the width of the main body portion 1121 in the second circuit region PCA2 may be smaller than the width of the main body portion 1121 in the third circuit region PCA3.

[0116] In an embodiment, electrode portion 1123 may be disposed in each of the first circuit region PCA1 and the second circuit region PCA2. Electrode portion 1123 may be associated with the first semiconductor pattern 1310 (see...). Figure 9 The electrodes overlap and may include the first capacitor electrode of the second capacitor C2 described above. The electrode portion 1123 may not be arranged in the third circuit region PCA3.

[0117] In one embodiment, the shielding portion SHP may include a first shielding portion 1125 and a second shielding portion 1127 extending in opposite directions. For example, the first shielding portion 1125 may extend in the -y direction, and the second shielding portion 1127 may extend in the +y direction. In another embodiment, the area of ​​the shielding portion SHP may be different in each circuit region. For example, the area of ​​the shielding portion SHP of the first circuit region PCA1 may be smaller than the area of ​​the shielding portion SHP of the second circuit region PCA2 and the area of ​​the shielding portion SHP of the third circuit region PCA3. The shielding portion SHP of the first circuit region PCA1 may include only the first shielding portion 1125, and the second circuit region PCA2 and the third circuit region PCA3 may each include the first shielding portion 1125 and the second shielding portion 1127. In another embodiment, the area of ​​the shielding portion SHP may be substantially the same in each circuit region. For example, the shielding portion SHP of the first circuit region PCA1, the shielding portion SHP of the second circuit region PCA2, and the shielding portion SHP of the third circuit region PCA3 may each have the first shielding portion 1125 and the second shielding portion 1127.

[0118] In this embodiment, and when viewed in a plan view, the shielding portion SHP can be arranged separately from the first semiconductor pattern 1310. In other words, the shielding portion SHP may not overlap with the first semiconductor pattern 1310. The shielding portion SHP may overlap with the data line DL.

[0119] In this embodiment, the reference voltage line VL1 may extend in a first direction (x-direction) and may pass through a first circuit region PCA1, a second circuit region PCA2, and a third circuit region PCA3. The reference voltage line VL1 may be configured to transmit a reference voltage Vref to a second terminal of a third transistor T3.

[0120] In an embodiment, when the data signal Vdata applied to the data line DL changes, the reference voltage Vref of the reference voltage line VL1 may change immediately due to the coupling of the parasitic capacitor formed between the reference voltage line VL1 and the data line DL. Because the reference voltage line VL1 is connected to the gate of the first transistor T1, a change in the voltage of the reference voltage line VL1 may cause a change in the gate-source voltage of the first transistor T1. Accordingly, pixels connected to the same reference voltage line VL1 may emit light at a brightness different from the predetermined brightness, resulting in horizontal line crosstalk in which linear patterns appear in the image.

[0121] In one embodiment, the first conductive layer 1100 located at the bottom of the conductive layer includes a reference voltage line VL1, thereby increasing the distance between the reference voltage line VL1 and the data line DL. Accordingly, the display device 10 can display a high-quality image in which the parasitic capacitance between the reference voltage line VL1 and the data line DL is reduced, thereby preventing or reducing line crosstalk.

[0122] In an embodiment, the repair line RPL extends in a first direction (x direction) and can pass through a first circuit region PCA1, a second circuit region PCA2 and a third circuit region PCA3.

[0123] In this embodiment, the first insulating layer may be disposed on the first conductive layer 1100, and the second conductive layer 1200 may be disposed on the first insulating layer, such as... Figure 8 As shown in the diagram, the second conductive layer 1200 may include a first gate line GWLa, a second initialization voltage line VL22, a third initialization voltage line VL23, and a second conductive pattern 1210.

[0124] In an embodiment, the second conductive pattern 1210 may be island-shaped and may be disposed in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. In each of the first circuit region PCA1 and the second circuit region PCA2, the second conductive pattern 1210 may be disposed to overlap with the first conductive pattern 1110 and may define an aperture 1210H exposing a portion of the first conductive pattern 1110. The second conductive pattern 1210 may include the lower gate electrode of the first transistor T1, the second capacitor electrode of the first capacitor C1, and the second capacitor electrode of the second capacitor C2. A portion of the second conductive pattern 1210 and a portion of the drive voltage line PL may overlap each other to form the second capacitor C2.

[0125] In the embodiment, the lower first gate line GWLa, the second initialization voltage line VL22, and the third initialization voltage line VL23 can extend in the first direction (x direction) and can pass through the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0126] In this embodiment, the second initialization voltage line VL22 can be connected to the pixel circuit PC of the second pixel PXg located in the second circuit region PCA2, and the third initialization voltage line VL23 can be connected to the pixel circuit PC of the third pixel PXb located in the second circuit region PCA2. The initialization voltage supplied to the second initialization voltage line VL22 may be different from the initialization voltage supplied to the third initialization voltage line VL23.

[0127] In this embodiment, the second insulating layer may be disposed on the second conductive layer 1200, and the semiconductor layer 1300 may be disposed on the second insulating layer, such as... Figure 9 As shown in the diagram. A third insulating layer may be disposed on the semiconductor layer 1300, and a third conductive layer 1400 may be disposed on the third insulating layer. For ease of description, Figure 9 The semiconductor layer 1300 and the third conductive layer 1400 are shown together.

[0128] In this embodiment, the semiconductor layer 1300 may include an oxide semiconductor material. The semiconductor layer 1300 may include a first semiconductor pattern 1310, a second semiconductor pattern 1320, and a third semiconductor pattern 1330. The first semiconductor pattern 1310, the second semiconductor pattern 1320, and the third semiconductor pattern 1330 may each include a source region, a drain region, and a channel region for a corresponding transistor from the first transistor T1 to the sixth transistor T6, with the channel region located between the source and drain regions.

[0129] In an embodiment, the first semiconductor pattern 1310 may include the source region S1 and drain region D1 of the first transistor T1 and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor pattern 1320 may include the source region S2 and drain region D2 of the second transistor T2 and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor pattern 1330 may include the source region S4 and drain region D4 of the fourth transistor T4 and the source region S6 and drain region D6 of the sixth transistor T6.

[0130] In an embodiment, the third conductive layer 1400 may include a first gate line GWLb, a second gate line GIL, a third gate line GRL, a first transmit control line EML, a second transmit control line EMBL, a first initialization voltage line VL21, a first connecting electrode 1410, a third conductive pattern 1420, a fourth conductive pattern 1430, and a second connecting electrode 1440.

[0131] In an embodiment, the first connection electrode 1410 may overlap with the reference voltage line VL1 and may be connected to the reference voltage line VL1 through a contact hole.

[0132] In an embodiment, the third conductive pattern 1420 and the fourth conductive pattern 1430 may be provided as islands. The third conductive pattern 1420 and the fourth conductive pattern 1430 may be arranged in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0133] In this embodiment, the third conductive pattern 1420 may overlap with the second semiconductor pattern 1320 and may include the gate electrode of the second transistor T2. The fourth conductive pattern 1430 may overlap with the first semiconductor pattern 1310 and may be connected to the first conductive pattern 1110 through a contact hole that overlaps with the hole 1210H of the second conductive pattern 1210. The fourth conductive pattern 1430 may include the upper gate electrode G1 of the first transistor T1 and the third capacitor electrode of the first capacitor C1.

[0134] In an embodiment, the second connection electrode 1440 may overlap with the first shielding portion 1125 of the drive voltage line PL and may be connected to the drive voltage line PL through a contact hole.

[0135] In the embodiment, the first gate line GWLb, the second gate line GIL, the third gate line GRL, the first transmit control line EML, the second transmit control line EMBL, and the first initialization voltage line VL21 can extend in the first direction (x direction) and can pass through the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3.

[0136] In an embodiment, the upper first gate line GWLb may substantially overlap with the lower first gate line GWLa, and can be connected to the lower first gate line GWLa through a contact hole.

[0137] In this embodiment, the second gate line GIL may overlap with the third semiconductor pattern 1330. The second gate line GIL may include the gate electrode G4 of the fourth transistor T4. The third gate line GRL may overlap with the second semiconductor pattern 1320. The third gate line GRL may include the gate electrode G3 of the third transistor T3. The first emitter control line EML may overlap with the first semiconductor pattern 1310. The first emitter control line EML may include the gate electrode G5 of the fifth transistor T5. The second emitter control line EMBL may overlap with the third semiconductor pattern 1330. The second emitter control line EMBL may include the gate electrode G6 of the sixth transistor T6.

[0138] In an embodiment, the first initialization voltage line VL21 can be connected to the pixel circuit PC of the first pixel PXr located in the first circuit region PCA1. The initialization voltage supplied to the first initialization voltage line VL21 can be different from the initialization voltage supplied to the second initialization voltage line VL22 and the initialization voltage supplied to the third initialization voltage line VL23.

[0139] In this embodiment, the fourth insulating layer may be disposed on the third conductive layer 1400, and the fourth conductive layer 1500 may be disposed on the fourth insulating layer, such as... Figure 10 As shown in the diagram, the fourth conductive layer 1500 may include a data line DL, a third connecting electrode 1510, a fourth connecting electrode 1520, a fifth connecting electrode 1530, a fifth conductive pattern 1540, a sixth connecting electrode 1550, a seventh connecting electrode 1560, and an eighth connecting electrode 1570.

[0140] In an embodiment, the data line DL can be arranged to extend in a second direction (y-direction) in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The data line DL can be electrically connected to the drain region D2 of the second transistor T2 through a contact hole passing through the insulating layer. The data line DL can overlap with the shielding portion SHP.

[0141] In one embodiment, the third connection electrode 1510 can connect the upper first gate line GWLb to the third conductive pattern 1420 via a contact hole. The third conductive pattern 1420 can transmit the first gate signal GW from the lower first gate line GWLa and the upper first gate line GWLb to the gate electrode G2 of the second transistor T2.

[0142] In this embodiment, the fourth connection electrode 1520 can connect the first connection electrode 1410 to the second semiconductor pattern 1320 through a contact hole. The fourth connection electrode 1520 can be connected to the reference voltage line VL1 through the first connection electrode 1410, and can transmit the reference voltage Vref from the reference voltage line VL1 to the source region S3 of the third transistor T3. Because one end of the second semiconductor pattern 1320 is connected to the data line DL, and the other end of the second semiconductor pattern 1320 is connected to the reference voltage line VL1, the second semiconductor pattern 1320 can be connected between the data line DL and the reference voltage line VL1.

[0143] In this embodiment, the fifth connection electrode 1530 can connect the second semiconductor pattern 1320 to the fourth conductive pattern 1430 through a contact hole. The fifth connection electrode 1530 can connect the source region S2 of the second transistor T2, the drain region D3 of the third transistor T3, the upper gate electrode G1 of the first transistor T1, and the third capacitor electrode of the first capacitor C1 to each other.

[0144] In this embodiment, the fifth conductive pattern 1540 may overlap with the fourth conductive pattern 1430, and the second conductive pattern 1210, the first semiconductor pattern 1310, and the third semiconductor pattern 1330 may be connected to each other through contact holes. The fifth conductive pattern 1540 may include the fourth capacitor electrode of the first capacitor C1. The fifth conductive pattern 1540 may connect the lower gate electrode of the first transistor T1, the second capacitor electrode of the first capacitor C1, the second capacitor electrode of the second capacitor C2, the source region S1 of the first transistor T1, and the drain region D6 of the sixth transistor T6 to each other. A portion of the overlapping first conductive pattern 1110, a portion of the second conductive pattern 1210, a portion of the fourth conductive pattern 1430, and a portion of the fifth conductive pattern 1540 may form the first capacitor C1.

[0145] In one embodiment, the sixth connection electrode 1550 can connect the first semiconductor pattern 1310 to the second connection electrode 1440 via a contact hole. Because the second connection electrode 1440 is connected to the drive voltage line PL, the sixth connection electrode 1550 can transmit the first drive voltage ELVDD from the drive voltage line PL to the drain region D5 of the fifth transistor T5.

[0146] In this embodiment, the seventh connection electrode 1560 can be connected to the third semiconductor pattern 1330 via a contact hole. The seventh connection electrode 1560 can connect the pixel electrode of the organic light-emitting diode (OLED), the drain region D4 of the fourth transistor T4, and the source region S6 of the sixth transistor T6 to each other.

[0147] In this embodiment, the eighth connection electrode 1570 can be connected to the initialization voltage line and the third semiconductor pattern 1330 via a contact hole. The eighth connection electrode 1570 of the first circuit region PCA1 can be connected to the first initialization voltage line VL21, the eighth connection electrode 1570 of the second circuit region PCA2 can be connected to the second initialization voltage line VL22, and the eighth connection electrode 1570 of the third circuit region PCA3 can be connected to the third initialization voltage line VL23. The eighth connection electrode 1570 can also connect the initialization voltage line to the source region S4 of the fourth transistor T4.

[0148] In this embodiment, the fifth insulating layer may be disposed on the fourth conductive layer 1500, and the fifth conductive layer 1600 may be disposed on the fifth insulating layer, such as... Figure 11 As shown in the diagram, the fifth conductive layer 1600 may include multiple vertical voltage lines VLv, a sixth conductive pattern 1610, and a ninth connecting electrode 1620.

[0149] In an embodiment, the sixth conductive pattern 1610 may be island-shaped and may be arranged in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The sixth conductive pattern 1610 may overlap with the fifth connecting electrode 1530 and may be connected to the fifth conductive pattern 1540 through a contact hole.

[0150] In this embodiment, the ninth connection electrode 1620 can be connected to the seventh connection electrode 1560 via a contact hole. The ninth connection electrode 1620 can connect the pixel electrode of the organic light-emitting diode (OLED) to the drain region D4 of the fourth transistor T4 and the source region S6 of the sixth transistor T6 via the seventh connection electrode 1560.

[0151] In an embodiment, vertical voltage lines VLv may extend in a second direction (y-direction), and two of them may be arranged in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. Each of the odd-numbered voltage lines VLv1, VLv3, and VLv5 in the vertical voltage lines VLv may overlap with the data line DL, and the even-numbered voltage lines VLv2, VLv4, and VLv6 in the vertical voltage lines VLv may overlap with the first semiconductor pattern 1310. In an embodiment, some adjacent vertical voltage lines in the vertical voltage lines VLv may be provided as a single unit. For example, as... Figure 11 As shown, the second vertical voltage line VLv2, the third vertical voltage line VLv3, and the fourth vertical voltage line VLv4 can be connected to each other through a connecting part and can be provided as a whole.

[0152] In one embodiment, some of the odd-numbered voltage lines VLv1, VLv3, and VLv5 may be shielding lines that are not electrically connected to other wiring, semiconductor patterns, and conductive patterns within the display area DA. The shielding lines may pass through the display area DA and connect via contact holes to voltage supply lines disposed in the peripheral area PA. In another embodiment, the voltage supply line may be a common voltage supply line configured to transmit a second drive voltage ELVSS. In yet another embodiment, the voltage supply line may be a drive voltage supply line configured to transmit a first drive voltage ELVDD, a first initialization voltage supply line configured to transmit a first initialization voltage Vaint1, a second initialization voltage supply line configured to transmit a second initialization voltage Vaint2, or a third initialization voltage supply line configured to supply a third initialization voltage Vaint3.

[0153] In an embodiment, the vertical voltage line VLv can receive multiple voltages supplied to pixels PXr, PXg, and PXb (e.g., a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage Vref, a first initialization voltage Vaint1, a second initialization voltage Vaint2, and a third initialization voltage Vaint3). The vertical voltage line VLv can be arranged in a first direction (x-direction) according to specific arrangement rules. (See below for reference.) Figure 15 Describe the arrangement rules for vertical voltage lines VLv.

[0154] Figure 12 This is a schematic layout diagram illustrating the arrangement of pixel electrodes of a pixel according to an embodiment.

[0155] In the embodiments and reference Figure 12 The sixth insulating layer can be disposed on the fifth conductive layer 1600, and the sixth conductive layer 1700 can be disposed on the sixth insulating layer. The sixth conductive layer 1700 may include a pixel electrode PE, an auxiliary electrode AE, and a horizontal voltage line VLh.

[0156] In an embodiment, the pixel electrode PE may include a first pixel electrode 210r contained in an organic light-emitting diode OLED of a first pixel PXr, a second pixel electrode 210g contained in an organic light-emitting diode OLED of a second pixel PXg, and a third pixel electrode 210b contained in an organic light-emitting diode OLED of a third pixel PXb.

[0157] In this embodiment, pixel electrodes PE can be formed in rows and columns within the display area DA. Second pixel electrodes 210g and first pixel electrodes 210r can be arranged in odd-numbered columns M1 and M3, and third pixel electrodes 210b can be arranged in even-numbered columns M2 and M4. In even-numbered columns M2 and M4, auxiliary electrodes AE can be arranged between the third pixel electrodes 210b. Second pixel electrodes 210g can be arranged in odd-numbered rows N1 and N3, and first pixel electrodes 210r can be arranged in even-numbered rows N2 and N4. Third pixel electrodes 210b can have a rectangular shape that is longer in the second direction (y-direction) and can be arranged across adjacent odd and even rows.

[0158] In this embodiment, the auxiliary electrodes AE arranged adjacent to each other in the first direction (x direction) can be connected via a horizontal voltage line VLh. Some of the auxiliary electrodes AE can directly contact the counter electrode of the organic light-emitting diode (OLED) through holes formed via a laser drilling process.

[0159] In an embodiment, the horizontal voltage line VLh may extend in a first direction (x direction) and may be arranged to be separated from each other by a two-row interval. For example, the first row N1 and the second row N2 may be arranged between the first horizontal voltage line VLh1 and the second horizontal voltage line VLh2, and the third row N3 and the fourth row N4 may be arranged between the second horizontal voltage line VLh2 and the third horizontal voltage line VLh3.

[0160] In this embodiment, the horizontal voltage line VLh can receive multiple voltages supplied to pixels PXr, PXg, and PXb (e.g., a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage Vref, a first initialization voltage Vaint1, a second initialization voltage Vaint2, and a third initialization voltage Vaint3). Each of the horizontal voltage lines VLh can be connected to the corresponding vertical voltage line VLv within the display area DA via a contact hole to form a grid structure.

[0161] Figure 13a , Figure 13b and Figure 14 This is a schematic diagram illustrating the first voltage line and data line according to an embodiment. For ease of description, Figure 13a and Figure 14 It is a schematic plan view showing the drive voltage line PL and the data line DL, and Figure 13b It is schematically shown along Figure 13a The diagram shows a cross-sectional view of the display device 10 taken along line I-I'.

[0162] In the embodiments and reference Figure 13aThe driving voltage line PL can extend in a first direction (x direction) and can pass through a first circuit region PCA1, a second circuit region PCA2, and a third circuit region PCA3. The driving voltage line PL can include a main body portion 1121 extending in the first direction (x direction) in each circuit region, an electrode portion 1123 protruding from the main body portion 1121 in a second direction (y direction), and a shielding portion SHP protruding from the main body portion 1121 in the second direction (y direction).

[0163] In an embodiment, the width of the main body portion 1121 of the drive voltage line PL in the second direction (y direction) may be different in each circuit region. For example, the width of the main body portion 1121 in the first circuit region PCA1 may be smaller than the width of the main body portion 1121 in the second circuit region PCA2, and the width of the main body portion 1121 in the second circuit region PCA2 may be smaller than the width of the main body portion 1121 in the third circuit region PCA3.

[0164] In an embodiment, the electrode portion 1123 may protrude from the body portion 1121 in a second direction (y-direction). The electrode portion 1123 may be arranged in each of the first circuit region PCA1 and the second circuit region PCA2. The electrode portion 1123 may not be arranged in the third circuit region PCA3.

[0165] In an embodiment, the shielding portion SHP may protrude from the body portion 1121 in a second direction (y-direction). The shielding portion SHP may be separate from the electrode portion 1123 in a first direction (x-direction). The shielding portion SHP may include a first shielding portion 1125 and a second shielding portion 1127 extending in opposite directions. For example, the first shielding portion 1125 may extend in the -y direction, and the second shielding portion 1127 may extend in the +y direction. In an embodiment, the area of ​​the shielding portion SHP may be substantially the same in each circuit region. For example, the shielding portion SHP of the first circuit region PCA1, the shielding portion SHP of the second circuit region PCA2, and the shielding portion SHP of the third circuit region PCA3 may each include a first shielding portion 1125 and a second shielding portion 1127.

[0166] In this embodiment, the data line DL may extend in a second direction (y-direction) and may be arranged in each of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. The data line DL may overlap with the shielding portion SHP.

[0167] In the embodiments and reference Figure 13bThe driving voltage line PL and the first conductive pattern 1110 can be disposed on the substrate 100. The driving voltage line PL may include an electrode portion 1123 and a second shielding portion 1127.

[0168] In this embodiment, a first insulating layer 111 may be disposed on the driving voltage line PL and the first conductive pattern 1110, and a second conductive pattern 1210 may be disposed on the first insulating layer 111. The second conductive pattern 1210 may overlap with the electrode portion 1123 and the first conductive pattern 1110. The portion of the second conductive pattern 1210 that overlaps with the electrode portion 1123 and the electrode portion 1123 may form a second capacitor C2.

[0169] In this embodiment, the second insulating layer 113 may be disposed on the second conductive pattern 1210, and the first semiconductor pattern 1310 may be disposed on the second insulating layer 113. The first semiconductor pattern 1310 may overlap with the electrode portion 1123.

[0170] In this embodiment, a third insulating layer 115 may be disposed on the first semiconductor pattern 1310. A fourth conductive pattern 1430 may be disposed on the third insulating layer 115. The fourth conductive pattern 1430 may overlap with the second conductive pattern 1210. The fourth conductive pattern 1430 may be connected to the first conductive pattern 1110 through contact holes passing through the first insulating layer 111, the second insulating layer 113, and the third insulating layer 115.

[0171] In this embodiment, the fourth insulating layer 117 may be disposed on the fourth conductive pattern 1430, and the fifth conductive pattern 1540 and the data line DL may be disposed on the fourth insulating layer 117. The fifth conductive pattern 1540 may overlap with the fourth conductive pattern 1430. The fifth conductive pattern 1540 may be connected to the second conductive pattern 1210 through contact holes passing through the third insulating layer 115 and the fourth insulating layer 117.

[0172] In an embodiment, the overlapping first conductive pattern 1110, second conductive pattern 1210, fourth conductive pattern 1430, and fifth conductive pattern 1540 can form a first capacitor C1. For example, the sum of the capacitance between the first conductive pattern 1110 and the second conductive pattern 1210, the capacitance between the second conductive pattern 1210 and the fourth conductive pattern 1430, and the capacitance between the fourth conductive pattern 1430 and the fifth conductive pattern 1540 can be the total capacitance of the first capacitor C1.

[0173] In this embodiment, the data line DL may overlap with the second shielding portion 1127 of the drive voltage line PL. A first parasitic capacitor Cp1 may be formed between the data line DL and the second shielding portion 1127, and a second parasitic capacitor Cp2 may be formed between the data line DL and the first conductive pattern 1110.

[0174] In this embodiment and as a comparative example, when the driving voltage line PL does not include the second shielding portion 1127, the capacitance of the second parasitic capacitor Cp2 between the data line DL and the first conductive pattern 1110 increases, resulting in a deterioration of the front-of-screen (FOS) characteristics of the display device. Furthermore, due to the coupling of the second parasitic capacitor Cp2, pixels connected to the same data line DL may emit light at a brightness different from the predetermined brightness, resulting in vertical line crosstalk where linear patterns appear in the image.

[0175] In an embodiment, the drive voltage line PL may include a second shielding portion 1127 overlapping the data line DL, and therefore, the capacitance of the second parasitic capacitor Cp2 can be reduced by the first parasitic capacitor Cp1 formed by the data line DL and the second shielding portion 1127. Accordingly, the FOS characteristics of the display device 10 can be improved, and the display device 10 can display a high-quality image in which vertical line crosstalk is prevented or reduced.

[0176] In this embodiment, the fifth insulating layer 118 may be disposed on the fifth conductive pattern 1540 and the data line DL, and the fourth vertical voltage line VLv4 and the fifth vertical voltage line VLv5 may be disposed on the fifth insulating layer 118. The fourth vertical voltage line VLv4 may overlap with the first semiconductor pattern 1310 of the second circuit region PCA2, and the fifth vertical voltage line VLv5 may overlap with the data line DL of the third circuit region PCA3.

[0177] In an embodiment, the sixth insulating layer 119 may be disposed on the fourth vertical voltage line VLv4 and the fifth vertical voltage line VLv5.

[0178] In the embodiments and reference Figure 14 The driving voltage line PL may not include the second shielding portion 1127 in any one of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3. Relatedly, Figure 14 The second shielding portion 1127 is not included in the first circuit region PCA1, as shown by the driving voltage line PL.

[0179] In this embodiment, the area of ​​the shielding portion SHP in the first circuit region PCA1 may be different from the area of ​​the shielding portion SHP in the second circuit region PCA2 and the area of ​​the shielding portion SHP in the third circuit region PCA3. The area of ​​the shielding portion SHP in the first circuit region PCA1 may be smaller than the area of ​​the shielding portion SHP in the second circuit region PCA2 and the area of ​​the shielding portion SHP in the third circuit region PCA3.

[0180] In the embodiment and as described above, the second shielding portion 1127 may form a first parasitic capacitor Cp1 together with the data line DL. When the data signal applied to the data line DL changes, the first driving voltage ELVDD of the driving voltage line PL may change instantaneously due to the coupling of the first parasitic capacitor Cp1. The voltage at the second terminal of the first transistor T1 (i.e., the voltage at the second node N2) may change due to the coupling of the second capacitor C2 connected to the driving voltage line PL, thereby changing the gate-source voltage of the first transistor T1. Accordingly, pixels connected to the same driving voltage line PL may emit light with a brightness different from the predetermined brightness, resulting in horizontal line crosstalk in which linear speckles appear in the image.

[0181] In an embodiment, to prevent or reduce horizontal line crosstalk, the second shielding portion 1127 of the drive voltage line PL can be omitted in a circuit region, thereby reducing the first parasitic capacitor Cp1 of the pixel circuit. In an embodiment, the second shielding portion 1127 of the drive voltage line PL can be omitted in the first circuit region PCA1 in which the pixel circuit of the first pixel PXr emitting red light is arranged.

[0182] [Table 1]

[0183] Table 1 shows the measured brightness deviation of pixels due to vertical line crosstalk of the display devices according to the first embodiment E1, the second embodiment E2, the third embodiment E3 and the comparative example CE1.

[0184] In the first embodiment E1, as Figure 13a As shown, the shielding portions SHP of the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3 have the same area. In the second embodiment E2, as... Figure 14As shown, the second shielding portion 1127 of the first circuit region PCA1 is omitted, and the area of ​​the shielding portion SHP of the first circuit region PCA1 is smaller than the area of ​​the shielding portion SHP of the second circuit region PCA2 and the area of ​​the shielding portion SHP of the third circuit region PCA3. In the third embodiment E3, the second shielding portion 1127 of the second circuit region PCA2 is omitted, and the area of ​​the shielding portion SHP of the second circuit region PCA2 is smaller than the area of ​​the shielding portion SHP of the first circuit region PCA1 and the area of ​​the shielding portion SHP of the third circuit region PCA3. In comparative example CE1, the drive voltage line PL includes a first shielding portion 1125 in each of the first circuit regions PCA1 to the third circuit regions PCA3, but does not include the second shielding portion 1127.

[0185] In the embodiments and referring to Table 1, in the first embodiment E1 where the second shielding portion 1127 is formed in all circuit regions of the drive voltage line PL, the brightness deviation due to vertical line crosstalk is the lowest. When a second shielding portion 1127 is omitted to account for horizontal line crosstalk, the brightness deviation of the second embodiment E2, where the second shielding portion 1127 is omitted in the first circuit region PCA1, is less than the brightness deviation of the third embodiment E3, where the second shielding portion 1127 is omitted in the second circuit region PCA2. That is, when the area of ​​the shielding portion SHP overlapping with the data line DL connected to the first pixel PXr is different from the area of ​​the shielding portion SHP overlapping with the data line DL connected to the second pixel PXg and the area of ​​the shielding portion SHP overlapping with the data line DL connected to the third pixel PXb, both vertical line crosstalk and horizontal line crosstalk can be reduced.

[0186] Figure 15 This is a schematic diagram illustrating the arrangement of vertical voltage lines according to an embodiment. Figure 15 The fifth conductive layer 1600, in which the vertical voltage line VLv is arranged, is shown.

[0187] In the embodiments and reference Figure 15 Two vertical voltage lines VLv extending in the second direction (y-direction) can be arranged in a pixel circuit. For example, a first vertical voltage line VLv1 overlapping with a data line and a second vertical voltage line VLv2 overlapping with a first semiconductor pattern can be arranged in a first circuit region PCA1. Some adjacent vertical voltage lines among the vertical voltage lines VLv can be connected to each other and can be provided as a single unit.

[0188] In an embodiment, the vertical voltage line VLv can be arranged in a first direction (x-direction) according to specific rules. In another embodiment, the vertical voltage line VLv can be arranged repeatedly in units of 12 circuit regions (i.e., the first to twelfth circuit regions PCA1, PCA2, ..., and PCA12). In this case, the pixel circuit of the first pixel PXr emitting red light can be arranged in the first circuit region PCA1, the fourth circuit region PCA4, the seventh circuit region PCA7, and the tenth circuit region PCA10; the pixel circuit of the second pixel PXg emitting green light can be arranged in the second circuit region PCA2, the fifth circuit region PCA5, the eighth circuit region PCA8, and the eleventh circuit region PCA11; and the pixel circuit of the third pixel PXb emitting blue light can be arranged in the third circuit region PCA3, the sixth circuit region PCA6, the ninth circuit region PCA9, and the twelfth circuit region PCA12.

[0189] In this embodiment, the shielding line SVL and the first auxiliary initialization voltage line VL21a can be arranged in the first circuit region PCA1, the shielding line SVL and the auxiliary reference voltage line VL1a can be arranged in the second circuit region PCA2, and the auxiliary driving voltage line PLA can be arranged in the third circuit region PCA3. The shielding line SVL and the auxiliary driving voltage line PLA can be arranged in the fourth circuit region PCA4, the auxiliary driving voltage line PLA can be arranged in the fifth circuit region PCA5, and the shielding line SVL and the third auxiliary initialization voltage line VL23a can be arranged in the sixth circuit region PCA6. The shielding line SVL and the auxiliary driving voltage line PLA can be arranged in the seventh circuit region PCA7, the shielding line SVL and the second auxiliary initialization voltage line VL22a can be arranged in the eighth circuit region PCA8, and the auxiliary driving voltage line PLA can be arranged in the ninth circuit region PCA9. The auxiliary drive voltage line PLA can be arranged in the tenth circuit region PCA10, the auxiliary common voltage line VSSL2 can be arranged in the eleventh circuit region PCA11, and the auxiliary common voltage line VSSL2 and the auxiliary drive voltage line PLA can be arranged in the twelfth circuit region PCA12.

[0190] In this embodiment, the shield line SVL can be a wiring to which a shielding voltage is applied, and can be a wiring within the display area DA that is not electrically connected to other wiring, semiconductor patterns, or conductive patterns. The shield line SVL can pass through the display area DA and connect to a voltage supply line arranged in the peripheral area PA.

[0191] Because the shield line SVL is not connected to the wiring extending in the first direction (x direction) within the display area DA, the effects of data signal variations are not transmitted to surrounding pixels. Accordingly, in an embodiment, by providing a shield line SVL that overlaps with the data lines, the display device can reduce or prevent multi-line horizontal crosstalk.

[0192] In one embodiment, the voltage supply line connected to the shield line SVL can be a common voltage supply line configured to transmit the second drive voltage ELVSS. In another embodiment, the voltage supply line can be a first drive voltage supply line configured to transmit the first drive voltage ELVDD, a first initialization voltage supply line configured to transmit the first initialization voltage Vaint1, a second initialization voltage supply line configured to transmit the second initialization voltage Vaint2, or a third initialization voltage supply line configured to supply the third initialization voltage Vaint3.

[0193] In one embodiment, the auxiliary driving voltage line PLA can be a wiring configured to transmit the first driving voltage ELVDD. The auxiliary driving voltage line PLA can be connected via a contact hole to a sixth connection electrode 1550 overlapping with the auxiliary driving voltage line PLA. The auxiliary driving voltage line PLA can form a mesh structure together with the driving voltage line PLA in the display area DA.

[0194] In this embodiment, the first auxiliary initialization voltage line VL21a may be a wiring configured to transmit the first initialization voltage Vaint1. The first auxiliary initialization voltage line VL21a may be connected via a contact hole to an eighth connection electrode 1570 overlapping with the first auxiliary initialization voltage line VL21a. The first auxiliary initialization voltage line VL21a may form a mesh structure together with the first initialization voltage line VL21 in the display area DA.

[0195] In an embodiment, the second auxiliary initialization voltage line VL22a may be a wiring configured to transmit the second initialization voltage Vaint2. The second auxiliary initialization voltage line VL22a may be connected via a contact hole to an eighth connection electrode 1570 overlapping with the second auxiliary initialization voltage line VL22a. The second auxiliary initialization voltage line VL22a may form a mesh structure together with the second initialization voltage line VL22 in the display area DA.

[0196] In this embodiment, the third auxiliary initialization voltage line VL23a may be a wiring configured to transmit the third initialization voltage Vaint3. The third auxiliary initialization voltage line VL23a may be connected via a contact hole to an eighth connection electrode 1570 that overlaps with the third auxiliary initialization voltage line VL23a. The third auxiliary initialization voltage line VL23a may form a mesh structure together with the third initialization voltage line VL23 in the display area DA.

[0197] In this embodiment, the auxiliary reference voltage line VL1a may be a wiring configured to transmit the reference voltage Vref. The auxiliary reference voltage line VL1a may be connected via a contact hole to a fourth connection electrode 1520 overlapping with the auxiliary reference voltage line VL1a. The auxiliary reference voltage line VL1a may form a mesh structure together with the reference voltage line VL1 in the display area DA.

[0198] In this embodiment, the auxiliary common voltage line VSSL2 may be wiring configured to transmit the second drive voltage ELVSS. The auxiliary common voltage line VSSL2 may be connected to the first horizontal voltage line VLh1 via contact holes. The auxiliary common voltage line VSSL2, together with the first horizontal voltage line VLh1, may form a mesh structure in the display area DA.

[0199] Figure 16 This is a schematic layout diagram illustrating the arrangement of pixels and voltage lines according to an embodiment, and Figure 17a and Figure 17b This is a schematic cross-sectional view of pixels and voltage lines according to an embodiment.

[0200] In an embodiment, Figure 16 The diagram shows a fifth conductive layer 1600 in which vertical voltage lines VLv are arranged and a sixth conductive layer 1700 in which pixel electrodes 210r, 210g and 210b are arranged. Figure 17a It shows along Figure 16 The cross-section of the display device is taken by line II-II' in the middle, and Figure 17b It shows along Figure 16 The cross-section of the display device is taken by line III-III' in the diagram.

[0201] In the embodiments and reference Figure 16 , Figure 17a and Figure 17b The sixth insulating layer 119 can be disposed on the fifth conductive layer 1600, and the sixth conductive layer 1700 can be disposed on the sixth insulating layer 119.

[0202] In an embodiment, the fifth conductive layer 1600 may include a shielding line SVL, a first auxiliary initialization voltage line VL21a, a second auxiliary initialization voltage line VL22a, a third auxiliary initialization voltage line VL23a, an auxiliary reference voltage line VL1a, an auxiliary driving voltage line PLA, and an auxiliary common voltage line VSSL2 arranged according to a specific rule.

[0203] In an embodiment, the sixth conductive layer 1700 may include a pixel electrode PE and an auxiliary electrode AE.

[0204] In an embodiment, the pixel electrode PE may include a first pixel electrode 210r contained in an organic light-emitting diode OLED containing a first pixel PXr, a second pixel electrode 210g contained in an organic light-emitting diode OLED containing a second pixel PXg, and a third pixel electrode 210b contained in an organic light-emitting diode OLED containing a third pixel PXb. The organic light-emitting diode OLED may further include a counter electrode 230 disposed on the pixel electrode PE and an intermediate layer 220 located between the pixel electrode PE and the counter electrode 230.

[0205] In an embodiment, a pixel defining layer PDL may be disposed on the sixth conductive layer 1700 to cover the edge of each of the pixel electrodes PE. The pixel defining layer PDL may define a pixel opening OP that exposes the central portion of each of the pixel electrodes PE and an auxiliary opening OPa that exposes the central portion of the first auxiliary electrode AE1. The emission region of the organic light-emitting diode OLED (i.e., the size and shape of each pixel) may be defined by the pixel opening OP.

[0206] In an embodiment, the pixel limiting layer PDL can prevent arcing at the edges of the pixel electrodes PE by increasing the distance between the edge of each of the pixel electrodes PE and the counter electrode 230.

[0207] In one embodiment, the intermediate layer 220 may include an emission layer 222 formed corresponding to each of the pixel electrodes PE. The emission layer 222 may include a polymeric or low-molecular-weight material and may emit red, green, blue, or white light. The first functional layer 221 and the second functional layer 223 may be disposed below and / or above the emission layer 222, respectively. The first functional layer 221 may be a hole transport layer (HTL). In another embodiment, the first functional layer 221 may include a hole injection layer (HIL) and an HTL. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 221 and the second functional layer 223 may each be integrally formed to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area DA.

[0208] In one embodiment, the counter electrode 230 may comprise a conductive material having a relatively low work function. The counter electrode 230 may be integrally formed to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area DA.

[0209] In this embodiment, pixel electrodes PE can be formed in rows and columns within the display area DA. Second pixel electrodes 210g and first pixel electrodes 210r can be arranged in odd-numbered columns M1, M3, ..., and third pixel electrodes 210b can be arranged in even-numbered columns M2, M4, ... In the even-numbered columns M2, M4, ..., auxiliary electrodes AE can be arranged between the third pixel electrodes 210b. The third pixel electrodes 210b, which are adjacent to each other in the second direction (y-direction), can be arranged to be spaced apart by a first distance d1 or a second distance d2. The first distance d1 can be less than the second distance d2. Auxiliary electrodes AE can be arranged between the third pixel electrodes 210b that are separated by a second distance d2.

[0210] In an embodiment, auxiliary electrodes AE arranged adjacent to each other in the first direction (x-direction) can be connected to each other via horizontal voltage lines VLh1 or VLh2. Horizontal voltage lines VLh1 and VLh2 may extend only in the first direction (x-direction). The auxiliary electrodes AE may include a first auxiliary electrode AE1 connected to the lower vertical voltage line via a contact hole CTm and a second auxiliary electrode AE2 in which no contact hole CTm is formed. In an embodiment, the first auxiliary electrode AE1 may be the auxiliary electrode among the auxiliary electrodes AE that overlaps with the auxiliary common voltage line VSSL2.

[0211] In the embodiments and as Figure 17b As shown, the first auxiliary electrode AE1 can be connected to the auxiliary common voltage line VSSL2 located below the first auxiliary electrode AE1 via the contact hole CTm passing through the sixth insulating layer 119. On the other hand, as... Figure 17a As shown, the second auxiliary electrode AE2 can be separated from the auxiliary driving voltage line PLA, the shielding line SVL and the third auxiliary initialization voltage line VL23a by the sixth insulating layer 119.

[0212] In one embodiment, the pixel defining layer PDL can expose the upper surface of the first auxiliary electrode AE1 through an auxiliary opening OPa. An intermediate layer 220 can be disposed on the exposed upper surface of the first auxiliary electrode AE1, and the intermediate layer 220 can define an aperture 220h overlapping the first auxiliary electrode AE1. In one embodiment, the aperture 220h of the intermediate layer 220 can be formed by a laser drilling process. The counter electrode 230 can directly contact the first auxiliary electrode AE1 through the aperture 220h of the intermediate layer 220. Accordingly, the counter electrode 230 can receive the second driving voltage ELVSS through the auxiliary common voltage line VSSL2 and the first horizontal voltage line VLh1. On the other hand, the pixel defining layer PDL can completely cover the second auxiliary electrode AE2, and the second auxiliary electrode AE2 can avoid contact with the counter electrode 230 due to the pixel defining layer PDL and the intermediate layer 220.

[0213] Figure 18a and Figure 18b This is a schematic diagram illustrating the voltage lines according to an embodiment.

[0214] In the embodiments, for ease of description and illustration, Figure 18a and Figure 18b The diagram shows 12 shielded lines SVL, 2 auxiliary common voltage lines VSSL2, and 5 common voltage lines VSSL1 spaced apart from each other at regular intervals. However, the invention is not limited thereto. The number of wires arranged in the display area DA can be increased, and the spacing between the wires can also be varied.

[0215] In the embodiments and reference Figure 18a and Figure 18b A common voltage line VSSL1 extending in the first direction (x direction), a shield line SVL extending in the second direction (y direction), and an auxiliary common voltage line VSSL2 can be arranged in the display area DA. The common voltage line VSSL1 can be the first horizontal voltage line VLh1 shown in Figure 17.

[0216] In one embodiment, the common voltage supply line VSSLo extending in the first direction (x direction) can be arranged in the peripheral area PA outside the display area DA. In another embodiment, the common voltage supply line VSSLo can be respectively positioned on the upper (+y direction side) and lower (-y direction side) side of the peripheral area PA, with the display area DA located therebetween. The common voltage supply line VSSLo can be wiring configured to transmit the second drive voltage ELVSS.

[0217] In an embodiment, the shield line SVL may be a vertical voltage line arranged to overlap with the data line, and may not be electrically connected to other wiring, semiconductor patterns, and conductive patterns in the display area DA. The shield line SVL may be connected to a voltage supply line in the peripheral area PA located outside the display area DA, and may receive a shielding voltage.

[0218] In an embodiment, such as Figure 18a As shown, the shielded wire SVL can be connected to the common voltage supply line VSSLo through the contact hole CTo1 located in the peripheral area PA.

[0219] In this embodiment, the auxiliary common voltage line VSSL2 can be connected to the common voltage supply line VSSLo via a contact hole CTo2 located in the peripheral region PA, and can be connected to the common voltage line VSSL1 via a contact hole CTm located in the display region DA. In the display region DA, the auxiliary common voltage line VSSL2 and the common voltage line VSSL1 can be connected to each other to form a mesh structure. The common voltage line VSSL1 can be connected to the counter electrode 230 via a first auxiliary electrode AE1, and can transmit the second driving voltage ELVSS to the counter electrode 230. The shielding line SVL can be separated from the common voltage line VSSL1 in the thickness direction (z-direction) by at least one insulating layer.

[0220] In an embodiment, such as Figure 18b As shown, the display device 10 may further include a voltage supply line VLo extending in a first direction (x direction) within the peripheral region PA, and a shielding line SVL may be connected to the voltage supply line VLo via a contact hole CTo3 located in the peripheral region PA. The voltage supply line VLo may be respectively disposed on the upper side (+y direction side) and lower side (-y direction side) of the peripheral region PA with the display region DA located therebetween.

[0221] In one embodiment, the voltage supply line VLo may be a first drive voltage supply line configured to transmit a first drive voltage ELVDD, a first initialization voltage supply line configured to transmit a first initialization voltage Vaint1, a second initialization voltage supply line configured to transmit a second initialization voltage Vaint2, or a third initialization voltage supply line configured to supply a third initialization voltage Vaint3. In another embodiment, the voltage supply line VLo may be a power line configured to supply a separate shield voltage.

[0222] According to an embodiment, because the shield line SVL is not connected to the wiring extending in the first direction (x direction) within the display area DA, the effects of data signal variations are not transmitted to surrounding pixels. Accordingly, by providing a shield line SVL that overlaps with the data lines, the display device can reduce or prevent multi-line horizontal crosstalk.

[0223] Figures 19a to 20b This is a cross-sectional view showing the structure of a display element according to an embodiment.

[0224] In an embodiment, the organic light-emitting diode (OLED) as a display element may include a pixel electrode 210, a counter electrode 230, and an intermediate layer 220m disposed between the pixel electrode 210 (anode) and the counter electrode 230 (cathode).

[0225] In embodiments, the pixel electrode 210 may include a transmissive conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). The pixel electrode 210 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. For example, the pixel electrode 210 may have a three-layer structure comprising an ITO layer / Ag layer / ITO layer.

[0226] In this embodiment, the counter electrode 230 may be disposed on the intermediate layer 220m. The counter electrode 230 may comprise a metal, alloy, conductive compound, or any combination thereof having a low work function. For example, the counter electrode 230 may comprise Li, Ag, Mg, Al, Al-Li, Ca, Mg-In, Mg-Ag, Yb, Ag-Yb, ITO, IZO, or any combination thereof. The counter electrode 230 may comprise a transmission electrode, a semi-transparent reflective electrode, or a reflective electrode.

[0227] In this embodiment, the intermediate layer 220m may comprise a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a specific color. In addition to various organic materials, the intermediate layer 220m may further comprise metal-containing compounds such as organometallic compounds and inorganic materials such as quantum dots.

[0228] In an embodiment, the intermediate layer 220m may include an emitter layer and a first functional layer and a second functional layer, respectively below and above the emitter layer. The first functional layer may include, for example, a hole transport layer (HTL), or may include a hole transport layer (HTL) and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Either the first or second functional layer may be omitted. The first and second functional layers may each be integrally formed to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA).

[0229] In an embodiment, the intermediate layer 220m may include a charge generation layer CGL and at least two emission units, wherein the at least two emission units may be sequentially stacked between the pixel electrode 210 and the counter electrode 230, and the charge generation layer CGL may be disposed between the at least two emission units. When the intermediate layer 220m includes emission units and the charge generation layer CGL, the organic light-emitting diode (OLED) can be a tandem light-emitting device. When the OLED has a stacked structure of multiple emission units, the OLED can have improved color purity and emission efficiency.

[0230] In an embodiment, an emitting unit may include an emitting layer and a first functional layer and a second functional layer located below and above the emitting layer, respectively. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. Based on the negative and positive charge generation layers, the emission efficiency of an organic light-emitting diode (OLED), which is a tandem light-emitting device comprising multiple emitting layers, can be further improved.

[0231] In this embodiment, the negative charge generation layer can be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer can include a host and a dopant. The host can include an organic material. The dopant can include a metallic material. The positive charge generation layer can be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer can include a host and a dopant. The host can include an organic material. The dopant can include a metallic material.

[0232] In an embodiment, such as Figure 19a As shown, an organic light-emitting diode (OLED) may include a first emitting unit EU1 containing a first emitting layer EML1 and a second emitting unit EU2 containing a second emitting layer EML2, wherein the first emitting unit EU1 and the second emitting unit EU2 are sequentially stacked. A charge-generating layer CGL may be provided between the first emitting unit EU1 and the second emitting unit EU2. For example, an OLED may include a pixel electrode 210, a first emitting layer EML1, a charge-generating layer CGL, a second emitting layer EML2, and a counter electrode 230 sequentially stacked. A first functional layer and a second functional layer may be included below and above the first emitting layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emitting layer EML2, respectively. The first emitting layer EML1 may be a blue emitting layer, and the second emitting layer EML2 may be a yellow emitting layer.

[0233] In an embodiment, such as Figure 19bAs shown, an organic light-emitting diode (OLED) may include a first emitting unit EU1 containing a first emitting layer EML1 and a third emitting unit EU3, and a second emitting unit EU2 containing a second emitting layer EML2. A first charge-generating layer CGL1 may be provided between the first emitting unit EU1 and the second emitting unit EU2, and a second charge-generating layer CGL2 may be provided between the second emitting unit EU2 and the third emitting unit EU3. For example, an OLED may include a pixel electrode 210, a first emitting layer EML1, a first charge-generating layer CGL1, a second emitting layer EML2, a second charge-generating layer CGL2, a first emitting layer EML1, and a counter electrode 230, stacked sequentially. A first functional layer and a second functional layer may be included below and above the first emitting layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emitting layer EML2, respectively. The first emitting layer EML1 may be a blue emitting layer, and the second emitting layer EML2 may be a yellow emitting layer.

[0234] In an embodiment, the organic light-emitting diode (OLED) may include a second emitting unit EU2, which, in addition to including a second emitting layer EML2, may further include a third emitting layer EML3 and / or a fourth emitting layer EML4 directly contacting the second emitting layer EML2 below and / or above it. Here, "direct contact" may mean that no layer is disposed between the second emitting layer EML2 and the third emitting layer EML3 and / or between the second emitting layer EML2 and the fourth emitting layer EML4. The third emitting layer EML3 may be a red emitting layer, and the fourth emitting layer EML4 may be a green emitting layer.

[0235] In the embodiments and as Figure 19c As shown, an organic light-emitting diode (OLED) may include a pixel electrode 210, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 230, which are sequentially stacked. In another embodiment and as shown... Figure 19d As shown, an organic light-emitting diode (OLED) may include a pixel electrode 210, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 230, which are stacked in sequence.

[0236] Figure 20a This illustrates an embodiment. Figure 19c A cross-sectional view of an example of an organic light-emitting diode (OLED), and Figure 20b This illustrates an embodiment. Figure 19dA cross-sectional view of an example of an organic light-emitting diode (OLED).

[0237] In the embodiments and reference Figure 20a An organic light-emitting diode (OLED) may include a first emitting unit EU1, a second emitting unit EU2, and a third emitting unit EU3 stacked in sequence. A first charge-generating layer CGL1 may be provided between the first emitting unit EU1 and the second emitting unit EU2, and a second charge-generating layer CGL2 may be provided between the second emitting unit EU2 and the third emitting unit EU3. Each of the first charge-generating layer CGL1 and the second charge-generating layer CGL2 may include a negative charge-generating layer nCGL and a positive charge-generating layer pCGL.

[0238] In an embodiment, the first emitting unit EU1 may include a blue emitting layer BEML. The first emitting unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL located between the pixel electrode 210 and the blue emitting layer BEML. In an embodiment, a p-doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer can be formed by doping the hole injection layer HIL with a p-type doping material. In an embodiment, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may be further included between the blue emitting layer BEML and the hole transport layer HTL. The blue light assist layer can improve the emission efficiency of the blue emitting layer BEML. The blue light assist layer can improve the emission efficiency of the blue emitting layer BEML by adjusting the hole charge balance. The electron blocking layer can prevent electrons from being injected into the hole transport layer HTL. The buffer layer can compensate for the resonant distance based on the wavelength of the light emitted from the emitting layer.

[0239] In an embodiment, the second emitting unit EU2 may include a yellow emitting layer YEML and a red emitting layer REML directly contacting the yellow emitting layer YEML below it. The second emitting unit EU2 may further include a hole transport layer HTL located between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emitting layer REML, and may further include an electron transport layer ETL located between the yellow emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0240] In an embodiment, the third emitting unit EU3 may include a blue emitting layer BEML. The third emitting unit EU3 may further include a hole transport layer HTL located between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emitting layer BEML. The third emitting unit EU3 may further include an electron transport layer ETL and an electron injection layer EIL located between the blue emitting layer BEML and the counter electrode 230. The electron transport layer ETL may include a single layer or multiple layers. In an embodiment, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may be further included between the blue emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may be further included between the blue emitting layer BEML and the electron transport layer ETL. The hole blocking layer prevents hole injection into the electron transport layer ETL.

[0241] In an embodiment, Figure 20b The organic light-emitting diode (OLED) illustrated in the middle can have the same characteristics as... Figure 20a The diagram shows a stacked structure of a second emitting unit EU2 in an organic light-emitting diode (OLED), and in addition to the stacked structure of the second emitting unit EU2, it can have the same... Figure 20a The structure shown in the image is the same as that of an organic light-emitting diode (OLED). (Reference) Figure 20b The second emitting unit EU2 may include a yellow emitting layer YEML, a red emitting layer REML directly contacting the yellow emitting layer YEML below it, and a green emitting layer GEML directly contacting the yellow emitting layer YEML above it. The second emitting unit EU2 may further include a hole transport layer HTL located between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emitting layer REML, and may further include an electron transport layer ETL located between the green emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0242] Figure 21 This is a cross-sectional view showing the structure of the pixels of a display device according to an embodiment.

[0243] In the embodiments and reference Figure 21The display device may include multiple pixels. These pixels may include a first pixel PXr, a second pixel PXg, and a third pixel PXb. Each of the first pixel PXr to the third pixel PXb may include a pixel electrode 210, a counter electrode 230, and an intermediate layer 220m. In an embodiment, the first pixel PXr may include a red pixel, the second pixel PXg may include a green pixel, and the third pixel PXb may include a blue pixel. Here, the pixels may include organic light-emitting diodes (OLEDs) as display elements, and the OLED of each pixel may be electrically connected to a corresponding pixel circuit.

[0244] In an embodiment, pixel electrode 210 may be provided independently in each of the first pixel PXr, the second pixel PXg, and the third pixel PXb.

[0245] In an embodiment, the intermediate layer 220m of the organic light-emitting diode (OLED) for each of the first pixel PXr to the third pixel PXb may include: a first emission unit EU1 and a second emission unit EU2 stacked sequentially; and a charge generation layer CGL disposed between the first emission unit EU1 and the second emission unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed throughout the first pixel PXr to the third pixel PXb.

[0246] In an embodiment, the first emitter unit EU1 of the first pixel PXr may include a hole injection layer HIL, a hole transport layer HTL, a red emitter layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode 210. The first emitter unit EU1 of the second pixel PXg may include a hole injection layer HIL, a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 210. The first emitter unit EU1 of the third pixel PXb may include a hole injection layer HIL, a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 210. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL in each of the first emitter units EU1 may be a common layer continuously formed throughout the first pixel PXr to the third pixel PXb.

[0247] In an embodiment, the second emitter unit EU2 of the first pixel PXr may include a hole transport layer HTL, an auxiliary layer AXL, a red emitter layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emitter unit EU2 of the second pixel PXg may include a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emitter unit EU2 of the third pixel PXb may include a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and electron transport layer ETL in each of the second emitter units EU2 may be a common layer continuously formed throughout the first pixel PXr to the third pixel PXb. In an embodiment, in the corresponding second emitter units EU2 of the first pixel PXr to the third pixel PXb, at least one of a hole blocking layer and a buffer layer may be further included between the emitter layer and the electron transport layer ETL.

[0248] In this embodiment, the thickness H1 of the red emitter layer REML, the thickness H2 of the green emitter layer GEML, and the thickness H3 of the blue emitter layer BEML can be determined based on the resonant distance. The auxiliary layer AXL can be a region added to adjust the resonant distance and can include a resonant auxiliary material. For example, the auxiliary layer AXL can include the same material as the hole transport layer HTL.

[0249] In an embodiment, Figure 21 The illustration shows that the auxiliary layer AXL can be included only in the first pixel PXr. However, the invention is not limited thereto. For example, the auxiliary layer AXL can be provided in at least one pixel from the first pixel PXr to the third pixel PXb to adjust the resonant distance of that at least one pixel from the first pixel PXr to the third pixel PXb.

[0250] In an embodiment, the display device may further include a capping layer 240 disposed outside the counter electrode 230. Based on the principle of constructive interference, the capping layer 240 can improve the emission efficiency. Therefore, because the light extraction efficiency of the organic light-emitting diode (OLED) is improved, the emission efficiency of the OLED can also be improved.

[0251] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention. Furthermore, embodiments or portions of embodiments may be combined in whole or in part without departing from the scope of the invention.

Claims

1. A display device comprising pixels arranged in a display area, the display device comprising: A first conductive layer, including a first voltage line; A second conductive layer is disposed on the first conductive layer and includes a first conductive pattern that overlaps with the first voltage line; A semiconductor layer is disposed on the second conductive layer and includes a first semiconductor pattern that overlaps with the first conductive pattern; A third conductive layer is disposed on the semiconductor layer and includes a second conductive pattern that overlaps with the first conductive pattern. as well as A fourth conductive layer is disposed on the third conductive layer and includes data lines and a third conductive pattern overlapping the second conductive pattern. The first voltage line includes a main body portion extending in a first direction and a shielding portion extending from the main body portion in a second direction to overlap with the data line, wherein the second direction intersects the first direction.

2. The display device according to claim 1, wherein, The third conductive layer further includes a first connection electrode, and the fourth conductive layer further includes a second connection electrode. The shielding portion is electrically connected to the first semiconductor pattern via the first connecting electrode and the second connecting electrode.

3. The display device according to claim 1, wherein, The shielding portion is spaced apart from the first semiconductor pattern in the plan view.

4. The display device according to claim 1, wherein, The first conductive layer further includes a fourth conductive pattern that overlaps with the second conductive pattern. The second conductive pattern is electrically connected to the fourth conductive pattern, and the first conductive pattern is electrically connected to the third conductive pattern.

5. The display device according to claim 1, wherein, The data lines include a first data line, a second data line, and a third data line, wherein the shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line. The first shielding portion, the second shielding portion, and the third shielding portion have the same area.

6. The display device according to claim 1, wherein, The data lines include a first data line, a second data line, and a third data line, wherein the shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line. The area of ​​the first shielding portion is different from the area of ​​the second shielding portion and the area of ​​the third shielding portion.

7. The display device according to claim 6, wherein, The pixels include red pixels that emit red light, blue pixels that emit blue light, and green pixels that emit green light. The first data line is electrically connected to the red pixel.

8. The display device according to claim 1, wherein, The first conductive layer further includes a second voltage line extending in the first direction, and wherein the semiconductor layer further includes a second semiconductor pattern electrically connected between the data line and the second voltage line.

9. The display device according to claim 8, wherein, The third conductive layer further includes a first gate line overlapping the first semiconductor pattern and configured to transmit a first gate signal, and a second gate line overlapping the second semiconductor pattern and configured to transmit a second gate signal, wherein the pixel operates during a non-emission period and an emission period during a frame time period. Specifically, during the non-transmission period, after the second gate signal becomes an on voltage, the first gate signal becomes an on voltage, and after the second gate signal becomes an off voltage, the first gate signal becomes an off voltage.

10. The display device according to claim 9, wherein, During the on-voltage period of the second gate signal, the reference voltage is transmitted to the second conductive pattern through the second voltage line.

11. The display device according to claim 1, further comprising: A fifth conductive layer is disposed on the fourth conductive layer and includes a third voltage line extending in the second direction and overlapping the data line.

12. The display device according to claim 11, further comprising: A voltage supply line is disposed in the peripheral area outside the display area and extends in the first direction. The third voltage line passes through the display area and connects to the voltage supply line in the peripheral area.

13. The display device according to claim 12, wherein, The pixel includes a display element, the display element includes a pixel electrode, a counter electrode, and an intermediate layer disposed between the pixel electrode and the counter electrode. The voltage supplied to the third voltage line is equal to the voltage supplied to the counter electrode.

14. The display device according to claim 12, wherein, The pixel includes a display element, the display element includes a pixel electrode, a counter electrode, and an intermediate layer disposed between the pixel electrode and the counter electrode. The voltage supplied to the third voltage line is different from the voltage supplied to the counter electrode.

15. The display device according to claim 1, further comprising: The fifth conductive layer is disposed on the fourth conductive layer and includes a fourth voltage line extending in the second direction; as well as A sixth conductive layer is disposed on the fifth conductive layer and includes a pixel electrode, an auxiliary electrode, and a fifth voltage line extending in the first direction and connecting adjacent auxiliary electrodes among the auxiliary electrodes.

16. The display device according to claim 15, further comprising a pixel defining layer disposed on the sixth conductive layer and defining a pixel opening and an auxiliary opening, in, Each of the pixel openings overlaps with a corresponding one of the pixel electrodes, and each of the auxiliary openings overlaps with a corresponding one of the auxiliary electrodes that overlaps with the fourth voltage line.

17. A display device, comprising: A first pixel circuit electrically connected to a first light-emitting diode and a second pixel circuit electrically connected to a second light-emitting diode. Each of the first pixel circuit and the second pixel circuit includes: The first voltage line extends in the first direction; A data line is disposed on the first voltage line and extends in a second direction intersecting the first direction; A capacitor includes a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode; The first transistor is electrically connected between the first voltage line and the capacitor; The second transistor is electrically connected to the data line and the gate electrode of the first transistor; A third transistor is electrically connected to the gate electrode of the first transistor and a second voltage line extending in the first direction; and The fourth transistor is electrically connected between the first voltage line and the first transistor. The first voltage line includes a main body portion and a shielding portion extending from the main body portion in the second direction to overlap with the data line.

18. The display device according to claim 17, wherein, The area of ​​the shielding portion of the first pixel circuit is smaller than the area of ​​the shielding portion of the second pixel circuit.

19. The display device according to claim 18, wherein, The first light-emitting diode emits red light.

20. The display device according to claim 17, wherein, The first voltage line and the second voltage line are disposed in the same layer.

21. The display device according to claim 17, wherein, Each frame time period of the first pixel circuit and the second pixel circuit includes a non-transmission period and a transmission period. The non-launch period includes: A first period during which the third and fourth transistors are turned on before the write period when the data signal is supplied from the data line; and The fourth transistor remains on for a second period after the third transistor is turned off.

22. The display device according to claim 17, wherein, Each of the first light-emitting diode and the second light-emitting diode includes a pixel electrode, a counter electrode, and an intermediate layer disposed between the pixel electrode and the counter electrode. The display device further includes: The auxiliary electrode is located in the same layer as the pixel electrode; and A third voltage line extends in the first direction and electrically connects the auxiliary electrodes to each other.

23. The display device of claim 22, further comprising a fourth voltage line disposed between the data line and the pixel electrode and extending in the second direction. in, Among the auxiliary electrodes, the auxiliary electrode that overlaps with the fourth voltage line is electrically connected to the third voltage line.

24. The display device according to claim 23, wherein, The auxiliary electrode, which overlaps with the fourth voltage line, is in direct contact with the counter electrode.

25. The display device of claim 23, further comprising a fifth voltage line located in the same layer as the fourth voltage line and overlapping the data line. in, The fifth voltage line is spaced apart from the third voltage line by at least one insulating layer.

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