Method and device for accessing permanent power supply area, electronic equipment and storage medium
By constructing an independent access channel in the integrated circuit and introducing a backup clock source, the problem of not being able to access AON resources in low-power conditions was solved, enabling real-time access and operation of AON resources and improving debugging efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAMEN UNISOC TECH CO LTD
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-15
AI Technical Summary
After an integrated circuit enters a low-power state, traditional debugging interfaces and access paths become ineffective, making it impossible to directly access permanently powered area (AON) resources, resulting in high debugging difficulty and long cycles.
An independent access channel is built between the debug access interface and the permanent power supply area, and a backup clock source is introduced to ensure that the debug access interface continues to operate in low-power mode.
It enables real-time access and operation of AON resources in a low-power state, reducing debugging difficulty and cycle, and improving development efficiency.
Smart Images
Figure CN122044329A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic equipment technology, and in particular to a method, apparatus, electronic device, and storage medium for accessing a permanently powered area. Background Technology
[0002] When an integrated circuit enters a low-power state, all other system modules will be powered off to reduce power consumption, except for the necessary permanent power supply areas (Always ON, AON).
[0003] In actual development and debugging, after an integrated circuit enters a low-power state, developers or testers need to access the registers in the AON area in real time to verify the correctness of the low-power logic, analyze abnormal states, or adjust the register configuration to optimize power consumption performance.
[0004] However, in related technologies, since the main power path of the integrated circuit is cut off in the low power state, the traditional debugging interface and access path are invalid, making it impossible to directly access AON resources. This forces developers to rely on indirect means or to repeatedly modify the code and restart the integrated circuit for debugging, which greatly increases the debugging difficulty and development cycle. Summary of the Invention
[0005] This application provides a method, apparatus, electronic device, and storage medium for accessing a permanently powered area, which can solve the technical problem in related technologies where AON cannot be accessed after the integrated circuit enters a low-power state.
[0006] In a first aspect, embodiments of this application provide a method for accessing a permanently powered region, applied in an integrated circuit. The integrated circuit includes a debug access interface and a permanently powered region, and an independent access channel is established between the debug access interface and the permanently powered region. This independent access channel does not pass through any power-down module in the integrated circuit. The method includes:
[0007] Monitor whether the integrated circuit has entered a low-power mode;
[0008] When the integrated circuit enters low-power mode, the clock of the debug access interface is switched to a backup clock source, which is used to enable the debug access interface to continue to operate in low-power mode.
[0009] Access resources in the permanently powered area via a separate access channel using the debug access interface.
[0010] In some embodiments, the aforementioned independent access channel includes at least one signal path, and the debug access interface uses at least one signal path to connect to the register interface of the permanent power supply area to form an independent access channel.
[0011] In some embodiments, the above-mentioned at least one signal path includes at least one of the following: metal layer wiring, logic gate-level circuit, and dedicated debug bus.
[0012] In some embodiments, the above method further includes:
[0013] A backup clock source is selected based on the low-power mode of the integrated circuit. This backup clock source includes a high-frequency oscillation circuit, which includes a 100MHz oscillation circuit.
[0014] In some embodiments, the above-described access to resources in a permanently powered area via a dedicated access channel using a debug access interface includes:
[0015] Establish a connection between the debugging tool and the debugging access interface;
[0016] Use debugging tools to send access requests to the debugging access interface; the debugging access interface is used to forward access requests to resources in the permanently powered area using an independent access channel.
[0017] In some embodiments, the above-described access to resources in a permanently powered area via a dedicated access channel using a debug access interface includes:
[0018] Using the debug access interface via a separate access channel, the status register configuration in the permanent power supply area can be read or modified.
[0019] Secondly, embodiments of this application provide a device for accessing a permanently powered region, applied in an integrated circuit. The integrated circuit includes a debug access interface and a permanently powered region, and an independent access channel is established between the debug access interface and the permanently powered region. This independent access channel does not pass through any power-down module in the integrated circuit. The device includes:
[0020] The monitoring module is used to monitor whether the integrated circuit has entered a low-power mode;
[0021] The switching module is used to switch the clock of the debug access interface to a backup clock source when the integrated circuit enters a low-power mode. The backup clock source is used to enable the debug access interface to continue to operate in low-power mode.
[0022] The access module is used to access resources in the permanently powered area via a separate access channel using the debug access interface.
[0023] In some embodiments, the aforementioned independent access channel includes at least one signal path, and the debug access interface uses at least one signal path to connect to the register interface of the permanent power supply area to form an independent access channel.
[0024] In some embodiments, the above-mentioned at least one signal path includes at least one of the following: metal layer wiring, logic gate-level circuit, and dedicated debug bus.
[0025] In some embodiments, the switching module is further configured to:
[0026] A backup clock source is selected based on the low-power mode of the integrated circuit. This backup clock source includes a high-frequency oscillation circuit, which includes a 100MHz oscillation circuit.
[0027] In some embodiments, the access module is used for:
[0028] Establish a connection between the debugging tool and the debugging access interface;
[0029] Use debugging tools to send access requests to the debugging access interface; the debugging access interface is used to forward access requests to resources in the permanently powered area using an independent access channel.
[0030] In some embodiments, the access module is used for:
[0031] Using the debug access interface via a separate access channel, the status register configuration in the permanent power supply area can be read or modified.
[0032] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;
[0033] The memory stores instructions that the computer executes;
[0034] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.
[0035] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.
[0036] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.
[0037] Sixthly, embodiments of this application provide a chip including at least one processor for executing program instructions to perform the above-described method for accessing a permanently powered region.
[0038] The method, apparatus, electronic device, and storage medium for accessing the permanent power supply area provided in this application construct an independent access channel independent of the conventional power path between the debug access interface and the permanent power supply area, and introduce a backup clock source. When the integrated circuit enters a low-power mode, the clock of the debug access interface is switched to the backup clock source, ensuring that the debug access interface can continue to operate when the integrated circuit enters a low-power state. This enables real-time access and operation of resources in the permanent power supply area, solving the technical problem in related technologies where AON cannot be accessed after the integrated circuit enters a low-power state. Attached Figure Description
[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0040] Figure 1 This is a schematic diagram of the structure of an integrated circuit provided in an embodiment of this application;
[0041] Figure 2 This is a flowchart illustrating a method for accessing a permanently powered area provided in an embodiment of this application;
[0042] Figure 3 This is a schematic diagram of a device for accessing a permanently powered area provided in an embodiment of this application;
[0043] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.
[0044] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0046] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0047] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.
[0048] In modern integrated circuit design, low power consumption has become one of the key performance indicators, especially in mobile devices, Internet of Things (IoT) devices, and embedded systems. The stability and energy efficiency of low power mode directly determine the product's battery life and user experience.
[0049] When an integrated circuit enters a low-power state (such as deep sleep, shutdown mode, etc.), except for the necessary always-on domain (AON), the power to other system modules, such as the central processing unit (CPU), memory, peripherals, etc., will be cut off to reduce power consumption.
[0050] AON is an independent power domain in an integrated circuit that is always powered. Even when the system enters a low-power mode (such as sleep or power-off state), the AON region continues to operate to maintain the basic functions of the integrated circuit, including but not limited to:
[0051] Real-time clock and timers: ensure the system can keep accurate time while in sleep mode and wake up the main processor when needed.
[0052] Interrupt controller: Used to detect external events (such as key presses, network data, etc.) and wake up the main processor when necessary.
[0053] Low-power sensors, such as accelerometers, are used to monitor system status or environmental changes.
[0054] Partial storage units: such as reserved memory, are used to store critical data to ensure that data is not lost when the system is in hibernation.
[0055] AON typically includes key resources such as the core status register of the integrated circuit, power management controller, and timers. These resources need to run continuously in low-power mode to maintain system wake-up, clock synchronization, and status monitoring functions.
[0056] In actual development and debugging, after the integrated circuit enters a low-power state, developers or testers need to access the AON registers in real time to verify the correctness of the low-power logic, analyze abnormal states (such as crashes or wake-up failures), or adjust register configurations to optimize power consumption performance.
[0057] For example, during the low-power debugging phase, it is necessary to read the status register in AON to confirm whether the integrated circuit has successfully entered the target low-power mode; during the testing and acceptance phase, it is necessary to monitor AON resources to troubleshoot stability issues.
[0058] However, in related technologies, since the main power path of the integrated circuit is cut off in the low power state, the traditional debugging interface and access path are invalid, making it impossible to directly access AON resources. This forces developers to rely on indirect means (such as logging and external sensor monitoring) or to repeatedly modify the code and restart the integrated circuit for debugging, which greatly increases the debugging difficulty and development cycle.
[0059] Furthermore, in low-power mode, if an integrated circuit enters an unrecoverable deadlock state due to an anomaly, developers may not even be able to obtain critical register information, making it difficult to locate the problem and seriously affecting the product delivery schedule.
[0060] For example, some solutions include:
[0061] Indirect debugging method: This method indirectly analyzes the behavior of integrated circuits in low-power states by pre-setting a logging mechanism before low-power mode or by reading a stored register snapshot after wake-up. However, this method cannot monitor dynamic state changes in real time and requires pre-designing complex logging logic, resulting in poor flexibility.
[0062] Hardware reset debugging method: The integrated circuit is forcibly woken up and entered the debugging mode by external signal. However, this method requires interrupting the low-power process of the integrated circuit, which may disrupt the continuity of the test scenario and cannot reproduce instantaneous anomalies (such as system crashes in low-power mode).
[0063] Furthermore, the lack of a dedicated low-power debugging path or backup clock source in the relevant technologies causes debugging tools to completely fail in low-power mode. Developers typically have to rely on experience to infer the cause of the problem and verify it by repeatedly modifying code and restarting integrated circuits, resulting in low debugging efficiency and high manpower and time costs.
[0064] Therefore, how to access AON resources through debugging tools after an integrated circuit enters a low-power state has become a technical problem that urgently needs to be solved.
[0065] To address the aforementioned technical issues, this application provides a method for accessing AON resources in a low-power state. By constructing an access channel independent of the conventional power path and introducing a backup clock source, it ensures that the debug access interface continues to operate when the integrated circuit enters a low-power state, thereby enabling real-time access and operation of AON resources. This method overcomes the dependence of traditional debug paths on the main power supply and solves the technical problem of debug tool failure in low-power states through a combination of hardware redundancy design (independent access channel) and clock redundancy design (backup clock source).
[0066] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0067] This application's embodiments are applicable to integrated circuits requiring low-power functionality, particularly mobile devices, IoT devices, and embedded systems. During the low-power debugging phase (e.g., verifying whether the low-power mode executes as expected) and the testing and acceptance phase (e.g., troubleshooting low-power stability issues), developers can access AON registers in real time to analyze the integrated circuit status, adjust configurations, or locate anomalies. For example, when an integrated circuit crashes due to a low-power logic error, developers can confirm the cause of the error by reading the status registers in AON.
[0068] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of an integrated circuit provided in an embodiment of this application.
[0069] In some embodiments, the integrated circuit 100 includes a debug access interface 101 and a permanent power supply region 102. An independent access channel 103 is established between the debug access interface 101 and the permanent power supply region 102. The independent access channel 103 does not pass through any power-down module in the integrated circuit 100.
[0070] The aforementioned power-down module can refer to the module in integrated circuit 100 whose power supply is cut off in a low-power state, such as the CPU, bus controller, etc.
[0071] For example, in deep sleep mode, the CPU core and memory modules are powered off to reduce power consumption.
[0072] Optionally, the debug access interface 101 can be a DAP (Debug Access Port) to provide debugging, testing, and programming access to the target device.
[0073] In some implementations, a new physical path can be added to the integrated circuit directly connecting the DAP to the AON, without passing through any power-down modules such as the CPU or bus controller.
[0074] For example, in the physical layout of an integrated circuit, the DAP's signal lines are directly connected to the register interface of the AON region, bypassing the conventional bus controller and power management module. This creates a debug channel independent of the conventional power path, ensuring that debug tools can access AON resources through this channel in low-power conditions.
[0075] like Figure 2 As shown, Figure 2 This is a flowchart illustrating a method for dynamically adjusting a buffer provided in an embodiment of this application.
[0076] In some embodiments, the above-described dynamic buffer adjustment method includes:
[0077] S201. Monitor whether the integrated circuit has entered low-power mode. If so, proceed to S202.
[0078] In some implementations, the power management unit or low-power mode entry signal can be used to monitor whether the integrated circuit has entered a low-power mode.
[0079] S202. Switch the clock of the debug access interface to the backup clock source.
[0080] The backup clock source is used to enable the debug access interface to continue operating in low-power mode.
[0081] In some implementations, a backup clock source can be introduced for the DAP, and the clock source of the DAP can be switched to the backup clock source when the integrated circuit enters a low-power state.
[0082] For example, when the integrated circuit enters a low-power mode, the system software switches the clock source of the DAP from the master clock to the backup clock source through the power management controller to ensure that the DAP logic circuit continues to operate.
[0083] By dynamically switching the clock source, the DAP can maintain the necessary clock signal even in low-power conditions, thereby supporting the real-time operation of debugging tools.
[0084] S203. Access resources in the permanently powered area via the debug access interface and independent access channel.
[0085] In some implementations, the registers of the permanent power supply area can be read and written directly via DAP.
[0086] For example, an external debugging tool (such as Trace32) sends an access request to AON through the DAP via an independent access channel. The DAP uses a backup clock source to maintain its operating state and forwards the access request to the AON register interface to complete the read or write operation of AON resources.
[0087] The method for accessing the permanent power supply area provided in this application constructs an independent access channel, independent of the conventional power path, between the debug access interface and the permanent power supply area, and introduces a backup clock source. When the integrated circuit enters a low-power mode, the clock of the debug access interface is switched to the backup clock source, ensuring that the debug access interface can continue to operate when the integrated circuit enters a low-power state. This enables real-time access and operation of resources in the permanent power supply area, solving the technical problem in related technologies where AON cannot be accessed after the integrated circuit enters a low-power state.
[0088] In some embodiments, the aforementioned independent access channel includes at least one signal path, and the debug access interface uses the aforementioned at least one signal path to connect to the register interface of the permanent power supply area to form an independent access channel.
[0089] The signal path can refer to the physical wiring or logic channel within an integrated circuit used to transmit debug signals. For example, the signal path may consist of metal layer wiring or logic gate-level circuitry, directly connecting the DAP and AON register interfaces.
[0090] A register interface can refer to a hardware module in a permanently powered area used to receive and send register read / write requests. For example, the register interface of AON's power management controller.
[0091] In the physical layout of the integrated circuit, a new signal path is added, directly connecting the DAP and the AON register interface. This signal path is designed to bypass the power-down module, ensuring that debug signals are not blocked in low-power mode. The DAP uses this signal path to send access requests to the AON register interface, completing read or write operations on AON resources.
[0092] Optionally, at least one of the above signal paths includes at least one of the following:
[0093] Metal layer wiring: refers to physical interconnections directly laid within the metal layer of an integrated circuit. For example, signal lines are laid within the metal layer of an integrated circuit.
[0094] Logic gate-level circuits: These are dedicated circuit paths composed of logic gates (such as AND gates and OR gates). For example, direct signal forwarding is achieved through logic gate-level circuits.
[0095] Dedicated debug bus: refers to an independent bus structure designed for debugging functions. For example, a dedicated debug bus that is independent of the main bus.
[0096] The method for accessing a permanently powered area provided in this application, through the physical layout design of the signal path, achieves the separation of debugging signals from the main power path, ensuring that the debugging channel remains available in a low-power state. For example, in deep sleep mode, the debugging tool can directly access the status register in AON through the signal path without going through the power-down module, avoiding signal interruption caused by module power failure.
[0097] In some embodiments, the above method further includes:
[0098] A backup clock source is selected based on the low-power mode of the integrated circuit. This backup clock source includes a high-frequency oscillation circuit, which includes a 100MHz oscillation circuit.
[0099] This refers to a high-frequency internal oscillation circuit used to support rapid debugging. For example, a backup clock source could include a 100MHz oscillation circuit.
[0100] Optionally, the backup clock source may also include a low-frequency oscillation circuit. For example, the backup clock source may include a 32kHz oscillation circuit.
[0101] In some implementations, an alternate clock source is selected based on the current low-power mode of the integrated circuit (such as shallow sleep, deep sleep, or shutdown mode) before configuring an alternate clock source for the debug interface. For example, a high-frequency oscillator circuit is selected in shallow sleep mode to support fast debugging, while a low-frequency oscillator circuit is selected in shutdown mode to reduce power consumption.
[0102] The method for accessing a permanently powered area provided in this application embodiment can balance debugging accuracy and power consumption by dynamically selecting a backup clock source.
[0103] In some embodiments, the above-described access to resources in a permanently powered area via a dedicated access channel using a debug access interface includes:
[0104] Establish a connection between the debugging tool and the debugging access interface; use the debugging tool to send an access request to the debugging access interface; wherein, the debugging access interface is used to forward the access request to the resources in the permanently powered area using an independent access channel.
[0105] In some implementations, when the integrated circuit enters a low-power state, the debugging tool (such as Trace32) sends an access request to the DAP through an independent debugging channel. The DAP uses a backup clock source to maintain its operation and forwards the request to the register interface of the AON area through an independent path.
[0106] In some embodiments, the status register configuration in the permanent power supply area can be read or modified via a separate access channel using the debug access interface.
[0107] Optionally, the debugging tool can read the status register in AON in real time, modify the register configuration, or perform other debugging operations, thereby enabling monitoring and intervention of the low-power state of the integrated circuit.
[0108] The method for accessing the permanent power supply area provided in this application allows developers to monitor the AON register status in real time using debugging tools and directly analyze low-power anomalies (such as crashes or wake-up failures) without needing to verify through indirect means or repeated code modifications, thus significantly shortening the debugging cycle.
[0109] In some embodiments, this application also provides a device for accessing a permanently powered region, applied in an integrated circuit, the integrated circuit including a debug access interface and a permanently powered region, an independent access channel being established between the debug access interface and the permanently powered region, the independent access channel not passing through any power-down module in the integrated circuit.
[0110] Reference Figure 3 , Figure 3 This is a schematic diagram of a device for accessing a permanently powered area provided in an embodiment of this application. The device 30 for accessing the permanently powered area includes:
[0111] Monitoring module 301 is used to monitor whether the integrated circuit has entered a low-power mode.
[0112] The switching module 302 is used to switch the clock of the debug access interface to a backup clock source when the integrated circuit enters a low-power mode. The backup clock source is used to enable the debug access interface to continue operating in low-power mode.
[0113] Access module 303 is used to access resources in the permanently powered area via an independent access channel using the debug access interface.
[0114] In some embodiments, the aforementioned independent access channel includes at least one signal path, and the debug access interface uses at least one signal path to connect to the register interface of the permanent power supply area to form an independent access channel.
[0115] In some embodiments, the above-mentioned at least one signal path includes at least one of the following: metal layer wiring, logic gate-level circuit, and dedicated debug bus.
[0116] In some embodiments, the switching module 302 is further configured to:
[0117] A backup clock source is selected based on the low-power mode of the integrated circuit. This backup clock source includes a high-frequency oscillation circuit, which includes a 100MHz oscillation circuit.
[0118] In some embodiments, the access module 303 is used for:
[0119] Establish a connection between the debugging tool and the debugging access interface;
[0120] Use debugging tools to send access requests to the debugging access interface; the debugging access interface is used to forward access requests to resources in the permanently powered area using an independent access channel.
[0121] In some embodiments, the access module 303 is used for:
[0122] Using the debug access interface via a separate access channel, the status register configuration in the permanent power supply area can be read or modified.
[0123] The device for accessing a permanently powered area provided in this embodiment can execute the method for accessing a permanently powered area provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0124] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 4 As shown, the electronic device 40 provided in this embodiment includes at least one processor 401 and a memory 402. Optionally, the electronic device 40 further includes a communication interface 403. The processor 401, memory 402, and communication interface 403 are connected via a bus.
[0125] In a specific implementation, at least one processor 401 executes computer execution instructions stored in memory 402, causing at least one processor 401 to perform the above-described method for accessing the permanent power supply area.
[0126] The specific implementation process of processor 401 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0127] In the above embodiments, it should be understood that the processor can be a CPU, or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules within the processor.
[0128] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0129] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0130] This application also provides a chip including at least one processor for executing program instructions to perform the above-described method of accessing a permanently powered region.
[0131] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method for accessing a permanently powered region.
[0132] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method for accessing a permanently powered area.
[0133] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0134] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0135] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0136] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
Claims
1. A method for accessing a permanently powered area, characterized in that, The method is applied in an integrated circuit, which includes a debug access interface and a permanent power supply area. An independent access channel is established between the debug access interface and the permanent power supply area, and this independent access channel does not pass through any power-down module in the integrated circuit. Monitor whether the integrated circuit enters a low-power mode; When the integrated circuit enters a low-power mode, the clock of the debug access interface is switched to a backup clock source, which is used to enable the debug access interface to continue operating in the low-power mode. The resources of the permanently powered area can be accessed via the independent access channel using the debug access interface.
2. The method according to claim 1, characterized in that, The independent access channel includes at least one signal path, and the debug access interface uses the at least one signal path to connect to the register interface of the permanent power supply area to form the independent access channel.
3. The method according to claim 2, characterized in that, The at least one signal path includes at least one of the following: metal layer wiring, logic gate circuit, and dedicated debug bus.
4. The method according to claim 1, characterized in that, The method further includes: The backup clock source is selected according to the low-power mode of the integrated circuit. The backup clock source includes a high-frequency oscillation circuit, which includes a 100MHz oscillation circuit.
5. The method according to claim 1, characterized in that, Accessing resources in the permanently powered area via the independent access channel using the debug access interface includes: Establish a connection between the debugging tool and the debugging access interface; The debugging tool sends an access request to the debugging access interface; wherein the debugging access interface is used to forward the access request to the resources of the permanently powered area using the independent access channel.
6. The method according to claim 1, characterized in that, Accessing resources in the permanently powered area via the independent access channel using the debug access interface includes: Using the debug access interface via the independent access channel, the status register configuration in the permanent power supply area can be read or modified.
7. A device for accessing a permanently powered area, characterized in that, The device is applied in an integrated circuit, which includes a debug access interface and a permanent power supply area. An independent access channel is established between the debug access interface and the permanent power supply area, and this independent access channel does not pass through any power-down module in the integrated circuit. The device includes: A monitoring module is used to monitor whether the integrated circuit enters a low-power mode; A switching module is used to switch the clock of the debug access interface to a backup clock source when the integrated circuit enters a low-power mode. The backup clock source is used to enable the debug access interface to continue operating in the low-power mode. The access module is used to access the resources of the permanently powered area via the independent access channel using the debug access interface.
8. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method of accessing a permanently powered area as described in any one of claims 1-6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method for accessing a permanently powered area as described in any one of claims 1-6.
10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method for accessing a permanently powered region as described in any one of claims 1-6.