Satellite-borne program management system based on anti-fuse type FPGA and design method

Abstract

The invention relates to the technical field of satellite high-reliability design, and provides a satellite-borne program management system based on an anti-fuse type FPGA and a design method. The invention discloses a universal satellite-borne program management system based on an anti-fuse type FPGA (Field Programmable Gate Array) and a design method. According to the invention, an anti-fuse type FPGA is adopted to realize peripheral function modules such as a lightweight general processor core, an application management unit, a bus interface driver, a FLASH control driver and the like, and embedded software is written to call the peripheral function modules and the interface driver to realize system functions such as satellite-borne program management, application processing and the like; system functions are updated by updating embedded software running in the processor, high flexibility is achieved, and meanwhile the system running reliability under the outer space complex electromagnetic environment and the high-energy particle interference condition can be guaranteed based on the design of the anti-fuse type FPGA.

Description

Technical Field

[0001] This invention relates to the technical field of high-reliability satellite design, and in particular to an onboard program management system and design method based on an antifuse FPGA. Background Technology

[0002] In the field of aerospace applications, satellites and other spacecraft operate for extended periods in the extremely complex and harsh electromagnetic environment of outer space. This environment contains a large number of high-energy protons, electrons, heavy ions, and other radiation particles and rays. This radiation can severely interfere with the electronic devices carried by the spacecraft, with a particularly significant impact on SRAM-type FPGAs (Static Random Access Memory Field Programmable Gate Arrays). It can easily trigger Single Event Upset (SEU) effects, causing unexpected flips in the logic states of the FPGA's internal memory cells. This can lead to logic malfunctions, data transmission errors, and even complete FPGA logic failure, seriously threatening the normal operation of individual signal processing modules. Ultimately, this could result in on-orbit malfunctions of the spacecraft, jeopardizing the safe and stable operation of the satellite mission.

[0003] To address this critical reliability issue, the industry widely adopts antifuse FPGAs as the core device for onboard program management, program reloading, and periodic configuration item updates. Due to their unique process architecture, antifuse FPGAs possess excellent single-event protection capabilities, effectively resisting interference from space radiation particles. This provides stable hardware support for onboard electronic systems, making them a crucial technology choice for ensuring the reliability of stand-alone signal processing modules and guaranteeing the safe and stable operation of satellites in orbit.

[0004] However, antifuse FPGAs, limited by their inherent process characteristics, suffer from unavoidable technical shortcomings: on the one hand, these chips are programmable devices, meaning that once the circuit configuration is completed, their internal logic architecture cannot be modified or reconstructed, resulting in a severe lack of flexibility; on the other hand, compared to SRAM FPGAs, antifuse FPGAs have a more limited number of logic operation units and storage resources, making it difficult to directly perform preliminary debugging and functional verification of complex programs on them. Therefore, in existing technical solutions, the development of spaceborne systems based on antifuse FPGAs typically requires first using a conventional FPGA platform (mostly SRAM FPGA platforms) for program debugging, functional verification, and performance optimization, before porting the design to the antifuse FPGA after it matures. This development model not only increases the investment in additional hardware platforms but also leads to a cumbersome product development process and a lengthy iteration cycle. Furthermore, due to hardware differences between different platforms, design incompatibility issues are prone to occur, resulting in poor engineering portability and severely restricting the development efficiency and industrial application of spaceborne program management systems.

[0005] In summary, the existing technology relies on the high reliability of antifuse FPGAs to cope with the space radiation environment, but is limited by their process defects, resulting in low development efficiency and insufficient portability. This technical contradiction has become a key problem that urgently needs to be solved in the development of the spaceborne program management system. Summary of the Invention

[0006] To address the aforementioned problems, the present invention aims to provide a spaceborne program management system and design method based on an antifuse FPGA. This system offers good versatility, reduces the complexity of the antifuse FPGA development process, and significantly shortens the product development cycle.

[0007] The above-mentioned objective of this invention is achieved through the following technical solutions: An onboard program management system based on an antifuse FPGA includes a hardware platform that uses an FPGA as the core processing unit, peripheral configurations of a storage module, a bus interface, and an external SRAM-type FPGA program loading interface. A lightweight processor core and peripheral functional modules are implemented using HDL language. The design files are simulated, verified, synthesized, and configuration files are generated. The system application functions are implemented using an embedded language, and an executable file that can run on the processor core is generated through compilation. Both the SRAM-type FPGA program file and the processor executable program are stored in FLASH memory and can be managed and updated via the bus. The core processing unit is connected to the storage module, the bus interface, the external SRAM-type FPGA program loading interface, and the peripheral functional modules. The lightweight processor core communicates with the peripheral functional modules. The storage module is used to store the program configuration file of the external SRAM-type FPGA and the processor execution program. The embedded software execution and update architecture supports program management and updates via the bus.

[0008] Furthermore, the core processing unit, which is the core of the hardware platform, is an antifuse FPGA, and is externally configured with three FLASH memories, the memory modules being NOR FLASH or NAND FLASH; the bus interface includes interfaces such as RS422 interface, LVDS interface, 1553B interface, and CAN interface. The antifuse FPGA controls the FLASH storage module and other peripheral chips through a general interface, interacts with an external SRAM FPGA through an RS422 interface, loads the power-on program and refreshes the external SRAM FPGA periodically through the SelectMap interface, and communicates with the spaceborne integrated electronics through the RS422 / LVDS / 1553B / CAN data bus to transmit remote control and telemetry information streams.

[0009] Furthermore, the lightweight processor core can adopt the ARM architecture instruction set, MCS-51 instruction set, or RSIC instruction set, and implement the processor soft core function through HDL language and embed it in the antifuse FPGA; The lightweight processor soft core is responsible for running system applications. It includes a control unit, a storage unit, and an arithmetic unit. The control unit contains an instruction register, an instruction decoder, and an operation controller for instruction set parsing. The arithmetic unit is used for arithmetic and logical operations. The storage unit includes the CPU's on-chip cache and register set for processor data caching. The processor soft core is used to run embedded software programs and call various functional modules and interface drivers to implement system functions.

[0010] Furthermore, the peripheral functional modules include an application management unit, a bus interface driver, a FLASH control driver, an arbitration module, an external SRAM-type FPGA program interface module, a processor initialization module, an on-board data bus interface driver, an internal data interface driver, and a SelectMap interface driver; Each module communicates with the processor soft core through a register address mapping table, and the function register mapping table of each module is fixed in the antifuse FPGA; The processor initialization module is responsible for initializing the processor soft core and driving the application software to run. The specific processing method of this module is to detect the working status of the processor soft core after the system is powered on, request application data from the application management unit according to the working status and working mode, and load the application data into the internal running RAM of the processor soft core. The application management unit is used to receive the arbitration post-processing result of the processor soft core, complete the scheduling control of each functional interface module through register addressing, and receive data from each functional interface and transmit it to the processor soft core. The FLASH control driver is used to control the FLASH chip, including reading, writing, and erasing, and to store the program configuration files of the externally loaded SRAM FPGA and the application files of the processor soft core. The on-board data bus interface driver is used to interact with the on-board integrated electronics to exchange remote control commands and telemetry data, and to realize functions including remote control and telemetry. The internal data interface driver is used to communicate with the external SRAM FPGA chip, send control commands and obtain its status parameters; The SelectMap interface driver is used to write the configuration item data stream output by FLASH into the external SRAM FPGA, thereby realizing program loading and refreshing.

[0011] Furthermore, the embedded software is written and runs on the processor core according to the specific project agreement. The processor core executes the embedded program and outputs control signals. After arbitration control, the control signals send the voting results to the application management unit. By calling peripheral function modules and interface peripherals, functions including remote control and telemetry, on-orbit reconfiguration, external SRAM-type FPGA configuration file management, monitoring refresh and reloading are realized.

[0012] Furthermore, the embedded application can be updated or modified online via the bus interface, and the peripheral functional modules can be parameterized via the processor core to adapt to the specific needs of different projects.

[0013] Furthermore, the storage module can choose whether to implement a triple redundancy design based on its own radiation resistance and actual application requirements.

[0014] Furthermore, three processor soft cores are instantiated within the antifuse FPGA. The three processor soft cores run the same embedded execution program simultaneously. The execution results are voted on by the arbitration execution module using a two-out-of-three method. The result after the decision is sent to the application management unit for execution, so as to effectively reduce the probability of system malfunction caused by single-event upset.

[0015] A design method for an onboard program management system based on an antifuse FPGA, as described above, includes the following steps: S1: Implement a lightweight processor core and peripheral functional modules using HDL language, and perform simulation verification on the design documents; S2: Utilize a hardware platform based on SRAM-based FPGA chips for functional design verification. Optimize HDL design and placement and routing to meet timing and resource constraints, enabling the deployment of the processor core and peripheral functional modules on the same chip. S3: Port the fully functionally verified HDL design file to the project based on the antifuse FPGA chip, perform synthesis, placement, pin configuration, generate configuration files and burn them, and deploy the processor core and other functional modules onto the FPGA chip; S4: Write embedded software to implement system functions according to the specific project agreement; S5: The embedded software compilation file is written into FLASH through the debugging interface, and the processor core is initialized and the power-on program is loaded through FPGA boot.

[0016] An operation method for a spaceborne program management system based on an antifuse FPGA as described above, characterized by comprising the following steps: S1: Power-on initialization, read FLASH data to complete the program loading of the processor soft core; S2: External SRAM FPGA loading. Reads FLASH data to complete the program loading of the external SRAM type FPGA. If loading fails, repeats until loading times out. S3: Enter the application status polling state and transition to the status based on the triggering conditions; S4: Periodically read FLASH data to refresh the external SRAM FPGA; S5: If a remote control command is received, the processor enters the remote control command receiving state, and the processor soft core receives, parses, and outputs the external command. S6: If a processor soft core instruction is received, the processor instruction execution flow is entered, and the relevant instruction is executed; S7: If an on-orbit reconstruction instruction is received, the on-orbit reconstruction process begins. The instruction is executed to erase and reconstruct the configuration file stored in the FLASH memory. After completion, the application status polling process S3 is executed again.

[0017] Compared with the prior art, the present invention has at least one of the following beneficial effects: (1) In this invention, the processor core based on antifuse FPGA adopts HDL design, which has universality and portability. When developing for different hardware platforms, it is only necessary to adjust the pin constraints according to the peripheral circuit and select to call the corresponding interface driver, which can ensure the inheritance and consistency of similar products and reduce the manpower and time costs of the development process. (2) The system functions in this invention are implemented by writing embedded software to call peripheral function modules and interface drivers, which has high flexibility. Online program debugging can be performed after the FPGA is soldered, which can determine the hardware status of the product as early as possible and effectively shorten the product development cycle. (3) In this invention, configuration items are loaded and refreshed on an external SRAM FPGA based on an antifuse FPGA platform, which can realize functions such as on-orbit reconstruction, reset and reload, and periodic configuration item refresh of a single machine, and can ensure the reliability of system operation under complex electromagnetic environment and high-energy particle interference conditions in space. Attached Figure Description

[0018] Figure 1 This is a block diagram illustrating the system implementation of the present invention; Figure 2 This is a hardware connection block diagram of the present invention; Figure 3 This is a flowchart of the system development process for this invention; Figure 4 This is a flowchart of the system operation of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] This invention utilizes antifuse FPGA hardware resources to build a lightweight, general-purpose processor and peripheral functional modules. During the development phase, general-purpose embedded software programs can be written according to specific protocols to implement onboard program management functions. It has high versatility and flexibility. Compared with traditional development processes, it can quickly determine the product hardware status and shorten the development cycle.

[0022] The following is an illustration through specific examples: First Embodiment like Figure 1 As shown, this embodiment provides a spaceborne program management system based on an antifuse FPGA. The hardware platform uses an FPGA as the core processing unit, with peripheral configurations including a storage module, bus interface, and external SRAM-type FPGA program loading interface. A lightweight processor core and peripheral functional modules are implemented using HDL language. The design files are simulated, verified, synthesized, and configuration files are generated. The system application functions are implemented using an embedded language, and an executable file that can run on the processor core is generated through compilation. Both the SRAM-type FPGA program file and the processor executable program are stored in FLASH memory and can be updated via the bus. The core processing unit is connected to the storage module, the bus interface, the external SRAM-type FPGA program loading interface, and the peripheral functional modules. The lightweight processor core communicates with the peripheral functional modules. The storage module is used to store the program configuration file of the external SRAM-type FPGA and the processor execution program. The embedded software execution and update architecture supports program management and updates via the bus.

[0023] The system is built on an antifuse FPGA as its core hardware foundation. Data storage and interaction are ensured through configuration storage modules, multi-bus interfaces, and external SRAM FPGA program loading interfaces. Meanwhile, HDL language is used to complete the design and simulation verification of lightweight processor cores and peripheral functional modules to ensure hardware reliability. On the software side, the system application is developed through embedded language. The compiled executable file and the program file of the external SRAM FPGA are stored together in FLASH. This not only realizes core functions such as remote control and telemetry, configuration management, but also allows for convenient online management and updates of the program through the bus, thus balancing high reliability and application flexibility in spaceborne scenarios.

[0024] In this embodiment, as Figure 2 As shown, the core processing unit, which is the core of the hardware platform, is an antifuse FPGA, and is externally configured with three FLASH memories. The storage modules are NOR FLASH or NAND FLASH. The bus interface includes interfaces such as RS422 interface, LVDS interface, 1553B interface, and CAN interface. The antifuse FPGA controls the FLASH storage module and other peripheral chips through a general interface, interacts with an external SRAM FPGA through an RS422 interface, loads the power-on program and refreshes the external SRAM FPGA periodically through a SelectMap interface, and communicates with the onboard integrated electronics through an RS422 / LVDS / 1553B / CAN data bus to transmit remote control and telemetry information.

[0025] This hardware platform is supported by an antifuse FPGA as its core, paired with three NOR FLASH or NAND FLASH chips to form a storage module. It also integrates multiple bus interfaces such as RS422, LVDS, 1553B, and CAN, forming a fully functional hardware architecture. The antifuse FPGA acts as the control hub, managing the FLASH storage module and other peripherals through a general-purpose interface. It also enables data communication with external SRAM-type FPGAs via the RS422 interface, loads power-on programs and performs timed refreshes through the SelectMap interface, and interfaces with the spaceborne integrated electronic system through multiple data buses, efficiently transmitting remote control commands and telemetry data. This comprehensively ensures the reliability of hardware interaction and the integrity of data transmission in spaceborne scenarios.

[0026] In this embodiment, the lightweight processor core can adopt the ARM architecture instruction set, MCS-51 instruction set, or RSIC instruction set, and implement the processor soft core function through HDL language and embed it in the antifuse FPGA. The lightweight processor soft core is responsible for running system applications. It includes a control unit, a storage unit, and an arithmetic unit. The control unit contains an instruction register, an instruction decoder, and an operation controller for instruction set parsing. The arithmetic unit is used for arithmetic and logical operations. The storage unit includes the CPU's on-chip cache and register set for processor data caching. The processor soft core is used to run embedded software programs and call various functional modules and interface drivers to implement system functions.

[0027] This lightweight processor core supports multiple instruction sets including ARM, MCS-51, and RISC. After being designed using HDL, the soft core is embedded within an antifuse FPGA. Structurally, it integrates three core units: control, storage, and computation. The control unit parses instructions using instruction registers and decoders; the computation unit handles arithmetic and logical operations; and the storage unit caches data through on-chip caches and register sets. Ultimately, by running embedded software and calling various functional modules and interface drivers, it becomes the core computational carrier for realizing system functions.

[0028] In this embodiment, the peripheral functional modules include an application management unit, a bus interface driver, a FLASH control driver, an arbitration module, an external SRAM-type FPGA program interface module, a processor initialization module, an on-board data bus interface driver, an internal data interface driver, and a SelectMap interface driver. Each module communicates with the processor soft core through a register address mapping table, and the function register mapping table of each module is fixed in the antifuse FPGA; The processor initialization module is responsible for initializing the processor soft core and driving the application software to run. The specific processing method of this module is to detect the working status of the processor soft core after the system is powered on, request application data from the application management unit according to the working status and working mode, and load the application data into the internal running RAM of the processor soft core. The application management unit is used to receive the arbitration post-processing result of the processor soft core, complete the scheduling control of each functional interface module through register addressing, and receive data from each functional interface and transmit it to the processor soft core. The FLASH control driver is used to implement control of the FLASH chip, including reading, writing, and erasing, and to store the program configuration files of the externally loaded SRAMFPGA and the application files of the processor soft core. The on-board data bus interface driver is used to interact with the on-board integrated electronics to exchange remote control commands and telemetry data, and to realize functions including remote control and telemetry. The internal data interface driver is used to communicate with the external SRAM FPGA chip, send control commands and obtain its status parameters; The SelectMap interface driver is used to write the configuration item data stream output by FLASH into the external SRAM FPGA, thereby realizing program loading and refreshing.

[0029] This peripheral functional module integrates multiple core units, including initialization, scheduling, driving, and storage control. Each module communicates with the processor's soft core through a register address mapping table embedded in the antifuse FPGA, ensuring stable interaction. Specifically, the processor initialization module is responsible for soft core startup and program loading after power-on; the application management unit coordinates module scheduling and data transmission and reception; the FLASH control driver implements program file storage, read / write, and erase control; and various interface drivers respectively handle remote control and telemetry interaction with the onboard integrated electronics, communication with the external SRAM FPGA, and program loading and refresh functions, collectively providing comprehensive support for the implementation of the system's core functions.

[0030] In this embodiment, the embedded software is written and runs on the processor core according to the specific project agreement. The processor core executes the embedded program and outputs control signals. After arbitration control, the control signals send the voting results to the application management unit. By calling peripheral function modules and interface peripherals, functions including remote control and telemetry, on-orbit reconfiguration, external SRAM-type FPGA configuration file management, monitoring refresh and reloading are realized.

[0031] The embedded software is custom-developed and runs on the processor core according to the specific project agreement. After the processor core executes the software program, it outputs control signals. After the arbitration module performs a "two out of three" voting process, the reliable result is transmitted to the application management unit. Then, by calling various peripheral function modules and interface peripherals, it fully realizes the core functions of spaceborne remote control and telemetry, on-orbit reconfiguration, external SRAM-type FPGA configuration file management and monitoring refresh, reloading, etc., to ensure that the system runs stably as needed.

[0032] In this embodiment, the embedded application can be updated or modified online through the bus interface, and the peripheral functional modules can be parameterized through the processor core to adapt to the specific needs of different projects.

[0033] In this embodiment, the storage module can choose whether to implement a triple redundancy design based on its own radiation resistance and actual application requirements.

[0034] In this embodiment, three processor soft cores are instantiated within the antifuse FPGA. The three processor soft cores run the same embedded executable program simultaneously. The execution results are voted on by the arbitration execution module using a two-out-of-three method. The result after the decision is sent to the application management unit for execution, so as to effectively reduce the probability of system malfunction caused by single-event upset.

[0035] Second Embodiment like Figure 3 As shown, the system development process in the first embodiment includes steps such as design, functional verification, engineering porting, and embedded software writing and debugging, specifically including: S1: Implement a lightweight processor core and peripheral functional modules using HDL language, and perform simulation verification on the design documents; S2: Utilize a hardware platform based on SRAM-based FPGA chips for functional design verification. Optimize HDL design and placement and routing to meet timing and resource constraints, enabling the deployment of the processor core and peripheral functional modules on the same chip. S3: Port the fully functionally verified HDL design file to the project based on the antifuse FPGA chip, perform synthesis, placement, pin configuration, generate configuration files and burn them, and deploy the processor core and other functional modules onto the FPGA chip; S4: Write embedded software to implement system functions according to the specific project agreement; S5: The embedded software compilation file is written into FLASH through the debugging interface, and the processor core is initialized and the power-on program is loaded through FPGA boot.

[0036] Third Embodiment like Figure 4 As shown, the system operation flow in the first embodiment includes processor initialization, external SRAM-type FPGA loading control, remote control command detection, and telemetry output, specifically including: S1: Power-on initialization, read FLASH data to complete the program loading of the processor soft core; S2: External SRAM FPGA loading. Reads FLASH data to complete the program loading of the external SRAM type FPGA. If loading fails, repeats until loading times out. S3: Enter the application status polling state and transition to the status based on the triggering conditions; S4: Periodically read FLASH data to refresh the external SRAM FPGA; S5: If a remote control command is received, the processor enters the remote control command receiving state, and the processor soft core receives, parses, and outputs the external command. S6: If a processor soft core instruction is received, the processor instruction execution flow is entered, and the relevant instruction is executed; S7: If an on-orbit reconstruction instruction is received, the on-orbit reconstruction process begins. The instruction is executed to erase and reconstruct the configuration file stored in the FLASH memory. After completion, the application status polling process S3 is executed again.

[0037] A computer-readable storage medium stores computer code that, when executed, performs the methods described above. Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0038] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

[0039] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A spaceborne program management system based on an antifuse FPGA, characterized in that, The hardware platform uses FPGA as the core processing unit, with peripheral configurations including storage modules, bus interfaces, and external SRAM-type FPGA program loading interfaces. The lightweight processor core and peripheral functional modules are implemented using HDL language. The design files are simulated, verified, synthesized, and configuration files are generated. The system application functions are implemented using an embedded language. An executable file that can run on the processor core is generated by compilation. The program file of the SRAM-type FPGA and the processor execution program are both stored in FLASH and can be managed and updated via the bus. The core processing unit is connected to the storage module, the bus interface, the external SRAM-type FPGA program loading interface, and the peripheral functional modules. The lightweight processor core communicates with the peripheral functional modules. The storage module is used to store the program configuration file of the external SRAM-type FPGA and the processor execution program. The embedded software execution and update architecture supports program management and updates via the bus.

2. The onboard program management system based on antifuse FPGA according to claim 1, characterized in that, The core processing unit, which serves as the core of the hardware platform, is an antifuse FPGA, externally configured with three FLASH memories, the memory modules being NOR FLASH or NAND FLASH; the bus interfaces include RS422, LVDS, 1553B, and CAN interfaces. The antifuse FPGA controls the FLASH storage module and other peripheral chips through a general interface, interacts with an external SRAM FPGA through an RS422 interface, loads the power-on program and refreshes the external SRAM FPGA periodically through the SelectMap interface, and communicates with the spaceborne integrated electronics through the RS422 / LVDS / 1553B / CAN data bus to transmit remote control and telemetry information streams.

3. The onboard program management system based on antifuse FPGA according to claim 1, characterized in that, The lightweight processor core can adopt the ARM architecture instruction set, MCS-51 instruction set or RSIC instruction set, implement the processor soft core function through HDL language and be embedded in the antifuse FPGA; The lightweight processor soft core is responsible for running system applications. It includes a control unit, a storage unit, and an arithmetic unit. The control unit contains an instruction register, an instruction decoder, and an operation controller for instruction set parsing. The arithmetic unit is used for arithmetic and logical operations. The storage unit includes the CPU's on-chip cache and register set for processor data caching. The processor soft core is used to run embedded software programs and call various functional modules and interface drivers to implement system functions.

4. The onboard program management system based on antifuse FPGA according to claim 1, characterized in that, The peripheral functional modules include an application management unit, a bus interface driver, a FLASH control driver, an arbitration module, an external SRAM-type FPGA program interface module, a processor initialization module, an on-board data bus interface driver, an internal data interface driver, and a SelectMap interface driver. Each module communicates with the processor soft core through a register address mapping table, and the function register mapping table of each module is fixed in the antifuse FPGA; The processor initialization module is responsible for initializing the processor soft core and driving the application software to run. The specific processing method of this module is to detect the working status of the processor soft core after the system is powered on, request application data from the application management unit according to the working status and working mode, and load the application data into the internal running RAM of the processor soft core. The application management unit is used to receive the arbitration post-processing result of the processor soft core, complete the scheduling control of each functional interface module through register addressing, and receive data from each functional interface and transmit it to the processor soft core. The FLASH control driver is used to control the FLASH chip, including reading, writing, and erasing, and to store the program configuration files of the externally loaded SRAM FPGA and the application files of the processor soft core. The on-board data bus interface driver is used to interact with the on-board integrated electronics to exchange remote control commands and telemetry data, and to realize functions including remote control and telemetry. The internal data interface driver is used to communicate with the external SRAM FPGA chip, send control commands and obtain its status parameters; The SelectMap interface driver is used to write the configuration item data stream output by FLASH into the external SRAM FPGA, thereby realizing program loading and refreshing.

5. The onboard program management system based on antifuse FPGA according to claim 1, characterized in that, The embedded software is written and runs on the processor core according to the specific project agreement. The processor core executes the embedded program and outputs control signals. After arbitration control, the control signals send the voting results to the application management unit. By calling peripheral function modules and interface peripherals, functions including remote control and telemetry, on-orbit reconfiguration, external SRAM-type FPGA configuration file management, monitoring refresh and reloading are realized.

6. The onboard program management system based on antifuse FPGA according to claim 1, characterized in that, The embedded application can be updated or modified online through the bus interface, and the peripheral functional modules can be parameterized through the processor core to adapt to the specific needs of different projects.

7. The onboard program management system based on antifuse FPGA according to claim 1, characterized in that, The storage module can choose whether to implement a triple redundancy design based on its own radiation resistance and actual application requirements.

8. The onboard program management system based on antifuse FPGA according to claim 1, characterized in that, The processor soft core is instantiated in three within the antifuse FPGA. The three processor soft cores run the same embedded program simultaneously. The execution result is voted on by the arbitration execution module using a two-out-of-three method. The result after the decision is sent to the application management unit for execution, so as to effectively reduce the probability of system malfunction caused by single-event upset.

9. A design method for a spaceborne program management system based on an antifuse FPGA as described in any one of claims 1-8, characterized in that, Includes the following steps: S1: Implement a lightweight processor core and peripheral functional modules using HDL language, and perform simulation verification on the design documents; S2: Utilize a hardware platform based on SRAM-based FPGA chips for functional design verification. Optimize HDL design and placement and routing to meet timing and resource constraints, enabling the deployment of the processor core and peripheral functional modules on the same chip. S3: Port the fully functionally verified HDL design file to the project based on the antifuse FPGA chip, perform synthesis, placement, pin configuration, generate configuration files and burn them, and deploy the processor core and other functional modules onto the FPGA chip; S4: Write embedded software to implement system functions according to the specific project agreement; S5: The embedded software compilation file is written into FLASH through the debugging interface, and the processor core is initialized and the power-on program is loaded through FPGA boot.

10. A method for operating a spaceborne program management system based on an antifuse FPGA as described in any one of claims 1-8, characterized in that, Includes the following steps: S1: Power-on initialization, read FLASH data to complete the program loading of the processor soft core; S2: External SRAM FPGA loading. Reads FLASH data to complete the program loading of the external SRAM type FPGA. If loading fails, repeats until loading times out. S3: Enter the application status polling state and transition to the status based on the triggering conditions; S4: Periodically read FLASH data to refresh the external SRAM FPGA; S5: If a remote control command is received, the processor enters the remote control command receiving state, and the processor soft core receives, parses, and outputs the external command. S6: If a processor soft core instruction is received, the processor instruction execution flow is entered, and the relevant instruction is executed; S7: If an on-orbit reconstruction instruction is received, the on-orbit reconstruction process begins. The instruction is executed to erase and reconstruct the configuration file stored in the FLASH memory. After completion, the application status polling process S3 is executed again.

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