Chip accelerator collaborative optimization method based on AutoCoDA framework
By using the AutoCoDA framework to achieve collaborative optimization of machine learning models and accelerators on FPGAs, the problem of low efficiency in matching model design with hardware resources is solved, enabling rapid and automated optimization deployment and improving the performance of embedded platforms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING JIAOTONG UNIV
- Filing Date
- 2026-02-05
- Publication Date
- 2026-05-15
AI Technical Summary
Existing technologies separate machine learning model design from FPGA accelerator design on embedded platforms, resulting in low resource matching efficiency and time-consuming adjustments. Furthermore, existing AutoML methods lack hardware resource awareness, making rapid iterative optimization difficult.
The AutoCoDA framework is adopted to build a resource prediction model and embed resource feedback from the proxy model to achieve collaborative optimization between the model and the accelerator. It combines multi-objective optimization of model accuracy and resource consumption, and uses high-level integrated code generation and optimization algorithms for automated deployment.
It achieves collaborative optimization of models and hardware resources, improves the overall performance of deployment schemes, shortens search time, reduces the professional knowledge requirements of designers, supports multiple optimization strategies, and improves development efficiency.
Smart Images
Figure CN122044871A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of machine learning model optimization and FPGA hardware acceleration technology. Specifically, it relates to a chip accelerator co-optimization method based on the AutoCoDA framework, which is an automated co-design framework for algorithms and chip accelerators. Background Technology
[0002] With the widespread application of artificial intelligence technology in IoT edge devices, higher demands are being placed on the efficient inference of machine learning models on embedded platforms. FPGAs, with their advantages of low power consumption and high parallelism, have become one of the important platforms for accelerating edge AI inference. However, traditional methods separate model design from accelerator design, which has two problems: first, the model structure may not be compatible with hardware resource constraints, making it difficult to achieve optimal implementation efficiency; second, manually adjusting the matching of model parameters with hardware resources is time-consuming and makes it difficult to obtain the optimal configuration.
[0003] In recent years, Automated Machine Learning (AutoML) technology has matured and can be used to automatically search for optimal model structures. However, existing AutoML methods primarily focus on accuracy metrics in their objective functions, lacking awareness of hardware resource constraints. Although some studies have attempted to introduce resource constraints during the search process, these methods mostly rely on actual hardware synthesis to obtain resource information, resulting in high time costs (typically requiring several minutes to several hours to complete a single synthesis) and making it difficult to achieve rapid iterative searches. Therefore, an automated method is needed that can quickly predict resource consumption during the search process and achieve co-optimization between the model and accelerator. Summary of the Invention
[0004] In view of this, this invention proposes a chip accelerator collaborative optimization method based on the AutoCoDA framework. This method uses a hardware-aware automatic machine learning mechanism to embed resource prediction feedback based on surrogate models in the model search iteration, and links with a high-level synthesis (HLS) code generation module to achieve multi-objective collaborative optimization of accuracy and resources and end-to-end automated deployment during the search process.
[0005] The technical solution of the present invention includes the following steps: Step 1: Building a Resource Prediction Model Before performing collaborative search, a regression model is constructed to predict hardware resource consumption. This includes: (1) In the configuration parameter search space, the Latin hypercube sampling method is used to obtain N sets of sample configuration parameters, where N is the preset number of samples, for example, N=50~200; (2) Configure parameters for each group of samples, execute the high-level synthesis process and FPGA synthesis process to obtain the corresponding actual hardware resource consumption, which includes lookup table (LUT) resource consumption, flip-flop (FF) resource consumption and block memory (BRAM) resource consumption; (3) Using configuration parameters as input features and actual hardware resource consumption as the prediction target, train a regression model. The regression model may be a linear regression model, a support vector regression model, a random forest regression model, or a neural network regression model.
[0006] Step 2: Defining the Search Space The search space for configuration parameters of candidate machine learning models is defined based on the target application. For decision tree models (including decision trees, random forests, and gradient boosting decision trees), the configuration parameters include maximum tree depth, number of trees, minimum number of leaf node samples, learning rate, feature sampling ratio, and regularization coefficient; for neural network models, the configuration parameters include number of network layers, number of neurons per layer, activation function type, quantization bit width, and pruning ratio.
[0007] An initial candidate configuration set is generated using a random sampling method or a Latin hypercube sampling method as the starting point for the search.
[0008] Step 3: Evaluation of Candidate Configurations In each iteration of the collaborative search, the current candidate configuration is evaluated, including both model accuracy evaluation and hardware resource consumption prediction.
[0009] (1) Model accuracy evaluation: Train the corresponding machine learning model based on the current candidate configuration parameters, and evaluate the model accuracy metrics on the validation dataset. The accuracy metrics are determined according to the task type. For classification tasks, the area under the curve (AUC) or accuracy is used, and for regression tasks, the mean squared error (MSE) or mean absolute error (MAE) is used.
[0010] (2) Hardware resource consumption prediction: Using the resource prediction model constructed in step one, predict the hardware resource consumption required for the corresponding FPGA implementation based on the current candidate configuration parameters.
[0011] Dynamic updates to the resource prediction model: During the search process, when a candidate configuration is selected for full comprehensive validation, the actual resource consumption data obtained from the validation is added to the training dataset. When the accumulated number of new samples reaches a preset threshold (e.g., every 10 new samples), the resource prediction model is retrained to improve prediction accuracy.
[0012] Step 4: Collaborative Search Optimization Based on the model accuracy index and predicted hardware resource consumption obtained in step three, the objective function value is calculated, and the search strategy is updated using an optimization algorithm to generate new candidate configurations.
[0013] (1) Definition of objective function By combining model accuracy metrics with predicted hardware resource consumption, a collaborative optimization objective function is defined. The general form of the objective function is: F(x) = α·f_accuracy(x) + β·f_resource(x) Where x is the candidate configuration parameter vector, f_accuracy(x) is the accuracy evaluation function, f_resource(x) is the resource evaluation function, and α and β are weighting factors.
[0014] Specifically, for classification tasks, the accuracy evaluation function is defined as: f_accuracy(x) = 1 - AUC(x) AUC(x) is the area under the curve of the candidate configuration model on the validation dataset.
[0015] For regression tasks, the accuracy evaluation function can be the mean squared error (MSE) or the mean absolute error (MAE). The resource evaluation function is defined as follows: f_resource(x) = ln(1 + RES(x)) Where RES(x) is the normalized hardware resource consumption. The normalized hardware resource consumption is calculated as follows: Where LUT(x), FF(x), and BRAM(x) are the predicted lookup table resource size, trigger resource size, and block memory resource size, respectively; , , These represent the total available lookup table resources, total trigger resources, and total block memory resources of the target FPGA, respectively. , , This is the weighting factor for various resources, with a default value of 1 / 3.
[0016] This invention supports the following optimization strategies: Strategy 1, Accuracy-First Strategy: Set α > β to make the optimization process focus more on model accuracy; Strategy 2, Resource Priority Strategy: Set β > α to make the optimization process pay more attention to hardware resource consumption; Strategy 3, Balancing Strategy: Set α = β = 0.5 to balance the relative importance of accuracy and resources; Strategy 4, Pareto multi-objective strategy: Treat f_accuracy(x) and f_resource(x) as two independent optimization objectives, and use a multi-objective evolutionary algorithm (such as the non-dominated sorting genetic algorithm NSGA-II) to find the Pareto optimal solution set.
[0017] (2) Optimize algorithm iteration An optimization algorithm is used to update the search strategy based on the objective function value. Possible optimization algorithms include Bayesian optimization, genetic algorithms, particle swarm optimization, and random search algorithms.
[0018] In each iteration, the optimization algorithm selects the next set of candidate configuration parameters from the search space for evaluation based on the historical evaluation results.
[0019] Step 5: Determine the search termination condition Determine whether a preset search termination condition is met. The search termination condition includes at least one of the following conditions: (1) Reach the preset maximum number of iterations; (2) The improvement in the objective function value over multiple consecutive iterations is less than a preset threshold; (3) The number of configurations searched has reached the preset limit; (4) Find a configuration that meets the preset accuracy threshold and whose hardware resource consumption is lower than the preset resource limit.
[0020] If the search termination condition is met, the optimal model configuration is output. The optimal model configuration is the configuration that meets the preset accuracy threshold requirement and has the minimum hardware resource consumption. If it is not met, return to step three to continue the iteration.
[0021] Step Six: FPGA Accelerator Generation and Deployment Based on the optimal model configuration and trained model parameters, an FPGA accelerator is generated and deployed.
[0022] (1) Generation of high-level synthesis source code Based on the structural parameters of the optimal model configuration and the parameters of the trained model, high-level synthesis source code is generated. The source code is written in C or C++ and conforms to the input specifications of high-level synthesis tools.
[0023] During source code generation, HLS optimization instructions are automatically applied based on the model structure to improve hardware performance. These optimization instructions include: Pipeline instructions: Pipeline the loop to improve throughput; Unroll instruction: Unrolls a loop into hardware units that can be executed in parallel; Array partitioning command (Array_Partition): Partitions an array to increase storage bandwidth.
[0024] (2) Hardware description code generation The source code is converted into register-transfer-level (RTL) hardware description code using high-level synthesis tools. The hardware description code is written in Verilog or VHDL.
[0025] (3) FPGA bitstream generation and deployment The hardware description code is synthesized, placed, and routed to generate an FPGA bitstream file. This bitstream file is then downloaded to the target FPGA platform to complete the accelerator deployment.
[0026] (4) Deployment verification After deployment, inference latency and resource usage are verified through actual operation to ensure that the optimization results meet expectations.
[0027] The system provided by this invention mainly includes the following modules: Resource prediction module: This module constructs a resource prediction model based on historical comprehensive data, predicting the hardware resource consumption required for the corresponding FPGA implementation according to the configuration parameters of the machine learning model. The resource prediction module includes a sampling unit, a synthesis execution unit, and a regression model training unit. The sampling unit samples parameters in the configuration parameter search space to generate sample configuration parameters; the synthesis execution unit performs high-level synthesis and FPGA synthesis on the sample configuration parameters to obtain the actual hardware resource consumption; the regression model training unit trains a regression model based on the sample configuration parameters and the corresponding actual hardware resource consumption.
[0028] The model training module is used to train the corresponding machine learning model based on the candidate configuration parameters and evaluate the model's accuracy on the validation dataset. The model training module includes a model building unit, a training execution unit, and an accuracy evaluation unit.
[0029] The collaborative search module defines the search space for configuration parameters. Using model accuracy metrics and predicted hardware resource consumption as optimization objectives, it employs a multi-objective optimization algorithm to automatically search the search space and output the optimal model configuration that meets the preset accuracy threshold and minimizes hardware resource consumption. The collaborative search module includes a search space definition unit, an objective function calculation unit, and an optimization algorithm execution unit.
[0030] Hardware generation module: Used to generate the corresponding FPGA accelerator implementation based on the optimal model configuration using high-level synthesis tools. The hardware generation module includes a code generation unit, a high-level synthesis unit, and a bitstream generation unit.
[0031] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) To address the matching efficiency problem caused by the separation of model design and accelerator design in traditional methods, this invention integrates model accuracy evaluation and hardware resource prediction into a unified optimization objective function, thereby achieving collaborative optimization of model configuration and hardware resources and improving the overall performance of the final deployment scheme.
[0032] (2) To address the search efficiency problem caused by existing AutoML methods relying on actual synthesis to obtain resource information, this invention uses a pre-trained resource prediction model to replace the actual synthesis operation in each iteration. The time taken for a single resource prediction is usually in the millisecond range, which significantly shortens the single iteration time compared to the actual synthesis operation (which usually takes several minutes to several hours), thereby improving the overall search efficiency.
[0033] (3) This invention supports a variety of optimization strategies (precision priority, resource priority, balanced strategy and Pareto multi-objective strategy), and the optimization direction can be flexibly selected according to the needs of different application scenarios.
[0034] (4) The resource prediction model of the present invention supports a dynamic update mechanism. During the search process, the prediction accuracy can be continuously improved through online incremental learning, making the resource prediction in the later stages of the search more accurate.
[0035] (5) This invention realizes full-process automation from model configuration search to FPGA accelerator deployment, reduces the requirements for designers' professional knowledge and improves development efficiency. Attached Figure Description
[0036] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. In the drawings: Figure 1 This is a schematic diagram of the system architecture of the AutoCoDA framework in this invention; Figure 2 This is a flowchart of the overall collaborative optimization method based on AutoCoDA in this invention; Figure 3 This is a flowchart illustrating the construction process of the resource prediction model for this invention. Figure 4 This is a flowchart of the collaborative search optimization iteration process of the present invention; Figure 5 This is a schematic diagram illustrating the configuration parameters of the decision tree model in this embodiment of the invention; Figure 6 This is a schematic diagram illustrating the configuration parameters of the neural network model in this embodiment of the invention; Figure 7This is a schematic diagram of the objective function and Pareto optimization in an embodiment of the present invention. Detailed Implementation
[0037] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0038] This embodiment proposes a chip accelerator co-optimization method based on the AutoCoDA framework, which is an automated co-design framework for algorithms and chip accelerators. Figure 1 The system architecture of the AutoCoDA framework is illustrated in the diagram. This diagram shows the data flow and interaction between the resource prediction module, collaborative search module, model training module, and hardware generation module.
[0039] Example 1 Co-optimization of gradient boosting decision tree models on FPGA This embodiment takes the collaborative optimization of a gradient boosting decision tree model on an FPGA as an example, and constructs a complete technical narrative chain through multiple attached figures: Figure 1 As a system architecture overview diagram, the data flow and interaction logic of each module are defined: the resource prediction module receives the configuration parameters (labeled 103→101) issued by the collaborative search module, generates samples through the internal sampling unit, and outputs the resource prediction value (labeled 101→103) by the regression model training unit after HLS synthesis; the prediction value and the accuracy evaluation output by the model training module (labeled 102→103) jointly drive the optimization decision of the collaborative search module. Figure 2 As a sequence diagram of method execution, it clarifies the optimization process. Figure 3 As a kernel diagram of the resource prediction module, the construction mechanism of module 101 is refined; Figure 4 As a flowchart of collaborative search iteration, it reveals the optimization decision logic of module 103.
[0040] In this embodiment, a gradient boosting decision tree model is used to perform a binary classification task on the SECOM public dataset, and the target FPGA platform is the Xilinx ZCU102 development board.
[0041] The search space for model configuration parameters is defined as follows (see configuration parameter composition). Figure 5 ): Maximum tree depth D: The value ranges from {3, 4, 5, 6, 7}. The number of trees N: takes values in the range {50, 100, 150, 200}; Minimum number of leaf node samples L: The value ranges from {16, 32, 64}.
[0042] The total number of configurations for the search space is 5×4×3=60.
[0043] Step 1: Resource Prediction Model Construction (See detailed process) Figure 3 ) Fifty sets of configuration parameters were collected within the aforementioned parameter search space using the Latin hypercube sampling method. A complete high-level synthesis and FPGA synthesis process was performed on each set of configuration parameters to obtain data on LUT resource quantities, FF resource quantities, and BRAM resource quantities.
[0044] A random forest regression model is trained using configuration parameters (D, N, L) as input features and resource occupancy as the regression objective. In this embodiment, 5-fold cross-validation is used to evaluate the prediction accuracy, and the average relative error of resource prediction is within 8%.
[0045] Steps 2 through 5: Collaborative Search Optimization (see detailed process) Figure 4 ) A Bayesian optimization algorithm is used to guide the selection of candidate configurations. In each iteration, a gradient boosting decision tree model is trained based on the current candidate configuration parameters, and the AUC metric is calculated on the validation dataset. Simultaneously, the predicted resource consumption RES is obtained through a resource prediction model.
[0046] The objective function employs an equilibrium strategy, with weighting factors α=β=0.5. This strategy... Figure 7 Point C corresponds to the Pareto front, specifically in the form of: F(x) = -0.5 × AUC(x) + 0.5 × ln(1 + RES(x)) After 40 iterations, the optimal configuration was found to be: maximum tree depth D=5, number of trees N=100, and minimum number of leaf node samples L=32. The model with this configuration achieved an AUC of 0.91 on the validation dataset, and the predicted hardware resource consumption was approximately 35% of the available resources on the target FPGA (of which LUTs accounted for 32%, FFs for 28%, and BRAMs for 45%).
[0047] Step Six: FPGA Accelerator Generation and Deployment High-level integrated source code is generated based on the optimal configuration (D=5, N=100, L=32) and the trained model parameters. The following is a code snippet example (pseudocode form) of the generated decision tree inference function: void predict(float features[FEATURE_NUM], int &result) { #pragma HLS PIPELINE int tree_results[NUM_TREES]; for (int t = 0; t < NUM_TREES; t++) { #pragma HLS UNROLL tree_results[t] = evaluate_tree(t, features); } result = aggregate(tree_results); } Where FEATURE_NUM is the number of input features, NUM_TREES is the number of trees (100 in this example), the evaluate_tree function is used to perform inference for a single decision tree, and the aggregate function is used to aggregate the results of all decision trees.
[0048] The following HLS optimization directives were applied in the code: #pragma HLS PIPELINE: Pipeline the outer inference function; #pragma HLS UNROLL: Fully expands the decision tree traversal loop, allowing 100 trees to execute in parallel.
[0049] The above code is converted into Verilog hardware description code using a high-level synthesis tool, and then synthesized, placed, and routed to generate a bitstream file. The bitstream file is then downloaded to the Xilinx ZCU102 development board for deployment.
[0050] The deployment verification results are as follows: The actual resource usage after integration is as follows: LUT usage is 31%, FF usage is 27%, and BRAM usage is 44%, which is close to the predicted values of the resource prediction model (LUT 32%, FF 28%, BRAM 45%), and the prediction error is within 3%.
[0051] The performance test results after deployment are as follows: single inference latency is 0.8ms, and throughput reaches 1250 samples / second.
[0052] Compared to the baseline model: The baseline model uses the default configuration (D=6, N=200, L=64), and its resource usage on the same FPGA platform is 52% for LUT, 45% for FF, and 73% for BRAM. Compared to the baseline model, the optimized model of this invention reduces resource usage by approximately 40% (40% reduction in LUT, 40% in FF, and 40% in BRAM). Simultaneously, due to the reduced resource usage, the operating frequency can be increased from 100MHz to 150MHz, resulting in approximately a 2x increase in inference speed.
[0053] Example 2 Co-optimization of neural network models on FPGA In this embodiment, a multilayer perceptron neural network model is used to perform a handwritten digit recognition task on the MNIST dataset, and the target FPGA platform is the Xilinx Artix-7 series.
[0054] The search space for model configuration parameters is defined as follows (see configuration parameter composition). Figure 6 ): Number of hidden layers: The value ranges from {1, 2, 3}; Number of neurons per layer: The value ranges from {32, 64, 128, 256}. Activation function type: The value range is {ReLU, Sigmoid, Tanh}; Quantization bit width: The value range is {8, 16, 32} bits.
[0055] The resource prediction model was constructed and collaborative search optimization was performed using the same method as in Example 1.
[0056] After 50 iterations, the optimal configuration was found to be: 2 hidden layers, 64 neurons per layer, ReLU activation function, and 8-bit quantization. The model with this configuration achieved an accuracy of 97.2% on the test dataset, and the predicted hardware resource consumption was approximately 42% of the available resources on the target FPGA.
[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A chip accelerator co-optimization method based on the AutoCoDA framework, wherein the AutoCoDA framework is an automated co-design framework for algorithms and chip accelerators, including a resource prediction module, a co-search module, a model training module, and a hardware generation module, characterized in that, Includes the following steps: Step 1: Resource prediction model construction: Using the Latin hypercube sampling method, multiple sets of sample configuration parameters are sampled in the configuration parameter search space. For each set of sample configuration parameters, a high-level synthesis process and an FPGA synthesis process are executed to obtain the corresponding actual hardware resource consumption. The regression model is trained with the sample configuration parameters as input and the actual hardware resource consumption as output to obtain the resource prediction model. Step 2: Define the configuration parameter search space for candidate machine learning models based on the target application. The configuration parameters include model structure parameters and model training parameters. Step 3: Candidate Configuration Evaluation: For the current candidate configuration parameters, train the corresponding machine learning model and evaluate the model accuracy on the validation dataset; use the resource prediction model to predict the hardware resource consumption required for the corresponding FPGA implementation based on the candidate configuration parameters; Step 4: Collaborative Search Optimization: Substitute the model accuracy index and the hardware resource consumption into the preset objective function to calculate the objective function value, and use an optimization algorithm to update the search strategy based on the objective function value to generate new candidate configuration parameters; the optimization algorithm is a Bayesian optimization algorithm, a genetic algorithm, a particle swarm optimization algorithm, or a random search algorithm; Step 5: Iteration and Termination: Repeat steps 3 and 4 until the preset search termination condition is met, and output the optimal model configuration; Step Six: FPGA Accelerator Generation: Based on the optimal model configuration, generate the corresponding FPGA accelerator implementation using high-level synthesis tools.
2. The method according to claim 1, characterized in that, The regression model mentioned in step one is a linear regression model, a support vector regression model, a random forest regression model, or a neural network regression model.
3. The method according to claim 1, characterized in that, The hardware resource consumption includes at least one of the following: lookup table resources, trigger resources, and block memory resources.
4. The method according to claim 1, characterized in that, The resource prediction model is dynamically updated during the search process. When a candidate configuration is selected for complete comprehensive verification, the actual resource consumption data obtained from the verification is added to the training dataset to retrain the resource prediction model.
5. The method according to claim 1, characterized in that, The objective function described in step four is in the following form: F(x) = α·f_accuracy(x) + β·f_resource(x), Where x is the candidate configuration parameter vector, f_accuracy(x) is the accuracy evaluation function, f_resource(x) is the resource evaluation function, and α and β are weighting factors.
6. The method according to claim 5, characterized in that, For classification tasks, the accuracy evaluation function is defined as follows: f_accuracy(x) = 1 - AUC(x), Where AUC(x) is the area under the curve of the model corresponding to the candidate configuration on the validation dataset; For regression tasks, the accuracy evaluation function can be the mean squared error (MSE) or the mean absolute error (MAE). The resource evaluation function is defined as follows: f_resource(x) = ln(1 + RES(x)), Where RES(x) is the normalized hardware resource consumption.
7. The method according to claim 1, characterized in that, The search termination conditions described in step five include at least one of the following conditions: reaching a preset maximum number of iterations; the improvement of the objective function value in multiple consecutive iterations being less than a preset threshold; finding a configuration that meets the preset accuracy threshold requirement and whose hardware resource consumption is lower than the preset resource limit.
8. The method according to claim 1, characterized in that, In step six, when generating the FPGA accelerator implementation, high-level synthesis optimization instructions are automatically applied according to the model structure. The optimization instructions include at least one of pipeline instructions, loop unrolling instructions, and storage array partitioning instructions.
9. The method according to claim 1, characterized in that, The machine learning model is a decision tree model, a random forest model, a gradient boosting decision tree model, or a neural network model. When the machine learning model is a decision tree model, a random forest model, or a gradient boosting decision tree model, the configuration parameters include at least two of the following: maximum tree depth, number of trees, minimum number of leaf node samples, learning rate, feature sampling ratio, and regularization coefficient. When the machine learning model is a neural network model, the configuration parameters include the number of network layers, the number of neurons per layer, the activation function type, the quantization bit width, and the pruning ratio.