On-chip routing storage and calculation fusion architecture based on single-chip three-dimensional integration

Abstract

The invention provides an on-chip routing, storage and calculation fusion architecture based on single-chip three-dimensional integration, and relates to the field of calculation architectures, and the on-chip routing, storage and calculation fusion architecture comprises a functional layer and a routing layer which are arranged in a stacked manner; the functional layer and the routing layer are electrically connected through interconnection of interlayer dielectric via holes; the functional layer comprises a functional circuit, and the functional circuit comprises a logic calculation array, a storage and calculation integrated array and a cache array; the routing layer comprises a routing array; the routing array comprises a plurality of routing units; in the first direction and the second direction, the adjacent routing units are connected through a bidirectional bus; in the third direction, the adjacent routing units and logic calculation subarrays are connected through bidirectional buses; the adjacent routing units are connected with the storage and calculation integrated sub-arrays through bidirectional buses; and the adjacent routing units are connected with the cache subarrays through bidirectional buses. According to the method and the device, on-chip computing and storage resources can be flexibly called to the maximum extent, and the maximum reconfigurability is realized.

Description

Technical Field

[0001] This application relates to the field of computing architecture, and in particular to an on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration. Background Technology

[0002] With the development of integrated circuit technology, the number of computing units integrated into on-chip systems is increasing daily, creating an urgent need for high-bandwidth, high-parallelism on-chip communication. To address this issue, on-chip communication architecture has evolved from a shared bus to point-to-point connections. The shared bus architecture connects all computing units via a single shared bus, resulting in low communication efficiency. Furthermore, as the number of units increases, bus conflicts and latency problems become increasingly severe, making it difficult to meet the demands of large-scale parallel computing. To overcome the bus bottleneck, point-to-point connection schemes were proposed, establishing dedicated paths between specific units. However, this scheme has extremely poor scalability, and as the number of computing units increases, the number of wires and area required for connections grows exponentially, leading to a sharp increase in system complexity and cost, making it unsuitable for large-scale systems. Summary of the Invention

[0003] This application proposes an on-chip routing and in-memory computing fusion architecture based on monolithic 3D integration, aiming to improve the problem that current on-chip systems are too complex and difficult to meet the requirements of large-scale parallel computing.

[0004] To achieve the above objectives, embodiments of this application provide an on-chip routing-in-memory computing converged architecture based on monolithic three-dimensional integration. This on-chip routing-in-memory computing converged architecture includes a stacked functional layer and a routing layer; the functional layer and the routing layer are electrically connected through inter-layer dielectric vias; the functional layer includes functional circuits, including a logic computing array, an in-memory computing array, and a cache array; the routing layer includes a routing array; the logic computing array includes multiple logic computing subarrays; the in-memory computing array includes multiple in-memory computing subarrays; the cache array includes multiple cache subarrays; the routing array includes multiple routing units; in a first direction and a second direction, adjacent routing units are connected via a bidirectional bus; in a third direction, adjacent routing units are connected to the logic computing subarray via a bidirectional bus; adjacent routing units are connected to the in-memory computing subarray via a bidirectional bus; adjacent routing units are connected to the cache subarray via a bidirectional bus.

[0005] The on-chip routing-in-memory computing architecture based on monolithic 3D integration provided in this application, by setting up a functional layer and a routing layer, with the functional layer including a logic computing array, an in-memory computing array, and a cache array, allows for flexible configuration of these arrays and routing units according to application scenarios, meeting the computing needs of different scenarios and exhibiting versatility. Furthermore, the routing layer and functional layer stack utilize high-density inter-layer interconnects for communication between the routing network and functional modules, which not only reduces area but also increases chip computing power per unit area. The routing units in the routing layer and the functional subarrays in the functional layer of this application are correspondingly connected, enabling maximum flexible access to on-chip computing and storage resources and achieving maximum chip reconfigurability.

[0006] In some embodiments, a routing unit connecting 5 bidirectional buses has 25 transmission gates and 25 registers; wherein one bidirectional bus corresponds to 5 transmission gates and 5 registers; a routing unit connecting 4 bidirectional buses has 16 transmission gates and 16 registers; wherein one bidirectional bus corresponds to 4 transmission gates and 4 registers; a routing unit connecting 3 bidirectional buses has 9 transmission gates and 9 registers; wherein one bidirectional bus corresponds to 3 transmission gates and 3 registers.

[0007] In some embodiments, a bidirectional bus is configured such that only one corresponding transmission gate is opened for each data transmission.

[0008] In some embodiments, there is a one-to-one correspondence between transmission gates and registers; the registers are used to control the opening or closing of their corresponding transmission gates.

[0009] In some embodiments, the output of a register is connected to the control port of a transmission gate; when the output signal of the register is high, the corresponding transmission gate is turned on; when the output signal of the register is low, the corresponding transmission gate is turned off.

[0010] In some embodiments, a transmission gate is composed of multiple complementary transmission gates. A complementary transmission gate includes a P-type transistor and an N-type transistor with opposite control signals and their source and drain shorted, respectively. When the control signal input to the complementary transmission gate is high, the P-type transistor and the N-type transistor in the complementary transmission gate are turned on simultaneously, and the input data is transmitted out. When the control signal input to the complementary transmission gate is low, the P-type transistor and the N-type transistor in the complementary transmission gate are turned off simultaneously, and the input data is isolated.

[0011] In some embodiments, the number of complementary transmission gates in a bidirectional bus is equal to the bit width of the bidirectional bus.

[0012] In some embodiments, a routing unit connected to 5 bidirectional buses requires 25 clock cycles to write the signal; a routing unit connected to 4 bidirectional buses requires 16 clock cycles to write the signal; and a routing unit connected to 3 bidirectional buses requires 9 clock cycles to write the signal.

[0013] In some embodiments, the logic computation subarray includes a selector, with its two ends connected to the output and input ends of the logic computation subarray, respectively; the selector is used to transmit the output data of the logic computation subarray to the input end.

[0014] In some embodiments, the sum of the number of logical computing subarrays, in-memory computing subarrays, and cache subarrays is equal to the number of routing units.

[0015] A second aspect of this application proposes a residual network module that operates based on the on-chip routing-in-memory fusion architecture based on monolithic 3D integration in any of the above embodiments.

[0016] The technical effect of the residual network module in this application is similar to the technical effect of the on-chip routing storage-computing fusion architecture based on monolithic 3D integration mentioned above. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0018] Figure 1 A schematic diagram of an on-chip routing and in-memory computing fusion architecture based on monolithic 3D integration provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the connection between a routing unit and a functional layer provided in an embodiment of this application; Figure 3 This is a schematic diagram of the internal structure of a routing unit provided in an embodiment of this application; Figure 4 A schematic diagram of a complementary transmission gate in a routing unit provided in an embodiment of this application; Figure 5 A schematic diagram of a logic computing subarray provided in an embodiment of this application; Figure 6 A schematic diagram of a memory computing subarray provided in an embodiment of this application; Figure 7A schematic diagram illustrating a residual network module based on an on-chip routing-in-memory computing architecture, provided in an embodiment of this application; Figure 8 This is a flowchart illustrating the process of an on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration, as provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0021] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0022] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part. It can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0023] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0024] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0025] In-memory computing (IMC) is a novel architecture that integrates computing functionality into storage units at the device level, fundamentally reducing data storage and the repeated transfer of large amounts of data between computing modules during computation. Its core unit consists of circuit units with storage capabilities, such as resistive random access memory (RRAM) and static random access memory (SRAM). This patent uses RRAM as the IMC unit. A storage array composed of non-volatile RRAM with variable resistance can be used to perform matrix-vector multiplication calculations. According to Kirchhoff's laws, the data to be stored can be mapped to the resistance values ​​of each memory unit and written into the array. The input vector is mapped to the read voltage of each row of the array, and the output current of each column is the product of the input voltage and the conductance of the RRAM. Compared to the von Neumann architecture, IMC arrays offer advantages such as faster computation speed, lower power consumption, and higher integration density in matrix-vector multiplication tasks, and are currently widely used in large-scale neural network computing tasks.

[0026] Monolithic 3D integration technology is an emerging semiconductor manufacturing technology. In traditional manufacturing processes, modules such as CPUs, GPUs, and memory need to be manufactured, packaged, and then soldered onto a PCB board due to process incompatibility, relying on circuit leads on the PCB board for data exchange. However, with the rapid increase in data transmission volume, the high parasitic and low-density interconnects on the PCB board lead to inefficient communication, which can no longer meet the demands. This technology improves process compatibility, such as by adopting back-end process logic and memory technologies, to integrate multiple functional layers on a single chip. These functional layers can exchange data through high-density, low-parasitic interlayer vias, thereby greatly improving the efficiency of data exchange. Unlike the technical path of achieving 3D integration through advanced packaging, monolithic 3D integration technology refers to manufacturing each layer of devices sequentially from bottom to top on a single wafer. However, considering that current silicon-based CMOS transistors cannot withstand the high-temperature processes (such as ion implantation) in the manufacturing of upper-layer devices, a mainstream research path is the hybrid integration of "silicon-based bottom layer + non-silicon-based top layer". That is, a high-performance functional layer is prepared on the lower layer of the chip using mature silicon-based CMOS technology, and then thin-film transistors, such as carbon nanotube transistors, oxide semiconductor transistors, and two-dimensional material transistors, are manufactured on the upper layer of the wafer using low-temperature processes.

[0027] Regarding on-chip network architecture chips, some design approaches place the in-memory computing array on the first layer, and then manufacture routing units and cache arrays on the second layer of the chip, achieving staggered layer placement. This allows the PE (Processing Element) to be shared by multiple module computing units. However, this architecture lacks functional diversity, considering only the in-memory computing module and unable to perform operations beyond matrix-vector multiplication. Furthermore, this architecture design, with a single routing unit corresponding to four in-memory computing arrays and four cache arrays, suffers from insufficient inter-array communication resources, leading to data congestion during the transmission of computation results from multiple arrays.

[0028] Based on the above, such as Figure 1 As shown, the on-chip routing-in-memory computing converged architecture 1 based on monolithic 3D integration of this application includes a stacked functional layer 10 and a routing layer 20; the functional layer 10 and the routing layer 20 are electrically connected through inter-layer dielectric vias; the functional layer 10 includes functional circuits, including a logic computing array, an in-memory computing array, and a cache array; the routing layer 20 includes a routing array; the logic computing array 11 includes multiple logic computing sub-arrays 110; the in-memory computing array includes multiple in-memory computing sub-arrays 120; the cache array 13 includes multiple cache sub-arrays 130; the routing array 21 includes multiple routing units 210; in the first direction X and the second direction Y, adjacent routing units 210 are connected through a bidirectional bus 40; in the third direction Z, adjacent routing units 210 are connected to the logic computing sub-array 110 through a bidirectional bus 40; adjacent routing units 210 are connected to the in-memory computing sub-array 120 through a bidirectional bus 40; adjacent routing units 210 are connected to the cache sub-array 130 through a bidirectional bus 40.

[0029] In some embodiments, the sum of the number of logical computing subarrays 110, in-memory computing subarrays 120 and cache subarrays 130 is equal to the number of routing units 210.

[0030] Understandably, the bidirectional bus 40 above is used for bidirectional data transmission.

[0031] The on-chip routing-in-memory computing architecture 1 based on monolithic 3D integration provided in this application, by setting up a functional layer 10 and a routing layer 20, wherein the functional layer 10 includes a logic computing array, an in-memory computing array, and a cache array, these arrays and routing units 210 can be flexibly configured according to application scenarios to meet the computing needs of different scenarios, and have diversity. Furthermore, the routing layer 20 and the functional layer 10 are stacked, utilizing high-density inter-layer interconnects for communication between the routing network and functional modules, which not only reduces area but also increases chip computing power per unit area. In this application, the routing units in the routing layer 20 and the functional subarrays in the functional layer 10 are correspondingly connected, enabling maximum flexible access to on-chip computing and storage resources, achieving maximum chip reconfigurability.

[0032] In some embodiments, a routing unit connecting 5 bidirectional buses has 25 transmission gates and 25 registers; wherein one bidirectional bus corresponds to 5 transmission gates and 5 registers. A routing unit connecting 4 bidirectional buses has 16 transmission gates and 16 registers; wherein one bidirectional bus corresponds to 4 transmission gates and 4 registers. A routing unit connecting 3 bidirectional buses has 9 transmission gates and 9 registers; wherein one bidirectional bus corresponds to 3 transmission gates and 3 registers.

[0033] Depend on Figure 1 It can be seen that the inner ring routing unit 210 is connected to 5 bidirectional buses 40, and is connected to 4 routing units 210 and one functional subarray through the 5 bidirectional buses 40. The routing units 210 located on the four sides are connected to 4 bidirectional buses, and are connected to 3 routing units 210 and 1 functional subarray through the 4 bidirectional buses 40. The routing units 210 at the four corners are connected to 3 bidirectional buses, and are connected to 2 routing units 210 and one functional subarray through the 3 bidirectional buses 40.

[0034] like Figure 2 The diagram shows the structure of a routing unit 210 in routing layer 20. For example, this routing layer 20 contains 16 routing units, forming a 4x4 routing network. Adjacent routing units 210, and routing units 210 with their corresponding functional subarrays, are connected by a bidirectional bus 40. The bidirectional bus 40 can have a bit width of 64 bits, or 128 bits bidirectionally. The calculated data format is INT4 (4-bit integer), and each cycle of the bidirectional bus 40 can transmit 16 INT4 data points bidirectionally.

[0035] like Figure 3As shown, for the routing unit 210 that connects 5 bidirectional buses, 25 registers are connected in series. When the chip is powered on, it is initialized by inputting an address control signal with a length of 25 cycles and a unified clock signal. After 25 clock cycles, the serial address control signal is written into each register as the control signal for the corresponding transmission gate.

[0036] Similarly, in some embodiments, a routing unit connecting 5 bidirectional buses requires 25 clock cycles to write the signal. A routing unit connecting 4 bidirectional buses requires 16 clock cycles to write the signal. A routing unit connecting 3 bidirectional buses requires 9 clock cycles to write the signal.

[0037] In some embodiments, a bidirectional bus 40 is configured such that only one corresponding transmission gate is opened for each data transmission.

[0038] In some embodiments, there is a one-to-one correspondence between transmission gates and registers; the register is used to control the opening or closing of its corresponding transmission gate. The output of a register is connected to the control port of a transmission gate; when the output signal of the register is high, the corresponding transmission gate is turned on; when the output signal of the register is low, the corresponding transmission gate is turned off.

[0039] In some embodiments, a transmission gate is composed of multiple complementary transmission gates. A complementary transmission gate includes a P-type transistor and an N-type transistor with opposite control signals and their source and drain shorted, respectively. When the control signal input to the complementary transmission gate is high, the P-type transistor and the N-type transistor in the complementary transmission gate are turned on simultaneously, and the input data is transmitted out. When the control signal input to the complementary transmission gate is low, the P-type transistor and the N-type transistor in the complementary transmission gate are turned off simultaneously, and the input data is isolated.

[0040] It is understandable that, such as Figure 4 As shown, the complementary transmission gate is a CMOS complementary transmission gate. Each CMOS complementary transmission gate includes a P-type transistor and an N-type transistor with opposite control signals and their source and drain shorted, respectively. When the input control signal is high, each bit of input data is transmitted to the corresponding output data; when the input control signal is low, the input data and output data are isolated.

[0041] In some embodiments, the number of complementary transmission gates in a bidirectional bus 40 is equal to the bit width of the bidirectional bus 40.

[0042] like Figure 5As shown, the logic computation subarray has two sets of bus data inputs. Under the control of the operation mode signal, it can perform one of the following basic operations: ① Addition: Add the two sets of bus data separately and output one set of bus data; ② Neural Network Activation Function (ReLU): Input one set of bus data. If each data is greater than 0, the corresponding bit is directly output as the original data. If the data is less than or equal to 0, the corresponding bit is output as 0; ③ Shift: Input one set of bus data, shift each INT4 data to the left by one bit (equivalent to *2) and output; ④ Vector Multiplication: Multiply the two sets of bus data separately and output one set of bus data.

[0043] In some embodiments, the logic computing subarray 110 includes a selector, with its two ends connected to the output and input ends of the logic computing subarray, respectively; the selector is used to transmit the output data of the logic computing subarray to the input end.

[0044] It is understandable that, in the above embodiments, in order to meet the need for continuous multi-round calculations in actual calculations (such as performing *4 calculations, which requires two consecutive shift operations), the logic calculation subarray 110 is provided with an additional connection that directly connects the output data to the input terminal. The data can be controlled by the input terminal selector to come from the external input bus or the output data of the calculation array.

[0045] In some embodiments, the number of bits at the input and the number of bits at the output of the in-memory array are equal to the quotient of the bit width of the bidirectional bus 40 divided by the bit width of the data format in the bidirectional bus 40.

[0046] It is understandable that in-memory computing subarray structures, such as Figure 6 As shown, each resistive random access memory (RRAM) cell in this array stores one weight data. With a 64-bit width on the bidirectional bus 40 and an INT4 data format, both the input and output signals of the in-memory computing array are 16 bits, and the weight matrix stored in the RRAM cell is 16*16=256. The 64-bit bus input data is connected to the 16-bit input terminals of the RRAM array via 16 sets of 4-bit parallel-to-serial registers (converting the 64-bit cycle into 4-cycle 16-bit bits), inputting 16 4-bit input data bits over 4 cycles. Assuming each RRAM device can store one 3-bit weight, each cycle can perform a multiplication of one bit of input data with the matrix and output 16 bits of output data. The 16 output terminals shift and add the output data from the four cycles respectively to obtain a set of bus data output results, which are then connected to the output bus.

[0047] As for the memory array, as a basic static random access memory array, it can be controlled by address signals and enable signals. When the write enable signal is selected, the bus input data is temporarily stored at the given address; when the read enable signal is selected, the signal is read out to the bus. This array can temporarily store input data or output data generated by other computing modules for scenarios that require repeated data retrieval, such as residual block calculation, or for adjusting pipeline cycle time.

[0048] The chip architecture described above includes multiple computing modules and cache modules connected by a high-bandwidth routing network, which are suitable for completing complex computing tasks involving multiple computing modes. Furthermore, the collaborative work of multiple modules can bring high computing efficiency.

[0049] Another embodiment of this application provides a Resnet block (residual network module), which operates based on the on-chip routing, storage, and computing fusion architecture based on monolithic three-dimensional integration in any of the above embodiments.

[0050] Figure 7 This demonstrates the parallel computing process of the ResNet block. In this process, data is sequentially transmitted to different subarrays for computation, and two sets of different data can be computed in parallel across different subarrays. Furthermore, idle subarrays can continue to receive the next set of data, forming a pipelined computation. Since the data width of the bidirectional bus is the same as the input and output data width of the computation module, all data transmission tasks can be completed within one cycle, without consuming excessive time. Simultaneously, during pipeline operation, the routing network connections used for data transmission in each cycle are not duplicated, preventing data congestion.

[0051] Based on the above-mentioned on-chip routing, storage, and computing fusion architecture based on monolithic 3D integration, such as Figure 8As shown, this application also proposes a process for an on-chip routing-in-memory fusion architecture based on monolithic 3D integration. The functional layer includes silicon-based transistors and RRAM (Resistive Random-Access Memory) devices required for the in-memory computing array. First, silicon-based transistors are fabricated using standard Si-CMOS logic processes, leaving interconnect vias for the functional array to connect with the upper routing network during the fabrication process. Then, RRAM is fabricated using a low-temperature (<= 300°C) process. The fabrication of RRAM includes the following steps: (a) Depositing a 30 nm TiN (physical vapor deposition, lower electrode) / 8 nm HfAlOx (atomic layer deposition, resistive switching layer) / 45 nm TaOx (physical vapor deposition, thermal enhancement layer) / 30 nm TiN (physical vapor deposition, upper electrode) stack. (b) Using photolithography and dry etching processes, the TiN / HfAlOx / TaOx / TiN stack is selectively etched to realize the patterning of the resistive random-access memory. (c) Deposit a 400 nm SiO2 thin film (passivation layer) using plasma-enhanced chemical vapor deposition. (d) Etch the SiO2 thin film using photolithography and dry etching to form interconnect connection points. (e) Deposit a layer of W using electroplating, then use chemical mechanical polishing to clean the W except for the SiO2 holes. (Forming metal vias) (f) Deposit a 400 nm Al metal (metal interconnect) using physical vapor deposition. (g) Selectively etch Al using photolithography and dry etching to form Al metal interconnects. (h) Deposit a 100 nm SiO2 / 900 nm Si3N4 thin film (passivation layer) using plasma-enhanced chemical vapor deposition. (i) Selectively etch the SiO2 / Si3N4 thin film using photolithography and dry etching to form openings.

[0052] The second-layer routing network consists of carbon nanotube transistors (CNTFETs) and interconnects between devices. The fabrication steps are as follows: (a) 40 nm Au is deposited using photolithography and electron beam evaporation, and then patterned by lift-off to form the back gate of the carbon nanotube transistor. (b) 3 nm AlO and 8 nm HfO2 are grown using atomic layer deposition, and etched using photolithography and wet etching to form the gate oxide layer structure. (c) A layer of carbon nanotubes is deposited using wet transfer, and the channel region is defined using O2 plasma to form the channel of the carbon nanotube transistor. (d) 40 nm Pd is deposited using photolithography and electron beam evaporation, and then patterned by lift-off to form the source and drain electrodes of the carbon nanotube transistor. (e) 7 nm HfO2 and 11 nm ALN are grown by atomic layer deposition to form doping of the channel, fabricating CNT-NMOS. (f) The HfO2 and ALN on the PMOS structure are removed, and 2 nm Y2O3 is grown by electron beam evaporation, and 11 nm HfO2 is grown by atomic layer deposition as a passivation layer.

[0053] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A single-chip on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration, characterized in that, The on-chip routing-in-memory computing converged architecture includes a stacked functional layer and a routing layer; the functional layer and the routing layer are electrically connected through inter-layer dielectric vias. The functional layer includes functional circuits, which include a logic computing array, an in-memory computing array, and a cache array. The routing layer includes a routing array; The logical computing array includes multiple logical computing subarrays; the in-memory computing array includes multiple in-memory computing subarrays; the cache array includes multiple cache subarrays; The routing array includes multiple routing units; In both the first and second directions, adjacent routing units are connected via a bidirectional bus. In the third direction, adjacent routing units are connected to the logical computing subarray via a bidirectional bus; adjacent routing units are connected to the in-memory computing subarray via a bidirectional bus; and adjacent routing units are connected to the cache subarray via a bidirectional bus.

2. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 1, characterized in that, A routing unit connecting 5 bidirectional buses has 25 transmission gates and 25 registers; one bidirectional bus corresponds to 5 transmission gates and 5 registers. A routing unit connecting four bidirectional buses has 16 transmission gates and 16 registers; one bidirectional bus corresponds to four transmission gates and four registers. A routing unit connecting three bidirectional buses has nine transmission gates and nine registers; one bidirectional bus corresponds to three transmission gates and three registers.

3. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 2, characterized in that, A bidirectional bus is configured such that only one corresponding transmission gate opens for each data transmission.

4. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 2, characterized in that, The transmission gate and the register are in one-to-one correspondence; the register is used to control the opening or closing of the corresponding transmission gate.

5. The on-chip routing-in-memory fusion architecture based on monolithic 3D integration according to claim 4, characterized in that, The output of a register is connected to the control port of a transmission gate; when the output signal of the register is high, the corresponding transmission gate is turned on; when the output signal of the register is low, the corresponding transmission gate is turned off.

6. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 5, characterized in that, A transmission gate is composed of multiple complementary transmission gates. A complementary transmission gate includes a P-type transistor and an N-type transistor with opposite control signals and their source and drain shorted respectively. When the control signal input to the complementary transmission gate is high, the P-type transistor and the N-type transistor in the complementary transmission gate are turned on simultaneously, and the input data is transmitted out. When the control signal input to the complementary transmission gate is low, the P-type transistor and N-type transistor in the complementary transmission gate are turned off simultaneously, thus isolating the input data.

7. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 6, characterized in that, The number of complementary transmission gates in a bidirectional bus is equal to the bit width of the bidirectional bus.

8. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 2, characterized in that, For a routing unit that connects 5 bidirectional buses, 25 clock cycles are required to write the signal; For a routing unit that connects four bidirectional buses, it takes 16 clock cycles to write the signal. For a routing unit that connects three bidirectional buses, it takes nine clock cycles to write the signal.

9. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 1, characterized in that, The logic computation subarray includes a selector, with its two ends connected to the output and input terminals of the logic computation subarray, respectively; the selector is used to transmit the output data of the logic computation subarray to the input terminal.

10. The on-chip routing-in-memory computing fusion architecture based on monolithic 3D integration according to claim 1, characterized in that, The sum of the number of the logical computing subarray, the in-memory computing subarray, and the cache subarray is equal to the number of the routing units.

11. A residual network module, characterized in that, The residual network module operates based on the on-chip routing, storage, and computing fusion architecture based on monolithic three-dimensional integration as described in any one of claims 1-10.

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