Link training method, kernel and computing system

Abstract

Embodiments of the present disclosure provide a link training method, a corelet and a computing system, and relate to the technical field of chips. The link training method is applied to an arbitrator of a corelet, the corelet further includes a plurality of modules, the module includes a main band channel and a side band channel based on a general corelet interconnection standard, and is used for interconnection with a corresponding module of another corelet. The arbitrator is used for link training management of the plurality of modules. The method comprises: determining whether the modules meet a preset initialization condition according to a first signal received from each module; in the case that the plurality of modules of the corelet meet the preset initialization condition, outputting a second signal to each module, and controlling each module to perform side band initialization in parallel based on a time division multiplexing mode; determining whether the modules complete the side band initialization according to a third signal output by each module; and in the case that the plurality of modules complete the side band initialization, controlling each module to perform main band initialization and a main band training task, thereby reducing multi-module link training delay.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more specifically, to a link training method, a chip, and a computing system. Background Technology

[0002] Universal Chiplet Interconnect Express (UCIe) is an open and unified interconnect protocol for chips, enabling high-bandwidth, low-latency interconnect communication between chips manufactured by different companies and using different processes within the same package. This improves system performance and reduces power consumption and cost. A chip can also be called a die.

[0003] The UCIe protocol is a layered protocol, which can be divided into a protocol layer, an adapter layer, and a physical layer. The physical layer implements functions such as signal transmission, link training, clock distribution, and power management. One or more modules can be deployed in the physical layer of a core. A module is a physically independent, fully functional UCIe interface unit that can contain a complete set of data lanes, sideband lanes, clock, and power, capable of independently running a complete UCIe protocol stack (from the physical layer to the adapter layer) to establish and maintain a complete core-to-core D2D link.

[0004] In related technologies, during the multi-module link training of the UCIe protocol, each module needs to complete the link initialization and training sequentially, resulting in a large total delay in multi-module link training, which affects the startup delay of the computing system composed of multiple chips. Summary of the Invention

[0005] One objective of this disclosure is to provide a new technical solution for link training.

[0006] According to a first aspect of the present disclosure, a link training method is provided, applied to an arbitrator of a chip, wherein the chip further includes multiple modules, each module including a main band channel and a sideband channel based on a common chip interconnection standard, for interconnecting with corresponding modules of other chips, and the arbitrator is used for link training management of the multiple modules; the method includes:

[0007] Determine whether the module meets the preset initialization conditions based on the first signal received from each module;

[0008] When multiple modules of the core meet the preset initialization conditions, a second signal is output to each module to control each module to perform sideband initialization in parallel based on time-division multiplexing mode;

[0009] The third signal output by each module determines whether the module has completed sideband initialization;

[0010] After the multiple modules have completed sideband initialization, each module is controlled to perform mainband initialization and mainband training tasks in order to carry out link training based on multiple modules.

[0011] Optionally, the channel resources of the sideband channel are configured as multiple frames in a time-division multiplexing mode, with each frame period including multiple time slot resources; the control modules perform sideband initialization in parallel based on the time-division multiplexing mode, including:

[0012] Each module is allocated a first time slot resource that is authorized for use in each frame period, so that each module sends a sideband initialization message corresponding to the sideband initialization based on its respective authorized first time slot resource;

[0013] Different modules are authorized to use different first time slot resources, while the same module is authorized to use the same first time slot resources in different frame periods.

[0014] Optionally, allocating the first time slot resources authorized for use by each module in each frame period includes: obtaining a static time slot mapping table, wherein the static time slot mapping table is a mapping table pre-generated during the power-on initialization process of the chip based on the number of modules and the frame period of the chip, and is used to characterize the static time slot resources corresponding to each module in each frame period; and according to the static time slot mapping table, using the static time slot resources corresponding to each module in each frame period as the first time slot resources of the module.

[0015] Optionally, the main band initialization process includes a first stage of main band initialization and / or a second stage of main band initialization, wherein the first stage of main band initialization is used for parameter exchange, and the second stage of main band initialization is used for calibration and / or clock repair; the arbitrator controls each module to perform main band initialization, including:

[0016] In the first stage of main band initialization, based on the time slot resource request signals of each module, a second time slot resource is dynamically allocated to each module from multiple time slot resources of the sideband channel, so that each module sends a first-stage message corresponding to the first stage of main band initialization based on the second time slot resource; or,

[0017] In the second phase of main band initialization, each module is allocated a third time slot resource authorized for use in each frame period according to the static time slot mapping table, so that each module sends a second phase message corresponding to the second phase of main band initialization based on its authorized third time slot resource.

[0018] Optionally, based on the time slot resource request signals of each module, a second time slot resource is dynamically allocated to each module from multiple time slot resources of the sideband channel, including: when receiving time slot resource request signals from multiple modules, determining the priority of each module; determining the first module with the highest priority from the multiple modules, and allocating the second time slot resource to the first module; when it is determined that the first module has completed the first stage message transmission, reclaiming the second time slot resource allocated to the first module for reallocation.

[0019] Optionally, the link training method is executed based on a physical layer link state machine, which includes a sideband parallel initialization state, a main band initialization state, and a main band training state. The sideband parallel initialization state is the state that multiple modules of the core enter after satisfying the preset initialization conditions. The main band initialization state is the state that multiple modules of the core enter after completing the sideband initialization. The main band training state is the state that multiple modules of the core enter after completing the main band initialization.

[0020] Optionally, the physical layer link state machine further includes a reset state and a sideband initialization state; wherein:

[0021] The reset state is the state that the multiple modules of the core chip enter after being powered on;

[0022] The sideband initialization state is the state that the module enters after the phase-locked loop stabilizes;

[0023] After the module is in the sideband initialization state and meets the preset initialization conditions, it sends the first signal to the arbiter so that the arbiter controls each module to enter the sideband parallel initialization state.

[0024] Optionally, the chip also includes a module timer corresponding to each of the modules; the module timer starts when the module enters the sideband parallel initialization state, stops when the module completes link training, and sends a first timeout signal to the arbitrator if the sideband initialization is not completed within a first preset time.

[0025] The method further includes:

[0026] Upon receiving the first timeout signal corresponding to any module, determine the number of times the module enters the sideband parallel initialization state;

[0027] If the number of times is less than or equal to the preset number of times, the module is controlled to re-enter the sideband parallel initialization state to perform sideband initialization;

[0028] If the number of attempts exceeds a preset number, then multiple modules of the chip are controlled to enter a training error state.

[0029] Optionally, the chip further includes a global timer; the global timer starts when the arbiter outputs a second signal to each module, stops when each module of the chip completes link training, and sends a second timeout signal to the arbiter if the sideband initialization of each module is not completed within a second preset time; the method further includes:

[0030] If it is determined that the multiple modules have completed sideband initialization before the global timer expires, then the multiple modules of the chip are controlled to enter the main band initialization state; or,

[0031] If the second timeout signal is received before the multiple modules complete sideband initialization, the multiple modules of the chip are controlled to enter the training error state.

[0032] Optionally, the first signal includes a power supply status signal and a clock status signal; the preset initialization conditions include:

[0033] Based on the power supply status signal, it is determined that the power supply status of the module is normal; and

[0034] The clock status of the module is determined to be normal based on the clock status signal. The clock of the module includes at least one of the sideband clock, the mainband clock, or the adapter clock.

[0035] According to a second aspect of the present disclosure, a chip is provided, the arbitrator of which can be configured to perform the method described in the first aspect.

[0036] According to a third aspect of the present disclosure, a computing system is provided that may include a plurality of cores, which may be the cores described in the second aspect of the present disclosure.

[0037] Based on the link training method provided in this disclosure, parallel link training of multiple modules can be realized. Compared with serial training, the total link training latency can be greatly reduced. Furthermore, the time-division multiplexing mechanism not only avoids state machine conflicts but also improves the utilization rate of sideband channel bandwidth, thus significantly improving the system resource utilization rate.

[0038] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0040] Figure 1 This is a schematic diagram of the structure of a computing system provided in an embodiment of this disclosure.

[0041] Figure 2 This is a schematic diagram of a physical layer link state machine provided in an embodiment of this disclosure.

[0042] Figure 3 This is a flowchart illustrating a link training method provided in an embodiment of this disclosure.

[0043] Figure 4 This is a schematic diagram of another physical layer link state machine provided in an embodiment of this disclosure.

[0044] Figure 5 This is a schematic diagram of a timeout control mechanism provided in an embodiment of this disclosure. Detailed Implementation

[0045] Various exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit this disclosure or its application or use. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus may be considered part of the specification.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items, so once an item is defined in one figure, it need not be discussed further in subsequent figures.

[0048] This disclosure relates to a technical solution for link training. Figure 1 This is a schematic diagram of the structure of a computing system that can apply the technical solutions provided in the embodiments of this disclosure. For example... Figure 1 As shown, the computing system 1000 may include multiple cores, for example... Figure 1 The first core 1100 and the second core 1200, or other cores, are shown.

[0049] The various chips in this computing system can be interconnected using the UCIe protocol, a layered protocol that can be divided into a protocol layer, an adapter layer, and a physical layer. The protocol layer and the adapter layer communicate via a Frame-Aware Die-to-Die Interface (FDI), while the adapter layer and the physical layer communicate via a Raw Die-to-Die Interface (RDI). The protocol layer can interconnect with the on-chip network within the chip via dedicated bridging logic. The protocol layer acts as a translator, converting and encapsulating information from the on-chip network into UCIe standard transaction packets, and converting and encapsulating UCIe transaction packets into data packet formats that the on-chip network can recognize and route. The adapter layer acts as a scheduler, performing flow control, sequencing, and multiplexing of transactions from the protocol layer, breaking them down into smaller, more regular data units (Flits) for transmission over the physical link. The physical layer can act as a courier, performing the lowest-level electrical or optical signal transmission, efficiently and reliably transmitting data units to other cores through actual physical connections (such as microbumps), thereby realizing interconnection and communication between cores.

[0050] Continue as Figure 1 As shown, the core in this embodiment may include an arbitrator and one or more modules. For example, the first core 1100 may include an arbitrator and modules 11 to 14, and the second core 1200 may include an arbitrator and modules 21 to 24. The arbitrator is connected to each module in the core and can be used to coordinate and manage multiple modules, such as for link training management or coordination of multiple modules, including triggering link training and monitoring training status.

[0051] Any chip in a computing system can be interconnected with corresponding modules of other chips through one or more modules, such as UCIe-based interconnects. Figure 1The first and second cores shown can be interconnected according to the UCIe standard based on four modules: module 11 is connected to module 21, module 12 is connected to module 22, module 13 is connected to module 23, and module 14 is connected to module 24. That is, modules 21 to 24 are the corresponding modules of modules 11 to 14. Interconnecting multiple modules can improve the bandwidth between cores and achieve high-bandwidth, low-latency core interconnect communication. For example, each module of the core can include a mainband channel and a sideband channel. The mainband channel can be used for high-speed data transmission and can also be called a data transmission channel, data transmission interface, or mainband channel. The sideband channel can be used for link management and state negotiation and can also be called a link management channel, link management interface, or sideband channel. For example, the sideband channel can operate at a fixed frequency of 800MHz.

[0052] For example, the aforementioned arbitrator and module can be used to implement the functions of the physical layer, that is, to deploy the aforementioned arbitrator and module at the physical layer of the chip. This module can be a physically independent and fully functional UCIe interface unit, which can contain a complete set of main band channels, sideband channels, clock, and power supply, and can independently run a complete UCIe protocol stack (from the physical layer to the adaptation layer) to establish and maintain a complete chip-to-chip D2D link. In this way, the physical layer can realize functions such as signal transmission, link training, clock distribution, or power management.

[0053] The cores in this computing system can be one or more of computing cores, storage cores, or input / output interface cores. For example, the computing core may include multiple streaming processor clusters (SPCs), and the SPC may include multiple computing cores (e.g., GPU Cores). The storage core may include high-bandwidth memory (HBM) or other memory devices. The computing system can implement functions related to artificial intelligence (AI), scientific computing, or image processing based on one or more cores. The computing system in this embodiment may also be referred to as a system-on-a-chip (SoC), a chip, an artificial intelligence chip, or a computing device, etc.

[0054] It should be noted that, Figure 1The structure of the computing system shown is illustrative. The computing system in this embodiment is not limited to the above structure and may include more or fewer devices as needed, and the devices may be combined or split. For example, the computing system may also include more chips, and each chip may include more or fewer modules, such as one module, two modules, or eight modules. Exemplarily, the computing system may also include other devices such as control devices and display devices.

[0055] The UCIe protocol can employ a layered link state machine (LSM) for link training, consisting of three layers: the FDI state machine between the protocol layer and the adaptation layer, the RDI state machine between the adaptation layer and the physical layer, and the physical layer link state machine (PHY LSM). The physical layer link state machine can be used to manage the link training process.

[0056] Figure 2 This is a schematic diagram of a physical layer link state machine as shown in an embodiment of this disclosure. Figure 2 As shown, the link training process based on the physical layer link state machine can be sequentially divided into: Reset state → Sideband initialization state (SBINIT) → Mainband initialization state (MBINIT) → Mainband training state (MBTRAIN) → Link initialization state (LINKINIT) → Activate state (ACTIVE). Furthermore, if a link quality degradation or other reasons requiring retraining are detected in the Activate state, it can enter the Physical Layer Retraining state (PHYRETRAIN). If an anomaly occurs in any state, it can also enter the Training Error state (TRAINERROR) and then re-enter the Reset state. In the Activate state, the system also supports a low-power management mechanism. When the system needs to reduce power consumption, it can enter Link State 1 (L1) or Link State 2 (L2). L1 is a mild low-power state, entered autonomously by the physical layer. The sideband and mainband clocks remain running, and the data path logic is kept powered, with an exit latency of less than 1 microsecond. L2 is a deep low-power state, entered through coordination between the protocol and physical layers. The sideband clock remains running while the mainband clock and most data path logic are powered down, with an exit latency of less than 4 microseconds. The entry and exit of low-power states are controlled by the system's power management strategy, with state negotiation conducted through the sideband channel. Physical layer link training can be triggered from either L1 or L2. For example, L1 can trigger link training starting from the mainband training state, while L2 can trigger link training starting from the reset state.

[0057] In related technologies, the physical layer of a single core can include multiple modules. In the multi-module link training of the UCIe protocol, each module needs to complete link initialization and training sequentially. This results in a linear relationship between the total link training latency and the number of modules. For example, if the training latency of a single module is 20 milliseconds, the total latency of four modules may reach 80 milliseconds. This leads to a large total latency in multi-module link training, affecting the startup latency of the computing system composed of multiple cores. Furthermore, in a multi-module configuration, all modules share the same set of RDI and RDI LSM, requiring serial processing of training requests between modules; otherwise, state machine scheduling conflicts may occur. Therefore, a technical solution to reduce the latency of multi-module link training is urgently needed.

[0058] To address the problems in related technologies, this disclosure provides embodiments such as Figure 3 The link training method shown is applicable to, for example, […]. Figure 1 The computing system shown illustrates an arbiter within a core. This core may include the arbiter and multiple modules. Each module may include a main band channel and sideband channels based on a common core interconnect standard for interconnection with corresponding modules of other cores. For example, the module correspondence between this core and other cores can be pre-defined, such as by setting... Figure 1 The diagram illustrates a one-to-one interconnection of modules. This arbitrator can be used for link training management of multiple modules. For example, this method can be executed by the arbitrator within the core, or by the arbitrator within the core in conjunction with various modules. The arbitrator can be a multi-module physical layer logic arbitrator (MMPL). Figure 3 As shown, the link training method in this embodiment may include the following steps S310 to S340.

[0059] Step S310: Determine whether the module meets the preset initialization conditions based on the first signal received from each module.

[0060] In some examples, the first signal may include a power supply status signal and a clock status signal. The clock status signal may include at least one of a sideband clock signal, a mainband clock signal, or an adapter clock signal. For example, the power management module within each module and the phase-locked loop (PLL) may output a power supply status signal and a clock signal, which are connected to the input port of the arbitrator.

[0061] The power supply status signal (pwr_good_x) can indicate whether the power supply status of the xth module is normal. For example, when the module's power supply voltage is stable within the rated range, this signal is at a high level.

[0062] The sideband clock status signal (sb_clk_lock_x) can indicate whether the sideband clock (800MHz) of the xth module is stable and available. For example, this signal is high when the sideband clock phase-locked loop is locked and the output clock frequency is stable.

[0063] The master clock status signal (mb_clk_lock_x) indicates whether the master clock of the xth module is stable and available. For example, when the master clock phase-locked loop is locked and the output clock frequency is stable, this signal is high.

[0064] The adapter clock status signal (d2d_clk_lock_x) can indicate whether the die-to-die (D2D) adapter clock of the xth module is stable and available. For example, this signal is high when the adapter clock PLL is locked and the output clock frequency is stable.

[0065] The aforementioned preset initialization conditions may include: determining that the power supply status of the module is normal based on the power supply status signal; and determining that the clock status of the module is normal based on the clock status signal. The clock of this module may include at least one of a sideband clock, a mainband clock, or an adapter clock.

[0066] For example, the arbitrator can perform an AND operation on the aforementioned status signals (e.g., power status signals and clock status information) of each module to generate a module ready signal (module_ready_x), indicating whether the module meets the power supply and clock stability conditions. The specific logical operation could be: module_ready_x = pwr_good_x AND sb_clk_lock_x AND mb_clk_lock_x AND d2d_clk_lock_x.

[0067] Subsequently, the arbitrator can perform a global AND operation on the `module_ready_x` signals of all modules to generate a global ready signal (`all_modules_ready`). The specific logical operation can be: `all_modules_ready = module_ready_0 AND module_ready_1 AND ... AND module_ready_n`, where `n` is the total number of modules within the core. When the `all_modules_ready` signal is high, it indicates that all modules meet the aforementioned preset initialization conditions.

[0068] In some examples, after the computing system chip is powered on or reset, all modules can enter a reset state (RESET) and wait for the phase-locked loop (PLL) to stabilize (e.g., at least 4ms). Once the PLL is stable, the modules enter a sideband initialization state (SBINIT), in which the individual clock signals of the modules gradually stabilize. When a module is in the sideband initialization state and meets the preset initialization conditions, the module sends a first signal to the arbitrator, enabling the arbitrator to determine whether all modules have met the initialization conditions.

[0069] Step S320: When multiple modules of the chip meet the preset initialization conditions, a second signal is output to each module to control each module to perform sideband initialization in parallel based on time-division multiplexing mode.

[0070] For example, when the arbiter determines, based on the first signal of each module, that all modules in the core meet the aforementioned preset initialization conditions (e.g., the all_modules_ready signal is high), it can trigger the physical layer link state machine (PHY LSM) to output a second signal (e.g., sbinit_parallel_trigger) to each module. This second signal controls all modules to synchronously enter the sideband parallel initialization state (SBINIT_PARALLEL). This second signal can be a global trigger signal, simultaneously sent to all modules within the core, indicating that each module can begin parallel execution of the sideband initialization process.

[0071] In some examples, each module can receive a second signal and first perform clock training in parallel, and then perform sideband initialization in parallel based on time-division multiplexing mode.

[0072] For example, the parallel clock training of each module can include: each module simultaneously transmitting a clock training sequence (Clock Pattern) on both the sideband clock line (SB Clock) and the data lane. The format of this clock training sequence can be 64 unit intervals (UI) of high-level clock signals + 32 unit intervals of low-level signals, i.e., 64 UI Clock + 32 UI Low. This training sequence can be used by the receiver to detect and synchronize clock signals.

[0073] It should be noted that the clock training sequence transmitted on the sideband clock line and the data channel can be identical. During the sideband initialization phase, the receiving end needs to detect consistent clock training sequences on both physical lines simultaneously to ensure reliable clock synchronization. After detecting two consecutive clock training sequences, the receiving end can confirm successful clock synchronization and send a link establishment confirmation message (e.g., SBINIT Out of Reset).

[0074] During the parallel execution of sideband initialization, each module can send sideband initialization messages based on Time Division Multiplexing (TDM) mode to avoid message collisions. For example, the channel resources of a sideband channel can be configured as multiple frames in a time-division multiplexing manner, with each frame period including multiple time slot resources. For instance, a frame period can be 125 microseconds (corresponding to 8000 frames / second), dividing each frame period into 32 time slots, each time slot approximately 3.9μs (125μs ÷ 32 ≈ 3.9μs), thereby achieving efficient time-division multiplexing of the sideband channel. The channel resources of this sideband channel can also be referred to as sideband channel resources.

[0075] The arbitrator can control the parallel execution of sideband initialization by various modules based on time-division multiplexing mode, which may include: allocating a first time slot resource authorized for use by each module in each frame period, so that each module sends a sideband initialization message corresponding to the sideband initialization based on its respective authorized first time slot resource. For example, different modules may be authorized to use different first time slot resources, and the same module may be authorized to use the same first time slot resource in different frame periods. The sideband initialization message may include a sideband initialization completion request message (SBINIT done req) and / or a sideband initialization completion response message (SBINIT done resp).

[0076] For example, during the sideband parallel initialization phase (SBINIT_PARALLEL), the arbiter can allocate a fixed time slot for each module to send the sideband initialization message. For instance, all time slots in each frame period can be evenly distributed among the modules. Assuming the core contains four modules (modules 11 to 14) and eight time slots in each frame period (time slots 1 to 8), the time slot allocation could include: allocating time slots 1 and 5 to module 11, time slots 2 and 6 to module 12, time slots 3 and 7 to module 13, and time slots 4 and 8 to module 14.

[0077] In this way, during parallel training, the four modules of the chip can simultaneously send clock training sequences (ClockPattern) and send sideband initial messages in their respective allocated time slots. This time-division multiplexing method can avoid message collisions. For example, module 1 sends sideband initial messages in time slot 1 and / or time slot 5, module 2 sends sideband initial messages in time slot 2 and / or time slot 6, and so on.

[0078] It should be noted that in a multi-module configuration, all modules of the core can share the same set of RDI and RDI LSM. In this way, the link training through the time-division multiplexing method in this embodiment can enable the RDI to process the training requests or data of different modules in a time-division manner, thereby avoiding RDI state machine scheduling conflicts and improving the reliability of sideband initialization and link training.

[0079] Step S330: Determine whether the module has completed sideband initialization based on the third signal output by each module.

[0080] For example, this third signal can be a signal output to the arbiter by each module after completing sideband initialization. For instance, after completing sideband initialization (e.g., completing the interaction between the sideband initialization completion request message and the sideband initialization completion response message), each module can generate this third signal and report it to the arbiter via a dedicated hardware signal line. This third signal can also be called the sideband initialization completion signal (sbinit_done_x).

[0081] The arbiter can monitor the third signals of each module to determine whether each module has completed sideband initialization. Specifically, the arbiter performs a global AND operation on the third signals of all modules to generate a global completion flag (e.g., sbinit_global_done). When the global completion flag is high, it indicates that all modules have completed sideband initialization.

[0082] It should be noted that the arbitrator obtains the third signals from each module through dedicated hardware signal lines, eliminating the need for transmission via sideband channels. Therefore, it is not limited by time-division multiplexing time slot allocation and can monitor the training status of each module in real time. This hardware signal mechanism ensures that the arbitrator can quickly and accurately determine the training completion status of all modules.

[0083] Step S340: After multiple modules have completed sideband initialization, control each module to perform mainband initialization and mainband training tasks to carry out link training based on multiple modules.

[0084] For example, after all modules have completed sideband initialization, the arbiter can control multiple modules to uniformly enter the main band initialization state (MBINIT) through a global completion flag (e.g., sbinit_global_done). The main band initialization process can include a first stage and a second stage. For example, the first stage can include MBINIT stage 1, such as parameter exchange (PARAM); the second stage can include MBINIT stage 2 and stage 3, such as calibration (CAL) and clock repair (REPAIRCLK), respectively. For example, the main band initialization process can also include other stages, such as the valid signal channel repair stage (REPAIRVAL), the channel inversion detection and negotiation stage (REVERSALMB), and the data channel repair stage (REPAIRMB).

[0085] In the first stage of mainband initialization (e.g., the parameter exchange stage), each module can exchange link parameter information, such as link width and speed. This stage can adopt a dynamic time slot allocation mechanism. Each module can send a time slot resource request signal (e.g., req_x) to the arbitrator according to the parameter exchange requirements. The arbitrator can authorize time slots in real time based on the request status, module priority, and time slot availability. Only authorized modules can send messages in the corresponding time slots to avoid message conflicts.

[0086] During the second phase of mainband initialization (e.g., calibration and clock repair), the system as a whole can still execute in phase sequence, and all modules can enter the same phase synchronously. Within the same phase, each module can independently and in parallel perform calibration operations. Only when reporting calibration status and interactive control information through the sideband channel can they send messages in time-division multiplexing-allocated independent time slots to avoid message conflicts. This phase can adopt a static time slot allocation mechanism, allocating fixed time slots to each module according to a static time slot mapping table.

[0087] Once all modules have completed mainband initialization, the arbiter can control each module to enter the mainband training state (MBTRAIN) and execute the mainband training task. After mainband training is completed, the modules can sequentially enter the link initialization state (LINKINIT) and the activation state (ACTIVE) to begin normal data transmission.

[0088] By using the methods described in steps S310 to S340, parallel link training of multiple modules can be achieved. Compared with serial training, the total link training latency can be greatly reduced. Furthermore, the time-division multiplexing mechanism not only avoids state machine conflicts but also improves the utilization rate of sideband channel bandwidth (in actual tests, it can be improved from 50% to over 90%), significantly improving the system resource utilization rate.

[0089] In some embodiments of this disclosure, the chip can be configured with a static time slot mapping table, which can be used to characterize the static time slot resources (e.g., fixed time slot numbers) corresponding to each module in each frame period. This static time slot mapping table can be a mapping table pre-generated during the chip's power-on initialization process based on the number of modules and the frame period. The arbitrator can obtain this static time slot mapping table. A specific implementation of allocating the first time slot resource authorized for use in each frame period for each module can include: using the static time slot resource corresponding to each module in each frame period as the first time slot resource of that module, according to the static time slot mapping table.

[0090] In some examples, the static time slot mapping table (e.g., slot_map[x]) can be pre-configured based on the number of modules and topology of the chip during power-on initialization and remains fixed during chip operation. It is used to identify the fixed time slot number corresponding to each module in time-division multiplexing mode. For example, the static time slot mapping table can be generated by: assigning a time slot number to each module based on the total number of modules n within the chip and the total number of time slots S in each frame period, and generating the static time slot mapping table based on the assigned time slot number.

[0091] For example, the static time slot mapping table can be stored in the chip and accessed by the arbitrator, for example, it can be stored in a configuration register that can be accessed by the arbitrator.

[0092] In this example, time slot numbers can be assigned to each module on an average basis. For instance, the total number of time slots S can be rounded down from the total number of modules n to obtain the number of time slots allocated to each module. Based on this number of time slots, consecutive time slots can be allocated to each module, or time slots can be allocated to each module at intervals.

[0093] Taking a scenario where the total number of modules n=4, the total number of time slots S=16, and the time slot numbers can be from 1 to 16, and the module numbers can be from 1 to 4, the continuous allocation method can be: module 1 is allocated time slot numbers 1-4, module 2 is allocated time slot numbers 5-8, module 3 is allocated time slot numbers 9-12, and module 4 is allocated time slot numbers 13-16. The time slot allocation method for each module with intervals can be: module 1 is allocated time slot numbers 1 / 5 / 9 / 13, module 2 is allocated time slot numbers 2 / 6 / 10 / 14, module 3 is allocated time slot numbers 3 / 7 / 11 / 15, and module 4 is allocated time slot numbers 4 / 8 / 12 / 16; another possible method is: module 1 is allocated time slot numbers 1 / 2 / 9 / 10, module 2 is allocated time slot numbers 3 / 4 / 11 / 12, module 3 is allocated time slot numbers 5 / 6 / 13 / 14, and module 4 is allocated time slot numbers 7 / 8 / 15 / 16.

[0094] During the sideband parallel initialization phase (SBINIT_PARALLEL), the arbiter can allocate fixed time slots to each module according to the static time slot mapping table. The time slot counter (current_slot) can be automatically incremented. When current_slot matches slot_map[x], the arbiter can authorize the module with the same number to send a grant signal (grant_x), enabling it to send sideband messages in the corresponding time slot.

[0095] In this way, for the periodic data transmission during the sideband initialization phase, fixed time slots are allocated to each module through a static time slot mapping table, and time-division multiplexing can be achieved without competing for time slot resources. Only the mapping table needs to be pre-configured, and no dynamic adjustment is required during operation. This can not only adapt to the data transmission characteristics of this phase, but also improve the utilization rate of sideband channels and the efficiency of sideband initialization through time-division multiplexing, thereby improving the reliability and efficiency of link training.

[0096] In some embodiments of this disclosure, the main band initialization process may include a first stage of main band initialization and / or a second stage of main band initialization. The first stage of main band initialization may be used for parameter exchange, and the second stage of main band initialization may be used for calibration and / or clock repair. The method by which the arbitrator controls each module to perform main band initialization may differ at different stages.

[0097] In some examples, during the first phase of main band initialization, based on the time slot resource request signals of each module, a second time slot resource is dynamically allocated to each module from multiple time slot resources of the sideband channel, so that each module can send a first-phase message corresponding to the first phase of main band initialization based on the second time slot resource.

[0098] The first stage of mainband initialization can be called MBINIT stage 1 or PARAM parameter exchange stage. During this stage, modules can exchange link parameter information, such as link width, speed, and power consumption mode. Since parameter exchange is a bursty service, the parameter exchange requirements of each module are not fixed; therefore, a dynamic time slot allocation mechanism can be adopted.

[0099] Each module can independently initiate a time slot resource request signal (e.g., req_x) based on business needs. The arbitrator can iterate through and compare the priorities of each requesting module in real time (e.g., priority_x), and select the module with the highest priority to set a permission signal (e.g., grant_x) to authorize transmission. After the authorized module completes message transmission, it can revoke req_x, and the arbitrator can re-determine in the next time slot, realizing dynamic on-demand allocation of time slot resources.

[0100] For example, dynamically allocating second time slot resources to each module from multiple time slot resources of the sideband channel based on the time slot resource request signals of each module may include: determining the priority of each module when receiving time slot resource request signals from multiple modules; determining the first module with the highest priority from the multiple modules, and allocating second time slot resources to the first module.

[0101] Furthermore, once it is determined that the first module has completed the first phase of message transmission, the second time slot resources allocated to the first module can be reclaimed for reallocation.

[0102] For example, suppose module 1 has a priority of 3, module 2 has a priority of 2, module 3 has a priority of 1, and module 4 has a priority of 0. At a certain moment, module 1 and module 3 simultaneously initiate a time slot resource request signal (req_x). The arbitrator can, after comparing priorities, authorize module 1 to send the signal (e.g., set grant_1=1). After module 1 completes the sending, it can revoke req_1, and the arbitrator can re-determine the priority in the next time slot.

[0103] In this way, dynamic time slot allocation can meet the low-latency scheduling requirements of bursty services. High-priority modules can obtain time slot resources first, and in non-periodic service scenarios such as parameter exchange, it can avoid the resource waste caused by fixed time slot allocation, further improving the utilization rate of time slot resources. Through this dynamic time slot allocation mechanism, flexible and efficient time slot resource scheduling can be achieved in the first stage of main band initialization, shortening the overall initialization time.

[0104] In some examples, if multiple modules have the same priority, time slot resources can be dynamically allocated to multiple modules equally using a round-robin approach.

[0105] In other examples, during the second phase of main band initialization, the arbitrator can allocate third time slot resources authorized for use in each frame period to each module according to a static time slot mapping table, so that each module can send second-phase messages corresponding to the second phase of main band initialization based on its own authorized third time slot resources.

[0106] The aforementioned second stage of main band initialization may include one or more stages. For example, the second stage of main band initialization may include calibration (CAL) of MBINIT stage 2 and / or clock repair (REPAIRCLK) of MBINIT stage 3.

[0107] During the second phase of mainband initialization, each module can periodically report calibration status and interactive control information. Since the primary service during this phase is periodic status reporting, a static time slot allocation mechanism can be employed.

[0108] For example, when no module sends a request (i.e., no_req is valid), the arbitrator can switch to the time-division multiplexing fixed time slot polling mode. Based on the matching relationship between the time slot counter (current_slot) and the static time slot mapping table (slot_map[x]), the arbitrator grants grant_x to the module with the same number. The time slot counter can automatically increment to achieve polling scheduling, ensuring that each module completes status reporting and calibration result feedback in an orderly and conflict-free manner.

[0109] In this example, static time slot allocation ensures the determinism and reliability of periodic training interactions. Each module can send messages in fixed time slots without competing for time slot resources, making it suitable for periodic tasks such as calibration status reporting. This static time slot allocation mechanism ensures that each module reports calibration status in a fixed time slot order during the second phase of mainband initialization, avoiding message conflicts and improving training reliability.

[0110] In some examples, the pseudocode for the arbitrator to allocate time slot resources during the main band initialization process (including the first and second phases) can be as follows:

[0111] if (req_x&&priority_x>current_max_priority) begin

[0112] grant_x = 1;

[0113] current_max_priority = priority_x;

[0114] end else if (no_req&&slot_map[x] == current_slot) begin

[0115] grant_x = 1;

[0116] end

[0117] Based on this approach, the arbitrator's resource allocation logic can include: when there is a transmission request (req_x), dynamic time slots are allocated competitively according to priority (priority_x); when there is no transmission request (no_req), time-division multiplexing of fixed time slots is performed in round-robin fashion according to the static time slot mapping table (slot_map). This hybrid scheduling mechanism can meet the low-latency scheduling requirements of bursty services while ensuring the determinism and reliability of periodic training interactions, providing stable sideband scheduling support for multi-module parallel link training. Through this hybrid scheduling mechanism, time slot allocation strategies can be flexibly switched at different stages of main band initialization, ensuring both rapid response to parameter exchange and orderly execution of the calibration phase, significantly improving the overall efficiency of main band initialization.

[0118] In some embodiments of this disclosure, the link training method can be executed based on a physical layer link state machine, which may include a sideband parallel initialization state, a main band initialization state, and a main band training state. The sideband parallel initialization state can be the state entered by multiple modules of the core after satisfying preset initialization conditions. The main band initialization state can be the state entered by multiple modules of the core after completing sideband initialization. The main band training state can be the state entered by multiple modules of the core after completing main band initialization.

[0119] This embodiment features a key reconstruction of the UCIe Physical Layer Link State Machine (PHY LSM), forming a novel parallel training architecture through the sideband parallel initialization state (SBINIT_PARALLEL). This state machine modification is fully compatible with existing UCIe standards, optimizing the state machine only at the physical layer without involving changes to the protocol or adapter layers. It should be noted that this sideband parallel initialization state can be a new module added to the existing state machine or can replace the existing sideband initialization state (SBINIT); this embodiment does not impose any limitations on this.

[0120] In some examples, the physical layer link state machine also includes a reset state and a sideband initialization state; wherein: the reset state can be the state that multiple modules of the chip enter after being powered on; the sideband initialization state can be the state that the module enters after the phase-locked loop stabilizes; after the module is in the sideband initialization state and meets the preset initialization conditions, it can send a first signal to the arbitrator so that the arbitrator controls each module to enter the sideband parallel initialization state.

[0121] Figure 4 This is a schematic diagram of another physical layer link state machine provided in an embodiment of this disclosure. For example... Figure 4 As shown, the physical layer link state machine may include one or more of the following states:

[0122] Reset State: This reset state can be the state that multiple modules of the chip enter after power-on. In this state, the module's power management module can be initialized, the phase-locked loop can start working, and wait for the phase-locked loop to stabilize (e.g., at least 4ms).

[0123] Sideband Initialization State (SBINIT): This sideband initialization state can be the state the module enters after its phase-locked loop stabilizes. In this state, the various clock signals of the module can be gradually stabilized, including the sideband clock (e.g., 800MHz), the main band clock, and the adapter clock. After the module is in the sideband initialization state and meets the preset initialization conditions, it can send a first signal to the arbiter, so that the arbiter controls each module to enter the sideband parallel initialization state. The preset initialization conditions may include: all modules meeting conditions such as stable power supply, stable and usable sideband clock, stable and usable main band clock, and stable and usable adapter clock.

[0124] Sideband Parallel Initialization State (SBINIT_PARALLEL): This state can be entered by multiple modules of the chip after meeting preset initialization conditions. In this state, all modules can simultaneously transmit clock training sequences (Clock Patterns) on the sideband clock line (SB Clock) and data lane. After the receiver detects two consecutive clock training sequences, it can send a link establishment acknowledgment message (e.g., SBINIT Out of Reset). Furthermore, in this state, the arbiter can allocate a fixed time slot for each module to send sideband initialization messages, such as SBINIT done req and SBINIT done resp messages. After all modules have completed sideband initialization, the arbiter can control all modules to enter the main band initialization state.

[0125] Main Band Initialization State (MBINIT): This state can be entered by multiple modules of the chip after completing sideband initialization. In this state, each module can perform main band data transmission channel initialization, including parameter exchange (PARAM), calibration (CAL), and clock repair (REPAIRCLK). This main band initialization state can include multiple stages (e.g., first stage, second stage, or other stages), and the system as a whole can still execute in stage order, with all modules synchronously entering the same stage. Within the same stage, each module can independently and in parallel perform calibration operations. Message transmission is time-division multiplexed only when reporting calibration status and interactive control information through the sideband channels, such as time-division transmission based on independent time slots allocated by the arbitrator, to avoid message conflicts and improve the reliability of main band initialization. After all modules of the chip have completed main band initialization, the arbitrator can control each module to simultaneously enter the main band training state.

[0126] Mainband Training State (MBTRAIN): This mainband training state can be the state that multiple modules of a chip enter after completing mainband initialization. In this state, each module can perform training tasks for the mainband channels, such as equalization training and timing adjustments.

[0127] Link Initialization State (LINKINIT): This state is entered by each module after completing mainband training. In this state, each module can complete the initialization of the link management layer and prepare to enter normal operation.

[0128] ACTIVE: This is the state that each module enters after completing link initialization. In this state, each module can begin normal data transmission.

[0129] Physical Layer Retraining State (PHYRETRAIN): This state is entered by the module when it detects a degradation in link quality or other conditions requiring retraining while in the active state. In this state, the module can re-execute the physical layer training process, for example, by retraining from the main-band training state. In some examples, the state machine can enter this physical layer retraining state from the main-band training state, for example, based on a timeout mechanism.

[0130] For example, this physical layer retraining state allows the physical layer training process to be re-executed without completely resetting the link, such as re-performing main band training (MBTRAIN) and link initialization (LINKINIT). Physical layer retraining can be performed while maintaining sideband channel connectivity, avoiding complete interruption of data transmission and improving system availability and robustness. After retraining is complete, the module can re-enter the ACTIVE state and continue normal operation.

[0131] Training Error State (TRAINERROR): This training error state can be the state that a module enters when an anomaly occurs during link training. In this state, the module can stop link training and wait for a global system reset or a local retry.

[0132] For example, at any stage of the link training process, if a module encounters an anomaly (such as timeout, link quality issues, hardware failure, etc.), the module can enter a training error state. In this state, the module stops link training and waits for a system global reset or a local retry. According to the timeout mechanism, if the module fails to complete training within a preset time (e.g., 8ms) and does not receive a sideband flow control message, a first timeout signal (timeout_error) is generated, and the module enters this state. The state transition controller decides whether the module enters the retry process (up to 3 times) or triggers a system global reset based on the timeout signal.

[0133] Low-power states (L1 / L2): In some examples, the physical layer link state machine may also include low-power states. These low-power states may include link state 1 (L1) and link state 2 (L2). When the system needs to reduce power consumption, it can transition from the active state to either L1 or L2.

[0134] L1 can be a mild low-power state, entered autonomously by the physical layer. The sideband and main band clocks can continue to run, the data path logic can remain powered, and the exit latency can be less than 1 microsecond. L2 can be a deep low-power state, entered through coordination between the protocol layer and the physical layer. The sideband clocks can continue to run, while the main band clock and most of the data path logic can be powered off. The exit latency can be less than 4 microseconds.

[0135] Entering and exiting low-power states can be controlled by the system power management strategy, with state negotiation performed through sideband channels. The physical layer link training can be triggered from either L1 or L2; for example, L1-based training can trigger link training starting from the main band training state, while L2-based training can trigger link training starting from the reset state.

[0136] In some examples, the state transition relationships of the above state machine can be as follows: RESET→SBINIT→SBINIT_PARALLEL→MBINIT→MBTRAIN→LINKINIT→ACTIVE.

[0137] In some examples, while in the active state, the system can enter the PHYRETRAIN state for physical layer retraining, or enter the L1 / L2 low-power state.

[0138] In some examples, if an exception occurs in any state, the module can enter the TRAINERROR state.

[0139] This physical layer link state machine, by adding a sideband parallel initialization state, enables parallel link training of multiple modules, significantly reducing link training latency and system startup latency. Furthermore, through physical layer retraining and low-power states, it supports dynamic link quality optimization and power management, improving system reliability and energy efficiency. Moreover, this state machine modification is fully compatible with existing UCIe standards, optimizing only the physical layer without affecting the protocol and adapter layers, facilitating practical deployment and application. Through this physical layer link state machine, advanced functions such as multi-module parallel training, dynamic retraining, and power management can be implemented while maintaining standard compatibility, significantly improving the performance and reliability of UCIe links.

[0140] In some embodiments of this disclosure, the link training method may include a timeout mechanism. Based on this multi-module parallel training architecture, the timeout mechanism may include module-level timeout detection and / or global timeout detection. Figure 5 An embodiment of this disclosure provides a timeout control mechanism, such as... Figure 5 As shown, the chip can be configured with one or more of the following: module timers, global timers, or state transition controllers. The global timer can be used to implement global timeout detection to trigger global timeout processing. The module timers corresponding to each module can be used to implement module-level timeout detection to trigger module-level timeout processing. The state transition controller can be used to control the state transition of the physical layer link state machine based on timeout processing logic (module-level and global).

[0141] In some examples, the chip may also include module timers corresponding to each module. These module timers can start when a module enters the sideband parallel initialization state and stop when the module completes link training. If sideband initialization is not completed within a first preset time, a first timeout signal is sent to the arbitrator. Thus, upon receiving the first timeout signal corresponding to any module, the arbitrator can determine the number of times that module has entered the sideband parallel initialization state. If this number is less than or equal to the preset number, the arbitrator controls the module to re-enter the sideband parallel initialization state to perform sideband initialization. If the number is greater than the preset number, the arbitrator controls multiple modules of the chip to enter a training error state. The first preset time can be any duration set based on engineering experience, such as 8 milliseconds or 16 milliseconds. The preset number of times can be any value set based on engineering experience, such as three or five times.

[0142] For example, the system can configure an independent module timer (e.g., a timeout counter) for each module, allowing each module to be monitored independently during parallel training. This module timer can start when the module enters the sideband parallel initialization state. If the module fails to complete sideband initialization and does not receive a sideband flow control message (Stall Sideband) within a first preset time (e.g., 8ms), the module can independently generate a first timeout signal (e.g., a module-level timeout signal `timeout_error`). Sideband initialization can be completed by generating a valid sideband initialization completion signal (`sbinit_done_x`).

[0143] The arbitrator or state transition controller can use the first timeout signal to partially retry abnormal modules, allowing them to re-enter the sideband parallel initialization state. Modules that have completed successfully do not need to restart the process, avoiding overall blocking. However, when a module reaches a preset number of retries (e.g., three consecutive failed retries), it will not re-enter the sideband parallel initialization state but will trigger a global reset, returning the system to the RESET state for retraining. The global sideband initialization completion signal is only valid after all modules have completed sideband initialization, allowing the system to uniformly enter the next stage (e.g., the main band initialization stage), thus achieving efficient and reliable state scheduling under parallel training.

[0144] It should be noted that the module timer can pause its countdown upon receiving a sideband flow control message. A sideband flow control message can be a link management message used to indicate that the receiving end is temporarily unable to process data, requesting the sending end to pause transmission. When the module receives a sideband flow control message, the module timer can pause its countdown to avoid false timeouts caused by the receiving end being busy. The module timer can resume its countdown once the sideband flow control message is cleared.

[0145] For example, suppose that after entering the sideband parallel initialization state, module 1 fails to complete the sideband initialization within 8ms due to link quality issues and does not receive a sideband flow control message, then the module timer of module 1 can generate a first timeout signal.

[0146] In this way, by introducing a module-level independent timeout detection and retry mechanism during the parallel training phase, the reliability and fault tolerance of the training process can be improved.

[0147] In some examples, the chip may also include a global timer. This global timer starts when the arbiter outputs a second signal to each module, stops when each module of the chip completes link training, and sends a second timeout signal to the arbiter if the sideband initialization of each module is not completed within a second preset time. Thus, if multiple modules are determined to have completed sideband initialization before the global timer expires, the multiple modules of the chip are controlled to enter the main band initialization state; or, if the second timeout signal is received before multiple modules have completed sideband initialization, the multiple modules of the chip are controlled to enter a training error state.

[0148] For example, the system can set a global timer (e.g., a global timeout counter). This global timer can start when all modules enter the sideband parallel initialization phase and only stop and reset when all modules have completed sideband initialization and reported a sideband initialization completion signal, avoiding indefinite waiting due to individual module malfunctions. If the global timer reaches a preset second preset time (e.g., 32ms) and all modules have not completed, the overall link training can be considered a failure, triggering a global system reset, causing all modules to uniformly enter a reset state. This second preset time can be greater than the first preset time. For example, the second preset time can be equal to N times the first preset time, where N can be set to the aforementioned preset number. It can also be set to the total number of modules within the core, or the product of the aforementioned preset number and the total number of modules within the core, to ensure that even if all modules retry serially, they can complete before the global timeout.

[0149] In some examples, the core may also include a state transition controller. This state transition controller can be used to determine the number of times a module enters the sideband parallel initialization state based on a first timeout signal, and control multiple modules of the core to enter the training error state when the number exceeds a preset number.

[0150] This state transition controller can be used to control the system state to transition correctly according to specifications based on module training status and timeout information, deciding whether a module should enter a retry process or an abnormal state. When the state transition controller receives the first timeout signal from any module, it can first count the number of timeout retries for that module. If the number of retries does not exceed a preset number (e.g., 3 times), the state controller can trigger the arbiter to reactivate the sideband parallel initialization state (SBINIT_PARALLEL) for the timed-out module individually, causing it to re-execute the sideband initialization process. Modules that have completed sideband initialization can maintain their current state without needing to be retrained. This local retry mechanism avoids the problem of all modules needing to be retrained due to the timeout of a few modules, improving system efficiency.

[0151] Once all modules have successfully completed sideband initialization, the state transition controller can output a global completion signal (sbinit_global_done) to control all modules to uniformly enter the main band initialization state (MBINIT).

[0152] If the same module fails to retries after a preset number of times (e.g., 3 times), the state transition controller can determine that the module link is abnormal, control it to enter the training error state (TRAINERROR), and trigger a global system reset, so that all modules return to the reset state (RESET).

[0153] It should be noted that the function of this state transition controller can be implemented by the arbitrator, or it can be a component within the arbitrator, or it can be a component that runs in parallel with the arbitrator.

[0154] For example, assuming module 1 times out on the first attempt, the state transition controller can trigger module 1 to re-enter the sideband parallel initialization state. If module 1 also times out on the second attempt, a retry can be triggered again. If module 1 still times out on the third attempt, the state transition controller can determine that module 1 has a link malfunction and trigger a system-wide reset.

[0155] This timeout mechanism enables independent timeout detection and retries at the module level, improving the system's fault tolerance. When individual modules experience temporary failures, the system can recover through local retries, preventing overall link training failure. By limiting the number of retries for a single module (e.g., 3 times), a global reset can be triggered promptly when a module experiences persistent anomalies, preventing the system from remaining in an abnormal state for extended periods. Furthermore, a global timer ensures the system doesn't wait indefinitely due to individual module anomalies, guaranteeing system reliability. Thus, this timeout mechanism improves system fault tolerance while also ensuring overall system reliability and startup efficiency.

[0156] This disclosure also provides a core, which may include an arbitrator and multiple modules. The core can be configured to perform all or part of the steps of any of the methods in the foregoing embodiments of this disclosure. For example, the arbitrator can perform all or part of the steps of any of the methods in the foregoing embodiments. Exemplarily, the core may be... Figure 1 The first core 1100 or the second core 1200 shown.

[0157] This disclosure also provides a computing system that may include multiple chips. Exemplarily, the computing system may be... Figure 1 The computing system 1000 shown can be a system that includes computing devices such as GPUs, GPGPUs, NPUs, or TPUs.

[0158] The computing system can be any type of electronic device, such as any type of terminal device, workstation or server, etc., and this embodiment does not limit it.

[0159] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0160] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and apparatuses according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, unit, or part of a circuit. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should be noted that embodiments of the present disclosure may include some or all of the functions marked in the multiple blocks in the drawings, and may also include other functions not shown in the blocks in the drawings. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented in hardware that performs the specified function or action, or in a combination of dedicated hardware and computer instructions. Unless otherwise specified, implementation in hardware, implementation in software, and implementation in a combination of software and hardware may be equivalent.

[0161] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.

Claims

1. A link training method, characterized in that, An arbitrator applied to a chip, wherein the chip further includes multiple modules, each module comprising a main band channel and a sideband channel based on a common chip interconnect standard, for interconnecting with corresponding modules of other chips; the arbitrator is used for link training management of the multiple modules; the method includes: Determine whether the module meets the preset initialization conditions based on the first signal received from each module; When multiple modules of the core meet the preset initialization conditions, a second signal is output to each module to control each module to perform sideband initialization in parallel. During the parallel execution of sideband initialization, each module sends a sideband initialization message corresponding to the sideband initialization based on the time-division multiplexing mode. The third signal output by each module determines whether the module has completed sideband initialization; After the multiple modules have completed sideband initialization, each module is controlled to perform mainband initialization and mainband training tasks in order to carry out link training based on multiple modules.

2. The method according to claim 1, characterized in that, The channel resources of the sideband channel are configured as multiple frames in time-division multiplexing mode, with each frame period including multiple time slot resources; the control modules perform sideband initialization in parallel, including: Each module is allocated a first time slot resource that is authorized for use in each frame period, so that each module sends a sideband initialization message corresponding to the sideband initialization based on its respective authorized first time slot resource; Different modules are authorized to use different first time slot resources, while the same module is authorized to use the same first time slot resources in different frame periods.

3. The method according to claim 2, characterized in that, The allocation of first time slot resources authorized for use in each frame period to each module includes: Obtain a static time slot mapping table, which is a mapping table pre-generated during the power-on initialization process of the chip based on the number of modules and the frame period of the chip, and is used to characterize the static time slot resources corresponding to each module in each frame period; According to the static time slot mapping table, the static time slot resources corresponding to each module in each frame period are used as the first time slot resources of the module.

4. The method according to claim 3, characterized in that, The main band initialization process includes a first stage of main band initialization and / or a second stage of main band initialization. The first stage of main band initialization is used for parameter exchange, and the second stage of main band initialization is used for calibration and / or clock repair. The arbitrator controls each module to perform mainband initialization, including: In the first stage of main band initialization, based on the time slot resource request signals of each module, a second time slot resource is dynamically allocated to each module from multiple time slot resources of the sideband channel, so that each module sends a first-stage message corresponding to the first stage of main band initialization based on the second time slot resource; or, In the second phase of main band initialization, each module is allocated a third time slot resource authorized for use in each frame period according to the static time slot mapping table, so that each module sends a second phase message corresponding to the second phase of main band initialization based on its authorized third time slot resource.

5. The method according to claim 4, characterized in that, Based on the time slot resource request signals of each module, second time slot resources are dynamically allocated to each module from multiple time slot resources of the sideband channel, including: When multiple modules send time slot resource request signals, determine the priority of each module. Determine the highest priority module from among multiple modules, and allocate the second time slot resource to the first module; If it is determined that the first module has completed the first phase of message transmission, the second time slot resource will be reclaimed for reallocation.

6. The method according to any one of claims 1 to 5, characterized in that, The link training method is executed based on the physical layer link state machine, which includes a sideband parallel initialization state, a main band initialization state, and a main band training state. The sideband parallel initialization state is the state that multiple modules of the core particle enter after the preset initialization conditions are met; The main strip initialization state is the state that the multiple modules of the core chip enter after completing the side strip initialization; The mainband training state is the state that multiple modules of the chip enter after completing the mainband initialization.

7. The method according to claim 6, characterized in that, The physical layer link state machine further includes a reset state and a sideband initialization state; wherein: The reset state is the state that the multiple modules of the core chip enter after being powered on; The sideband initialization state is the state that the module enters after the phase-locked loop stabilizes; After the module is in the sideband initialization state and meets the preset initialization conditions, it sends the first signal to the arbiter so that the arbiter controls each module to enter the sideband parallel initialization state.

8. The method according to claim 6, characterized in that, The core also includes a module timer corresponding to each of the modules; the module timer starts when the module enters the sideband parallel initialization state, stops when the module completes link training, and sends a first timeout signal to the arbitrator if the sideband initialization is not completed within a first preset time. The method further includes: Upon receiving the first timeout signal corresponding to any module, determine the number of times the module enters the sideband parallel initialization state; If the number of times is less than or equal to the preset number of times, the module is controlled to re-enter the sideband parallel initialization state to perform sideband initialization; If the number of attempts exceeds a preset number, then multiple modules of the chip are controlled to enter a training error state.

9. The method according to claim 8, characterized in that, The core also includes a global timer; the global timer starts when the arbiter outputs a second signal to each module, stops when each module of the core completes link training, and sends a second timeout signal to the arbiter if the sideband initialization of each module is not completed within a second preset time. The method further includes: If it is determined that the multiple modules have completed sideband initialization before the global timer expires, then the multiple modules of the chip are controlled to enter the main band initialization state; or, If the second timeout signal is received before the multiple modules complete sideband initialization, the multiple modules of the chip are controlled to enter the training error state.

10. The method according to any one of claims 1 to 5, characterized in that, The first signal includes a power supply status signal and a clock status signal; The preset initialization conditions include: Based on the power supply status signal, it is determined that the power supply status of the module is normal; and The clock status of the module is determined to be normal based on the clock status signal. The clock of the module includes at least one of the sideband clock, the mainband clock, or the adapter clock.

11. A core element, characterized in that, The arbitrator of the core is configured to perform the method of any one of claims 1 to 10.

12. A computing system, characterized in that, It includes multiple cores as described in claim 11.

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