Data processing method, network-on-chip, chip and electronic equipment

Abstract

The invention provides a data processing method, a network-on-chip, a chip and electronic equipment. The network-on-chip comprises at least two isomorphic routing nodes, each routing node comprises an identifier storage unit, at least two input interfaces and at least two output interfaces, and the at least two routing nodes are interconnected according to a target topology; the first input interface of the first routing node is used for receiving a first identification signal in the process of initializing the network-on-chip, and the first routing node is one of the at least two routing nodes; and the identifier storage unit of the first routing node is used for setting the identifier of the first routing node based on the first identifier signal.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of computer technology, and in particular to a data processing method, on-chip network, chip, and electronic device. Background Technology

[0002] Network on Chip (NoC) is an architecture used to achieve efficient communication in multi-core system-on-a-chip (SoC). NoC employs a distributed routing structure to connect multiple processing units, and achieves interconnection and information exchange between computing modules by forwarding data packets through each routing node, thereby meeting the requirements of high-performance and low-latency communication.

[0003] In related technologies, each routing node of NoC can be configured in a fixed manner based on its physical location or address range, or flexibly configured through software. This heterogeneous design has problems such as high complexity, high verification cost, poor scalability, cumbersome configuration, and low accuracy. Summary of the Invention

[0004] This application provides a data processing method, an on-chip network, a chip, and an electronic device.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides an on-chip network including at least two homogeneous routing nodes. Each routing node includes an identifier storage unit, at least two input interfaces, and at least two output interfaces. The at least two routing nodes are interconnected according to a target topology. The first input interface of the first routing node is used to receive a first identification signal during the initialization process of the on-chip network; wherein the first routing node is one of at least two routing nodes, and the first input interface is one of at least two input interfaces. The identifier storage unit of the first routing node is used to set the identifier of the first routing node based on the first identifier signal.

[0006] This application provides a data processing method applied to a network-on-a-chip (NIC). The NIC includes at least two homogeneous routing nodes. Each routing node includes an identifier storage unit, at least two input interfaces, and at least two output interfaces. The at least two routing nodes are interconnected according to a target topology. The data processing method includes: During the initialization of the on-chip network, the first input interface of the first routing node receives the first identification signal; wherein, the first routing node is one of at least two routing nodes, and the first input interface is one of at least two input interfaces. The identifier storage unit of the first routing node sets the identifier of the first routing node based on the first identifier signal.

[0007] This application provides a chip including the above-described on-chip network.

[0008] This application provides an electronic device including the chip described above.

[0009] The embodiments of this application have the following beneficial effects: On the one hand, by employing multiple homogeneous routing nodes in the on-chip network, all routing nodes achieve complete consistency in hardware structure and logical function. Compared to heterogeneous designs caused by address mapping differences in related technologies, firstly, this completely homogeneous modular design eliminates the problem of inconsistent logic among routing nodes in existing designs, enabling true modularization and standardization of on-chip system design; secondly, since multiple routing nodes can reuse the same layout, the physical design of the on-chip network becomes simpler and more efficient. Moreover, the homogeneous routing nodes are completely identical in area, shape, and pin position, facilitating regular layout and routing on the chip plane, thereby greatly shortening the back-end design cycle and simplifying the back-end design. At the same time, since the timing convergence and power consumption heat distribution characteristics of each routing node are almost identical, it can reduce local congestion or heat dissipation problems caused by uneven distribution of different logic units, improving overall performance and yield; thirdly, with homogeneous routing nodes, only the function and timing of a single routing node need to be verified, rather than verifying them one by one, greatly reducing verification costs. On the other hand, during the on-chip network initialization process, a unique identifier is automatically assigned to each routing node through the identifier storage unit, a hardware unit, without manual configuration or software intervention. This not only improves allocation efficiency, reliability, and accuracy but also shortens startup time. Furthermore, compared to related technologies that require dedicated bus, controller, and interface logic configuration, it reduces area overhead and avoids heterogeneity issues caused by the interfaces themselves. Additionally, when adding or deleting routing nodes, identifier allocation can be automatically performed with a single initialization, without modifying the design of existing nodes or replanning address mappings, thus enhancing scalability and flexibility. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the composition structure of an on-chip network provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the implementation flow of a data processing method provided in an embodiment of this application; Figure 3 This is a schematic diagram of an on-chip network in related technologies. Figure 1 ; Figure 4 This is a schematic diagram of an on-chip network in related technologies. Figure 2 ; Figure 5 This is a schematic diagram of an on-chip network provided in an embodiment of this application.

[0011] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0014] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0016] The technical solutions in the embodiments of this application will now be clearly and completely described with reference to the accompanying drawings.

[0017] Figure 1 This application provides a schematic diagram of the first component structure of an on-chip network, as shown in the embodiment of the present application. Figure 1 As shown, the on-chip network 100 includes at least two homogeneous routing nodes 10. Each routing node 10 includes an identifier storage unit 11, at least two input interfaces 12, and at least two output interfaces 13. The at least two routing nodes 10 are interconnected according to the target topology. The first input interface of the first routing node is used to receive a first identification signal during the initialization process of the on-chip network; wherein the first routing node is one of at least two routing nodes, and the first input interface is one of at least two input interfaces. The identifier storage unit 11 of the first routing node is used to set the identifier of the first routing node based on the first identifier signal.

[0018] Here, homogeneity refers to the fact that all routing nodes in a NoC are completely identical in structure and function. In other words, the circuit design, logic implementation, and physical layout of each routing node are the same. This consistency allows each routing node to be copied and pasted for use without the need for customized design or configuration for different routing nodes, or for logical modifications to each routing node, thereby reducing design complexity and verification difficulty.

[0019] Router nodes (or routing nodes) are the basic communication units that make up a NoC (No of Core), primarily used to forward data packets between multiple processing cores and / or other routing nodes. It can be understood that routing nodes on a NoC are interconnected through a target topology. The target topology is the physical or logical connection method used to interconnect the routing nodes. The target topology can be any suitable and common topology, such as mesh topology, torrent topology, ring topology, etc. Mesh topology is a two-dimensional grid-like connection method, where each node is connected to its neighbors above, below, left, and right. Tor topology is an extension of mesh topology, where edge nodes are connected end-to-end to form a closed loop. Ring topology is a ring-shaped connection method, where nodes are connected end-to-end to form a ring. In implementation, choosing a suitable target topology is crucial for system performance and scalability. For example, mesh topology is suitable for applications with high bandwidth requirements, while ring topology is suitable for low-power, low-latency scenarios.

[0020] An input interface (or input port) is a physical or logical channel through which a routing node receives external signals. This input interface is used to acquire data packets or signals sent by other nodes or the processing core. In implementation, each routing node includes at least two input interfaces to support multi-directional data transmission and flexibility in the interconnect topology. For example, in a mesh topology, each node can have five input interfaces. Four of these input interfaces correspond to the north, south, east, and west directions, respectively, and are used to acquire data packets or other signals from neighboring nodes or the processing core. The remaining input interface (i.e., the first input interface) is used to receive a preset signal or a second identification signal sent by the preceding routing node.

[0021] An output interface (or output port) is a physical or logical channel through which a routing node sends data packets or signals to other routing nodes or the processing core. In implementation, each routing node also includes at least two output interfaces to support multipath forwarding of data packets and the transmission of identification signals.

[0022] It is understandable that the output and input interfaces of a routing node together constitute the communication link between the routing node and other objects (such as other routing nodes or processing cores).

[0023] The identifier storage unit is a hardware module within the routing node used to store unique identifiers (IDs). This identifier storage unit can be implemented using registers, storage circuitry (such as flip-flops), etc. For example, it may include one or a set of registers. During implementation, the routing node's ID can be set to a unique value during NoC initialization; the ID represents the routing node's identity within the NoC. It is understood that the ID stored in the identifier storage unit will not change throughout the entire operation. In implementation, the NoC initializes itself when it is reset or powered on.

[0024] The first routing node can be any routing node in the NoC, such as the first routing node, an intermediate routing node, or the last routing node. It's understandable that during the NoC initialization process, each routing node will act as a first routing node.

[0025] The first input interface is a dedicated input interface in the routing node used to receive the first identification signal.

[0026] In some implementations, the routing nodes are simply chained together via a first input interface and a first output interface; that is, the first output interface of one routing node is connected to the first input interface of another routing node. The first output interface is one of at least two output interfaces. In practice, an existing pair of unused input / output interfaces in the routing node can be used as the first input and first output interfaces. This eliminates the need for dedicated wiring, simplifies the design, and reduces the complexity of the on-chip network.

[0027] The first identification signal can be the second identification signal output from the first output interface of the preceding routing node, or it can be a preset signal. The preset signal can be a fixed initial value or control signal automatically assigned by hardware; this preset signal can be any suitable high level, low level, pulse sequence, etc. For example, for the first routing node, since there are no other routing nodes connected to it, the first identification signal received by the first input interface of the first routing node can be the preset signal. For other routing nodes, since there are other nodes connected to them, the first identification signal received by the first input interface of the other routing nodes can be the second identification signal output by the preceding routing node. It can be understood that when the first input interface receives the first identification signal, it marks the starting point of the ID setting process for that routing node. That is, the first identification signal triggers the subsequent automatic ID generation mechanism of the routing node, ensuring that each node can obtain a unique identifier, thereby providing the foundation and necessary support for subsequent routing operations and address decoding functions.

[0028] The ID of the routing node can be in any suitable form, such as numbers or letters. The method for determining the ID of the routing node can also be any suitable method. For example, the ID of the routing node can be a first identification signal. Alternatively, the ID of the routing node can be generated based on the first identification signal, such as by incrementing a first preset value (e.g., 1, 2, etc.) based on the first identification signal. The identification storage unit then stores the identifier of the routing node and remains unchanged throughout the entire operation. In practical implementation, the configuration of this identification storage unit is a key step in achieving homogeneous design. Since the identification storage units of each routing node use the same circuit structure, initialization can be completed simply by performing a write operation based on the received identification signal. This purely hardware-based automatic enumeration of the routing node's identifier improves initialization speed while enhancing reliability and avoiding routing conflicts caused by configuration errors.

[0029] In some embodiments, the first output interface of the first routing node is used to output a second identification signal. This first output interface is a dedicated output interface within the routing node for outputting the second identification signal. In some embodiments, for a non-last routing node, since a next routing node exists, the second identification information can be output to the first input interface of the next routing node. The next routing node is connected to the first routing node; that is, the first output interface of the first routing node is connected to the first input interface of the next routing node. In some embodiments, for the last routing node, since there is no next routing node, the second identification information may or may not be output.

[0030] The second identification signal can be a control signal passed by a routing node to the next routing node after completing its own identification settings. This second identification signal can be used to indicate that the predecessor routing node is ready and to notify the next routing node to perform identification settings. For example, the second identification signal can be an ID ready signal. When a routing node receives an ID ready signal, it indicates that the predecessor routing node has completed initialization. At this time, the routing node can perform its own ID generation operation. In this way, chained initialization is achieved by passing the second identification signal sequentially to each routing node, ensuring that all routing nodes complete identification allocation in order. It can be understood that the second identification signal is the first identification signal received by the first input interface of the next routing node.

[0031] The second identification signal is determined based on the identifier of the first routing node. The determination of the second identification signal can be any suitable method. For example, the second identification signal can be the identifier of the routing node. Alternatively, the second identification signal can be generated based on the identifier of the routing node, such as by incrementing a second preset value (e.g., 1, 2, etc.) based on the identifier of the routing node.

[0032] Understandably, there is a close relationship between the configuration of the identifier storage unit and the transmission of identifier signals. After receiving the first identifier signal and storing the ID, the identifier storage unit immediately generates and sends out a second identifier signal, which serves as the trigger condition for the initialization of the next routing node. This signal transmission mechanism ensures the orderliness and efficiency of the initialization process.

[0033] In implementation, the second identification signal is passed to the next routing node through the first output interface, thereby initiating the initialization process of the next routing node. This chain-like transmission method ensures that all nodes can complete ID allocation in an orderly manner, avoiding problems such as contention and conflict. In addition, since the transmission of the identification signal depends only on hardware logic and does not require software intervention, the overall efficiency is greatly improved.

[0034] Throughout the initialization process, through the collaboration between the identifier storage units of each routing node, not only can the ID allocation of all routing nodes be completed quickly during the initialization phase to support the correct routing of subsequent data packets, but also the complete consistency of all routes in terms of structure and function can be ensured while guaranteeing that each node has a unique identifier. This improves scalability and initialization reliability, making it suitable for large-scale multi-core on-chip system designs.

[0035] Understandably, for the last routing node, since there is no next routing node, that is, the first output interface of this routing node is not connected to the first input interface of other routing nodes, the first output interface of this routing node does not need to output the second identification signal; however, for non-last routing nodes, since there is a next routing node, that is, the first output interface of this routing node is connected to the first input interface of the next routing node, the first output interface of this routing node needs to output the second identification signal.

[0036] In this embodiment, on the one hand, by employing multiple homogeneous routing nodes in the on-chip network, all routing nodes achieve complete consistency in hardware structure and logical function. Compared with the heterogeneous design caused by address mapping differences in related technologies, firstly, this completely homogeneous modular design eliminates the problem of inconsistent logic among routing nodes in existing designs, enabling the on-chip system design to truly achieve modularity and standardization; secondly, since multiple routing nodes can reuse the same layout, the physical design of the on-chip network becomes simpler and more efficient. Moreover, the homogeneous routing nodes are completely consistent in area, shape, pin position, etc., which facilitates regular layout and routing on the chip plane, thereby greatly shortening the back-end design cycle and simplifying the back-end design. At the same time, since the timing convergence and power consumption heat distribution characteristics of each routing node are almost identical, it can reduce local congestion or heat dissipation problems caused by uneven distribution of different logic units, thereby improving overall performance and yield; thirdly, after adopting homogeneous routing nodes, only the function and timing of a single routing node need to be verified, instead of verifying them one by one, which greatly reduces the verification cost. On the other hand, during the on-chip network initialization process, a unique identifier is automatically assigned to each routing node through the identifier storage unit, a hardware unit, without manual configuration or software intervention. This not only improves allocation efficiency, reliability, and accuracy but also shortens startup time. Furthermore, compared to related technologies that require dedicated bus, controller, and interface logic configuration, it reduces area overhead and avoids heterogeneity issues caused by the interfaces themselves. Additionally, when adding or deleting routing nodes, identifier allocation can be automatically performed with a single initialization, without modifying the design of existing nodes or replanning address mappings, thus enhancing scalability and flexibility.

[0037] In some implementations, when the first routing node is the first routing node, the first identification signal is a preset signal; the identification storage unit 11 of the first routing node is also used to set the identification of the first routing node based on the preset signal during the first clock cycle.

[0038] Here, the first routing node refers to the routing node that starts first and begins the identifier allocation process after NoC boots up; that is, the first routing node is the starting point of the entire chain-like automatic identifier setting mechanism. Identification of the first routing node can be achieved through hardware wiring or by direct control via a control signal after boot. In implementation, since no other routing nodes are connected to the preceding stage of the first routing node, its first input interface can be connected to other hardware to obtain the preset signal.

[0039] This preset signal can be a fixed initial signal used to trigger the first routing node to automatically generate an ID. This ensures that the identifier allocation process has a definite starting point, avoiding multiple nodes simultaneously vying for the first identifier, thereby improving stability and reliability.

[0040] It is understandable that there is a logical connection between the first routing node and the preset signal. The reason why the first routing node can receive the preset signal is that the first routing node is at the beginning of the entire link in terms of physical connection and logical control. This allows the communication system to complete the initialization process without relying on external configuration or software intervention.

[0041] The identifier storage unit is used to store the ID of the routing node. The routing node's ID is used for address decoding and routing decisions during subsequent operation.

[0042] The first clock cycle refers to the moment when the clock signal first arrives after the NoC is powered on. During the first clock cycle, the identifier storage unit sets the ID of the first routing node according to the received preset signal. This ID setting operation is completed automatically without external intervention, ensuring the speed and consistency of identifier allocation.

[0043] The ID of the first routing node can be a preset signal, or it can be an ID incremented by a first preset value based on the preset signal. For example, when the preset signal is zero, the identifier storage unit can set the identifier of the routing node to 0 or 1 (i.e., increment by 1); when the preset signal is other values ​​(such as -1), the identifier storage unit can set the identifier of the routing node to 0 (i.e., increment by 1). This ensures that the first routing node can obtain the correct identifier in the shortest possible time, laying the foundation for the identifier allocation of subsequent nodes.

[0044] In some implementations, the identifier of the first routing node is a preset signal. That is, the identifier of the first routing node is a preset signal. In practice, when the NoC powers on, all routing nodes are in a state of pending initialization. When the first routing node receives the preset signal (e.g., 0), its identifier storage unit sets its ID to the preset signal. Subsequently, the first routing node transmits an ID ready signal (i.e., the second identifier signal) to the second routing node. The second routing node sets its own ID within the second clock cycle and continues to transmit the ID ready signal. Subsequent routing nodes then perform ID setting operations according to the received identifier signals within their respective clock cycles, ultimately achieving automatic allocation and configuration of IDs for all routing nodes. This process is entirely implemented by hardware logic without any software intervention. By directly setting the identifier of the first routing node to the preset signal, the identifier allocation process is simplified, initialization efficiency is improved, and the determinism of the identifier allocation process is guaranteed. Furthermore, this setting method enables the function of automatically generating unique identifiers in pure hardware, thereby enabling the construction of a highly scalable and flexible on-chip distributed interconnect system.

[0045] In this embodiment, by setting the initial identifier signal of the first routing node to a preset value and completing its identifier setting within the first clock cycle, the orderly startup of the entire identifier allocation link is ensured, avoiding identifier conflicts and initialization delays. Simultaneously, by introducing a coordination mechanism between the first routing node and the preset signal, as well as a synchronization mechanism between the preset signal and the clock signal, a chain-like initialization structure is formed, which can quickly and reliably assign a unique identifier to each routing node without relying on software configuration.

[0046] In some implementations, when the first routing node is not the first routing node, the first identification signal is the second identification signal output by the first output interface of the previous routing node, and the previous routing node is connected to the first routing node; the identification storage unit 11 of the first routing node is used to set the identification of the first routing node based on the second identification signal output by the first output interface of the previous routing node within one clock cycle.

[0047] Here, when a routing node in the network is not at the start of a link, the first identification signal received by that routing node comes from the preceding routing node. The preceding routing node refers to the routing node located before the first routing node in the network topology and which has successfully completed ID allocation. For example, in a chain-connected mesh network, each routing node sequentially receives the ID-ready signal (i.e., the first identification signal) from the preceding routing node as the basis for its own identification settings. This mechanism ensures that all routing nodes in the entire network can automatically obtain unique identifiers in sequence, thus achieving an identification allocation process without external software configuration or manual intervention. It can be understood that the preceding routing node can be the first routing node or any other routing node. For example, for the second routing node, its preceding routing node is the first routing node.

[0048] Each routing node contains an identifier storage unit. This unit receives a second identifier signal from the previous routing node within one clock cycle after power-on and sets its own ID based on this signal. The identifier storage unit automatically generates IDs through hardware logic, allowing each routing node to independently complete the initialization process without a central controller or software configuration. The design of the identifier storage unit ensures the correctness and uniqueness of the IDs, thus guaranteeing the accuracy of subsequent routing decisions.

[0049] The method for determining the identifier of a non-first routing node can be any suitable method. This identifier can be determined based on the second identifier information output by the first output interface of the previous routing node. For example, the identifier can be incremented by a first preset value (such as 1, 2, etc.) based on the second identifier signal. Alternatively, the identifier can be the second identifier signal itself. It is understood that the identifier of each routing node is unique.

[0050] In this embodiment, by introducing the identification signal of the previous routing node as input into the routing node that is not the first node, and combining it with the local identification storage unit, the identification is automatically set, ensuring that each routing node can obtain a unique identification during the initialization phase without the need for additional configuration logic, thereby further reducing complexity and resource consumption.

[0051] In some implementations, the first output interface of the first routing node is further used to output a second identification signal to the first input interface of the next routing node when the first routing node is not the last routing node; wherein the first output interface is one of at least two output interfaces, the second identification signal is determined based on the identification of the first routing node, and the next routing node is connected to the first routing node.

[0052] Here, the first routing node refers to the routing node currently setting the ID. In implementation, a conditional judgment mechanism is introduced to determine whether to execute the forwarding operation of the second identification signal by ensuring that the first routing node is not the last routing node. It can be understood that the topology and chained connections determined during the initialization phase, through this conditional judgment mechanism, ensure that only non-terminal nodes continue to transmit the second identification signal, thereby achieving correct routing and propagation of identification signals in the distributed network.

[0053] The second identification signal is determined based on the ID of the first routing node. For example, the second identification signal can be the ID of the first routing node. Alternatively, the second identification signal can be an increment of a second preset value based on the ID of the routing node. As a key component of the chained transmission mechanism, the second identification signal ensures that each routing node can obtain a unique ID sequentially according to a preset order.

[0054] In some implementations, the second identification signal is the identifier of the first routing node. That is, the second identification signal refers to the unique identity information sent by the first routing node to downstream routing nodes during the routing process. It can be understood that the second identification signal not only carries identity information but also triggers the ID setting operation of the next routing node. For example, in a mesh network containing 16 routing nodes, after the first routing node completes initialization and is assigned ID=0, it passes its ID to the next routing node through its output interface. The next routing node increments the received second identification signal by 1 in the next clock cycle as its own ID and then continues to pass its ID down the chain. In this way, by directly using the identifier of the current routing node as the output signal, the identification signal generation logic is simplified, transmission efficiency is improved, and consistency between routing nodes is enhanced.

[0055] In some implementations, the second identification signal may also carry additional status information, such as a ready flag or a link interruption flag, thereby enhancing its fault tolerance and debugging capabilities. When a routing node detects that the preceding stage has not sent the expected second identification signal on time, the routing node can trigger exception handling logic to prevent the entire ID allocation process from failing due to a single point of failure.

[0056] During implementation, by passing their own IDs between routing nodes, the entire process forms a closed-loop chain ID allocation path, thereby ensuring that all routing nodes can obtain unique and continuous ID values ​​without external configuration, achieving the purpose of a purely hardware-driven ID allocation mechanism.

[0057] In this embodiment, a conditional judgment mechanism is set up to output the second identification signal only when the routing node is not the last routing node. This ensures that the second identification signal is transmitted correctly, orderly, and reliably in the network according to the preset path, ensuring the continuity and correctness of the identification allocation process, and avoiding invalid forwarding or deadlock problems.

[0058] In some embodiments, routing node 10 further includes a routing calculation unit; after the on-chip network completes initialization, the second input interface of the second routing node is used to receive data packets; wherein the second routing node is one of at least two routing nodes, the second input interface is an input interface that is different from the first input interface among at least two input interfaces, and the data packet includes target information representing the identifier of the target routing node; the routing calculation unit of the second routing node is used to determine a second output interface based on the target information and the identifier of the second routing node; wherein the second output interface is an output interface that is different from the first output interface among at least two output interfaces; the second output interface of the second routing node is used to output data packets to the target end; wherein the target end is a routing node or a target processing core corresponding to the second routing node.

[0059] Here, the second routing node refers to any routing node that receives the data packet.

[0060] The second input interface can be any input interface different from the first input interface. The second input interface is responsible for passing the received data packets to the routing calculation unit for further processing. It can be understood that the first input interface is mainly used to receive identification signals sent by other routing nodes, while the second input interface mainly refers to the physical or logical channel within the routing node used to receive data packets from other nodes or the processing core. Each routing node is typically equipped with multiple second input interfaces to achieve multi-directional communication. For example, in a two-dimensional mesh structure, each routing node may include five second input interfaces: an input interface for receiving data packets from routing nodes in the north, south, east, and west directions, and an input interface for receiving data packets from the connected processing core. In this way, by setting multiple input interfaces, each routing node in the network can flexibly receive data packets from different directions, and the network can ensure efficient data flow transmission within the network, avoiding single-point bottlenecks and improving its parallel processing and throughput capabilities.

[0061] This data packet may encapsulate a source address, destination address, data content, control information, etc. It is understood that this data packet at least contains target information identifying the destination routing node. Target information is part of the data packet and is used to indicate the target routing node to which the data packet should be sent. Target information can be any suitable content such as node ID, node coordinates, or the address corresponding to the node; this target information is used to indicate the target routing node to which the data packet should be sent.

[0062] The routing calculation unit is the core logic module within a routing node, used to determine the next-hop output interface of a data packet based on the current node's identifier and the packet's destination information. In this application, the routing calculation unit in all routing nodes adopts a unified logic circuit, treating all routing nodes equally and relying solely on the comparison result between the local ID and the destination routing node's ID to determine the forwarding direction. Thus, through the unified logic processing of the routing calculation unit, each routing node can automatically select the appropriate output interface based on the relationship between its own ID and the destination ID, thereby achieving correct packet forwarding. This unified logic processing design eliminates the heterogeneity problem caused by the need for customized decoding logic for each node in related schemes, achieving completely homogeneous routing nodes.

[0063] In some implementations, XY routing algorithms, dimensional order routing algorithms, shortest path routing algorithms, etc., can be used to determine the forwarding direction (i.e., the output interface).

[0064] In some implementations, the output interface can be determined based on the comparison result between the local ID and the ID of the target routing node.

[0065] A second output interface is one of at least two output interfaces that is different from the first output interface. The second output interface is responsible for delivering data packets to the target end. It can be understood that the first output interface is mainly used to send identification signals to other routing nodes, while the second output interface is mainly used to send data packets to other nodes or the physical or logical channels of the target processing core. Each routing node is typically equipped with multiple second output interfaces to enable multidirectional communication. For example, in a two-dimensional mesh structure, each routing node may include five second output interfaces, such as north, south, east, and west direction output interfaces and a local output interface.

[0066] The destination refers to the final destination of the data packet. The destination can be another routing node or a processing core (such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), or other IP core) directly connected to the current routing node. When the destination is another routing node, the data packet will continue to be transmitted through the network; when the destination is a processing core, the data packet will be sent to the local machine for processing. In this way, by ensuring that data packets are output to the correct destination, the routing node ensures that data can be correctly transmitted throughout the entire on-chip network, thereby meeting the requirements for communication performance and reliability and improving data transmission efficiency.

[0067] In this embodiment, by introducing a routing calculation unit to make routing decisions using the routing node's own identifier and the target information in the data packet, all routing nodes can share a unified routing calculation logic, thereby achieving homogeneous design and improving scalability and maintenance efficiency.

[0068] In some implementations, the routing calculation unit of the second routing node is further configured to, when the target information matches the identifier of the second routing node, use the output interface communicating with the target processing core as the second output interface; when the target information does not match the identifier of the second routing node, determine the second output interface based on the location information of the target routing node and the location information of the second routing node.

[0069] Here, the target information may include the target address or ID of the target routing node, indicating which destination the data packet should be sent to. It is understood that the identifier of the second routing node is automatically generated via a chain during the aforementioned hardware initialization.

[0070] When the target node ID in the target information matches the local ID of the second routing node, it indicates that the data packet should be processed at this routing node. Therefore, the data packet can be sent to the processing core connected to the second routing node. In this case, the routing calculation unit will select the output interface that communicates directly with the target processing core as the second output interface. In this way, by using a specific data packet routing mechanism, it can be ensured that the data packet is accurately delivered to the corresponding processing core, avoiding unnecessary forwarding path selection by network devices and improving data transmission efficiency.

[0071] When the target node ID in the target information does not match the local ID of the second routing node, it indicates that the data packet should be processed at another routing node. Therefore, the data packet can be sent to another routing node.

[0072] The location information of a routing node refers to its coordinates or relative position within the overall network topology. In some implementations, the location information of a routing node can be implicitly represented by its ID. For example, in a 4×4 mesh network, a routing node with ID=5 might be located in the first row and second column. It is understood that the location information is known for the current routing node; for the target routing node, its location information can be carried in the data packet.

[0073] In some implementations, when the target routing node ID does not match the current routing node ID, the routing calculation unit will determine the next hop direction based on the relative position between the target routing node and the current routing node using a unified routing algorithm (such as XY routing) and select the corresponding output interface as the second output interface.

[0074] In some implementations, when the target routing node ID does not match the current routing node ID, the routing calculation unit will determine the next hop direction based on the absolute position between the target routing node and the current routing node using a unified routing algorithm (such as XY routing), and select the corresponding output interface as the second output interface.

[0075] In this embodiment, by combining local identifiers and target location information for dynamic routing decisions, routing calculation can be made adaptive to select paths for data packets without requiring manual configuration of routing rules for each node. This allows data packets to gradually approach the target node along the optimal path. This not only optimizes network resource utilization, thereby improving the throughput and response speed of the communication system, but also maintains the logical consistency of each routing node, thus enhancing overall flexibility and stability.

[0076] In some implementations, at least two routing nodes include at least one of the following: a third routing node adjacent to the left side of the second routing node, a fourth routing node adjacent to the right side of the second routing node, a fifth routing node adjacent to the upper side of the second routing node, and a sixth routing node adjacent to the lower side of the second routing node; the location information includes row information and column information; the routing calculation unit of the second routing node is further configured to, when the row information of the second routing node is the same as the row information of the target routing node, determine a first target routing node based on the column information of the second routing node and the column information of the target routing node, wherein the first target routing node includes either the third routing node or the fourth routing node; use the output interface communicating with the first target routing node as a second output interface; and determine the first target routing node based on the column information of the second routing node and the target routing node. If the column information of nodes is the same, a second target routing node is determined based on the row information of the second routing node and the row information of the target routing node. The second target routing node includes either the fifth or sixth routing node. The output interface communicating with the second target routing node is used as the second output interface. If the row information of the second routing node is different from that of the target routing node, and the column information of the second routing node is different from that of the target routing node, a third target routing node is determined based on the row information of the second routing node, the row information of the target routing node, the column information of the second routing node, and the column information of the target routing node. The third target routing node is either the third, fourth, fifth, or sixth routing node. The output interface communicating with the third target routing node is used as the second output interface.

[0077] Here, since the routing nodes of the on-chip network are connected according to the target topology, each routing node has at least one adjacent routing node around it.

[0078] When the row information of the second routing node matches that of the target routing node, it means that the second routing node and the target routing node are in the same row. In this case, the left and right directions are determined by comparing the column information of the two nodes. If the column information of the target routing node is greater than that of the second routing node, the fourth routing node adjacent to the right of the second routing node is selected; if the column information of the target routing node is less than that of the second routing node, the third routing node adjacent to the left of the second routing node is selected. This lateral path determination method ensures that data packets are transmitted along the correct lateral path, and can quickly determine the next-hop direction without using complex logic, thereby improving the overall communication efficiency and reducing the demand for hardware resources.

[0079] When the column information of the second routing node matches that of the target routing node, it means that the second routing node and the target routing node are in the same column. In this case, the vertical direction is determined by comparing their row information. If the row information of the target routing node is greater than that of the second routing node, the sixth routing node adjacent to the second routing node below it is selected; if the row information of the target routing node is less than that of the second routing node, the fifth routing node adjacent to the second routing node above it is selected. This routing strategy effectively avoids erroneous forwarding in the column direction, ensuring that data packets are transmitted along the correct vertical path, thereby improving stability and response speed.

[0080] When the row and column information of the source routing node (i.e., the second routing node) differs from that of the destination routing node, the relationship between the rows and columns needs to be considered comprehensively to determine the optimal path. In implementation, the next hop (i.e., the third destination routing node) can be determined by first comparing the row information and then comparing the column information, or by first comparing the column information and then comparing the row information.

[0081] In some implementations, the nearest neighboring routing node to the target routing node can be selected for packet forwarding based on their relative positions. For example, if the target routing node is located to the lower right, the better of the fourth and sixth routing nodes can be preferentially selected as the next hop. This enables efficient routing decisions between any non-aligned locations. For instance, if the location information of the second routing node is (2,2) and the location information of the target routing node is (4,1), then the location information of the third routing node is (2,1), the location information of the fourth routing node is (2,3), the location information of the fifth routing node is (1,2), and the location information of the sixth routing node is (3,2). Therefore, since the target routing node is located to the lower left of the second routing node, the better of the third and sixth routing nodes can be selected as the next hop.

[0082] In some implementations, the nearest neighboring routing node to the target routing node can be selected for packet forwarding based on the difference between the two. For example, if the location information of the second routing node is (2, 2) and the location information of the target routing node is (0, 1), then the better of the third or fifth routing node can be selected as the next hop based on the row difference of -2 and the column difference of -1.

[0083] During implementation, the system first determines whether the source and destination routing nodes are located in the same row or column, and then applies either a horizontal or vertical routing strategy based on the result. If the source and destination routing nodes are neither in the same row nor the same column, a comprehensive judgment mode is entered, and the optimal routing path is selected based on the position of the destination routing node relative to the current routing node. This hierarchical routing decision-making mechanism simplifies the routing logic. Furthermore, through a unified logic processing mechanism, good routing performance is maintained even in complex network topologies, ensuring that all routing nodes use the same logic processing method, thus achieving true isomorphic design.

[0084] The routing node also includes a crossbar switch, which enables physical connection switching between input and output ports, supporting multi-channel concurrent transmission. During implementation, once the second output interface is determined, the physical connection between the second input interface and the second output interface is established via this crossbar switch.

[0085] This routing node also includes an arbitrator, a control unit, etc. The arbitrator is used to determine which input interface's data packet has priority when multiple input interfaces compete for the same output interface. The control unit is used to coordinate and manage the work between the various units within the routing node.

[0086] In this embodiment, a routing strategy that incorporates row and column information is adopted to achieve more accurate routing decisions, enabling routing nodes to dynamically select the optimal path based on the target location, thereby improving data transmission efficiency and reducing network congestion risks.

[0087] Based on the foregoing embodiments, this application also provides a data processing method, applicable to any of the aforementioned on-chip networks. Figure 2 This is a schematic diagram illustrating the implementation flow of a data processing method provided in an embodiment of this application, such as... Figure 2 As shown, the data processing method includes steps S21 and S22, wherein: Step S21: During the initialization of the on-chip network, the first input interface of the first routing node receives the first identification signal; wherein, the first routing node is one of at least two routing nodes, and the first input interface is one of at least two input interfaces. Step S22: The identifier storage unit of the first routing node sets the identifier of the first routing node based on the first identifier signal.

[0088] Here, the first identification signal can be the second identification signal output by the first output interface of the previous routing node, or it can be a preset signal. The ID of the routing node can be any suitable form, such as numbers, letters, etc. In implementation, the process of setting this ID can be referred to the aforementioned on-chip system embodiment.

[0089] In this embodiment, on the one hand, by employing multiple homogeneous routing nodes in the on-chip network, all routing nodes achieve complete consistency in hardware structure and logical function. Compared with the heterogeneous design caused by address mapping differences in related technologies, firstly, this completely homogeneous modular design eliminates the problem of inconsistent logic among routing nodes in existing designs, enabling the on-chip system design to truly achieve modularity and standardization; secondly, since multiple routing nodes can reuse the same layout, the physical design of the on-chip network becomes simpler and more efficient. Moreover, the homogeneous routing nodes are completely consistent in area, shape, pin position, etc., which facilitates regular layout and routing on the chip plane, thereby greatly shortening the back-end design cycle and simplifying the back-end design. At the same time, since the timing convergence and power consumption heat distribution characteristics of each routing node are almost identical, it can reduce local congestion or heat dissipation problems caused by uneven distribution of different logic units, thereby improving overall performance and yield; thirdly, after adopting homogeneous routing nodes, only the function and timing of a single routing node need to be verified, instead of verifying them one by one, which greatly reduces the verification cost. On the other hand, during the on-chip network initialization process, a unique identifier is automatically assigned to each routing node through the identifier storage unit, a hardware unit, without manual configuration or software intervention. This not only improves allocation efficiency, reliability, and accuracy but also shortens startup time. Furthermore, compared to related technologies that require dedicated bus, controller, and interface logic configuration, it reduces area overhead and avoids heterogeneity issues caused by the interfaces themselves. Additionally, when adding or deleting routing nodes, identifier allocation can be automatically performed with a single initialization, without modifying the design of existing nodes or replanning address mappings, thus enhancing scalability and flexibility.

[0090] In some implementations, when the first routing node is the first routing node, the first identification signal is a preset signal; this step S22 includes: the identification storage unit of the first routing node sets the identification of the first routing node based on the preset signal within the first clock cycle.

[0091] In some implementations, the identifier of the first routing node is a preset signal.

[0092] In some implementations, when the first routing node is not the first routing node, the first identification signal is the second identification signal output by the first output interface of the previous routing node, and the previous routing node is connected to the first routing node; this step S22 includes: the identification storage unit of the first routing node sets the identification of the first routing node based on the second identification signal output by the first output interface of the previous routing node within one clock cycle; wherein, the identification of the first routing node is determined based on the second identification signal output by the first output interface of the previous routing node.

[0093] In some implementations, the data processing method further includes: when the first routing node is not the last routing node, the first output interface of the first routing node outputs a second identification signal to the first input interface of the next routing node; wherein the first output interface is one of at least two output interfaces, the second identification signal is determined based on the identification of the first routing node, and the next routing node is connected to the first routing node.

[0094] In some implementations, the second identification signal is the identifier of the first routing node.

[0095] In some implementations, the routing node further includes a routing calculation unit; after the on-chip network completes initialization, the data processing method further includes: the second input interface of the second routing node receives a data packet, the second routing node being one of at least two routing nodes, the second input interface being an input interface different from the first input interface among the at least two input interfaces, and the data packet including target information representing an identifier of the target routing node; the routing calculation unit of the second routing node determines a second output interface based on the target information and the identifier of the second routing node, the second output interface being an output interface different from the first output interface among the at least two output interfaces; the second output interface of the second routing node outputs the data packet to the target end, the target end being a routing node or a target processing core corresponding to the second routing node.

[0096] In some implementations, "the routing calculation unit of the second routing node determines the second output interface based on the target information and the identifier of the second routing node" includes: if the target information and the identifier of the second routing node are compatible, the output interface communicating with the target processing core is used as the second output interface; if the target information and the identifier of the second routing node are not compatible, the second output interface is determined based on the location information of the target routing node and the location information of the second routing node.

[0097] In some implementations, at least two routing nodes include at least one of the following: a third routing node adjacent to the left of the second routing node, a fourth routing node adjacent to the right of the second routing node, a fifth routing node adjacent to the upper side of the second routing node, and a sixth routing node adjacent to the lower side of the second routing node; the location information includes row information and column information; "determining the second output interface based on the location information of the target routing node and the location information of the second routing node" includes: if the row information of the second routing node is the same as the row information of the target routing node, determining a first target routing node based on the column information of the second routing node and the column information of the target routing node, and using the output interface communicating with the first target routing node as the second output interface, wherein the first target routing node includes the third routing node or the fourth routing node; in the second routing node... If the column information of a node is the same as that of the target routing node, a second target routing node is determined based on the row information of the second routing node and the row information of the target routing node. The output interface communicating with the second target routing node is used as the second output interface. The second target routing node may include a fifth routing node or a sixth routing node. If the row information of the second routing node is different from that of the target routing node, and the column information of the second routing node is different from that of the target routing node, a third target routing node is determined based on the row information of the second routing node, the row information of the target routing node, the column information of the second routing node, and the column information of the target routing node. The output interface communicating with the third target routing node is used as the second output interface. The third target routing node may be a third routing node, a fourth routing node, a fifth routing node, or a sixth routing node.

[0098] The description of the above method embodiments is similar to that of the above graphics processor embodiments, and has similar beneficial effects. For technical details not disclosed in the method embodiments of this application, please refer to the description of the graphics processor embodiments of this application for understanding.

[0099] The technical solution of this application is described in detail below. It is understood that in the following text, Router module, Router, router, router module, routing unit, etc., all refer to the routing node mentioned above.

[0100] In current embedded heterogeneous computing platforms, CPUs and GPUs typically share a unified off-chip DDR (Double Data Rate Synchronous Dynamic Random Access Memory). In existing on-chip distributed networks (such as Mesh-based NoCs), the address decoding and routing logic of each router node is usually customized based on the address range it is responsible for. This means that each router module often carries circuitry specific to its "coordinates" or address range. For example, in a classic XY-routing Mesh network, each router is assigned a unique coordinate (X, Y) or ID identifier. The destination address in the packet header contains the destination coordinates, and the router module determines the forwarding direction by comparing its local coordinates with the destination coordinates. Similarly, in on-chip system address mapping, different router modules are responsible for different address ranges. Typically, hardware compares the high-order bits of the address with the router's fixed identifier to determine whether the address belongs to a local resource or needs to be forwarded via the interconnection network. Because each routing unit is located in a different location, its address decoding logic contains different constants or parameters, which are often fixed during the RTL (Register-Transfer Level) design. This results in the logic circuits of each router module not being completely identical, forming a heterogeneous design, such as... Figure 3 As shown.

[0101] For each of the above-mentioned methods of fixed address mapping in router hardware, there are also related technologies that attempt to achieve more flexible address mapping schemes through software configuration, such as... Figure 4 As shown. For example, the interconnect architecture incorporates a software routing configuration mechanism: its on-chip network supports both fixed address mapping routes and routing directions determined by pre-configured software routing tables. This approach allows for dynamic setting of address mapping / routing rules by setting configuration registers or routing tables writable by the processor in each router module. During system initialization, the central processing unit writes the address mapping information of each router module into its configuration register, enabling network paths to be adjusted as needed.

[0102] The above technical solutions have obvious shortcomings: First, in traditional hardware fixed mapping ( Figure 3In the scheme shown, because each router module embeds local address constants or coordinates, its logic circuitry varies from node to node, making module-level reuse impossible. This means high design and verification costs: designers must customize or configure address decoding logic for each router node, and as the network scales up, customization becomes tedious and error-prone; verification also requires verifying the correctness of address mapping node by node. Physical implementation is difficult: due to the different logic of each router, it is not possible to simply copy and paste the same layout; the layout and routing of each node need to be optimized separately, increasing the workload of SoC backend design. Moreover, fixed mapping limits the scalability of the on-chip network: every time a node is added or adjusted, it may be necessary to reallocate address space for each router module and modify the address decoding logic of multiple router modules, resulting in poor flexibility.

[0103] Secondly, a software-configurable address mapping method is adopted ( Figure 4 The proposed solution improves flexibility to some extent, but still fails to achieve true homogeneity. This is because the introduction of a configuration interface leads to additional heterogeneity. Each router module, in addition to its normal data channel, requires an additional configuration register and related access logic to receive configuration instructions from the processor. This typically means adding a separate configuration bus or serial link to the on-chip network, along with corresponding decoding / selection circuitry to differentiate configuration operations for different routers. Since each router has a different address or location on the configuration bus, structural differences inevitably arise (e.g., one router's configuration enable signal only responds to a specific address range, while another router responds to a different address range). Therefore, although the behavior of all routers can be unified through software settings, the hardware structure is not entirely uniform. Furthermore, relying on software configuration introduces additional considerations regarding timing and reliability: after system power-on, all node address mappings must be correctly configured by software before the network can function properly; omissions or errors in the configuration process can lead to routing conflicts.

[0104] In summary, the relevant technologies have failed to provide a solution that allows for a completely isomorphic hardware implementation of the on-chip Internet of Things (IoNET) routing module.

[0105] The technical problem this application aims to solve is: how to provide a design method for an on-chip distributed interconnection system that ensures all router modules in the network are identical in structure and logic circuitry, while also guaranteeing that each module has a unique address identification capability, thereby correctly performing packet routing or address decoding. This technical solution needs to eliminate the module customization problems caused by address mapping differences in related technologies, achieving "copy and paste" at the router module level to simplify design verification and improve large-scale scalability.

[0106] The main objective of this application is to provide a homogeneous design method for on-chip distributed interconnect systems to overcome the aforementioned shortcomings in related technologies. This method ensures that all router modules in the on-chip network are completely identical in circuit structure and logical function, eliminating the need for customized address decoding logic or additional interface configuration for different nodes. This significantly reduces the design complexity and verification overhead of the SoC interconnect section and substantially improves system scalability. Without requiring manual configuration of each node's address mapping, the hardware automatically assigns a unique identifier to each router, enabling it to use unified logic to determine its routing decoding behavior, thus achieving the homogeneous design goal.

[0107] To achieve the above objectives, this application proposes a complete isomorphic design scheme, the core of which is to introduce an "ID increment register" module (corresponding to the aforementioned identifier storage unit) into each Router module, such as... Figure 5 ID register 51 (corresponding to the aforementioned identifier storage unit) is used to assign a unique identifier (ID) to the router during the system reset initialization phase. The key design idea is to utilize hardware timing control to ensure that the N on-chip Router modules sequentially obtain incrementing ID values ​​0, 1, ..., N-1 after reset. Specifically, all Routers can be connected in a certain topological order to form an ID link: after the global reset signal is released, the ID register of the first Router module is set to 0 in the first clock cycle. Then, this Router module sends a signal (i.e., the second identifier signal) or its incremented value (i.e., the second identifier signal) to the next Router module via the link; after receiving the signal from the first Router module, the second Router sets its own ID register to 1 in the second clock cycle; and so on, with the third Router setting its ID to 2 in the third clock cycle, ..., until the Nth Router obtains ID = N-1. Through this "step-by-step increment" process, each Router is automatically assigned a globally unique ID number.

[0108] All router modules have identical ID register circuits and associated control logic (i.e., packet forwarding logic). Therefore, the entire ID allocation process does not require any software intervention or special hardware processing for any particular router.

[0109] Several implementation methods can be used to ensure reliable and orderly ID allocation. For example, chained triggering can be used: each router has an input that waits for the "ID ready" signal (i.e., the second identification signal) from the preceding router. When this signal is detected, it sets the value of its own ID register to the preceding ID + 1 and continues to pass the signal to the next level. For the first router at the start of the link, global initialization logic can be used to ensure that it receives ID=0 by default after reset and starts chaining. It is worth emphasizing that this link control logic is a consistent circuit design for all router modules; only in actual connection, the preceding input of the first router is driven by the system initialization unit (equivalent to an additional trigger source). Overall, this scheme achieves pure hardware automatic enumeration of on-chip routing node IDs without relying on any external configuration through simple hardware sequence control.

[0110] Once the ID allocation is complete during the reset phase, each Router module possesses its own unique ID value. This ID is then fed as an input signal to the address decoding / routing logic module within the Router module. All Routers share the same decoding logic design: this logic determines whether the data packet terminates locally or is forwarded via which port (i.e., interface) based on the input destination address or destination ID field and the locally stored ID. For example, in a memory-mapped scenario, the global address space can be divided into several blocks, each corresponding to a Router ID. The decoding logic only needs to compare whether the high-order bits of the received address (representing the destination block ID) are equal to the local ID: if they match, the address belongs to the local node resource and is processed by this Router; if they do not match, the routing algorithm determines the direction for forwarding. Similarly, in packet routing scenarios (such as when the NoC routing header contains the destination node ID), the router can directly compare the destination node ID with the local ID: if they are equal, the data packet is sent to the local processing unit; otherwise, a unified routing algorithm is used to calculate the next-hop direction based on the difference or relative position between the two. In either case, the implementation involves using composable logic circuits to compare and perform calculations between the "target ID" and the "local ID" to determine the routing action. Since all routers have identical circuits, but different local IDs lead to different output behaviors, this perfectly achieves the goal of "homogeneous circuits, different behaviors".

[0111] exist Figure 5In this architecture, each Router module, in addition to the regular routing function unit, includes an ID increment register and a small amount of control logic. After system power-on reset, these ID increment register modules work in concert to assign a unique ID to each Router. Throughout this process, no manual differentiation of the Router hardware circuitry is required. After initialization, the on-chip network enters normal operation, with each Router participating in address decoding and routing decisions based on its ID. For example, in a Mesh network with 16 Router nodes, the ID register chain can be designed to connect all nodes in row-major order, automatically assigning IDs from 0 to 15 within 16 clock cycles after reset. Subsequently, all Routers execute XY routing algorithms or other routing algorithms based on a unified logic to determine the relationship between the destination ID of a data packet and its own ID. This allows for the simple replication of the same Router module to build the system, regardless of network size, with each module automatically recognizing its own identity upon power-on and thus performing its specific function.

[0112] To further clarify the solution of this application, the workflow and effect are described below with reference to a specific embodiment. Assume that a SoC integrates a 4×4 Mesh two-dimensional network interconnect with a total of 16 router nodes. The related design requires specifying the coordinates (e.g., (0, 0) to (3, 3)) for each router and embedding these coordinates in the hardware for route comparison; Using the method described in this application, all 16 Routers can be instantiated using the same RTL module. At the top level, these Routers are simply interconnected in a Mesh topology, and their ID register modules are linked together via a simple chained connection interface. Upon system reset, the chained interface controls ID allocation: the Router located in the upper left corner of the Mesh network, having no predecessor, has its ID register set to 0 in the first cycle and sends a "next ID request" signal to the Router to its right; immediately after receiving the request in the second cycle, the second Router sets its ID register to 1 and continues to pass the request to the next Router. Propagating in row priority, the IDs of all Routers are allocated in less than two microseconds (16 clock cycles, assuming a clock speed of 1 GHz). At this point, the ID of node (0,0) is 0, the ID of node (0,1) is 1, ..., the ID of node (3,3) is 15. It is worth noting that the chained connection here can share on-chip wiring resources with the Mesh data path; for example, it can utilize a pair of unused ports already present in each Router as a channel for serializing ID signals, thus eliminating the need for dedicated wiring.

[0113] After ID enumeration is complete, the entire Mesh network can begin normal communication. For a storage access request originating from a processor core (including the physical address), it is processed by a unified address decoding logic upon entering the Router: the high 4 bits of the address represent the target Router's ID, for example, 0x3xxx… means the target Router's ID = 3. If the high 4 bits are equal to the local Router's ID, it means the target is on this node, such as locally mounted memory or IP modules, and the Router sends the request to the local interface; if they are not equal, the Router uses the XY routing algorithm to determine whether to send the packet in the east / west / south / north direction based on the relationship between its own ID and the target Router's ID. A typical logic is: compare the row and column positions of the target Router's ID and the local ID; if the row number corresponding to the target Router's ID is greater than the local row number, send to the south; if it is less, send to the north; if the row numbers are equal, compare the column numbers, with the larger one sending to the east and the smaller one sending to the west. If the target ID is exactly equal to the local ID, it is routed to the Local port. The above judgment is entirely performed by hardwired logic, with the only difference being the unique "local ID" stored internally by each router. Because the design guarantees the uniqueness and continuity of the IDs, the routing algorithm can run correctly on all nodes without any differentiated configuration. This embodiment demonstrates that, using the solution of this application, on-chip networks of a scale such as a 16-node Mesh can be easily constructed, and regardless of changes in the number of nodes, there is no need to modify the internal design of the router module; simply replicate the number of nodes as needed.

[0114] The method provided in this application brings many beneficial effects and technical advantages: 1) Completely isomorphic modular design: All router nodes use the same circuit structure and logic, and can directly reuse the same module for expansion regardless of the increase in network size. This uniformity eliminates the problem of inconsistent logic among nodes in traditional designs, enabling NoC design to truly achieve modularity and standardization.

[0115] 2) Simplified Backend Design and Layout: Since multiple router nodes can be implemented using the same layout, SoC physical design becomes simpler and more efficient. Homogeneous router modules are completely identical in area, shape, and pin positions, facilitating regular array-style layout and routing on the chip plane. Designers no longer need to optimize the layout individually for each node, significantly shortening the backend design cycle. For large-scale multi-core chips, this translates to a significant reduction in design complexity and manufacturing risk.

[0116] 3) Reduced verification costs and improved reliability: With a homogeneous router, only the functionality and timing of a single module need to be verified to infer that all other replicated nodes also possess the same correctness, eliminating the need to verify the decoding logic of each node individually. This is particularly beneficial for address mapping / routing functions, as the unified logic reduces the possibility of errors. Furthermore, the automatic ID allocation mechanism is handled by hardware, avoiding manual configuration errors and improving the reliability of system initialization. Once the hardware circuitry is verified, there is no need to worry about functional deviations in newly added nodes when expanding to more nodes.

[0117] 4) Excellent scalability and flexibility: This solution supports on-chip network expansion as needed. When adding a router node, it only needs to connect to the ID link to automatically obtain a new unique ID, without modifying the design of existing nodes or replanning address mapping. Therefore, the SoC can easily expand from dozens of nodes to hundreds of nodes while maintaining the design architecture. This scalability provides support for future large-scale multi-core systems. In addition, since fixed addressing is not required, this solution is also suitable for some dynamic networking scenarios. In chip assembly or reconfigurable architectures, plug-and-play interconnection can be achieved through ID enumeration during reset.

[0118] 5) Low performance overhead: The ID increment register module occupies very few hardware resources, consisting only of some flip-flops and simple control logic, and its impact on the router area is negligible. The ID allocation process only occurs during the reset initialization phase, typically lasting N clock cycles (N being the number of nodes), which is negligible relative to the system runtime, thus causing no performance degradation for normal data transmission. Furthermore, compared to software configuration methods that require the processor to configure each node individually, this solution's automatic hardware allocation is much faster and more efficient.

[0119] In summary, the isomorphic design method of this application significantly improves the design quality and efficiency of on-chip distributed interconnect systems, making it possible to "use a single circuit design for seamless replication and expansion." This application assigns node IDs through a distributed, chain-like, auto-incrementing method, eliminating centralized control and parameter configuration and ensuring module consistency from the outset.

[0120] Compared with related technical solutions, the isomorphic design method of this application has significant technical advantages: Design simplification: No separate decoding logic or configuration method needs to be designed for each router node; only one type of router module is required for the entire network. Compared to traditional heterogeneous designs, this significantly reduces design complexity, allowing engineers to focus their efforts on optimizing a single module.

[0121] Significantly reduced verification workload: Because all nodes share a single set of logic, achieving "design once, reuse many times," verification personnel only need to perform functional and performance verification on one router module to extend it to the entire network. This saves a significant amount of verification time compared to manually customizing the logic for each node and also reduces the risk of missing errors.

[0122] Advantages of module reuse and scalability: This solution supports system expansion by simply replicating router modules, using the same circuitry for both 16 and 64 nodes. In contrast, traditional solutions often require redesigning address mappings or adding new configuration processes when expanding the number of nodes, resulting in high expansion costs. This application can linearly scale the network, exhibiting excellent scalability.

[0123] Reduced back-end physical design challenges: Since all router modules are homogeneous, back-end layout and routing can adopt a gridded and regular pattern, which is beneficial for global optimization such as clock distribution and signal integrity. The timing convergence and power consumption thermal distribution characteristics of each module are also almost identical, facilitating design margin management. Compared with heterogeneous module combinations, unified modules can avoid local congestion or heat dissipation problems caused by uneven distribution of different logic units, improving the overall chip performance and yield.

[0124] Avoiding configuration interface overhead and potential problems: Compared to software configuration schemes, this application eliminates the need for dedicated configuration buses and controllers, saving chip resources and reducing potential configuration errors or delays. Simultaneously, automatic hardware ID configuration enables interconnection and communication upon power-up, eliminating the need for software node-by-node initialization, thus shortening startup time and improving system reliability.

[0125] In summary, this application achieves an unprecedented modular homogeneous design while ensuring the integrity of on-chip network functionality. In large-scale chip design, this approach can significantly improve development efficiency and system reliability, demonstrating significant engineering value.

[0126] It should be noted that, in the embodiments of this application, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of software products. These software products are stored in a storage medium and include several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0127] This application provides a chip including any of the aforementioned on-chip networks. A chip is a semiconductor device that integrates multiple functional modules and is typically used to perform specific computing tasks or communication functions.

[0128] This application provides an electronic device including the aforementioned chip. The electronic device can be various types of terminals such as laptops, tablets, desktop computers, set-top boxes, and mobile devices (e.g., mobile phones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices), or it can be implemented as a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0129] It should be noted that the descriptions of the chip and device embodiments above are similar to those of the on-chip network embodiments above, and have similar beneficial effects. For technical details not disclosed in the chip and device embodiments of this application, please refer to the descriptions of the on-chip network embodiments of this application for understanding.

[0130] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0131] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0132] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0133] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0134] In addition, each functional unit in the embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0135] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0136] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0137] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A network-on-a-chip, characterized in that, It includes at least two homogeneous routing nodes, each routing node comprising an identifier storage unit, at least two input interfaces, and at least two output interfaces, the at least two routing nodes being interconnected according to a target topology; The first input interface of the first routing node is used to receive a first identification signal during the initialization process of the on-chip network; wherein the first routing node is one of the at least two routing nodes, and the first input interface is one of the at least two input interfaces. The identifier storage unit of the first routing node is used to set the identifier of the first routing node based on the first identifier signal.

2. The on-chip network according to claim 1, characterized in that, When the first routing node is the first routing node, the first identification signal is a preset signal; The identifier storage unit of the first routing node is also used to set the identifier of the first routing node based on the preset signal during the first clock cycle.

3. The on-chip network according to claim 2, characterized in that, The identifier of the first routing node is the preset signal.

4. The on-chip network according to claim 1, characterized in that, If the first routing node is not the first routing node, the first identification signal is the second identification signal output by the first output interface of the previous routing node, and the previous routing node is connected to the first routing node; The identifier storage unit of the first routing node is used to set the identifier of the first routing node based on the second identifier signal output by the first output interface of the previous routing node within one clock cycle.

5. The on-chip network according to claim 1, characterized in that, The first output interface of the first routing node is used to output a second identification signal to the first input interface of the next routing node when the first routing node is not the last routing node; wherein, the first output interface is one of the at least two output interfaces, the second identification signal is determined based on the identification of the first routing node, and the next routing node is connected to the first routing node.

6. The on-chip network according to claim 5, characterized in that, The second identification signal is the identifier of the first routing node.

7. The on-chip network according to any one of claims 1 to 6, characterized in that, The routing node also includes a routing calculation unit; after the on-chip network completes initialization... The second input interface of the second routing node is used to receive data packets; wherein the second routing node is one of the at least two routing nodes, the second input interface is an input interface that is different from the first input interface among the at least two input interfaces, and the data packet includes target information that represents the identifier of the target routing node; The routing calculation unit of the second routing node is used to determine the second output interface based on the target information and the identifier of the second routing node; wherein the second output interface is an output interface that is different from the first output interface among the at least two output interfaces; The second output interface of the second routing node is used to output the data packet to the target end; wherein the target end is a routing node or a target processing core corresponding to the second routing node.

8. The on-chip network according to claim 7, characterized in that, The routing calculation unit of the second routing node is also used for: If the target information matches the identifier of the second routing node, the output interface that communicates with the target processing core will be used as the second output interface. If the target information does not match the identifier of the second routing node, the second output interface is determined based on the location information of the target routing node and the location information of the second routing node.

9. The on-chip network according to claim 8, characterized in that, The at least two routing nodes include at least one of the following: a third routing node adjacent to the left side of the second routing node, a fourth routing node adjacent to the right side of the second routing node, a fifth routing node adjacent to the upper side of the second routing node, and a sixth routing node adjacent to the lower side of the second routing node; the location information includes row information and column information; the routing calculation unit of the second routing node is further used for: If the row information of the second routing node is the same as the row information of the target routing node, a first target routing node is determined based on the column information of the second routing node and the column information of the target routing node. The first target routing node includes the third routing node or the fourth routing node. The output interface that communicates with the first target routing node is used as the second output interface; If the column information of the second routing node is the same as the column information of the target routing node, a second target routing node is determined based on the row information of the second routing node and the row information of the target routing node. The second target routing node includes the fifth routing node or the sixth routing node. The output interface that communicates with the second target routing node is used as the second output interface; If the row information of the second routing node is different from the row information of the target routing node, and the column information of the second routing node is different from the column information of the target routing node, a third target routing node is determined based on the row information of the second routing node, the row information of the target routing node, the column information of the second routing node, and the column information of the target routing node. The third target routing node is the third routing node, the fourth routing node, the fifth routing node, or the sixth routing node. The output interface that communicates with the third target routing node is used as the second output interface.

10. A data processing method, characterized in that, The method is applied to an on-chip network, wherein the on-chip network includes at least two homogeneous routing nodes, each routing node including an identifier storage unit, at least two input interfaces, and at least two output interfaces, and the at least two routing nodes are interconnected according to a target topology; the data processing method includes: During the initialization of the on-chip network, the first input interface of the first routing node receives a first identification signal; wherein, the first routing node is one of the at least two routing nodes, and the first input interface is one of the at least two input interfaces; The identifier storage unit of the first routing node sets the identifier of the first routing node based on the first identifier signal.

11. The data processing method according to claim 10, characterized in that, When the first routing node is the first routing node, the first identification signal is a preset signal; The identifier storage unit of the first routing node sets the identifier of the first routing node based on the first identifier signal, including: the identifier storage unit of the first routing node sets the identifier of the first routing node based on the preset signal within the first clock cycle.

12. The data processing method according to claim 10, characterized in that, If the first routing node is not the first routing node, the first identification signal is the second identification signal output by the first output interface of the previous routing node, and the previous routing node is connected to the first routing node; The identifier storage unit of the first routing node sets the identifier of the first routing node based on the first identifier signal, including: within one clock cycle, the identifier storage unit of the first routing node sets the identifier of the first routing node based on the second identifier signal output by the first output interface of the previous routing node.

13. The data processing method according to any one of claims 10 to 12, characterized in that, After the on-chip network completes initialization, the data processing method further includes: The second input interface of the second routing node receives data packets; wherein the second routing node is one of the at least two routing nodes, the second input interface is an input interface that is different from the first input interface among the at least two input interfaces, and the data packet includes target information that represents the identifier of the target routing node; The routing calculation unit of the second routing node determines the second output interface based on the target information and the identifier of the second routing node; wherein, the second output interface is an output interface that is different from the first output interface among the at least two output interfaces; The second output interface of the second routing node outputs the data packet to the target end; wherein the target end is a routing node or a target processing core corresponding to the second routing node.

14. A chip, characterized in that, The on-chip network includes any one of claims 1 to 9.

15. An electronic device, characterized in that, Includes the chip described in claim 14.

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