Rapid vector diagram rasterization system based on circuit

Abstract

The invention discloses a rapid vector diagram rasterization system based on a circuit. In a vector diagram rasterization process, if a layout coverage area exceeds a single processing capability range of a rasterization processor, the whole layout coverage area needs to be divided into a plurality of independent processing areas called'frames', meanwhile, an original vector diagram covering a plurality of frames is cut into closed vector diagrams located in different frames, and then rasterization operation is completed step by step by taking the frames as units. Based on this, the whole process can be divided into three stages: 1) cutting all vector diagrams into closed vector diagrams located in different frames according to vertex coordinates of a single vector diagram; 2) calculating contour coordinates of all intra-frame closed vector diagrams, and sorting the contour coordinates according to a certain specified direction (row or column); and 3) according to the sorting result, performing intra-frame multi-row or multi-column parallel pixel filling according to a certain rule. Through the method, the vector diagram processing capability of a hardware circuit can be improved, on-chip cache resources can be greatly reduced, and vector image pixel filling can be rapidly completed.

Description

Technical Field

[0001] This invention belongs to the field of computer graphics, and particularly relates to a fast vector rasterization system, specifically a circuit-based fast vector rasterization system. Background Technology

[0002] In the field of computer graphics processing, converting vector graphic data into bitmap pixels is a fundamental and computationally intensive task. Traditional hardware rasterization processors typically need to load the entire coordinate data of the strip layout into an on-chip cache when processing vector graphics. This method places extremely high demands on cache capacity when dealing with large layout areas. Sequential boundary generation and filling processes are inefficient, limiting system throughput and making it difficult to meet the production efficiency requirements of real-time graphics generation.

[0003] Therefore, there is an urgent need for a filling scheme that can effectively segment and process data, reduce cache dependency, and support parallelization in order to improve the overall performance and productivity of graphics processing systems. Summary of the Invention

[0004] This application discloses a circuit-based fast vector rasterization system, which can improve the hardware circuit's ability to process vector graphics and greatly reduce on-chip cache resources, and quickly complete the filling of vector graphics pixels.

[0005] This invention discloses a circuit-based fast vector rasterization system, which includes a cropping and framing module, a contour generation module, and a pixel filling module.

[0006] The cropping and framing module is used to acquire a collection of multiple vector graphics data, divide it according to the preset independent processing area frames, and crop the collection of multiple vector graphics data into closed vector graphics located in different frames;

[0007] A frame is a regular sub-region with a fixed frame width, frame height, and coordinate range, obtained by dividing the overall coordinate space of the vector image to be rasterized.

[0008] The contour generation module calculates the contour coordinates of all closed vector graphics within the frame and sorts the pixels corresponding to the contour coordinates by row or column direction.

[0009] The pixel filling module performs parallel pixel filling of multiple rows or columns within the frame based on the sorting result of all contour pixels within the frame.

[0010] Furthermore, the cropping and framing module includes an intra-frame coordinate calculation unit;

[0011] The intra-frame coordinate calculation unit obtains a set of multiple vector graphics data from the host computer; among them, the integer part of the fixed-point number output by multiplying the x-coordinate of the vertex in the vector graphics data by the reciprocal of the frame width is the frame number of the current vector graphics vertex in the x direction, and the fractional part of the fixed-point number multiplied by the frame width is the x-coordinate of the vertex in the current frame;

[0012] The integer part of the fixed-point number output by multiplying the y-coordinate of a vertex by the reciprocal of the frame height is the frame number of the current vector vertex in the y direction, and the decimal part of the fixed-point number is multiplied by the frame height to obtain the y-coordinate of the vertex in the current frame.

[0013] The true frame number of the current vertex is obtained by multiplying the frame number of the strip horizontally by the frame number of the vertex in the y-direction and then adding it to the frame number of the current vertex in the x-direction.

[0014] After calculating the intra-frame coordinates and frame number, the intra-frame coordinate calculation unit determines whether the current intra-frame coordinates and the next intra-frame coordinates are in the same frame. If they are in different frames, it issues a cross-frame identifier, combines the coordinates of different frames into cross-frame coordinate pairs and corresponding frame number pairs, and outputs the single-frame intra-coordinates and corresponding frame number. If they are in the same frame, it only outputs the single-frame intra-coordinates and corresponding frame number.

[0015] Furthermore, the cropping and framing module includes an intersection point calculation unit;

[0016] The intersection calculation unit calculates the straight line equation between the coordinate pairs of the cross-frame line segments based on the vertex coordinate pairs; and calculates the cross-frame boundary based on the frame number of the start point and the frame number of the end point of the cross-frame line segment.

[0017] When a line segment exits a frame boundary, the intersection point with that frame boundary is the exit point; when a line segment enters a frame boundary, the intersection point with that frame boundary is the entry point; and coordinate pairs are generated for the intersection points of the line segment with all the frame boundaries it passes through.

[0018] Intersections are divided into non-continuous cross-frame intersections and continuous cross-frame intersections; among them, the intersection closest to the start point of the line segment and the intersection farthest from the start point of the line segment are non-continuous cross-frame intersections, and the other intersections are continuous cross-frame intersections.

[0019] Furthermore, the cropping and framing module includes an on-chip buffer unit for frame coordinates;

[0020] When storing vector coordinate data into the frame coordinate chip buffer unit, an identifier flag is added to the coordinate data; when the coordinate is the last coordinate point of the vector or the intersection of the outgoing frame, the identifier flag is set to 1; for other coordinate points, the identifier flag is set to 0.

[0021] The frame coordinate on-chip buffer unit includes a first coordinate on-chip buffer and a second coordinate on-chip buffer;

[0022] The first on-chip coordinate buffer is used to store the coordinates of non-continuous cross-frame intersection points and non-intersection point coordinates within a single frame; the first on-chip coordinate buffer is divided into several buffer space blocks, each buffer block contains several storage spaces to store the coordinate points of each vector map within the same frame; the final output is continuous coordinates within a single frame;

[0023] The second on-chip coordinate buffer is used to store the coordinates of consecutive cross-frame intersection points, and finally outputs the coordinates of consecutive cross-frame intersection points.

[0024] Furthermore, the contour generation module includes an endpoint pairing unit, a boundary generation selection unit, multiple boundary generation units, and multiple contour pixel memories;

[0025] The contour generation module obtains the coordinates of all vector graphics within a frame, performs vertex pairing on the current coordinate data through the endpoint pairing unit, forms endpoint coordinate pairs of each boundary line segment of the vector graphic contour, and transmits these coordinate pairs to the boundary generation selection unit.

[0026] The boundary generation selection unit is assigned a corresponding boundary generation unit based on the y-coordinate of the starting point in the endpoint coordinate pair.

[0027] Each boundary generation unit is used to generate the pixel coordinates of the vector outline within the assigned y-coordinate range;

[0028] Input the corresponding outline pixels into the outline pixel memory based on the outline pixel coordinates of the vector graphic.

[0029] Furthermore, the endpoint pairing unit performs vertex pairing by detecting the flag identifier in the coordinate data; if the detected vertex flag is 0, the current vertex is paired with the next input vertex and output; if the detected current vertex flag is 1, the current vertex is not paired with the next vertex and the endpoint coordinate pair is output.

[0030] Furthermore, each boundary generation unit is used to generate the vector image outline pixel coordinates within the assigned y-coordinate range; the remaining outline pixel coordinates that are not generated outside this range are generated by the adjacent boundary generation units in the direction outside the range.

[0031] Furthermore, the contour pixel memory includes n*m RAM storage spaces, where n is the number of boundary generation units and m is the number of rows processed by each boundary generation unit;

[0032] The depth of each RAM storage space is set to the frame width. The boundary generation unit outputs the outline pixel coordinates of the vector diagram. The corresponding RAM storage space is allocated according to the y-coordinate value of the outline pixel coordinates, and the storage address in the RAM storage space is allocated according to the x-coordinate value of the outline pixel coordinates. The outline pixel coordinates generated by the boundary generation unit are written to the corresponding address space storage value.

[0033] Furthermore, the pixel filling module simultaneously and sequentially reads the stored value of each space in each of the n*m ​​RAM storage spaces in parallel, generates n*m filling identifiers based on the outline pixel storage values, fills the corresponding areas according to the filling identifiers, and stores the pixel values ​​0 or 1 into the n*m ​​RAM filling storage spaces according to the corresponding addresses, thus realizing pixel filling of the entire frame of graphics. The beneficial effects achieved by this invention are:

[0034] This application discloses a circuit-based fast vector graphic rasterization system. The method divides the layout of the vector graphic to be rasterized into several independent processing regions called "frames." Then, the original vector graphic covering multiple frames is cropped into closed vector graphics located within different frames, and rasterization is completed step-by-step in units of "frames." Based on the vertex coordinates of the vector graphic, all vector graphics are cropped into closed vector graphics located in different frames. This cropping can be done in one step or multiple times. Frame-based processing improves the hardware circuit's processing capability for vector graphics and significantly reduces on-chip cache resources. Through one or more boundary generation units, the contour coordinates of all vector graphics within a frame are found, and a storage structure is built to quickly sort the coordinates within the same row or column. Based on the sorting result, starting from one end of the frame (top, bottom, left, right), the system scans simultaneously across multiple rows or columns and assigns values ​​according to certain rules to quickly fill pixels. The method described in this application significantly reduces the time required for vector graphic rasterization, thereby improving production efficiency. Attached Figure Description

[0035] Figure 1 This is an overall structural diagram of a circuit-based fast vector rasterization system according to an embodiment of the present invention.

[0036] Figure 2 This is an example of strip layout division according to an embodiment of the present invention.

[0037] Figure 3 This is an example of vector graphic cropping according to an embodiment of the present invention.

[0038] Figure 4 This is a cropping and frame-splitting structure diagram of an embodiment of the present invention.

[0039] Figure 5 This is a diagram illustrating the intra-frame coordinate calculation structure according to an embodiment of the present invention.

[0040] Figure 6 This is a diagram of the intersection calculation unit according to an embodiment of the present invention.

[0041] Figure 7 This is a cropped and stored coordinate data format according to an embodiment of the present invention.

[0042] Figure 8 This is an illustration of the coordinate storage format in the on-chip cache of frame coordinates according to an embodiment of the present invention.

[0043] Figure 9 This is a diagram of the on-chip cache structure for frame coordinates according to an embodiment of the present invention.

[0044] Figure 10 This is a contour generation structure diagram of an embodiment of the present invention.

[0045] Figure 11 This is a boundary generation unit selection structure diagram according to an embodiment of the present invention.

[0046] Figure 12 This is a flowchart of the hardware implementation of the Bresenham algorithm according to an embodiment of the present invention.

[0047] Figure 13 This is an example of vector graphic outline generation according to an embodiment of the present invention.

[0048] Figure 14 This is a structural diagram of the pixel filling process according to an embodiment of the present invention.

[0049] Figure 15 This is an example of vector graphic filling according to an embodiment of the present invention. Detailed Implementation

[0050] The present invention will be further described below with reference to specific embodiments, and the advantages and features of the present invention will become clearer as a result. However, these embodiments are merely exemplary and do not constitute any limitation on the scope of the present invention. Those skilled in the art should understand that modifications or substitutions can be made to the details and form of the technical solutions of the present invention without departing from the spirit and scope of the present invention, but all such modifications and substitutions fall within the protection scope of the present invention.

[0051] like Figure 1 As shown, this embodiment constructs a fast vector rasterization system based on circuit implementation. The system includes a cropping and framing module, a contour generation module, and a pixel filling module. The three modules operate in a staged pipeline manner.

[0052] In vector graphics rasterization, if the layout area exceeds the single-processing capacity of the rasterization processor, it needs to be divided into several independent processing regions called "frames." Simultaneously, the original vector graphics covering multiple frames are cropped into closed vector graphics located within different frames. This frame-by-frame rasterization operation is then completed step-by-step, thereby improving system processing capabilities and significantly reducing on-chip cache resource consumption. For example... Figure 2 As shown in (a), a layout with a size of 10240*8192 is divided into 32 frames, each with a size of 2560*1024; Figure 2As shown in (b), a layout with a size of 10240*8192 is divided into 8 frames, each with a size of 10240*1024.

[0053] For vector graphics spanning multiple frames, they need to be cropped. The cropping and framing module crops the vector graphic based on the coordinates of each vertex, resulting in the original vector graphic being divided into multiple new closed vector graphics stored in the storage space of each frame. For example... Figure 3 As shown, a vector graphic is cropped into three new vector graphics and divided into three different frames. This cropping can be done in one step or in multiple steps; this embodiment considers doing it in one step.

[0054] like Figure 4 As shown, the cropping and framing module includes an intra-frame coordinate calculation unit, an intersection point calculation unit, and an on-chip buffer unit for framing coordinates.

[0055] The coordinates of a portion of the strip data (a collection of multiple vector graphics data) are obtained from the host computer and stored in the on-chip buffer. When the clipping and framing module is idle, it retrieves the strip data from the on-chip buffer and obtains the vector coordinate data by parsing the strip data.

[0056] The intra-frame coordinate calculation unit calculates the intra-frame coordinates of the coordinates in the vector map coordinate data within a preset frame, and determines whether the current coordinate and the next coordinate are in the same frame.

[0057] The vector map coordinate data is transmitted to the intra-frame coordinate calculation unit. This module calculates the coordinates and frame number of the vector map within a single frame after it has been framed, and determines whether the current coordinate and the next coordinate are in the same frame. If they are in the same frame, the intra-frame coordinates and frame number of the current vector map are transmitted to the on-chip buffer unit for the framed coordinates. If they are in different frames, the intra-frame coordinates and frame number of the current vector map are transmitted to the on-chip buffer unit for the framed coordinates, and the cross-frame flag is raised for one clock cycle to indicate that the current coordinate and the next coordinate are in different frames. If the current coordinate and the next coordinate belong to the same vector map, the cross-frame coordinate pair formed by the current coordinate point and the next coordinate point, along with the corresponding frame number, is transmitted to the intersection calculation unit, which then calculates the intersection point of the cross-frame line segment of the vector map with the boundary of the frame it crosses. When the intersection buffer of the intersection calculation unit is about to be full, or before the on-chip buffer unit for the framed coordinates needs to send continuous intra-frame coordinate data (including the coordinate data of the frame containing the original vertices of the vector map) to the off-chip buffer, the intersection points buffered by the unit are transmitted to the on-chip buffer unit for the framed coordinates.

[0058] like Figure 5As shown, multiplying the "x-coordinate" of the vector graphic by the "reciprocal of the frame width" yields a fixed-point number. The integer part of this fixed-point number is the frame number of the current vector graphic vertex in the x-direction, and the decimal part is multiplied by the frame width to obtain the x-coordinate of that vertex within the current frame. Similarly, multiplying the "y-coordinate" of the vector graphic by the "reciprocal of the frame height" yields a fixed-point number. The integer part of this fixed-point number is the frame number of the current vector graphic vertex in the y-direction, and the decimal part is multiplied by the frame height to obtain the y-coordinate of that vertex within the current frame. Multiplying the frame number of the current vertex in the y-direction by the number of horizontal frames of the strip, and then adding this to the frame number of the current vertex in the x-direction, yields the true frame number of the current vertex. If the frame number of the current vertex differs from the frame number of the next vertex, it is determined that the line segment has crossed frames. The frame crossing marker is raised for one clock cycle, and the frame crossing coordinate pair is output.

[0059] like Figure 6 As shown, the intersection point calculation unit's processing flow is as follows: The cross-frame coordinate pair ((x0, y0), (x1, y1)) and the corresponding frame number (id0, id1) are first entered into the unit's input buffer. Once the subsequent intersection point calculation is idle, a set of cross-frame coordinate pairs and the corresponding frame numbers are read to begin calculation. The line equation of the line segment is calculated based on the cross-frame line segment vertex coordinate pair. The frame boundary spanned by the cross-frame line segment is calculated based on the frame number of the starting point (id0) and the frame number of the ending point (id1). Intersection points are calculated sequentially based on the line equation and frame boundary coordinates. For any cross-frame line segment (i.e., a line segment whose two endpoints are located in different frames), the intersection points of this line segment with all the frame boundaries it crosses need to be calculated. Specifically, this includes: the intersection point (out frame point) where the line segment exits the starting frame (the frame containing the starting point of the cross-frame line segment); the intersection point (in frame point) where the line segment enters the ending frame (the frame containing the ending point of the cross-frame line segment); and the intersection points with all intermediate frame boundaries when the line segment crosses more than two frames. These intersection points are categorized into two types based on their distance from the starting point of the line segment: ① Non-contiguous cross-frame intersection points: the intersection point closest to the starting point and the intersection point farthest from the starting point; ② Contiguous cross-frame intersection points: all other intersection points except for those not contiguous cross-frame intersection points. After calculating the intersection point coordinates, the intersection point closest to the starting point and the farthest intersection point are stored sequentially in a FIFO5 buffer (First-In-First-Out memory), and the contiguous cross-frame intersection points are output to the on-chip buffer unit for the frame coordinates in order of distance from the starting point to the farthest point.

[0060] When storing vector coordinate data into the frame-by-frame coordinate chip buffer, add an identifier flag to the coordinate data;

[0061] like Figure 7 As shown, an identifier flag is added to the coordinate data to facilitate subsequent vertex coordinate pairing; identifier flag:

[0062] 1: The last coordinate point or the intersection point of a vector map;

[0063] 0: Other coordinate points.

[0064] The frame-segmented coordinate on-chip cache unit constructs an on-chip cache structure for separately storing the coordinate data of the new vector map within each frame after partial framing, and then outputting it to the off-chip cache storage area for each frame.

[0065] like Figure 8 As shown, the frame-segmented coordinate on-chip buffer unit uses two sets of on-chip buffers to store vector map coordinate data. Coordinate on-chip buffer 1 is divided into several buffer space blocks, each containing several storage spaces to store coordinate points within the same frame of each vector map. When the first non-intersecting coordinate within a single frame of a set of vector map data (the vector map data processed from when the data volume stored in coordinate on-chip buffer 1 is 0 until the buffer volume of coordinate on-chip buffer 1 reaches a threshold and needs to be transferred to an off-chip buffer) enters this unit, an empty buffer block is allocated for it. Subsequent vertices within the same frame are stored in this buffer block. If subsequent cross-frame coordinates appear, a new buffer block is allocated for them, and subsequent non-cross-frame coordinates are stored in this buffer block. If the storage space of this buffer block is exceeded, a new continuation buffer block is allocated for the frame data. Coordinate on-chip buffer 2 is divided into several buffer space blocks, each containing storage space for two coordinates, used to store consecutive cross-frame intersection coordinate pairs.

[0066] like Figure 9As shown. When processing a set of vector map data, the first step is to input the non-intersecting coordinates within a single frame of the frame-slicing buffer unit. When inputting non-intersecting coordinates within a single frame, a raised first-point marker indicates that the current coordinate point is the first point of the current group of vector map data; a raised cross-frame marker indicates that the next coordinate point is not in the same frame as the current coordinate point; and a raised last-point marker indicates that the current coordinate point is the last point of the current group of vector map data. When cross-frame coordinates occur, the address following the starting point of the cross-frame line segment is recorded as the outgoing frame point address and stored in FIFO_0. The address preceding the last point address in the buffer block containing the last point of the cross-frame line segment (the first address of the new buffer block during the cross-frame process) is recorded as the incoming frame point address and stored in FIFO_1. When the amount of data stored in coordinate on-chip cache 1 reaches a threshold or the intersection calculation unit's non-contiguous cross-frame intersection cache is about to fill, the non-contiguous cross-frame intersection coordinates in the intersection calculation unit are read. Simultaneously, the addresses in the corresponding FIFO_0 and FIFO_1 are read, and the non-contiguous cross-frame intersection coordinates are stored in the corresponding coordinate on-chip cache 1 address space. For continuous cross-frame intersection coordinates of cross-frame line segments, additional storage space—coordinate on-chip cache 2—is allocated. When a non-intersection coordinate enters the first single frame of the current frame, the first address of the current cache block is stored in FIFO_2 as the starting address of the current frame's on-chip frame storage. The first address of the current cache block includes two cases: ① the storage address of the first coordinate in each group of vector data; ② the storage address of the in-frame coordinate of each cross-frame. When a non-intersection coordinate enters the last single frame of the current frame, the last address actually stored in the current frame is stored in FIFO_3 as the ending address of the current frame's on-chip frame storage. The last address of the current frame includes two cases: ① the storage address of the last coordinate in each group of vector data; ② the storage address of the out-frame coordinate of each cross-frame. The start and end addresses in FIFO_2 and FIFO_3 correspond one-to-one with the frame numbers in FIFO_4; each cache block in on-chip cache 2 stores the coordinates of two consecutive cross-frame intersection points and each cache block corresponds one-to-one with the frame number in FIFO_5.

[0067] Sending coordinate data to the off-chip cache is divided into two cases: sending continuous coordinate data within a single frame and sending continuous cross-frame intersection coordinate data. When the on-chip cache 1 reaches its storage threshold, it begins sending continuous coordinate data within a single frame to the off-chip cache. At this time, the coordinate data in the corresponding storage space of the on-chip cache 1 is read out according to the start and end addresses of each frame cached in FIFO_2 and FIFO_3. The start address of the corresponding frame storage space in the off-chip cache is read out according to the frame sequence number read out of FIFO_4. The data storage address in the off-chip cache is calculated according to this start address, and then the corresponding frame data of the on-chip cache 1 is stored in the corresponding storage space of the off-chip cache. When the on-chip cache 2 reaches its storage threshold, it sends continuous cross-frame intersection coordinate data to the off-chip cache. The start address of the corresponding frame storage space in the off-chip cache is read out according to the frame sequence number read out of FIFO_5. At the same time, the data of the corresponding frame in the on-chip cache 2 is read out. The data storage address in the off-chip cache is calculated according to this start address, and then the corresponding frame data of the on-chip cache 2 is stored in the corresponding storage space of the off-chip cache. When each frame of data is stored in the on-chip cache and then transferred to the off-chip cache, the starting address of each frame in the off-chip cache is updated according to the amount of data stored, so that it can be used when accessing the storage space of that frame in the off-chip cache next time.

[0068] like Figure 10 As shown, the contour generation module quickly finds the contour coordinates of all vector graphics within a frame through one or more boundary generation units, and builds a storage structure to quickly sort the contour pixels along the axis (within the same row or column).

[0069] Contour generation for a strip begins when the processing of a single frame is complete and both the contour generation and pixel filling modules are idle. First, all vector coordinates within a frame are retrieved from the off-chip buffer and stored in the on-chip buffer. Once the contour generation module is idle, the vector coordinate data is read. Vertex pairing is performed on the current coordinate data to form endpoint coordinate pairs for each boundary segment of the vector contour. These coordinate pairs are then transmitted to the boundary generation selection unit. The boundary generation selection unit allocates a suitable boundary generation unit for boundary generation based on the magnitude of the starting point y-coordinate (y1 in endpoint coordinate pairs (x1, y1), (x2, y2)) and the idle status of the boundary generation unit. The boundary generation unit generates all coordinates of each point on the line segment using the two endpoint coordinates. Each boundary generation unit is allocated a certain calculation range in the y-coordinate direction. When storing the pixels corresponding to the contour coordinates generated by the boundary generation unit, corresponding RAM (random access memory) is allocated based on their y-coordinates. During boundary generation, if a generated line segment reaches the y-coordinate range boundary of the current boundary generation unit before the current line segment generation is complete, the endpoint coordinates and intermediate parameters of the line segment are transmitted to the nearest boundary generation unit in the direction exceeding the line segment range for further boundary generation, until the line segment boundary generation is complete. A contour pixel memory structure is designed to write the contour coordinates generated by the boundary generation unit into the corresponding address space for storage. This structure enables the rapid generation, storage, and sorting of contour pixel coordinates for all vector graphics within a frame.

[0070] All vector coordinates within a frame are retrieved from the off-chip buffer and stored in the on-chip buffer. Once the vector outline generation module is idle, it begins reading the vector coordinate data.

[0071] After acquiring the vector coordinate data, vertex pairing is performed by detecting the flag identifiers in the coordinate data. If a vertex flag of 0 is detected, the current vertex is paired with the next input vertex for output; if a vertex flag of 1 is detected, the current vertex is not paired with the next vertex for output.

[0072] like Figure 11As shown, it mainly consists of n sets of registers and an on-chip buffer FIFO. Paired endpoint coordinates are input from the endpoint pairing unit. These pairs sequentially enter the register sets. If the starting point y-coordinate of the current coordinate pair is within the y-value range of the boundary generation unit corresponding to the current register set and the boundary generation unit is idle, the current coordinate pair is output to the corresponding boundary generation unit; otherwise, it is output to the next register set. This process continues in a pipelined manner. If a coordinate pair is not output after one round of n sets of register set transmission, it is transmitted to the FIFO. When the FIFO is nearly full (i.e., the number of coordinate pairs buffered in that unit reaches a certain threshold), the endpoint pairing unit stops inputting coordinate pairs, and the input of register set 0 switches to the output of the FIFO. After all endpoint coordinate pairs in the FIFO have been output, the input interface of register set 0 switches back to the output of the endpoint pairing unit to resume accepting paired vertices.

[0073] The boundary generation unit uses the Bresenham algorithm, which is fast and only involves addition and subtraction operations, consuming fewer resources. The hardware implementation flowchart of the Bresenham algorithm is shown below. Figure 12 As shown, after generating cells for the input boundary coordinates, the system first determines whether to swap the roles of the x and y axes based on the absolute values ​​of the differences between two points (x1, y1) and (x2, y2), |y2-y1| and |x2-x1|. This is done to select a more suitable step size reference to ensure the accuracy of line drawing. If |y2-y1| < |x2-x1|, it means the absolute value of the line slope is less than 1. In this case, the x-axis direction should be chosen as the main stepping direction, and there is no need to swap the roles of x and y. Conversely, if |y2-y1| ≥ |x2-x1|, the absolute value of the line slope is greater than or equal to 1. In this case, the y-axis direction is more suitable as the main stepping direction, and the roles of x and y need to be swapped to simplify the calculation. Next, calculate the following key parameters: ①∆x = |x2 - x1|; ②∆y = |y2 - y1|; ③2∆y; ④2∆y - 2∆x; ⑤ Initial decision parameter p0 = 2∆y - ∆x. Then, in the process of drawing the straight line, use the decision parameter p0. k (k ranges from 0 to ∆x) to determine the position of the next point: if p k If < 0, then the y-coordinate of the next point remains unchanged, i.e., y k+1 = y k And update the decision parameter to p. k+1 = p k + 2∆y. If p k If ≥ 0, then the y-coordinate of the next point increases by 1 (or decreases by 1, depending on the relative positions of the starting and ending points), i.e., y...k+1 = y k ± 1, and simultaneously update the decision parameter to p. k+1 = p k + 2∆y - 2∆x. Finally, based on whether the x-axis and y-axis were swapped previously, it is determined whether the final output coordinates need to be swapped again to ensure that the final drawn line conforms to the expected direction and position. Each boundary generation unit is configured with a certain range of computation space in the y-direction. The remaining line segments outside this range that are not generated are generated by the adjacent boundary generation units in the direction outside the range. Therefore, each boundary generation unit sets up two sets of FIFOs to store the vertex coordinates and intermediate parameters from the adjacent boundary generation units. When the current line segment generation is completed and the FIFO is not empty, a set of data is read from the FIFO to continue boundary generation until both sets of FIFO are empty, after which the coordinate pairs output by the boundary generation selection unit can be accepted.

[0074] like Figure 10 As shown, in this embodiment, boundary generation is performed in row form, and the same principle is applied when using column form. For a frame containing n*m rows, RAM0_0, ..., RAM0_m-1, ..., RAM0_(n-1)m, RAM0_n*m-1 constitute the frame pixel mapping storage space. Each RAM corresponds to a row of frame pixel data storage space, meaning the depth of each RAM is set to the frame width. The boundary generation unit outputs the vector graphic contour pixel coordinates. Based on the y-coordinate value of the contour pixel coordinates, it allocates the corresponding RAM and the x-coordinate value, respectively. The boundary generation unit generates contour coordinates and writes them into the corresponding address space for storage. This storage method enables rapid sorting of contour pixels with the same y-coordinate value in the frame. The vector graphic contour generation effect is shown below. Figure 13 As shown.

[0075] The pixel filling module, based on the sorting results, starts from one end of the frame (top, bottom, left, or right) and simultaneously scans across multiple rows or columns, assigning values ​​according to certain rules to quickly fill pixels. This embodiment considers scanning all rows contained within the frame in parallel, starting from the left end.

[0076] like Figure 14As shown, RAM1_0, RAM1_1, ..., RAM1_(n-1)m, RAM1_n*m-1 also constitute the frame pixel mapping storage space, with the depth of each RAM set to the frame width. After the contour pixels of all graphics in a frame are generated, the stored values ​​of each space in each memory are read simultaneously and sequentially from RAM0_0, RAM0_1, ..., RAM0_(n-1)m, RAM0_n*m-1. Based on the stored values ​​of several pairs of contour pixels representing the graphic contours in the current frame, n*m fill identifiers are generated. The pixel data of the corresponding area is filled according to the fill identifiers, and the generated pixel data is stored in RAM1_0, RAM1_1, ..., RAM1_(n-1)m, RAM1_n*m-1 according to the corresponding addresses. After the entire frame data is filled, the pixel data of the frame is transferred to the corresponding storage space of the off-chip cache. An example of vector graphic filling is shown below. Figure 15 As shown.

[0077] The strip pixel data is read frame by frame from the off-chip buffer for use by subsequent devices.

[0078] This embodiment constructs a circuit-based vector rasterization system, which mainly consists of three modules: clipping and framing, contour generation, and pixel filling. The clipping and framing module divides the layout of the vector image to be rasterized into N regions of equal size, where N≥2; these regions are called frames. Based on the vertex coordinates of the vector images, all vector images are clipped into new vector images located in different frames. Clipping and framing the vector images improves the hardware circuit's processing capability for vector images and significantly reduces on-chip cache resources. The contour generation module quickly finds the contour coordinates of all vector images within a frame using multiple boundary generation units and builds a storage structure to quickly sort pixels within the same row. The pixel filling module, based on the sorting results, scans simultaneously across multiple rows starting from the left end of the frame and assigns values ​​according to certain rules to quickly fill pixels. The vector rasterization system proposed in this embodiment significantly reduces the time required for vector image rasterization, thereby improving production efficiency.

[0079] The steps in this application can be rearranged, combined, or deleted according to actual needs.

[0080] The units in the device of this application can be merged, divided, or deleted according to actual needs.

[0081] Although this application has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of this application. The scope of protection of this application is defined by the appended claims and may include various modifications, alterations, and equivalents of the invention without departing from the scope and spirit of this application.

Claims

1. A circuit-based fast vector rasterization system, characterized in that, The circuit-based fast vector rasterization system includes a cropping and framing module, a contour generation module, and a pixel filling module. The cropping and framing module is used to acquire a collection of multiple vector graphics data, divide it according to the preset independent processing area frames, and crop the collection of multiple vector graphics data into closed vector graphics located in different frames; A frame is a regular sub-region with a fixed frame width, frame height, and coordinate range, obtained by dividing the overall coordinate space of the vector image to be rasterized. The contour generation module calculates the contour coordinates of all closed vector graphics within the frame and sorts the pixels corresponding to the contour coordinates by row or column direction. The pixel filling module performs parallel pixel filling of multiple rows or columns within the frame based on the sorting result of all contour pixels within the frame.

2. The circuit-based fast vector rasterization system according to claim 1, characterized in that, The cropping and framing module includes an intra-frame coordinate calculation unit; The intra-frame coordinate calculation unit obtains a set of multiple vector graphics data from the host computer; among them, the integer part of the fixed-point number output by multiplying the x-coordinate of the vertex in the vector graphics data by the reciprocal of the frame width is the frame number of the current vector graphics vertex in the x direction, and the fractional part of the fixed-point number multiplied by the frame width is the x-coordinate of the vertex in the current frame; The integer part of the fixed-point number output by multiplying the y-coordinate of a vertex by the reciprocal of the frame height is the frame number of the current vector vertex in the y direction, and the decimal part of the fixed-point number is multiplied by the frame height to obtain the y-coordinate of the vertex in the current frame. The true frame number of the current vertex is obtained by multiplying the frame number of the strip horizontally by the frame number of the vertex in the y-direction and then adding it to the frame number of the current vertex in the x-direction. After calculating the intra-frame coordinates and frame number, the intra-frame coordinate calculation unit determines whether the current intra-frame coordinates and the next intra-frame coordinates are in the same frame. If they are in different frames, it issues a cross-frame identifier, combines the coordinates of different frames into cross-frame coordinate pairs and corresponding frame number pairs, and outputs the single-frame intra-coordinates and corresponding frame number. If they are in the same frame, it only outputs the single-frame intra-coordinates and corresponding frame number.

3. The circuit-based fast vector rasterization system according to claim 1, characterized in that, The cropping and framing module includes an intersection point calculation unit; The intersection calculation unit calculates the straight line equation between the coordinate pairs of the cross-frame line segments based on the vertex coordinate pairs; and calculates the cross-frame boundary based on the frame number of the start point and the frame number of the end point of the cross-frame line segment. When a line segment exits a frame boundary, the intersection point with that frame boundary is the exit point; when a line segment enters a frame boundary, the intersection point with that frame boundary is the entry point; and coordinate pairs are generated for the intersection points of the line segment with all the frame boundaries it passes through. Intersections are divided into non-continuous cross-frame intersections and continuous cross-frame intersections; among them, the intersection closest to the start point of the line segment and the intersection farthest from the start point of the line segment are non-continuous cross-frame intersections, and the other intersections are continuous cross-frame intersections.

4. The circuit-based fast vector rasterization system according to claim 1, characterized in that, The cropping and framing module includes an on-chip buffer unit for frame coordinates; When storing vector coordinate data into the frame coordinate chip buffer unit, an identifier flag is added to the coordinate data; when the coordinate is the last coordinate point of the vector or the intersection of the outgoing frame, the identifier flag is set to 1; for other coordinate points, the identifier flag is set to 0. The frame coordinate on-chip buffer unit includes a first coordinate on-chip buffer and a second coordinate on-chip buffer; The first on-chip coordinate buffer is used to store the coordinates of non-continuous cross-frame intersection points and non-intersection point coordinates within a single frame; the first on-chip coordinate buffer is divided into several buffer space blocks, each buffer block contains several storage spaces to store the coordinate points of each vector map within the same frame; the final output is continuous coordinates within a single frame; The second on-chip coordinate buffer is used to store the coordinates of consecutive cross-frame intersections, and finally outputs the coordinates of consecutive cross-frame intersections.

5. The circuit-based fast vector rasterization system according to claim 1, characterized in that, The contour generation module includes an endpoint pairing unit, a boundary generation selection unit, multiple boundary generation units, and multiple contour pixel memories; The contour generation module obtains the coordinates of all vector graphics within a frame, performs vertex pairing on the current coordinate data through the endpoint pairing unit, forms endpoint coordinate pairs of each boundary line segment of the vector graphic contour, and transmits these coordinate pairs to the boundary generation selection unit. The boundary generation selection unit is assigned a corresponding boundary generation unit based on the y-coordinate of the starting point in the endpoint coordinate pair. Each boundary generation unit is used to generate the pixel coordinates of the vector outline within the assigned y-coordinate range; Input the corresponding outline pixels into the outline pixel memory based on the outline pixel coordinates of the vector graphic.

6. The circuit-based fast vector rasterization system according to claim 5, characterized in that, The endpoint pairing unit performs vertex pairing by detecting the flag identifier in the coordinate data; if the detected vertex flag is 0, the current vertex is paired with the next input vertex and output. If the current vertex is detected to be 1, then the current vertex and the next vertex will not be paired to output endpoint coordinate pairs.

7. The circuit-based fast vector rasterization system according to claim 5, characterized in that, Each boundary generation unit is used to generate the vector image outline pixel coordinates within the assigned y-coordinate range; the remaining outline pixel coordinates that are not generated outside this range are generated by the adjacent boundary generation units in the direction outside the range.

8. The circuit-based fast vector rasterization system according to claim 5, characterized in that, The contour pixel memory includes n*m RAM storage spaces, where n is the number of boundary generation units and m is the number of rows processed by each boundary generation unit; The depth of each RAM storage space is set to the frame width. The boundary generation unit outputs the outline pixel coordinates of the vector diagram. The corresponding RAM storage space is allocated according to the y-coordinate value of the outline pixel coordinates, and the storage address in the RAM storage space is allocated according to the x-coordinate value of the outline pixel coordinates. The outline pixel coordinates generated by the boundary generation unit are written to the corresponding address space storage value.

9. The circuit-based fast vector rasterization system according to claim 8, characterized in that, The pixel filling module reads the stored value of each space in each memory from n*m RAM storage spaces simultaneously and sequentially, generates n*m filling identifiers based on the outline pixel storage value, fills the corresponding area according to the filling identifiers, and stores the pixel value 0 or 1 into the n*m ​​RAM filling storage space according to the corresponding address, thus realizing pixel filling of the entire frame of graphics.

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