Grid driving circuit, grid driving unit and display device
By adding a clock signal terminal and a negative voltage signal terminal to the gate drive circuit of the OLED display device, the operating state of the NMOS transistor and capacitor is controlled, the problem of unstable signal transmission is solved, and a better display effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
- Filing Date
- 2024-11-15
- Publication Date
- 2026-05-15
AI Technical Summary
The gate driving circuit of existing OLED display devices suffers from unstable voltage signals during signal transmission, resulting in poor display performance.
By adding clock signal terminals and negative voltage signal terminals, and controlling the operating states of NMOS transistors and capacitors, different potential level signals can be output, thereby improving signal stability.
It provides a more stable voltage signal output, improving the display effect of OLED display devices.
Smart Images
Figure CN122050307A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit, its unit, and a display device. Background Technology
[0002] Compared to traditional liquid crystal display devices, organic light-emitting diode (OLED) display devices have advantages such as faster response speed, better color purity and brightness, higher contrast, and wider viewing angle, and therefore have gradually gained increasing attention from display technology developers.
[0003] Among them, the Gate Driver on Array (GOA) technology integrates the gate switching circuit of the thin-film transistor (TFT) onto the array substrate of the display device to form a gate driver for the display device.
[0004] like Figure 1 The diagram illustrates a gate driving circuit of the related art. The gate driving circuit typically consists of multiple cascaded gate driving circuit units, each connected to a scan gate line. Furthermore, in two cascaded gate driving circuit units, the output signal of the preceding stage gate driving circuit unit serves as the input signal for the following stage gate driving circuit unit.
[0005] During the operation of an OLED display device, the input signal is converted into an on / off driving signal by the gate driving circuit unit and then applied sequentially to the scanning gate lines of each row of pixels in the OLED display device to select each row of pixels and achieve display refresh.
[0006] like Figure 1 As shown, each stage of the gate drive circuit passes down step by step, and the drive signal output by each stage is passed to the AA area in the current row. Therefore, both high and low voltage signals will be passed to the AA area.
[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0008] In view of the problems in the prior art, the purpose of the present invention is to provide a gate driving circuit and its unit display device, which overcomes the difficulties of the prior art and can provide a good display effect.
[0009] The first aspect of this disclosure provides a gate driving circuit unit, which includes:
[0010] The first input module is connected to the positive voltage signal terminal and the first node, and is used to write the positive voltage signal of the positive voltage signal terminal into the first node under the control of the second clock signal terminal.
[0011] A first NMOS transistor and a first capacitor, wherein the first NMOS transistor is connected to a second negative voltage signal terminal and a signal output terminal, and is used to input a second negative voltage signal from the second negative voltage signal terminal to the signal output terminal under the control of the positive voltage signal, wherein the first capacitor is connected to the first negative voltage signal terminal and the first node;
[0012] The second input module is connected to the signal input terminal and the second node, and is used to input the input signal of the signal input terminal to the second node under the control of the second clock signal terminal;
[0013] The second NMOS transistor and the second capacitor are connected to the second node and the signal output terminal. The second capacitor is used to store the input signal written to the second node. The second NMOS transistor is connected to the third clock signal terminal and the signal output terminal. Under the control of the input signal written to the second node and the input signal stored in the second capacitor, the corresponding potential of the third clock signal terminal is input to the signal output terminal.
[0014] A first control module, connected to a first negative voltage signal terminal and a second node, is used to write a first negative voltage signal from the first negative voltage signal terminal to the second node under the control of the first node and a first clock signal terminal, so that the second NMOS transistor blocks the third clock signal terminal from the signal output terminal under the control of the first negative voltage signal. The clock signals connected to the first clock signal terminal and the second clock signal terminal are of the same period and have opposite voltage polarities, and the clock signals connected to the third clock signal terminal are of the same period and have the same potential as the clock signals connected to the first clock signal terminal.
[0015] The second control module is connected to the second clock signal terminal and the first node. Under the control of the input signal of the second node, it writes the corresponding level signal of the second clock signal terminal into the first node, so that the first NMOS transistor, under the control of the corresponding level signal of the first node, inputs the second negative voltage signal of the second negative voltage signal terminal into the signal output terminal.
[0016] In some embodiments, the first input module includes:
[0017] The third NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the positive voltage signal terminal, and its drain connected to the first node.
[0018] In some embodiments, the second input module includes:
[0019] The fourth NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the signal input terminal, and its source connected to the second node.
[0020] In some embodiments, at least one of the first NMOS transistor and the second NMOS transistor further has a back gate structure, the back gate structure being connected to a control electrode.
[0021] In some embodiments, the first control module includes:
[0022] The fifth NMOS transistor has its gate connected to the first node, its drain connected to the first negative voltage signal terminal, and its source connected to the fourth node.
[0023] The sixth NMOS transistor has its gate connected to the first clock signal terminal, its drain connected to the fourth node, and its source connected to the second node.
[0024] In some embodiments, the second control module includes:
[0025] The seventh NMOS transistor has its gate connected to the second node, its drain connected to the second clock signal terminal, and its source connected to the first node;
[0026] The eighth NMOS transistor has its gate connected to the positive voltage signal terminal, its drain connected to the fifth node, and its source connected to the second node. It is used to keep the transistor on under the control of the positive voltage signal terminal and to write the input signal and the first negative voltage signal to the second node through the fifth node with a delay.
[0027] In some embodiments, the second negative voltage signal is higher than the first negative voltage signal, the high-level voltages connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are all equal to the positive voltage signal, the low-level voltages connected to the signal input terminal, the first clock signal terminal, and the second clock signal terminal are all equal to the second negative voltage signal, and the low-level voltage of the third clock signal terminal is equal to the positive voltage signal.
[0028] A second aspect of this disclosure provides a gate driving circuit that includes a plurality of gate driving circuit units according to any of the above embodiments.
[0029] Multiple gate drive circuit units are electrically coupled in a cascaded manner, wherein the signal input terminal of the first-stage gate drive circuit unit is coupled to the start pulse signal, and the signal output terminal of each of the remaining gate drive circuit units, except for the last-stage gate drive circuit unit, is coupled to the signal input terminal of the next-stage gate drive circuit unit.
[0030] In some embodiments, in the cascade chain from the first-stage gate driving circuit unit to the last-stage gate driving circuit unit, the first clock signal terminal and the second clock signal terminal in each of the gate driving circuit units are alternately connected to the first clock signal line and the second clock signal line, and the third clock signal terminal in each of the gate driving circuit units is alternately connected to the third clock signal line and the fourth clock signal line; the clock signals of the third clock signal line and the fourth clock signal line have the same period and opposite voltage polarities.
[0031] A third aspect of this disclosure provides a display device that includes a gate driving circuit according to any of the above embodiments.
[0032] Compared to related technologies, the gate drive circuit unit of this embodiment adds a clock signal terminal and a negative voltage signal terminal. For the second NMOS transistor, when the input potential of the signal input terminal is written to the second node, a potential level signal is input to the third clock signal terminal and output from the signal output terminal, while the second capacitor stores the input potential; in the next time period, the third clock signal terminal inputs an opposite potential level signal, the second capacitor keeps the second node at the input potential, and the signal output terminal outputs the aforementioned opposite potential level signal. In this way, the gate drive circuit unit of this embodiment can provide level signals of different potentials to achieve the display effect of the display device.
[0033] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0034] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0035] Figure 1 A structural diagram of a gate driver that includes cascaded gate drive circuitry is shown in the relevant technology.
[0036] Figure 2 This is a circuit structure diagram of the gate drive circuit unit provided in the embodiments of this disclosure.
[0037] Figure 3 yes Figure 2 The equivalent circuit diagram of the gate drive circuit unit shown is shown.
[0038] Figure 4 exhibit Figure 3 One of the timing waveform diagrams corresponding to the gate drive circuit unit shown.
[0039] Figure 5 yes Figure 3 The gate drive circuit unit shown corresponds to Figure 4 A schematic diagram of the working status during the first time period.
[0040] Figure 6 exhibit Figure 3 The second timing waveform diagram corresponding to the gate drive circuit unit shown.
[0041] Figure 7 yes Figure 3 The gate drive circuit unit shown corresponds to Figure 6 A schematic diagram of the working status during the second time period.
[0042] Figure 8 exhibit Figure 3 The third timing waveform diagram corresponding to the gate drive circuit unit shown.
[0043] Figure 9 yes Figure 3 The gate drive circuit unit shown corresponds to Figure 8 A schematic diagram of the work status during the third time period.
[0044] Figure 10 exhibit Figure 3 The fourth timing waveform diagram corresponding to the gate drive circuit unit shown.
[0045] Figure 11 yes Figure 3 The gate drive circuit unit shown corresponds to Figure 10 A schematic diagram of the working status during the fourth time period.
[0046] Figure 12 exhibit Figure 3 The fifth timing waveform diagram corresponding to the gate drive circuit unit shown.
[0047] Figure 13 yes Figure 3 The gate drive circuit unit shown corresponds to Figure 12 A schematic diagram of the work status during the fifth time period.
[0048] Figure 14 exhibit Figure 2 The flowchart shows the control method of the gate drive circuit unit.
[0049] Figure 15 exhibit Figure 2 Another equivalent circuit diagram of the gate drive circuit unit shown.
[0050] Figure 16 exhibit Figure 2 Another equivalent circuit diagram of the gate drive circuit unit shown.
[0051] Figure 17 Demonstration and use Figure 2 The circuit structure diagram of the gate drive circuit of the gate drive circuit unit shown is shown. Detailed Implementation
[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0053] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0054] Furthermore, the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to define the order of functions performed by these devices, modules or units or their interdependencies.
[0055] like Figure 2 As shown, this disclosure provides a gate driving circuit unit, which includes:
[0056] The first input module S1 is connected to the positive voltage signal terminal VDD and the first node n1, and is used to write the positive voltage signal of the positive voltage signal terminal VDD into the first node n1 under the control of the second clock signal terminal CLK2.
[0057] The first NMOS transistor T1 and the first capacitor C1 are connected. The first NMOS transistor P1 is connected to the second negative voltage signal terminal VEE2 and the signal output terminal Gout. Under the control of the positive voltage signal, the second negative voltage signal of the second negative voltage signal terminal VEE2 is input to the signal output terminal Gout, and Gout outputs a low level signal. The first capacitor C1 is connected to the first negative voltage signal terminal VEE1 and the first node n1.
[0058] The second input module S2 is connected to the signal input terminal STV / in and the second node n2. It is used to write the input signal of STV / in into the second node n2 under the control of the second clock signal terminal CLK2.
[0059] The second NMOS transistor T2 and the second capacitor C2 are connected to the second node n2 and the signal output terminal Gout. The second capacitor C2 is used to store the input signal written to the second node n2. The second NMOS transistor T2 is connected to the third clock signal terminal CLK3 and the signal output terminal Gout. Under the control of the input signal written to the second node n2 and the input signal stored in the second capacitor C2, the corresponding potential of the third clock signal terminal CLK3 is input to the signal output terminal Gout.
[0060] The first control module K1 is connected to the first negative voltage signal terminal VEE1 and the second node n2. Under the control of the first node n1 and the first clock signal terminal CLK1, it writes the first negative voltage signal of the first negative voltage signal terminal VEE1 into the second node n2, so that the second NMOS transistor T2 blocks the third clock signal terminal CLK3 and the signal output terminal Gout under the control of the first negative voltage signal. The clock signals connected to the first clock signal terminal CLK1 and the second clock signal terminal CLK2 are in the same period and have opposite voltage polarities. The clock signals connected to the third clock signal terminal CLK3 are in the same period and have the same potential as the clock signals connected to the first clock signal terminal CLK1.
[0061] The second control module K2 is connected to the second clock signal terminal CLK2 and the first node n1. Under the control of the input signal of the second node n2, it writes the corresponding level signal of the second clock signal terminal CLK2 into the first node n1, so that the first NMOS transistor P1, under the control of the corresponding level signal of the first node n1, outputs the second negative voltage signal of the second negative voltage signal terminal VEE2 to the output signal Gout.
[0062] Compared to related technologies, the gate drive circuit unit of this embodiment adds a clock signal terminal and a negative voltage signal terminal. For the second NMOS transistor T2, when the input potential of the signal input terminal STV / in is written to the second node n2, the third clock signal terminal CLK3 inputs a potential level signal and outputs it from the signal output terminal Gout, while the second capacitor C2 stores the input potential; in the next time period, the third clock signal terminal CLK3 inputs an opposite potential level signal, the second capacitor C2 keeps the second node n2 at the input potential, and the signal output terminal Gout outputs the aforementioned opposite potential level signal. In this way, the gate drive circuit unit of this embodiment can provide level signals of different potentials to achieve the display effect of the display device.
[0063] like Figure 3 As shown, the first input module S1 includes:
[0064] The third NMOS transistor T3 has its gate connected to the second clock signal terminal CLK2, its drain connected to the positive voltage signal terminal VDD, and its source connected to the first node n1. The third NMOS transistor T3 turns on when a high-level signal is input to the second clock signal terminal CLK2 and turns off when a low-level signal is input. When it is on, it inputs the positive voltage signal from the positive voltage signal terminal VDD to the first node n1, causing the first NMOS transistor T1 to turn on. The signal output terminal Gout outputs the low-level signal provided by the second negative voltage signal terminal VEE2.
[0065] In this embodiment of the disclosure, the second input module S2 includes:
[0066] The fourth NMOS transistor T4 has its gate connected to the second clock signal terminal CLK2, its drain connected to the signal input terminal STV / in, and its source connected to the second node n2.
[0067] In this embodiment, when the gate driving circuit unit is used as the first-stage gate driving circuit unit in the gate driving circuit, the signal input terminal STV / in is connected to the start pulse signal; when it is used as other stages of the gate driving circuit unit, the signal input terminal STV / in is connected to the signal output terminal of the previous stage gate driving circuit unit.
[0068] For the fourth NMOS transistor T4, when the second clock signal terminal CLK2 provides a high-level signal, it is triggered to conduct, causing the second node n2 to be written with the input potential, and the second capacitor C2 stores the input potential of the second node n2. Conversely, when CLK2 changes from a high-level signal to a low-level signal, the fourth NMOS transistor T4 is turned off, and the second capacitor C2 keeps the second node n2 at the input potential.
[0069] In this embodiment of the disclosure, the first control module K1 includes:
[0070] The fifth NMOS transistor T5 has its gate connected to the first node n1, its drain connected to the first negative voltage signal terminal VEE1, and its source connected to the fourth node n4.
[0071] The sixth NMOS transistor T6 has its gate connected to the first clock signal terminal CLK1, its drain connected to the fourth node n4, and its source connected to the second node n2.
[0072] In this embodiment, when the fifth NMOS transistor T5 and the sixth NMOS transistor T6 are turned on simultaneously, the low-level signal provided by the first negative voltage signal terminal VEE1 is input to the second node n2, resetting the second node n2 and triggering the second NMOS transistor T2 to turn off. At the same time, the second capacitor C2 stores the low-level signal of node n2.
[0073] In this embodiment of the disclosure, the second control module K2 includes:
[0074] The seventh NMOS transistor T7 has its gate connected to the second node n2, its drain connected to the second clock signal terminal CLK2, and its source connected to the first node n1.
[0075] In this embodiment, when a high-level signal is input to the second node n2, the seventh NMOS transistor T7 is turned on, and the level signal provided by CLK2 is input to the first node n1. When the level signal provided by CLK2 is a low-level signal, the first node n1 is pulled low, triggering the first NMOS transistor T1 to turn off.
[0076] In this embodiment of the disclosure, the gate drive circuit unit further includes:
[0077] The eighth NMOS transistor T8 has its gate connected to the positive voltage signal terminal VDD, its drain connected to the fifth node n5, and its source connected to the second node n2. It is used to keep the transistor on under the control of the positive voltage signal terminal VDD and to write the input signal and the first negative voltage signal into the second node n2 through the fifth node n5 with a delay.
[0078] As shown in the figure, the gate of the eighth NMOS transistor T8 is connected to the positive voltage signal terminal VDD, its drain is connected to the second node n2, and its source is connected to the fifth node n5. Under the influence of the positive voltage signal provided by VDD, T8 remains in the on state to transmit the signal between the fifth node n5 and the second node n2. The fifth node n5 is coupled to the source of T3, the gate of T7, and the source of T6. T8 serves to delay the signal transmission.
[0079] right Figure 3 The gate drive circuit unit shown below has the following working process:
[0080] Combination Figure 4 and Figure 5 During the first time period t1, STV = 0, CLK1 is connected to CKV1, CLK1 = 0, CLK2 is connected to CKV2, CLK2 = 1, CLK3 is connected to CKV3, and CLK3 = 0, where 0 represents a low-level signal and 1 represents a high-level signal;
[0081] When T3 is turned on, n1 is pulled high. When T1 is turned on, it inputs a low-level signal provided by VEE2 to Gout. When T5 is turned on and T6 is turned off, C1 stores a high potential.
[0082] When T4 is turned on, n2 and n5 are pulled low, T2 and T7 are turned off, and C2 stores a low potential.
[0083] Combination Figure 6 and Figure 7As shown, in the second time period t2, STV = 0, CLK1 = 1, CLK2 = 0, CLK3 = 1;
[0084] T3 and T4 are cut off, C1 keeps n1 at a high potential, T1 continues to output a low level signal, and Gout keeps outputting a low level signal.
[0085] T5 and T6 are turned on simultaneously, n2 and n5 are pulled low by VEE1, T7 and T2 are turned off, and C2 stores a low potential.
[0086] Combination Figure 8 and Figure 9 As shown, in the third time period t3, STV=1, CLK1=0, CLK2=1, CLK3=0;
[0087] T3, T4 and T7 are turned on, n1, n2 and n5 are pulled high, T1 and T2 are both turned on, and the low-level signals provided by CLK3 and VEE2 are input to the signal output terminal Gout, and Gout maintains the output low-level signal.
[0088] T5 is on and T6 is off, so both C1 and C2 store high potential.
[0089] Combination Figure 10 and Figure 11 As shown, in the fourth time period t4, STV=0, CLK1=1, CLK2=0, CLK3=1;
[0090] With T3 and T4 off, C2 keeps n2 at a high potential, T7 is on, CLK2 provides a low-level signal to n1, n1 is pulled low, T1 is off, and at the same time n2 turns on T2, providing a high-level signal from CLK3 to Gout, and Gout outputs a high-level signal.
[0091] Combination Figure 12 and Figure 13 As shown, in the fifth time interval t5, STV=0, CLK1=0, CLK2=1, CLK3=0;
[0092] Among them, the state reference of each transistor Figure 4 and Figure 5 This will not be elaborated further here; at this point, Gout outputs a low-level signal.
[0093] Then, repeat the above process.
[0094] Specifically, VDD voltage is a positive constant voltage signal, while VEE1 and VEE2 voltages are both negative constant voltage signals. VEE1 voltage is lower than VEE2 voltage, which is characterized by VEE1-VEE2 < Vth_T1 and VEE1-VEE2 < Vth_T.
[0095] The high-level voltages of STV, CLK1, CLK2, and CLK3 signals are all equal to the VDD voltage;
[0096] The low-level voltages of STV, CLK1, and CLK2 signals are all equal to the VEE1 voltage;
[0097] The low-level voltage of the CLK3 signal is equal to the VEE2 voltage.
[0098] Its advantage is that the low-level voltage of node n3 is controlled by STV, and the low-level potential written by n3 is VEE1. When Vth of T1 and T2 is less than 0, VEE1-VEE2<Vth_T1 and Vth_T2, which can ensure that T1 and T2 will not be turned on when they should be turned off.
[0099] Therefore, this disclosure provides a method for... Figure 2 The control method of the gate drive circuit unit shown is as follows: Figure 14 As shown, it includes the following steps:
[0100] Step 1410, in the first time period, control the input terminal, the first clock signal terminal and the third clock signal terminal to input low-level signals and control the second clock signal terminal to input high-level signals, so that the first input module writes the positive voltage signal to the first node, the first NMOS transistor inputs the second negative voltage signal to the signal output terminal, and the signal output terminal outputs a low-level signal;
[0101] Step 1420, Second time period: Control the input terminal and the second clock signal terminal to input the low-level signal and control the input terminal and the third clock signal terminal to input the high-level signal. Under the control of the positive voltage signal of the first node stored in the first capacitor, the first NMOS transistor inputs the second negative voltage signal to the signal output terminal, and the signal output terminal outputs a low-level signal.
[0102] Step 1430, in the third time period, control the signal input terminal and the second clock signal terminal to input the high-level signal and control the first clock signal terminal and the third clock signal terminal to input the low-level signal, so that the first input module writes the positive voltage signal to the first node, thereby controlling the first NMOS transistor to input the second negative voltage signal to the signal output terminal and the second input module to write the high-level signal to the second node, thereby controlling the second NMOS transistor to input the low-level signal to the signal output terminal, and the signal output terminal outputs a low-level signal;
[0103] Step 1440, fourth time period: control the signal input terminal and the second clock signal terminal to input the low-level signal and control the first clock signal terminal and the third clock signal terminal to input the high-level signal. Under the control of the high-level signal of the second node stored in the second capacitor, the second control module writes the low-level signal to the first node to turn off the first NMOS transistor. The second NMOS transistor inputs the high-level signal to the signal output terminal, and the signal output terminal outputs a high-level signal.
[0104] Figure 14 The control method is provided as a unit process, which is then repeated.
[0105] In this embodiment of the disclosure, the second negative voltage signal is higher than the first negative voltage signal. The high-level voltages connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are all equal to the positive voltage signal. The low-level voltages connected to the signal input terminal, the first clock signal terminal, and the second clock signal terminal are all equal to the second negative voltage signal. The low-level voltage of the third clock signal terminal is equal to the positive voltage signal.
[0106] In another embodiment of this disclosure, such as Figure 15 As shown, the fourth NMOS transistor is a dual-gate NMOS transistor, consisting of two NMOS transistors, T4a and T4b, connected in series and sharing the same gate node. Its advantage is that when one transistor experiences conductor formation, the other transistor can still function. For example, if the probability of a single transistor failing due to conductor formation is 0.0001, then the probability of both transistors connected in series failing simultaneously is mathematically calculated to be 0.0001² = 10⁻⁸.
[0107] For other transistors, the same principle applies as the fourth NMOS transistor, which can be configured as a dual-gate transistor.
[0108] In the above embodiment, each transistor is a TFT.
[0109] refer to Figure 16 In another embodiment shown, the first NMOS transistor T1 further has a first back gate structure G1, which is connected to a control electrode. Specifically, the front gate G0 of T1 is connected to a first node n1, and G1 is connected to a control electrode.
[0110] The second NMOS body transistor T2 also has a second back gate structure G2, which is connected to a control electrode. Specifically, the front gate G3 of T2 is connected to the second node n2, and G2 is connected to a control electrode.
[0111] Its advantages are:
[0112] To achieve stronger output capability, T1 and T2 are generally designed with a larger W / L ratio (W is the channel width of the MOS transistor, and L is the channel length of the MOS transistor). This may result in a relatively negative threshold voltage Vth. Setting G1 and G2 can apply a negative back gate voltage to make Vth drift in the positive direction.
[0113] When T1 and T2 are under stress for a long time, Vth may drift positively, making it difficult to output a positive voltage VDD signal. The back gate voltages of G1 and G2 can be set to positive to make Vth of T1 and T2 drift negatively, thus improving the problem of reduced output capability caused by stress.
[0114] In one embodiment, at least one of the first NMOS transistor T1 and the second NMOS transistor T2 may have a back gate structure, and the back gate structure is connected to a control electrode.
[0115] In this embodiment of the disclosure, in addition to the first NMOS transistor T1 and the second NMOS transistor T2, other NMOS transistors may also be provided with a back gate structure, and the back gate structure is connected to a control electrode.
[0116] This disclosure also provides a gate driving circuit, such as Figure 17 As shown, it includes multiple gate drive circuit units of any of the above embodiments.
[0117] Multiple gate drive circuit units are electrically coupled in a cascaded manner, wherein the signal input terminal of the first-stage gate drive circuit unit is coupled to the start pulse signal, and the signal output terminal of each of the remaining gate drive circuit units, except for the last-stage gate drive circuit unit, is coupled to the signal input terminal of the next-stage gate drive circuit unit.
[0118] like Figure 17As shown, in this embodiment, four cascaded gate drive circuit units are used as an example. The output signal Gout[1] of the first-stage gate drive circuit unit SRC1 is used as the input signal of the second-stage gate drive circuit unit SRC2, and the output signal Gout[2] of the second-stage gate drive circuit unit SRC2 is used as the input signal of the third-stage gate drive circuit unit SRC3, and so on. After a low-level start pulse signal STV is input to the signal input terminal of the first-stage gate drive circuit unit SRC1, a stable output signal can be generated at its first signal output terminal Gout[1]. This output signal of the first signal output terminal Gout[1] is input to the signal input terminal in of the second-stage gate drive circuit unit SRC2. This process is repeated to obtain the waveforms of the first signal output terminal Gout[1] of the four-stage gate drive circuit units and the final output of the fourth-stage gate drive circuit unit SRC4, thereby enabling the output of a stable signal.
[0119] like Figure 17 As shown, in the cascaded chain from the first-stage gate drive circuit unit SRC1 to the last-stage gate drive circuit unit, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 in each of the gate drive circuit units are alternately connected to the first clock signal line CKV1 and the second clock signal line CKV2, and the third clock signal terminal CLK3 in each of the gate drive circuit units is alternately connected to the third clock signal line CKV3 and the fourth clock signal line CKV4.
[0120] Among them, the clock signals of the third clock signal line CKV3 and the fourth clock signal line CKV4 have the same period but opposite voltage polarities.
[0121] For example, for the first-stage gate drive circuit unit SRC1, its first clock signal terminal CLK1 is connected to the first clock signal line CKV1, its second clock signal terminal CLK2 is connected to the second clock signal line CKV2, and its third clock signal terminal CLK3 is connected to the third clock signal line CKV3; for the second-stage gate drive circuit unit SRC2, its second clock signal terminal CLK2 is connected to the first clock signal line CKV1, its first clock signal terminal CLK1 is connected to the second clock signal line CKV2, and its third clock signal terminal CLK3 is connected to the fourth clock signal line CKV4. The subsequent gate drive circuit units follow the same alternating connection method and will not be described further.
[0122] This embodiment also provides a display device, including the gate driving circuit described above, and sequentially turning on the gate scan lines in the display device line by line using the gate driving circuit units. The display device also includes a drain driving circuit for providing data voltage to the corresponding pixels when the gate scan lines are turned on.
[0123] In one embodiment, the display device can be a variety of electronic display products, specifically including but not limited to at least one of mobile phones, tablet computers, e-book readers, media players, digital cameras, laptops, in-vehicle computers, desktop computers, set-top boxes, smart TVs, and wearable devices. Furthermore, depending on actual needs, the display device may also include other structures such as a touch-sensitive layer, a polarizing film, and a cover plate.
[0124] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A gate driving circuit unit, characterized in that, include: The first input module is connected to the positive voltage signal terminal and the first node, and is used to write the positive voltage signal of the positive voltage signal terminal into the first node under the control of the second clock signal terminal. A first NMOS transistor and a first capacitor, wherein the first NMOS transistor is connected to a second negative voltage signal terminal and a signal output terminal, and is used to input a second negative voltage signal from the second negative voltage signal terminal to the signal output terminal under the control of the positive voltage signal, wherein the first capacitor is connected to the first negative voltage signal terminal and the first node; The second input module is connected to the signal input terminal and the second node, and is used to input the input signal of the signal input terminal to the second node under the control of the second clock signal terminal; The second NMOS transistor and the second capacitor are connected to the second node and the signal output terminal. The second capacitor is used to store the input signal written to the second node. The second NMOS transistor is connected to the third clock signal terminal and the signal output terminal. Under the control of the input signal written to the second node and the input signal stored in the second capacitor, the corresponding potential of the third clock signal terminal is input to the signal output terminal. A first control module, connected to a first negative voltage signal terminal and a second node, is used to write a first negative voltage signal from the first negative voltage signal terminal to the second node under the control of the first node and a first clock signal terminal, so that the second NMOS transistor blocks the third clock signal terminal from the signal output terminal under the control of the first negative voltage signal. The clock signals connected to the first clock signal terminal and the second clock signal terminal are of the same period and have opposite voltage polarities, and the clock signals connected to the third clock signal terminal are of the same period and have the same potential as the clock signals connected to the first clock signal terminal. The second control module is connected to the second clock signal terminal and the first node. Under the control of the input signal of the second node, it writes the corresponding level signal of the second clock signal terminal into the first node, so that the first NMOS transistor, under the control of the corresponding level signal of the first node, inputs the second negative voltage signal of the second negative voltage signal terminal into the signal output terminal.
2. The gate drive circuit unit according to claim 1, characterized in that, The first input module includes: The third NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the positive voltage signal terminal, and its drain connected to the first node.
3. The gate drive circuit unit according to claim 1, characterized in that, The second input module includes: The fourth NMOS transistor has its gate connected to the second clock signal terminal, its drain connected to the signal input terminal, and its source connected to the second node.
4. The gate driving circuit unit according to claim 1, characterized in that, At least one of the first NMOS transistor and the second NMOS transistor further has a back gate structure, which is connected to a control electrode.
5. The gate drive circuit unit according to claim 1, characterized in that, The first control module includes: The fifth NMOS transistor has its gate connected to the first node, its drain connected to the first negative voltage signal terminal, and its source connected to the fourth node. The sixth NMOS transistor has its gate connected to the first clock signal terminal, its drain connected to the fourth node, and its source connected to the second node.
6. The gate driving circuit unit according to claim 1, characterized in that, The second control module includes: The seventh NMOS transistor has its gate connected to the second node, its drain connected to the second clock signal terminal, and its source connected to the first node; The gate drive circuit unit further includes: The eighth NMOS transistor has its gate connected to the positive voltage signal terminal, its drain connected to the fifth node, and its source connected to the second node. It is used to keep the transistor on under the control of the positive voltage signal terminal and to write the input signal and the first negative voltage signal to the second node through the fifth node with a delay.
7. The gate drive circuit unit according to claim 1, characterized in that, The second negative voltage signal is higher than the first negative voltage signal. The high-level voltages connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are all equal to the positive voltage signal. The low-level voltages connected to the signal input terminal, the first clock signal terminal, and the second clock signal terminal are all equal to the second negative voltage signal. The low-level voltage of the third clock signal terminal is equal to the positive voltage signal.
8. A gate driving circuit, characterized in that, Includes the gate drive circuit unit as described in any one of claims 1-7; Multiple gate drive circuit units are electrically coupled in a cascaded manner, wherein the signal input terminal of the first-stage gate drive circuit unit is coupled to the start pulse signal, and the signal output terminal of each of the remaining gate drive circuit units, except for the last-stage gate drive circuit unit, is coupled to the signal input terminal of the next-stage gate drive circuit unit.
9. The gate driving circuit according to claim 8, characterized in that, From the first-stage gate drive circuit unit to the last-stage gate drive circuit unit in the cascaded chain, the first clock signal terminal and the second clock signal terminal in each gate drive circuit unit are alternately connected to the first clock signal line and the second clock signal line, and the third clock signal terminal in each gate drive circuit unit is alternately connected to the third clock signal line and the fourth clock signal line. The third clock signal line has the same clock signal period as the fourth clock signal line, but the voltage polarities are opposite.
10. A display device, characterized in that, Includes the gate drive circuit as described in claim 8 or 9.