Surge protection circuit and electronic device

Abstract

The invention provides a surge protection circuit and an electronic device, the surge protection circuit comprises an impedance unit and a first surge protection unit, and the impedance unit is used for reducing the amplitude of a surge current of a surge signal; the first surge protection unit comprises a first blocking unit, a first clamping unit and a first discharge unit; the first clamping unit is used for clamping the surge voltage of the surge signal to a target range of the target chip; the first discharge unit is used for discharging a surge signal; the first blocking unit is used for blocking the surge signal from flowing to the target chip. According to the surge protection circuit, when the target chip suffers from the surge signal, the impedance unit can be utilized to reduce the amplitude of the surge current of the surge signal, and the clamping unit is utilized to clamp the surge voltage of the surge signal to the target range of the target chip, so that the probability of damage to the target chip is reduced, and the reliability of the surge protection circuit is improved. The surge protection circuit is high in protection level and can adapt to a lightning sensitive area or a large power equipment area.

Description

Technical Field

[0001] This application relates to the field of power electronics, and in particular to a surge protection circuit and electronic device. Background Technology

[0002] Some existing surge protection circuits have low protection levels, which can cause chip damage when used in lightning-sensitive areas or areas with large power equipment.

[0003] Therefore, in order to enable automated control equipment to better adapt to lightning-sensitive areas or areas with large power equipment, a surge protection circuit with a high protection level is needed. Summary of the Invention

[0004] This application mainly provides a surge protection circuit and electronic device. The surge protection circuit has a high protection level and can be adapted to lightning-sensitive areas or areas with large power equipment.

[0005] The first technical solution adopted in this application is: providing a surge protection circuit, including: Impedance unit, used to reduce the amplitude of surge current in surge signals; The first surge protection unit includes a first blocking unit, a first clamping unit, and a first discharge unit; the first clamping unit and the first blocking unit are connected between the target chip and the impedance unit, and the first discharge unit is connected to the impedance unit. The first clamping unit is used to clamp the surge voltage of the surge signal to the target range of the target chip; the first discharge unit is used to discharge the surge signal; and the first blocking unit is used to block the surge signal from flowing to the target chip.

[0006] In one embodiment, the surge protection circuit further includes: At least one second surge protection unit, the second surge protection unit including a second blocking unit, a second clamping unit and a second discharge unit; The first surge protection unit is connected to the power input terminal; a second surge protection unit is connected to a corresponding load output terminal.

[0007] In one embodiment, the power input terminal includes a power supply terminal and a ground terminal; The first discharge unit includes: The first differential mode discharge path is connected between the power supply terminal and the ground terminal, and is used to discharge the differential mode surge signal received by the power supply terminal; The first common-mode discharge path is connected between the power supply terminal and the ground terminal to discharge the common-mode surge signal received by the power supply terminal and the ground terminal; The second venting unit includes: The second differential mode discharge path is connected between the ground terminal and the load output terminal to discharge the differential mode surge signal received at the load output terminal. The second differential mode discharge path is connected to the first common mode discharge path and is also used to discharge the common mode surge signal received at the load output terminal.

[0008] In one embodiment, the first differential mode discharge path includes: a first gas discharge tube and a first varistor; The first end of the first gas discharge tube is connected to the grounding terminal, the second end of the first gas discharge tube is connected to the first end of the first varistor, and the second end of the first varistor is connected to the power supply terminal. The first common-mode discharge path includes: a second gas discharge tube, a second varistor, and a third varistor; The first end of the second varistor is connected to the power supply terminal, the first end of the second gas discharge tube is connected to the second end of the second varistor, the second end of the second gas discharge tube is connected to the first end of the third varistor, the second end of the third varistor is connected to the ground terminal, and the third end of the second gas discharge tube is connected to the common ground terminal.

[0009] In one embodiment, the second differential mode discharge path includes: a third gas discharge tube and a fourth varistor; The first end of the fourth varistor is connected to the ground terminal, the second end of the fourth varistor is connected to the first end of the third gas discharge tube, and the second end of the third gas discharge tube is connected to the corresponding load output terminal.

[0010] In one embodiment, the first blocking unit includes: a first diode and a second diode, the anode of the first diode is connected to an impedance unit, the cathode of the first diode is connected to a first clamping unit and is used to connect to the target chip; the anode of the second diode is connected to the first clamping unit and is used to connect to the target chip, and the cathode of the second diode is connected to an impedance unit. The first clamping unit includes: a first Zener diode, the first end of which is connected to the cathode of the first diode, and the second end of which is connected to the anode of the second diode.

[0011] In one embodiment, the first blocking unit further includes: a third diode; the anode of the first diode and the anode of the third diode are connected and connected to an impedance unit; the cathode of the first diode and the cathode of the third diode are connected and connected to a first clamping unit, and are used to connect to the target chip.

[0012] In one embodiment, the second blocking unit includes: a fourth diode, the anode of the fourth diode being connected to the target chip, and the cathode of the fourth diode being connected to the second clamping unit; In the second surge protection unit, the clamping unit includes: a second Zener diode, the anode of the second Zener diode is connected to the impedance unit, and the cathode of the second Zener diode is connected to the cathode of the fourth diode.

[0013] In one embodiment, the impedance unit includes: The first inductor is connected between the first discharge unit and the first blocking unit; The second inductor is connected between the second clamping unit and the second discharge unit.

[0014] The second technical solution adopted in this application is: to provide an electronic device, comprising: Target chip; Surge protection circuit, which includes any of the above-mentioned surge protection circuits.

[0015] The beneficial effects of this application are as follows: The surge protection circuit provided by this application includes an impedance unit and a first surge protection unit. The impedance unit is used to reduce the amplitude of the surge current of the surge signal. The first surge protection unit includes a first blocking unit, a first clamping unit, and a first discharging unit. The first clamping unit and the first blocking unit are connected between the target chip and the impedance unit, and the first discharging unit is connected to the impedance unit. The first clamping unit is used to clamp the surge voltage of the surge signal to the target range of the target chip. The first discharging unit is used to discharge the surge signal. The first blocking unit is used to block the surge signal from flowing to the target chip. When the target chip is subjected to a surge signal, the surge protection circuit of this application can reduce the amplitude of the surge current of the surge signal using the impedance unit and clamp the surge voltage of the surge signal to the target range of the target chip using the first clamping unit, thereby reducing the probability of damage to the target chip. The surge protection circuit of this application has a high protection level and can be adapted to lightning-sensitive areas or areas with large power equipment. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a first embodiment of the surge protection circuit of this application; Figure 2 This is a schematic diagram of the second embodiment of the surge protection circuit of this application; Figure 3 This is a schematic diagram of the third embodiment of the surge protection circuit of this application; Figure 4 This is a schematic diagram of the fourth embodiment of the surge protection circuit of this application; Figure 5 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation

[0018] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0020] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0021] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0023] To enable those skilled in the art to better understand the technical solutions of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a first embodiment of the surge protection circuit of this application. The surge protection circuit 100 of this embodiment includes an impedance unit 12 and a first surge protection unit 101. The impedance unit 12 is used to reduce the amplitude of the surge current of the surge signal. The first surge protection unit 101 includes a first blocking unit 141, a first clamping unit 131, and a first discharging unit 111; the first clamping unit 131 and the first blocking unit 141 are connected between the target chip 200 and the impedance unit 12, and the first discharging unit 111 is connected to the impedance unit 12.

[0025] The first clamping unit 131 is used to clamp the surge voltage of the surge signal to the target range of the target chip 200; the first discharge unit 111 is used to discharge the surge signal; and the first blocking unit 141 is used to block the surge signal from flowing to the target chip 200.

[0026] It should be noted that in lightning-sensitive areas or areas with large power equipment, the surge current of surge signals may reach the kiloampere level. Due to current limitations in the manufacturing process of some devices, it is impossible to directly discharge surge currents at the kiloampere level, resulting in insufficient protection level of the current surge protection circuit 100. The surge protection circuit 100 of this application incorporates an impedance unit 12 to reduce the amplitude of the surge current of the surge signal, for example, reducing the kiloampere level surge current to the hundred ampere level, so that the current can meet the discharge standard. Furthermore, the first clamping unit 131 clamps the surge voltage of the surge signal to the target range of the target chip 200, which helps to reduce the possibility of damage to the target chip 200 due to excessive surge voltage. Finally, the surge signal is discharged through the first discharge unit 111. This improves the protection level of the surge protection circuit and makes it suitable for lightning-sensitive areas or areas with large power equipment.

[0027] In one embodiment, combined with Figure 2 , Figure 2 This is a schematic diagram of the structure of a second embodiment of the surge protection circuit of this application. The surge protection circuit 100 further includes at least one second surge protection unit 102, which includes a second blocking unit 142, a second clamping unit 132, and a second discharge unit 112.

[0028] In this embodiment, the first surge protection unit 101 is connected to the power input terminal P, and a second surge protection unit 102 is connected to a load output terminal OUT.

[0029] In one specific embodiment, in the first surge protection unit 101, the first blocking unit 141 is connected between the first clamping unit 131 and the impedance unit 12. In the second surge protection unit 102, the second blocking unit 142 is connected to the second clamping unit 132 and is used to connect to the target chip 200.

[0030] Combination Figure 3 , Figure 3 This is a schematic diagram of the third embodiment of the surge protection circuit of this application. This embodiment is described using a load output terminal OUT and a second surge protection unit 102 as an example.

[0031] Specifically, the power input terminal P includes the power supply terminal VCC and the ground terminal GND. The first discharge unit 111 in the first surge protection unit 101 includes: a first differential mode discharge path 111a and a first common mode discharge path 111b.

[0032] The first differential mode discharge path 111a is connected between the power supply terminal VCC and the ground terminal GND, and is used to discharge the differential mode surge signal received by the power supply terminal VCC. Specifically, the first differential mode discharge path 111a includes a first gas discharge tube GT1 and a first varistor Rv1. The first end of the first gas discharge tube GT1 is connected to the ground terminal GND, the second end of the first gas discharge tube GT1 is connected to the first end of the first varistor Rv1, and the second end of the first varistor Rv1 is connected to the power supply terminal VCC.

[0033] The first common-mode discharge path 111b is connected between the power supply terminal VCC and the ground terminal GND, and is used to discharge the common-mode surge signal received by the power supply terminal VCC and the ground terminal GND. Specifically, the first common-mode discharge path 111b includes: a second gas discharge tube GT2, a second varistor Rv2, and a third varistor Rv3. The first end of the second varistor Rv2 is connected to the power supply terminal VCC, the first end of the second gas discharge tube GT2 is connected to the second end of the second varistor Rv2, the second end of the second gas discharge tube GT2 is connected to the first end of the third varistor Rv3, the second end of the third varistor Rv3 is connected to the ground terminal GND, and the third end of the second gas discharge tube GT2 is connected to the common ground terminal PE.

[0034] The second discharge unit 112 in the second surge protection unit 102 includes a second differential mode discharge path, which is connected between the ground terminal GND and the load output terminal OUT, and is used to discharge the differential mode surge signal received by the load output terminal OUT. Further, the second differential mode discharge path and the first common mode discharge path 111b are jointly connected to the ground terminal GND, and the second differential mode discharge path and the first common mode discharge path 111b are connected through the ground terminal GND, which is used to discharge the common mode surge signal received by the load output terminal OUT.

[0035] The second differential mode discharge path includes a third gas discharge tube GT3 and a fourth varistor Rv4. The first terminal of the fourth varistor Rv4 is connected to the ground terminal GND, the second terminal of the fourth varistor Rv4 is connected to the first terminal of the third gas discharge tube GT3, and the second terminal of the third gas discharge tube GT3 is connected to the corresponding load output terminal OUT.

[0036] In one embodiment, the first blocking unit 141 in the first surge protection unit 101 includes: a first diode D1 and a second diode D2, the anode of the first diode D1 is connected to the impedance unit 12, the cathode of the first diode D1 is connected to the first clamping unit 131 and is used to connect to the target chip 200; the anode of the second diode D2 is connected to the first clamping unit 131 and is used to connect to the target chip 200, and the cathode of the second diode D2 is connected to the impedance unit 12.

[0037] In another embodiment, the first blocking unit 141 further includes a third diode D3, the anode of the first diode D1 and the anode of the third diode D3 are connected and connected to the impedance unit 12, the cathode of the first diode D1 and the cathode of the third diode D3 are connected and connected to the first clamping unit 131, and the cathodes of the first diode D1 and the third diode D3 are also used to connect to the target chip 200.

[0038] It should be noted that the rated forward current of a single diode is limited, while the surge current is large. In this embodiment, the third diode D3, which is connected in parallel with the first diode D1 in the same direction, can increase the forward conduction current, distribute power consumption, and help reduce the risk of a single diode burning out due to current overload.

[0039] The clamping unit 131 in the first surge protection unit 101 includes: a first Zener diode DZ1, the first end of the first Zener diode DZ1 being connected to the cathode of the first diode D1 and the cathode of the second diode D2, and the second end of the first Zener diode DZ1 being connected to the anode of the third diode D3.

[0040] In one specific embodiment, the second blocking unit 142 in the second surge protection unit 102 includes a fourth diode D4, the anode of which is connected to the target chip 200, and the cathode of which is connected to the second clamping unit 132. Specifically, the cathode of the fourth diode D4 is also connected to the second end of the third gas discharge tube GT3.

[0041] The second clamping unit 132 in the second surge protection unit 102 includes: a second Zener diode DZ2, the anode of the second Zener diode DZ2 is connected to the impedance unit 12, specifically, the anode of the second Zener diode DZ2 is also connected to the cathode of the third diode D3; the cathode of the second Zener diode DZ2 is connected to the cathode of the fourth diode D4.

[0042] In one embodiment, the impedance unit 12 includes a first inductor L1 and a second inductor L2. The first inductor L1 is connected between the first discharge unit 111 and the first blocking unit 141 in the first surge protection unit 101. Specifically, the first end of the first inductor L1 is connected to the second end of the first varistor Rv1 in the first discharge unit 111; the second end of the first inductor L1 is connected to the anode of the first diode D1 and the anode of the second diode D2 in the first blocking unit 141. The second inductor L2 is connected between the second clamping unit 132 and the second discharge unit 112 in the second surge protection unit 102. Specifically, the first end of the second inductor L2 is connected to the anode of the second Zener diode DZ2 in the second clamping unit 132, and the second end of the second inductor L2 is connected to the first end of the first gas discharge tube GT1 in the second discharge unit 112.

[0043] It should be noted that the first gas discharge tube GT1 and the third gas discharge tube GT3 are diode gas discharge tubes, containing only two electrodes and no common terminal, primarily used for differential mode surge protection. The second gas discharge tube GT2 is a triode gas discharge tube, differing from the diode gas discharge tube in that it includes a common terminal, which is connected to the common grounding terminal PE. The common grounding terminal PE needs to be reliably grounded, and it is primarily used for common mode surge protection.

[0044] The first Zener diode DZ1 and the second Zener diode DZ2 are transient voltage suppressor diodes (TVS). It should be noted that, due to the limitations of TVS device manufacturing processes, large surge currents, such as those in the kiloampere range, cannot be directly discharged, resulting in insufficient protection level for the current surge protection circuit 100. The surge protection circuit 100 of this application incorporates an impedance unit 12 to reduce the amplitude of the surge current signal, for example, reducing the kiloampere surge current to the hundred ampere range, ensuring that the current falls within the discharge range of the TVS device. Then, the TVS device clamps the surge voltage signal to the target range of the target chip 200, which helps reduce the possibility of excessive surge voltage damaging the target chip 200. Finally, the surge signal is discharged, thus improving the protection level of the surge protection circuit and making it suitable for lightning-sensitive areas or areas with large power equipment.

[0045] The above embodiment illustrates the example of one load output terminal OUT connected to one second surge protection unit 102. In other embodiments, multiple load output terminals may be included, with each load output terminal connected to one second surge protection unit 102, as detailed below. Figure 4 As shown.

[0046] Specifically, the surge protection circuit 100 includes, for example: Figure 4 The four load output terminals shown are OUT1, OUT2, OUT3, and OUT4, and each load output terminal is connected to a corresponding second surge protection unit 102. The specific structure of the second surge protection unit 102 is as described above. Figure 3 As shown, it will not be elaborated further here.

[0047] See Figure 5 , Figure 5 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. The electronic device of this application includes a target chip 200 and a surge protection circuit 100. The target chip 200 is, for example, a chip used in automatic control equipment. This embodiment of the application will be described using an integrated multi-channel high-side switch chip as an example of the target chip 200.

[0048] Integrated multi-channel high-side switch chips are widely used in the field of industrial automation control. Due to their advantages such as miniaturization, high integration, and high cost performance, they are particularly suitable for miniaturized automatic control equipment, such as PLCs, frequency converters, and IO modules. They are used to control loads such as relays, indicator lights, and motors, playing an extremely important role in the field of industrial control.

[0049] When integrated multi-channel high-side switching chips are used in automated control equipment, especially in high-altitude, high-rise buildings and equipment, which are susceptible to lightning transient overvoltage and surge voltage from the start-up and shutdown of large power electronic equipment, they cannot directly withstand the impact of surge voltage and current due to their high integration. Therefore, external surge protection circuits are required to protect them from the damage of surge voltage.

[0050] Currently, the surge protection circuit solutions for integrated multi-channel high-side switching chips are conventionally defined as asymmetric signal lines and subjected to a 42Ω impedance network during surge immunity testing. This greatly reduces the impact of surge voltage on the chip, resulting in a low protection level. This makes them unsuitable for equipment operating in lightning-sensitive areas and areas with large power equipment. Under these conditions, integrated multi-channel high-side switching chips often suffer damage when faced with surge voltage.

[0051] The surge protection circuit 100 designed in this application can clamp the surge voltage to the chip's tolerance range in a timely manner and quickly guide the surge current according to the planned route when the integrated multi-channel high-side switch chip is subjected to a strong surge voltage attack. This helps to reduce the risk of damage to the integrated multi-channel high-side switch chip and plays a protective role.

[0052] like Figure 5 As shown, the integrated multi-channel high-side switch chip includes a voltage receiver (VSS), a ground terminal (GND'), and an output terminal (OUT'). A surge protection circuit 100 is connected to the integrated multi-channel high-side switch chip. Specifically, the cathode of the first diode D1 of the first blocking unit 141 of the surge protection circuit 100 is connected to the voltage receiver (VSS) of the integrated multi-channel high-side switch chip, and the anode of the second diode D2 of the first blocking unit 141 is connected to the ground terminal (GND') of the integrated multi-channel high-side switch chip. The anode of the fourth diode D4 of the second blocking unit 142 is connected to the output terminal (OUT') of the integrated multi-channel high-side switch chip.

[0053] In the electronic device of this application, when the power supply terminal VCC is subjected to a differential-mode positive surge signal, i.e., the surge signal is input from the power supply terminal VCC and the ground terminal GND, the power supply terminal VCC is positive and the ground terminal GND is negative. According to the device characteristics of TVS and gas discharge tube, the first Zener diode DZ1 operates earlier than the first gas discharge tube GT2. The surge signal forms a loop through the first inductor L1, the first diode D1, the third diode D3, the first Zener diode DZ1, the second diode D2, and the second inductor L2. Specifically, the voltage between the voltage receiving terminal VSS and the ground terminal GND' of the integrated multi-channel high-side switch chip is clamped to the target range (the maximum voltage range that the chip can tolerate) of the target chip through the first Zener diode DZ1. The surge signal is current-limited by the first inductor L1 and the second inductor L2, thereby reducing the amplitude of the surge current. The surge signal is discharged from the ground terminal GND through the first differential-mode discharge path 111a. Specifically, when the first gas discharge tube GT1 reaches the operating condition (i.e., the voltage at both ends reaches the breakdown voltage), the surge signal is discharged from the ground terminal GND through the first gas discharge tube GT1 and the first varistor Rv1 to form a large current loop.

[0054] When the power supply terminal VCC receives a differential-mode negative surge signal (i.e., the surge signal is input from the power supply terminal VCC and the ground terminal GND, with VCC being the negative terminal and GND being the positive terminal), the surge signal is blocked by the second diode D2, preventing the formation of a loop. The surge signal is then discharged from the power supply terminal VCC through the first differential-mode discharge path 111a. Specifically, when the first gas discharge tube GT1 reaches its operating condition, the surge signal forms a large current loop through the first gas discharge tube GT1 and the first varistor Rv1, discharging from the power supply terminal VCC. It should be noted that if the ground terminal GND is positive, the surge signal it receives is blocked by the second diode D2 and will not flow to the chip and the first Zener diode DZ. Therefore, the current limitation imposed by the TVS process does not need to be considered. Thus, even if the first inductor L1 and the second inductor L2 do not participate in the reduction of the surge current, large current discharge can still be achieved.

[0055] When the power supply terminal VCC experiences a common-mode positive surge signal, i.e., the surge signal is input from the power supply terminal VCC and the common ground terminal PE, with the power supply terminal VCC being the positive terminal and the common ground terminal PE being the negative terminal, the voltage between the voltage receiving terminal VSS of the integrated multi-channel high-side switching chip and the ground terminal GND' is clamped to the target range of the target chip through the first Zener diode DZ1. The surge signal is current-limited by the first inductor L1 and the second inductor L2, thereby reducing the amplitude of the surge current. The surge signal is discharged from the common ground terminal PE through the first common-mode discharge path 111b. Specifically, when the second gas discharge tube GT2 reaches the operating condition (i.e., the voltage across its terminals reaches the breakdown voltage), the surge signal forms a large current loop through the second gas discharge tube GT2 and the second varistor Rv2 and is discharged from the common ground terminal PE.

[0056] When the power supply terminal VCC experiences a common-mode negative surge signal (i.e., the surge signal is input from the power supply terminal VCC and the common ground terminal PE, with VCC being the negative terminal and PE being the positive terminal), the surge signal is blocked by the second diode D2, preventing the formation of a loop. The surge signal is then discharged from the power supply terminal VCC through the first common-mode discharge path 111b. Specifically, when the second gas discharge tube GT2 reaches its operating condition, the surge signal forms a large-current loop through the second gas discharge tube GT2 and the second varistor Rv2, discharging from the power supply terminal VCC.

[0057] When the grounding terminal GND is subjected to a common-mode positive surge signal, i.e., the surge signal is input from the grounding terminal GND and the common grounding terminal PE, with the grounding terminal GND being the positive terminal and the common grounding terminal PE being the negative terminal, the surge signal is blocked by the second diode D2, preventing the formation of a loop. The surge signal is then discharged from the common grounding terminal PE through the first common-mode discharge path 111b. Specifically, when the second gas discharge tube GT2 reaches its operating condition, the surge signal forms a large current loop through the second gas discharge tube GT2 and the third varistor Rv3, and is discharged from the common grounding terminal PE.

[0058] When the ground terminal GND is subjected to a common-mode negative surge signal, i.e., the surge signal is input from the ground terminal GND and the common ground terminal PE, with the ground terminal GND being the negative terminal and the common ground terminal PE being the positive terminal, the voltage between the voltage receiving terminal VSS of the integrated multi-channel high-side switch chip and the ground terminal GND' is clamped to the target range through the first Zener diode DZ1. The surge signal is current-limited by the first inductor L1 and the second inductor L2, thereby reducing the amplitude of the surge current. The surge signal is discharged from the ground terminal GND through the first common-mode discharge path 111b. Specifically, when the second gas discharge tube GT2 reaches the operating condition, the surge signal is discharged from the ground terminal GND through the second gas discharge tube GT2 and the third varistor Rv3 to form a large current loop.

[0059] When the load output terminal OUT experiences a differential-mode positive surge signal (i.e., the surge signal is input from the load output terminal OUT and the ground terminal GND, with the load output terminal OUT being positive and the ground terminal GND being negative), the surge signal is blocked by the fourth diode D4 and cannot enter the integrated multi-channel high-side switch chip. Based on the device characteristics of the TVS and gas discharge tube, the second Zener diode DZ2 activates earlier than the third gas discharge tube. The surge signal forms a loop through the second Zener diode DZ2 and the second inductor L2. The surge current passing through the second inductor L2 is limited, and the voltage between the output terminal OUT' and the ground terminal GND' of the integrated multi-channel high-side switch chip is clamped to the target range by the second Zener diode DZ2. When the third gas discharge tube GT3 reaches its activation condition, the surge signal is discharged from the ground terminal GND through a large current loop formed by the second differential-mode discharge path, namely the fourth varistor RV4 and the third gas discharge tube GT3.

[0060] When the load output terminal OUT experiences a differential-mode negative surge signal, the surge signal is input from the load output terminal OUT and the ground terminal GND. The load output terminal OUT is negative, and the ground terminal GND is positive. The surge signal is blocked by the fourth diode D4 and cannot enter the integrated multi-channel high-side switch chip. The surge signal forms a loop through the second Zener diode DZ2 and the second inductor L2. The surge current through the second inductor L2 is limited, and the voltage between the output terminal OUT' and the ground terminal GND' of the integrated multi-channel high-side switch chip is clamped to the target range by the second Zener diode DZ2. When the third gas discharge tube GT3 reaches the operating condition, the surge signal is discharged from the load output terminal OUT through the second differential-mode discharge path, i.e., the fourth varistor RV4 and the third gas discharge tube GT3, forming a large current loop.

[0061] When the load output terminal OUT experiences a common-mode positive surge signal (i.e., the surge signal is input from the load output terminal OUT and the common ground terminal PE, with the load output terminal OUT being positive and the common ground terminal PE being negative), the surge signal is blocked by the fourth diode D4 and cannot enter the integrated multi-channel high-side switch chip. The voltage between the output terminal OUT' of the integrated multi-channel high-side switch chip and the ground terminal GND' is clamped to the target range by the second Zener diode DZ2. When the third gas discharge tube GT3 and the second gas discharge tube GT2 reach their operating conditions, the surge signal is discharged from the common ground terminal PE through the second differential mode discharge path (i.e., the fourth varistor RV4 and the third gas discharge tube GT3) and the third varistor RV3 and the second gas discharge tube GT2 in the first common-mode discharge path 111b, forming a large current loop.

[0062] When the load output terminal OUT experiences a common-mode negative surge signal, i.e., the surge signal is input from the load output terminal OUT and the common ground terminal PE, with the load output terminal OUT being the negative terminal and the common ground terminal PE being the positive terminal, the voltage between the output terminal OUT' of the integrated multi-channel high-side switch chip and the ground terminal GND' is clamped to the target range by the second Zener diode DZ2. When the third gas discharge tube GT3 and the second gas discharge tube GT2 reach their operating conditions, the surge signal is discharged from the load output terminal OUT through the second differential mode discharge path, i.e., the fourth varistor RV4, the third gas discharge tube GT3, and the third varistor RV3 and the second gas discharge tube GT2 in the first common mode discharge path 111b, forming a large current loop.

[0063] It should be noted that the surge protection process is the same for multiple load output terminals, and will not be described in detail here.

[0064] This application integrates surge protection circuits with integrated multi-channel high-side switching chips into electronic devices. When used in large power generation and substation sites and wind turbine generator sets, these devices can reduce the risk of damage caused by lightning transient overvoltage and surge voltage from the start-up and shutdown of large power electronic equipment. This greatly protects the equipment, reduces losses from maintenance and equipment replacement, and helps improve the stability and reliability of equipment operation.

[0065] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A surge protection circuit, characterized in that, include: Impedance unit, the impedance unit being used to reduce the amplitude of the surge current of a surge signal; The first surge protection unit includes a first blocking unit, a first clamping unit, and a first discharge unit; the first clamping unit and the first blocking unit are connected between the target chip and the impedance unit, and the first discharge unit is connected to the impedance unit. The first clamping unit is used to clamp the surge voltage of the surge signal to the target range of the target chip; the first discharge unit is used to discharge the surge signal; and the first blocking unit is used to block the surge signal from flowing to the target chip.

2. The surge protection circuit according to claim 1, characterized in that, The surge protection circuit also includes: At least one second surge protection unit, the second surge protection unit including a second blocking unit, a second clamping unit and a second discharge unit; The first surge protection unit is connected to the power input terminal; each second surge protection unit is connected to a corresponding load output terminal.

3. The surge protection circuit according to claim 2, characterized in that, The power input terminal includes a power terminal and a ground terminal; The first discharge unit includes: The first differential mode discharge path is connected between the power supply terminal and the ground terminal to discharge the differential mode surge signal received by the power supply terminal; The first common-mode discharge path is connected between the power supply terminal and the ground terminal to discharge the common-mode surge signal received by the power supply terminal and the ground terminal. The second discharge unit includes: The second differential mode discharge path is connected between the ground terminal and the load output terminal to discharge the differential mode surge signal received by the load output terminal; The second differential mode discharge path is connected to the first common mode discharge path and is also used to discharge the common mode surge signal received at the load output terminal.

4. The surge protection circuit according to claim 3, characterized in that, The first differential mode discharge path includes: a first gas discharge tube and a first varistor; The first end of the first gas discharge tube is connected to the grounding terminal, the second end of the first gas discharge tube is connected to the first end of the first varistor, and the second end of the first varistor is connected to the power supply terminal. The first common-mode discharge path includes: a second gas discharge tube, a second varistor, and a third varistor; The first end of the second varistor is connected to the power supply terminal, the first end of the second gas discharge tube is connected to the second end of the second varistor, the second end of the second gas discharge tube is connected to the first end of the third varistor, the second end of the third varistor is connected to the ground terminal, and the third end of the second gas discharge tube is connected to the common ground terminal.

5. The surge protection circuit according to claim 3, characterized in that, The second differential mode discharge path includes: a third gas discharge tube and a fourth varistor; The first end of the fourth varistor is connected to the ground terminal, the second end of the fourth varistor is connected to the first end of the third gas discharge tube, and the second end of the third gas discharge tube is connected to the corresponding load output terminal.

6. The surge protection circuit according to claim 1, characterized in that, The first blocking unit includes: a first diode and a second diode, wherein the anode of the first diode is connected to the impedance unit, the cathode of the first diode is connected to the first clamping unit, and is used to connect to the target chip; the anode of the second diode is connected to the first clamping unit, and is used to connect to the target chip, and the cathode of the second diode is connected to the impedance unit. The first clamping unit includes: a first Zener diode, a first end of which is connected to the cathode of the first diode, and a second end of which is connected to the anode of the second diode.

7. The surge protection circuit according to claim 6, characterized in that, The first blocking unit further includes: a third diode; the anode of the first diode and the anode of the third diode are connected and connected to the impedance unit; the cathode of the first diode and the cathode of the third diode are connected and connected to the first clamping unit, and are used to connect to the target chip.

8. The surge protection circuit according to claim 2, characterized in that, The second blocking unit includes: a fourth diode, the anode of which is connected to the target chip, and the cathode of which is connected to the second clamping unit; In the second surge protection unit, the clamping unit includes: a second Zener diode, the anode of the second Zener diode is connected to the impedance unit, and the cathode of the second Zener diode is connected to the cathode of the fourth diode.

9. The surge protection circuit according to claim 2, characterized in that, The impedance unit includes: A first inductor is connected between the first discharge unit and the first blocking unit; The second inductor is connected between the second clamping unit and the second discharge unit.

10. An electronic device, characterized in that, include: Target chip; A surge protection circuit, wherein the surge protection circuit comprises the surge protection circuit described in any one of claims 1 to 9.

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