Adaptive damping control method of bidirectional dc converter under throw load condition

Abstract

The application provides a self-adaptive damping control method of a bidirectional DC converter under a load-throwing working condition, relates to the field of power electronics, and comprises the following steps: a bidirectional DC converter system is established, circuit data is collected for initialization, and a start mode is set; in the start mode, a soft start combined with a PI control strategy is adopted, a duty cycle is calculated through a reference voltage ramp and a PI regulator, four driving signals are generated by a PWM module to control the turn-on and turn-off of full-bridge MOS tubes; in the control process, the system working condition is analyzed according to the collected circuit data, and the system is switched to a steady-state mode when the load-throwing working condition occurs; in the steady-state mode, a composite duty cycle control law is constructed by using a LADRC linear active disturbance rejection control strategy, a complementary PWM signal is generated after amplitude limiting, and the system recovers energy. Through mode switching and the LADRC linear active disturbance rejection control, the application effectively suppresses voltage oscillation under load-throwing disturbance, and improves the dynamic stability and voltage stabilization precision of the system.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to an adaptive damping control method for bidirectional DC-DC converters under load dumping conditions. Background Technology

[0002] Bidirectional DC-DC converters, as key energy interface devices in energy storage systems, DC microgrids, and multi-voltage interconnected systems, are widely used in electric vehicle auxiliary power supplies, new energy power generation systems, and industrial power supplies. In practical engineering applications, to suppress high-frequency switching noise and improve power quality, an LC filter is usually connected in parallel on the high-voltage DC bus input side of the converter. However, while the introduction of this LC filter improves power quality under steady-state conditions, it introduces new stability problems under certain operating conditions. Specifically, when the system experiences load dumping (i.e., sudden load disconnection) or the converter implements a throttling control strategy to maintain a constant load-side voltage, the converter's input port exhibits a significant "negative incremental impedance" characteristic, i.e., constant power load characteristics. This negative impedance characteristic is highly susceptible to coupling with the inherent resonant parameters of the input-side LC filter, leading to a significant decrease in the overall system damping ratio and even triggering high-amplitude voltage oscillations. This resonant instability caused by source-load interaction not only causes severe overshoot of the bus voltage and threatens the safety of power devices, but in severe cases, it can also lead to the collapse of the entire power supply system. To address the aforementioned LC filter resonance instability problem, existing technologies are mainly divided into two categories: passive damping schemes and active damping schemes.

[0003] Passive damping solutions typically increase system damping by connecting physical resistors in series or parallel within an LC filter to dissipate resonant energy. While this method is simple to implement and reliable, the physical resistors continuously dissipate energy throughout the system's normal operation, significantly reducing system efficiency and increasing the complexity of heat dissipation design in high-power, long-duration operation. Active damping solutions primarily simulate resistive characteristics by improving control algorithms, such as virtual damping techniques based on proportional-integral (PI) regulators. However, traditional PI control inherently relies on error feedback and has inherent hysteresis; its parameter tuning often depends on a precise operating point model. When faced with rapid, large-amplitude nonlinear disturbances such as load dumping, a single PI control may struggle to provide sufficient dynamic damping, or may sacrifice dynamic response speed to maintain steady-state accuracy, resulting in an inability to effectively suppress transient voltage surges.

[0004] In view of the above, this application is hereby submitted. Summary of the Invention

[0005] This invention provides an adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions, which can at least partially improve the above-mentioned problems.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] An adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions includes:

[0008] Establish a bidirectional DC-DC converter system, collect the circuit data of the bidirectional DC-DC converter system, initialize the bidirectional DC-DC converter system based on the circuit data, and set its control mode to startup mode.

[0009] In startup mode, the bidirectional DC-DC converter system adopts a soft-start combined with PI control strategy. The duty cycle is calculated by the reference voltage ramp and the PI regulator. The preset PWM module generates four drive signals according to the duty cycle, which control the four MOSFETs in the full-bridge topology to turn on and off according to the set duty cycle.

[0010] During the control process, the system analyzes various indicators related to the system operating conditions based on the collected circuit data to determine the operating conditions of the bidirectional DC-DC converter system. When a load dumping condition occurs, the system switches to steady-state mode.

[0011] In steady-state mode, a composite duty cycle control law is constructed using the LADRC linear active disturbance rejection control strategy, and the composite duty cycle control law is amplitude-limited to generate a complementary PWM signal to drive the bidirectional DC-DC converter system to recover energy.

[0012] In summary, the LADRC linear active disturbance rejection control method for bidirectional DC-DC converters under load dump conditions provided by this invention effectively solves the resonant instability problem caused by the coupling of LC filters and constant power loads in traditional schemes through hardware and software co-design, without increasing physical damping resistors. Specifically, compared to the shortcomings of existing passive damping schemes that require additional physical resistors, leading to increased power loss and complex heat dissipation design, this invention only adds a lightweight energy recovery auxiliary branch composed of diodes and RC circuits on the main inductor side. This, combined with the control strategy, enables active absorption and utilization of resonant energy, avoiding additional losses. Compared to traditional active damping schemes based on PI control, this invention introduces a damping strategy based on linear active disturbance rejection control. It utilizes an extended state observer to estimate and compensate for the total system disturbance in real time, overcoming the inherent hysteresis and dependence on accurate models of PI control. Especially under large-signal nonlinear disturbances such as load dump, it can quickly suppress bus voltage overshoot and oscillation. Furthermore, this invention incorporates an adaptive switching mechanism between startup and steady-state modes. The soft-start strategy ensures a smooth voltage establishment on the load side, avoiding startup shocks, while the automatic switching under load shedding conditions ensures the system's voltage regulation accuracy and dynamic stability across all operating conditions. Experimental results show that, using the method of this invention, bus voltage fluctuations under load shedding conditions can be suppressed within a preset range, with no significant oscillations, significantly improving the system's anti-disturbance capability and operational reliability. Therefore, this invention achieves a breakthrough in balancing efficiency, dynamic response, and robustness, and is particularly suitable for applications with stringent stability requirements, such as electric vehicle auxiliary power supplies and DC microgrids. Attached Figure Description

[0013] Figure 1 This is a flowchart illustrating the adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions provided in an embodiment of the present invention.

[0014] Figure 2 This is a circuit model and a circuit diagram of the energy absorption branch provided in an embodiment of the present invention.

[0015] Figure 3 This is a schematic flowchart of the adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions provided in an embodiment of the present invention.

[0016] Figure 4 This is a specific control block diagram for constructing an ESO observer provided in an embodiment of the present invention.

[0017] Figure 5 This is a specific control block diagram of the composite duty cycle control law provided in the embodiments of the present invention.

[0018] Figure 6 This is a comparison of the voltage status before and after the load dumping optimization of the 380V system provided in the embodiments of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] refer to Figure 1 , Figure 3 As shown, the first embodiment of the present invention discloses an adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions. This method can be executed by an adaptive damping control device for a bidirectional DC-DC converter under load dumping conditions (hereinafter referred to as the control device), specifically by one or more processors within the control device, to implement the following method:

[0021] S1. Establish a bidirectional DC-DC converter system, collect the circuit data of the bidirectional DC-DC converter system, initialize the bidirectional DC-DC converter system according to the circuit data, and set its control mode to the start-up mode.

[0022] Specifically, step S1 further includes: establishing a circuit model based on the topology of the bidirectional DC-DC converter with a main inductor, and connecting an energy absorption branch consisting of a diode and an RC parallel unit in series across the buffer capacitor of the circuit model, while connecting an external sampling circuit on the circuit model to form a bidirectional DC-DC converter system, wherein the RC parallel unit consists of a bleed resistor R and a buffer capacitor Cs connected in parallel.

[0023] Real-time acquisition of circuit data from the bidirectional DC-DC converter system, including: bus voltage. Load side voltage and inductor current Among them, bus voltage The voltage should not exceed the high-voltage side range. If it exceeds the set high-voltage side voltage by about 5% to 8%, the bidirectional DC-DC converter will operate in startup mode.

[0024] The bidirectional DC-DC converter system is initialized based on the circuit data, and its control mode is set to startup mode. The load-side reference voltage is set according to actual needs, and the sampling frequency (20kHz) and sampling period (50μs) are set for the MCU. Based on the LADRC linear active disturbance rejection control theory, the parameters of the second-order state observer ESO, the bandwidth of the controller, the bandwidth of the observer, and the parameters of the PD controller are set. At the same time, the system feedforward is set, and the duty cycle is limited based on the above.

[0025] Preferably, the buffer capacitor of the energy absorption branch is selected as a capacitor with a withstand voltage value exceeding the set bus voltage by 50% to 100%.

[0026] Preferably, based on LADRC linear active disturbance rejection control theory, the parameters of the second-order state observer (ESO), the bandwidth of the controller, the bandwidth of the observer, and the parameters of the PD controller are set. Specifically, for the current topology of the bidirectional DC-DC converter system, a second-order system is constructed. ,in, Bus voltage The measured value, , , All are state variables. The value is the bus voltage. , for The first derivative, The value is the bus voltage. rate of change, for The first derivative, The control gain (i.e., the rate of change of the main dynamic caused by a unit control input, including parameters such as inductance, capacitance, and load resistance, which can be obtained analytically from circuit parameters or identified through experimental data). For control inputs related to duty cycle, The total disturbance of the bidirectional DC-DC converter system (including the combined effects of load changes, bus fluctuations, device non-ideals, noise, etc.).

[0027] Analysis of the parameters in the second-order system reveals that f is actually used to measure all unknown changes that need to be estimated and offset. These are conversion factors used to map control signals to the system. An extended state is introduced, letting... And assume Extending the second-order system to a third-order system , for The first derivative, for The first derivative, The rate of change of the disturbance;

[0028] Based on the Romberg observer form, the defined bus voltage The estimated value Bus voltage The estimated rate of change Estimate of the total disturbance of the bidirectional DC-DC converter system ;

[0029] A Romberg-form full-dimensional state observer is constructed in the continuous time domain, and the dynamic equations of the observer are obtained. ,in, for The first derivative, for The first derivative, for The first derivative, , , All are observer gains;

[0030] Let the observation error be... To obtain the error dynamics , This represents the first-order state estimation error. This represents the second-order state estimation error. For the disturbance estimation error, for The first derivative, for The first derivative, for The first derivative;

[0031] because Bounded and smaller, will Subsuming it into higher-order remainder terms, we obtain the linear error system. , , For the coefficient matrix of the linear error system, its eigenvalues ​​determine the convergence rate of the observation error;

[0032] The desired pole location is selected based on the pole placement method. That is, selecting triple real poles Let the desired third-order characteristic polynomial of the observer be... , For complex variables, For observer bandwidth;

[0033] Based on the linear error system, its characteristic polynomial is obtained. And the observer gain is determined by the matching coefficient. , , Among them, let ,get , , Observer error Exponential convergence, This is the matrix determinant operator. It is a third-order identity matrix.

[0034] Let the target value of the bus voltage of the bidirectional DC-DC converter system be... The PD controller is controlled by adjusting its output. The state variables estimated by ESO Track r while utilizing state variables The differential term suppresses voltage fluctuations, because in actual systems... It cannot be measured directly; it must be measured using... Replace the direct differential term, where, The output of the PD controller will be used as the subsequent LADRC composite control law. PD feedback component in This is the set value for the bus voltage.

[0035] Match the PD controller to the topology of the bidirectional DC-DC converter, assuming the bidirectional DC-DC converter object model is as follows. Under ideal conditions, ignoring disturbances, we obtain ;

[0036] Obtained through PD control rate Substitute ,get , , These are all PD controller parameters;

[0037] Assume error ,right Taking the derivative, we get , , ;

[0038] The homogeneous differential equation of the error is obtained by rearranging. And by performing a Laplace transform on the aligned differential equation, we obtain... , For error Laplace transform;

[0039] Let the controller bandwidth be The closed-loop characteristic equation is obtained. Take complex variables This determines the attenuation of the error. In the case of double roots, the modal behavior is as follows: , The larger the value, the faster the error decays, and the better the system tracks the setpoint. The faster the speed, the better, because the desired closed-loop poles are critically damped. Then the expected characteristic equation is By comparing the closed-loop characteristic equation and the desired characteristic equation, the PD controller parameters are obtained. , .

[0040] Preferably, the observer bandwidth With controller bandwidth The ratio is 4:1.

[0041] Please see Figure 2 Specifically, in this embodiment, a bidirectional DC-DC converter topology with integrated energy recovery function is constructed to complete system initialization and parameter acquisition. This step aims to provide the hardware foundation and initial parameters for the control strategy. Specifically, a bidirectional DC-DC converter topology with integrated energy recovery function is constructed: the system input is connected to the DC bus (“+” and “–” pole markings), the output is connected to a 380V auxiliary battery, and the core power stage uses four switching transistors (e.g., ...). Figure 2 The system uses an H-bridge structure composed of Q1~Q4 in the circuit. The two nodes of the H-bridge are coupled to the battery side via an LC filter (main inductor L=10μH, buffer capacitor C=220μF) to achieve bidirectional energy transfer. To suppress the transient impact of load dump, an energy absorption branch is introduced across the buffer capacitor C. This branch consists of a fast recovery diode D (model 1N5408) connected in series with an RC parallel unit. The RC parallel unit is composed of a discharge resistor R (resistance value 10Ω) and a buffer capacitor Cs (capacitance value 10μF, withstand voltage 600V) connected in parallel. The diode is reverse-biased and cut off during normal steady state of the system. It only conducts forward when the capacitor voltage exceeds the bus voltage due to the transient load dump, discharging the excess transient energy to the RC unit. Therefore, compared with the traditional passive damping scheme, it does not introduce steady-state losses.

[0042] After completing the topology setup, system initialization (setting parameters such as switching frequency 20kHz and bus voltage reference value 380V) and electrical parameter acquisition (including bus voltage V) are performed based on this topology model. bus Load side voltage V rec Inductor current I L (Sampling channel configuration).

[0043] Please refer to Figure 4 , Figure 4 The following is a detailed control block diagram of the Extended State Observer (ESO) constructed in steps S1 and S4. This diagram describes in detail the internal signal flow of the ESO: the observer takes the system's control and controlled variables as inputs, and estimates the system's internal state variables and the total disturbance caused by load dumping (as the extended state) in real time through internally constructed nonlinear or linear state equations. The observer's output directly serves as the basis for subsequent control law calculations and is the core component for achieving the "active disturbance rejection" characteristic.

[0044] S2, In startup mode, the bidirectional DC-DC converter system adopts a soft-start combined with PI control strategy. The duty cycle is calculated by the reference voltage ramp and the PI regulator. The preset PWM module generates four drive signals according to the duty cycle, which control the four MOSFETs in the full-bridge topology to turn on and off according to the set duty cycle, so as to achieve a stable establishment of the load side voltage.

[0045] Specifically, step S2 further includes: in startup mode, the soft-start process of the bidirectional DC-DC converter system, specifically: setting the reference voltage ramp time. (Select 5ms) When it is determined that the system running time t is less than the reference voltage ramp time At that time, reference voltage It grows linearly over time. The target load-side voltage;

[0046] When it is determined that the system running time t is greater than or equal to the reference voltage ramp time At that time, reference voltage If it remains unchanged, proceed to the PI control phase.

[0047] The PI control process specifically involves: calculating the load-side voltage. With reference voltage Error between And according to the preset soft-start PI parameters , Sum of error integral terms Calculate the pre-duty cycle Execute integral anti-saturation logic;

[0048] Only when the pre-duty cycle is within the preset allowable range When the error is within the limit range or at the limit range boundary and the error direction is opposite to the limit range direction, update the error integral term. To obtain the final duty cycle The amplitude and rate of change are limited. The preset PWM module generates four corresponding drive signals according to the duty cycle, controlling the four MOSFETs in the full-bridge topology to turn on and off according to the set duty cycle. This is the updated error integral term, where h is the sampling period. This is the absolute lower limit of the duty cycle. This represents the absolute upper limit of the duty cycle.

[0049] Considering the dead time (2μs) of the full-bridge complementary PWM, avoiding magnetic flux saturation of magnetic components, and preventing power transistor shoot-through risk under extreme operating conditions, the absolute upper limit of the duty cycle is set to 0.45, i.e., the absolute upper limit of the duty cycle. The absolute lower limit of the duty cycle The maximum allowable change in duty cycle between adjacent periods That is, the maximum change within 1ms It performs safety limits on the PWM duty cycle change rate and amplitude to protect power circuits, avoid impacts, and ensure the smoothness of control quantities.

[0050] In this embodiment, after the system is powered on or reset, it first enters the startup mode (Mode=0). In this mode, a soft-start combined with PI control strategy is used to achieve a stable establishment of the load-side voltage. When the bus voltage is detected to rise significantly due to load dumping and exceed the set threshold, it automatically switches to the linear active disturbance rejection control (ADRC) mode based on the extended state observer to ensure voltage regulation performance and disturbance rejection capability under all operating conditions.

[0051] Specifically, a PI soft-start strategy is used to achieve a smooth establishment of the load-side voltage. After system initialization, the startup phase begins, employing a PI soft-start control strategy: the reference voltage is linearly increased from 0 to 380V (equivalent slope approximately 76V / ms) within 5ms using a reference voltage ramp generator, thus setting the current bus voltage V... bus Error input to the reference voltage PI regulator (proportional gain K) p =0.2, Integral gain K i =0.05), the initial duty cycle is calculated; then the PWM module generates four complementary drive signals (dead time 2μs) to control Q1~Q4 in the H bridge to turn on / off according to the duty cycle, gradually increasing the load side voltage to 380V, avoiding current surges during startup.

[0052] In the startup mode, soft start is used. The purpose is to suppress surge current and voltage overshoot by limiting the initial duty cycle and increasing the load-side voltage at a controlled rate, thereby protecting power devices and loads, reducing electromagnetic interference, and providing stable initial conditions for subsequent closed-loop control, ensuring safe and smooth system startup.

[0053] S3, during the control process, analyzes various indicators related to the system operating conditions based on the collected circuit data, judges the operating conditions of the bidirectional DC-DC converter system, and switches to steady-state mode when a load dumping condition occurs.

[0054] Specifically, step S3 further includes: calculating the bus voltage. With bus voltage setting value relative deviation When the system encounters a load shedding condition, the bus voltage rises rapidly, causing... Once the preset switching range is entered, a relative deviation is detected. When the system enters the preset switching range, it is determined that the system has entered a load shedding condition (i.e., the system determines that the bus voltage has entered an abnormally high range and tends to stabilize). The system immediately exits the startup mode and PI control process and switches to steady-state mode (Mode=1). The preset switching range is 5% to 8% of the rated voltage. In practice, reliable switching should be ensured through experimental verification and adjustable design based on the system's overvoltage tolerance, normal fluctuation range and control stability requirements.

[0055] In this embodiment, electrical parameters are monitored in real time during operation to identify load dumping disturbances and switch to steady-state mode. After the system enters the operating state, the collected electrical parameters are monitored in real time: when a bus voltage fluctuation is detected to exceed 5% (i.e., When a load shedding condition is detected, the control mode is immediately switched from "startup mode" to "steady-state mode". Once the system enters steady-state mode, if the load shedding occurs within a continuous Thold period (e.g., 50ms), the system will continue to operate in steady-state mode. If the load dump transient ends, the control mode is switched back to normal voltage regulation mode; if no disturbance is detected ( If the current control state is maintained, the system will continue to operate.

[0056] S4. In steady-state mode, a composite duty cycle control law is constructed using the LADRC linear active disturbance rejection control strategy. The composite duty cycle control law is then subjected to amplitude limiting to generate a complementary PWM signal to drive the bidirectional DC-DC converter system to recover energy.

[0057] Specifically, step S4 further includes: calculating the bus voltage. With bus voltage setting value Deviation between And according to the preset feedforward parameters Calculate the duty cycle feedforward correction. To construct bus voltage feedforward compensation;

[0058] Estimation of total disturbance based on bidirectional DC-DC converter system Control gain In the calculation of the linear active disturbance rejection control law (LADRC), the LADRC composite control law is constructed. , The output of the PD controller, where the LADRC composite control law is... Includes PD feedback components and ESO feedback components;

[0059] Constructing a composite duty cycle control law As the center duty cycle, and the control law for the composite duty cycle. Amplitude and rate-of-change limiting are applied to generate complementary PWM signals to drive the bidirectional DC-DC converter system to recover energy. The duty cycle feedforward correction is used in this process. LADRC composite control law is used to quickly compensate for the impact of bus voltage deviation on steady-state duty cycle. It undertakes the compensation and dynamic adjustment for unknown disturbances. The control input u related to the duty cycle in the ESO feedback loop is taken as the final output after limiting. This ensures that the input to the ESO model is consistent with the control quantity actually applied to the controlled object.

[0060] Among them, setting feedforward parameters Used for bus voltage compensation, its dimension is 1 / V. Based on steady-state relationships... For small signal changes The steady-state coefficients under the ideal model are calculated (their values ​​are based on the steady-state coefficients under the ideal model). Due to factors such as voltage drop from the switching transistor, additional losses caused by inductors, resistors, and capacitors, a slightly smaller effective duty cycle due to dead time, voltage dips caused by load current variations, and measurement errors in actual circuits, the load-side voltage may be slightly lower than the ideal value. The gain of the correct model will be less than the model prediction, so a margin should be left. The margin.

[0061] In this embodiment, a LADRC linear active disturbance rejection control strategy incorporating an extended state observer (ESO) is employed to generate a composite duty cycle control law, achieving energy recovery and bus voltage stability. In steady-state mode, the LADRC linear active disturbance rejection control strategy is used to construct the control law. First, the unknown state and total disturbance of the system are estimated using the extended state observer (ESO); then, the error is calculated using the ESO output and the bus voltage. Input to the PD controller (replace the error with bus voltage deviation as described above). And estimated by ESO Replace the direct differential term; K p_adrc =1.5, K d_adrc =0.3), generating an active disturbance rejection feedback component; simultaneously introducing feedforward compensation (based on the load-side voltage V). rec Feedforward gain K f =0.8), together with the feedforward component, constitutes a composite duty cycle control law; finally, the duty cycle is limited to generate a complementary PWM signal to drive the H-bridge, realizing two core functions: first, the excess energy generated by the load dump transient is discharged to the RC unit through the energy absorption branch (the diode only conducts in the transient state and does not introduce steady-state losses); second, the LADRC control law quickly adjusts the full-bridge duty cycle to stabilize the bus voltage within the range of 380V±2%.

[0062] Please refer to Figure 5 , Figure 5 The diagram illustrates the specific control logic block diagram for constructing the composite duty cycle control law in step S4. The diagram clearly depicts the dual-channel control structure: the upper channel is a feedback control loop based on the ESO observation state, utilizing a PD controller to handle voltage tracking error and disturbance compensation; the lower channel is based on the load-side voltage V... recThe feedforward compensation loop improves the system's response speed to load changes through the gain K_ff. The output signals of the two channels converge at the summing node to form a composite control quantity, which is then processed by the saturation limiting circuit to finally generate the PWM waveform driving the H-bridge switches Q1-Q4, thereby achieving precise regulation of the bus voltage and recovery of excess energy.

[0063] In simple terms, after the system enters steady-state mode (Mode=1), a damping control strategy based on linear active disturbance rejection control (ADRC) is adopted. The system state and total disturbance are estimated in real time through an extended state observer (ESO). A composite duty cycle control law is constructed by combining feedforward compensation and PD control. After amplitude and rate of change limiting, a complementary PWM signal is generated to drive the bidirectional DC-DC converter to achieve stable energy transfer and recovery.

[0064] In this embodiment, Figure 6 This diagram illustrates the comparison of bus voltage response waveforms before and after optimization for a 380V system under load dump conditions. The horizontal axis represents time, and the vertical axis represents bus voltage amplitude. The comparison curve (before optimization / traditional PI control) shows that at the moment of load dump, the bus voltage experiences a significant overshoot, with the peak voltage far exceeding the 380V safety range, accompanied by prolonged and difficult-to-converge oscillations. The curve in this embodiment (after optimization / LADRC linear active disturbance rejection control) shows that, using the strategy of this invention, when facing the same load dump disturbance, the bus voltage fluctuation is significantly suppressed within the range of 380V ± 2%, and the voltage waveform shows no obvious oscillations, rapidly returning to and stabilizing at the 380V reference value. This comparison strongly verifies the superior performance of the ESO-based LADRC linear active disturbance rejection control method proposed in this invention in suppressing load dump disturbances, ensuring bus voltage stability, and achieving efficient energy recovery.

[0065] In summary, this invention innovatively introduces an RC circuit and a diode to form an auxiliary branch based on the traditional topology. This design aims to explore a novel vibration-damping and voltage-regulating scheme that combines high efficiency and high stability by optimizing the control strategy and the synergistic effect of the auxiliary circuit parameters without changing the main power loop. Please refer to [link / reference]. Figure 3 The flowchart visually illustrates the complete logical closed loop of the system from power-on: First, step S1 is executed to construct the bidirectional DC-DC converter topology and initialize the parameters; then step S2 is executed, and the H-bridge switching transistor is controlled by the PI soft-start strategy to make the load-side voltage rise smoothly to 380V at a preset slope; after entering the operation phase, the system executes the real-time monitoring loop of step S3 to continuously determine whether the bus voltage fluctuation rate exceeds the 5% threshold; once a load dump disturbance is detected, the process immediately jumps to step S4 and enters the LADRC linear active disturbance rejection control algorithm in steady-state mode to maintain system stability.

[0066] Specifically, the converter introduces an energy recovery auxiliary branch consisting of diodes and an RC circuit on the main inductor side. The control method includes: establishing a circuit model with the auxiliary branch and initializing parameters; entering startup mode after system power-on, using a PI soft-start strategy to control the full-bridge MOSFETs to achieve stable load-side voltage establishment; real-time monitoring of bus voltage and load status, automatically switching to steady-state mode when a load dump condition causes an abnormal voltage increase; in steady-state mode, a damping strategy based on Linear Active Disturbance Rejection Control (LADRC) is adopted, utilizing a second-order extended state observer (ESO) to estimate and compensate for the total system disturbance in real time, combined with voltage feedforward to construct a composite duty cycle control law to drive the converter. This invention, through hardware and software collaboration, effectively suppresses the resonance generated by the coupling between the input-side LC filter and the constant power load without increasing physical damping losses, significantly improving the system's voltage regulation accuracy and dynamic stability under load dump disturbances.

[0067] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions, characterized in that, include: A bidirectional DC-DC converter system is established, its circuit data is collected, and the system is initialized based on this data. Its control mode is then set to startup mode. Specifically: Based on the topology of the bidirectional DC-DC converter with a main inductor, a circuit model is established, and an energy absorption branch consisting of a diode and an RC parallel unit connected in series is introduced on the main inductor side of the circuit model. At the same time, a sampling circuit is connected externally to the circuit model to form a bidirectional DC-DC converter system. The RC parallel unit consists of a bleed resistor R and a buffer capacitor Cs connected in parallel. Real-time acquisition of circuit data from the bidirectional DC-DC converter system, including: bus voltage. Load side voltage and inductor current ; The bidirectional DC-DC converter system is initialized based on the circuit data, and its control mode is set to the startup mode. Based on the LADRC linear active disturbance rejection control theory, the parameters of the second-order state observer ESO, the bandwidth of the controller, the bandwidth of the observer, and the parameters of the PD controller are set. In startup mode, the bidirectional DC-DC converter system adopts a soft-start combined with PI control strategy. The duty cycle is calculated by the reference voltage ramp and the PI regulator. The preset PWM module generates four drive signals according to the duty cycle, which control the four MOSFETs in the full-bridge topology to turn on and off according to the set duty cycle. During the control process, the system analyzes various indicators related to the system operating conditions based on the collected circuit data to determine the operating conditions of the bidirectional DC-DC converter system. When a load dumping condition occurs, the system switches to steady-state mode. In steady-state mode, a composite duty cycle control law is constructed using the LADRC linear active disturbance rejection control strategy, and the composite duty cycle control law is amplitude-limited to generate a complementary PWM signal to drive the bidirectional DC-DC converter system to recover energy. In startup mode, the soft-start process of the bidirectional DC-DC converter system is as follows: Set reference voltage ramp time When it is determined that the system running time t is less than the reference voltage ramp time At that time, reference voltage It grows linearly over time. The target load-side voltage; When it is determined that the system running time t is greater than or equal to the reference voltage ramp time At that time, reference voltage The value remains unchanged, and the system enters the PI control phase. During the control process, the operating conditions of the bidirectional DC-DC converter system are determined by analyzing the collected circuit data and various indicators related to the system's operating conditions. When a load dump condition occurs, the system switches to steady-state mode, specifically by calculating the bus voltage. With bus voltage setting value relative deviation When the relative deviation is determined When the system enters the preset switching range, it is determined that the system is experiencing a load dumping condition, and it immediately exits the startup mode and PI control process, switching to steady-state mode; wherein, the preset switching range is 5% to 8% of the rated voltage.

2. The adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions according to claim 1, characterized in that, The buffer capacitor Cs in the energy absorption branch is selected as a capacitor with a withstand voltage value exceeding the set bus voltage by 50% to 100%.

3. The adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions according to claim 1, characterized in that, Based on LADRC linear active disturbance rejection control theory, the parameters of the second-order state observer (ESO), the bandwidth of the controller, the bandwidth of the observer, and the parameters of the PD controller are set as follows: For the current topology of the bidirectional DC-DC converter system, construct a second-order system. ,in, Bus voltage The measured value, , , All are state variables. The value is the bus voltage. , for The first derivative, The value is the bus voltage. rate of change, for The first derivative, To control the gain, For control inputs related to duty cycle, This represents the total disturbance of the bidirectional DC-DC converter system. Introduce extended states, let And assume Extending the second-order system to a third-order system , for The first derivative, for The first derivative, The rate of change of the disturbance; Based on the Romberg observer form, the defined bus voltage The estimated value Bus voltage The estimated rate of change Estimate of the total disturbance of the bidirectional DC-DC converter system ; A Romberg-form full-dimensional state observer is constructed in the continuous-time domain, yielding the continuous-time observer dynamic equations. ,in, for The first derivative, for The first derivative, for The first derivative, , , All are observer gains; Let the observation error be... To obtain the error dynamics , This represents the first-order state estimation error. This represents the second-order state estimation error. For the disturbance estimation error, for The first derivative, for The first derivative, for The first derivative; Will Subsuming it into higher-order remainder terms, we obtain the linear error system. , , For the coefficient matrix of the linear error system, its eigenvalues ​​determine the convergence rate of the observation error; The desired pole location is selected based on the pole placement method. Let the desired third-order characteristic polynomial of the observer be... , For complex variables, For observer bandwidth; Based on the linear error system, its characteristic polynomial is obtained. And the observer gain is determined by the matching coefficient. , , Among them, let ,get , , Observer error Exponential convergence, This is the matrix determinant operator. It is a third-order identity matrix.

4. The adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions according to claim 3, characterized in that, Also includes: Let the target value of the bus voltage of the bidirectional DC-DC converter system be... The PD controller is controlled by adjusting its output. The state variables estimated by ESO Track r while utilizing state variables The differential term suppresses voltage fluctuations, because in actual systems... It cannot be measured directly; it must be measured using... Replace the direct differential term, where, The output of the PD controller will be used as the subsequent LADRC composite control law. PD feedback component in The bus voltage setting value; Match the PD controller to the topology of the bidirectional DC-DC converter, assuming the bidirectional DC-DC converter object model is as follows. Under ideal conditions, ignoring disturbances, we obtain ; Obtained through PD control rate Substitute ,get , , These are all PD controller parameters; Assume error ,right Taking the derivative, we get , , , for The first derivative, for The first derivative, for The second derivative; The homogeneous differential equation of the error is obtained by rearranging. And by performing a Laplace transform on the aligned differential equation, we obtain... , For error The Laplace transform of; Let the controller bandwidth be The closed-loop characteristic equation is obtained. Take complex variables The expected characteristic equation is By comparing the closed-loop characteristic equation and the desired characteristic equation, the PD controller parameters are obtained. , .

5. The adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions according to claim 4, characterized in that, Observer bandwidth With controller bandwidth The ratio is 4:

1.

6. The adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions according to claim 4, characterized in that, The PI control process is as follows: Calculate the load-side voltage With reference voltage Error between And according to the preset soft-start PI parameters , Sum of error integral terms Calculate the pre-duty cycle Execute integral anti-saturation logic; Only when the pre-duty cycle is within the preset allowable range When the error is within the limit range or at the limit range boundary and the error direction is opposite to the limit range direction, update the error integral term. To obtain the final duty cycle The amplitude and rate of change are limited. The preset PWM module generates four corresponding drive signals according to the duty cycle, controlling the four MOSFETs in the full-bridge topology to turn on and off according to the set duty cycle. This is the updated error integral term, where h is the sampling period. This is the absolute lower limit of the duty cycle. This represents the absolute upper limit of the duty cycle.

7. The adaptive damping control method for a bidirectional DC-DC converter under load dumping conditions according to claim 6, characterized in that, A composite duty cycle control law is constructed using the LADRC linear active disturbance rejection control strategy. This composite duty cycle control law is then amplitude-limited to generate a complementary PWM signal, which drives the bidirectional DC-DC converter system to recover energy. Specifically: Calculate bus voltage With bus voltage setting value Deviation between And according to the preset feedforward parameters Calculate the duty cycle feedforward correction. To construct bus voltage feedforward compensation; Estimation of total disturbance based on bidirectional DC-DC converter system Control gain In the calculation of the linear active disturbance rejection control law (LADRC), the LADRC composite control law is constructed. , The output of the PD controller, where the LADRC composite control law is... Includes PD feedback components and ESO feedback components; Constructing a composite duty cycle control law As the center duty cycle, and the control law for the composite duty cycle. Amplitude and rate-of-change limiting are applied to generate complementary PWM signals to drive the bidirectional DC-DC converter system to recover energy. The duty cycle feedforward correction is used in this process. LADRC composite control law is used to quickly compensate for the impact of bus voltage deviation on steady-state duty cycle. It undertakes the compensation and dynamic adjustment for unknown disturbances. The control input u related to the duty cycle in the ESO feedback loop is taken as the final output after limiting. This ensures that the input to the ESO model is consistent with the control quantity actually applied to the controlled object.

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