Energy recovery circuit device applied to parasitic capacitance and control method thereof

Abstract

Embodiments of the present application provide an energy recovery circuit device applied to parasitic capacitance, which can be applied to the technical field of integrated circuit chip control. The device comprises a double-edge delay circuit module, a logic drive circuit module, a full-bridge drive circuit module and a resonant inductor. The logic drive circuit module is used to generate at least one drive control signal according to at least one timing control signal; the full-bridge drive circuit module is used to update a drive electrical signal applied to a target load according to at least one drive control signal; the resonant inductor and the target load are connected in series between two output terminals of the full-bridge drive circuit module, and in a window period in which the drive electrical signal is controlled and updated, the resonant inductor and the target load form an inductor-capacitor resonant loop to realize energy recovery of the parasitic capacitance of the target load. Embodiments of the present application also provide a control method, equipment, storage medium and program product of the energy recovery circuit device applied to parasitic capacitance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip control technology, specifically to the field of chip driver circuit technology, and more specifically to an energy recovery circuit device for parasitic capacitance and its control method, equipment, medium and product. Background Technology

[0002] Various portable electronic products (such as mobile phones and tablets) and cutting-edge technologies (such as lithography, artificial intelligence, and aerospace) rely on common supporting technologies like precision drive to achieve high-precision operation of their core technologies. The various drive parameters of precision drive technology directly determine the processing precision (such as lithography machines), control precision (such as robots), detection precision (such as various testing instruments and even mobile phones), and flight trajectory precision (such as spacecraft) of related high-precision products. Traditional precision drive is mainly achieved through electromagnetic drive technology, but with technological advancements, piezoelectric drive technology is gradually becoming the core direction of precision drive technology.

[0003] Piezoelectric actuation is a novel driving technology that utilizes the inverse piezoelectric effect of piezoelectric materials to convert electrical energy into mechanical energy, thereby achieving motion output. However, the energy loss problem caused by the parasitic capacitance of piezoelectric ceramic elements is widely recognized, especially in high-frequency square wave driving applications. Moreover, during the voltage step transition across the capacitor, if a large amount of energy is generated, it will create a large current pulse. The voltage overshoot caused by this large current can easily damage circuit components such as chips and ceramic sheets. Traditional solutions are currently unable to efficiently and cost-effectively recover the pulse energy released by the parallel parasitic capacitance during drive switching, making it difficult to further improve system efficiency. Summary of the Invention

[0004] To address at least one of the technical problems in existing piezoelectric drive technology, namely increased circuit energy consumption due to parasitic capacitance and the generation of large current pulses during voltage step transitions across the capacitor, embodiments of the present invention propose an energy recovery circuit device for parasitic capacitance, as well as its control method, equipment, medium, and products. This provides a new parasitic capacitance energy recovery drive architecture that is simpler, more efficient, stable, and lower in cost. It can directly recover parasitic capacitance energy that is easily dissipated by resistance during voltage switching of a target load (such as a piezoelectric ceramic air pump or other loads based on an RLC circuit model or a similar RLC circuit model), thereby significantly improving the overall efficiency of the circuit system and effectively avoiding energy waste and the danger of overcharging caused by parasitic capacitance during voltage switching in circuits such as piezoelectric actuators.

[0005] Another aspect of the present invention provides an energy recovery circuit device for parasitic capacitance, comprising a bilateral delay circuit module, a logic drive circuit module, a full-bridge drive circuit module, and a resonant inductor. The bilateral delay circuit module generates at least one timing control signal in response to a preset clock signal; the logic drive circuit module is connected to at least one output terminal of the bilateral delay circuit module and generates at least one drive control signal according to the at least one timing control signal; the full-bridge drive circuit module is connected to both ends of the target load and at least one output terminal of the logic drive circuit module, and is used to connect to a preset input power supply and update the drive signal applied to the target load according to the at least one drive control signal; the resonant inductor is connected in series with the target load between the two output terminals of the full-bridge drive circuit module. During the window period when the drive signal is controlled to be updated, the resonant inductor and the target load form an inductor-capacitor resonant circuit, realizing energy recovery from the parasitic capacitance of the target load.

[0006] According to an embodiment of the present invention, the bilateral delay circuit module operates to output a first delay signal and a second delay signal according to a preset clock signal; wherein, the first delay signal is a timing control signal formed by delaying the rising edge of the preset clock signal by a preset fixed time; the second delay signal is another timing control signal formed by delaying the falling edge of the preset clock signal by a preset fixed time; wherein, the preset fixed time is half of the series resonance period of the inductor-capacitor resonant circuit.

[0007] According to an embodiment of the present invention, the logic driving circuit module includes a first logic driving unit, a second logic driving unit, a third logic driving unit, and a fourth logic driving unit. The first logic driving unit is used to output a first driving control signal according to a first delay signal; the second logic driving unit is used to output a second driving control signal according to the first delay signal; the third logic driving unit is used to output a third driving control signal according to the first delay signal; and the fourth logic driving unit is used to output a fourth driving control signal according to the second delay signal. The first, second, third, and fourth driving control signals are simultaneously input to four different input terminals of the full-bridge driving circuit module to update the driving electrical signal applied to the target load according to a preset input power supply.

[0008] According to an embodiment of the present invention, a first logic driving unit includes a first latch unit, wherein the source of a first transistor of the first latch unit is connected to a first preset reference power supply, the source of a second transistor of the first latch unit is grounded, and the drains of the first transistor and the second transistor are connected to form an output terminal of the first latch unit for outputting a first driving control signal; a second logic driving unit includes a second latch unit, wherein the source of a third transistor of the second latch unit is connected to the first preset reference power supply, the source of a fourth transistor of the second latch unit is grounded, and the drains of the third transistor and the fourth transistor are connected to form an output terminal of the second latch unit for outputting a second driving control signal.

[0009] According to one embodiment of the present invention, a third logic driving unit includes a third latch unit and a first level converter connected in series therewith. The source of the fifth transistor of the third latch unit is connected to a preset input power supply, the source of the sixth transistor of the third latch unit is connected to a second preset reference power supply, and the drains of the fifth transistor and the sixth transistor are connected to form the output terminal of the third latch unit. The first level converter is used to convert a first delayed signal input to the third latch unit into a first high-voltage domain signal, and the third latch unit converts the first high-voltage domain signal into a third drive control signal. A fourth logic driving unit includes a fourth latch unit and a second level converter connected in series therewith. The source of the seventh transistor of the fourth latch unit is connected to a preset input power supply, the source of the eighth transistor of the fourth latch unit is connected to a second preset reference power supply, and the drains of the seventh transistor and the eighth transistor are connected to form the output terminal of the fourth latch unit. The second level converter is used to convert a second delayed signal input to the fourth latch unit into a second high-voltage domain signal, and the fourth latch unit converts the second high-voltage domain signal into a fourth drive control signal.

[0010] According to an embodiment of the present invention, the full-bridge drive circuit module includes a first control switch, a second control switch, a third control switch, and a fourth control switch. The gate of the first control switch is connected to a first drive control signal, its drain is connected to one end of the target load, and its source is grounded; the gate of the second control switch is connected to a second drive control signal, its drain is connected to one end of the resonant inductor, and its source is grounded; the gate of the third control switch is connected to a third drive control signal, its drain is connected to the drain of the second control switch to form an output terminal of the full-bridge drive circuit module, and its source is connected to a preset input power supply; the gate of the fourth control switch is connected to a fourth drive control signal, its drain is connected to the drain of the first control switch to form another output terminal of the full-bridge drive circuit module, and its source is connected to a preset input power supply.

[0011] According to an embodiment of the present invention, the energy recovery circuit device applied to parasitic capacitance further includes a zero-crossing comparator circuit module. The first input terminal of the zero-crossing comparator circuit module is connected to one end of the resonant inductor and is used to detect the actual operating electrical signal of the resonant inductor; its second input terminal is grounded, and its third input terminal is connected to a preset clock signal; its output terminal is connected to a bilateral delay circuit module; wherein, in response to the preset clock signal, the zero-crossing comparator circuit module outputs a delay control signal to the bilateral delay circuit module according to the change in the actual operating electrical signal of the resonant inductor.

[0012] According to an embodiment of the present invention, a bilateral delay circuit module updates a first delay signal and / or a second delay signal according to a delay control signal, including: after the rising edge of a preset clock signal, when the absolute value of the actual working electrical signal reaches a preset threshold, pulling the preset clock signal high to generate the updated first delay signal within a preset fixed time; and / or after the falling edge of the preset clock signal, when the absolute value of the actual working electrical signal reaches a preset threshold, pulling the preset clock signal low to generate the updated second delay signal within a preset fixed time.

[0013] Another aspect of the present invention provides a control method for the above-described energy recovery circuit device applied to parasitic capacitance, wherein the energy recovery circuit device applied to parasitic capacitance includes a resonant inductor connected in series with a target load to form an inductor-capacitor resonant circuit, and the control method includes: generating at least one timing control signal in response to a preset clock signal; generating at least one drive control signal according to the at least one timing control signal; and updating a drive electrical signal applied to the target load according to the at least one drive control signal; wherein, during the window period in which the drive electrical signal is controlled to be updated, the inductor-capacitor resonant circuit is used to realize energy recovery of the parasitic capacitance of the target load.

[0014] Another aspect of the present invention provides an electronic device including one or more processors and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to perform the control method described above for an energy recovery circuit device for parasitic capacitance.

[0015] Another aspect of the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the control method described above for an energy recovery circuit device applied to a parasitic capacitor.

[0016] Another aspect of the present invention provides a computer program product including a computer program that, when executed by a processor, implements the control method described above for an energy recovery circuit device applied to a parasitic capacitor.

[0017] The energy recovery circuit device and control method for parasitic capacitance provided in this invention can at least partially solve at least one of the technical problems in piezoelectric drive technology, namely, increased circuit energy consumption due to parasitic capacitance and the generation of large current pulses during voltage step transitions across the capacitor. Therefore, it can achieve at least one of the following technical effects:

[0018] 1. Significantly improve driving efficiency: Through the inductor-capacitor resonant circuit composed of the above-mentioned bilateral delay circuit module, logic drive circuit module, full-bridge drive circuit module and resonant inductor, the energy of parasitic capacitance dissipated by resistors during the switching of drive voltage in traditional piezoelectric drive design can be directly recovered (especially in high-speed, high-frequency switching piezoelectric applications, the energy loss caused by this part of parasitic capacitance accounts for a very large proportion). The recovery of parasitic capacitance energy can significantly improve the overall system efficiency (the efficiency can be improved by more than 20%, the specific value depends on the operating frequency and voltage amplitude).

[0019] 2. Improved voltage switching waveform: The resonance process of the inductor-capacitor resonant circuit can make the voltage change of the parasitic capacitance closer to a sinusoidal trajectory. Therefore, compared with the sharp voltage jump (dV / dt) generated by direct hard switching, the voltage waveform edge is softened to a certain extent, which effectively reduces the occurrence of overcharging and ringing. It is safer for the target load such as piezoelectric elements and surrounding circuits, and has less electromagnetic interference (EMI) radiation and noise impact.

[0020] 3. Simpler circuit structure: Compared with the traditional piezoelectric drive circuit design, the energy recovery circuit device of this invention adds only an inductor and its matching timing signal drive control module (such as a bilateral delay circuit module and a logic drive circuit module) as the core components. Compared with the existing complex active energy recovery schemes, the structure is simpler, the cost is lower, and it is easier to integrate into the existing piezoelectric drive architecture.

[0021] In summary, this invention provides an efficient, practical, and easy-to-implement energy recovery scheme for piezoelectric drive technology, effectively solving the core problem of energy waste caused by parallel parasitic capacitance in square wave drive processes of piezoelectric actuators, etc., and has significant practical value and economic benefits.

[0022] Therefore, the energy recovery circuit device and control method for parasitic capacitance described above in the embodiments of the present invention can be more widely adapted to the needs of small and high-efficiency scenarios. Even under the current chip manufacturing process level, it can be better applied to high-precision electronic products (such as micro heat sinks for automotive chips or mobile phone chips) or equipment (such as extreme ultraviolet light source chips for lithography machines), and has a very wide range of product applications.

[0023] Therefore, the energy recovery circuit device and control method for parasitic capacitors based on the embodiments of the present invention can provide a parasitic capacitor energy recovery technology that is more efficient, more stable, lower power consumption, lower cost, more practical, easier to implement and promote compared to existing energy recovery schemes. It can directly recover the energy of parasitic capacitors that are dissipated by resistors at the moment of driving voltage switching in traditional piezoelectric drive design schemes, significantly improve the working efficiency of circuit system, and has extremely important practical value and economic benefits.

[0024] It should be understood that the above general description and the following specific embodiments are merely exemplary and illustrative, and do not limit the scope of the invention. Attached Figure Description

[0025] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1 The diagram schematically illustrates the equivalent circuit composition of a simplified electrical model of a target load (piezoelectric ceramic air pump) according to an embodiment of the present invention.

[0027] Figure 2A This schematic diagram illustrates the circuit structure of an energy recovery circuit device 100 applied to parasitic capacitance according to an embodiment of the present invention.

[0028] Figure 2B The illustration shows the corresponding embodiment of the present invention. Figure 2A The diagram shows the equivalent circuit composition of the inductor-capacitor resonant circuit used in an energy recovery circuit device for parasitic capacitance.

[0029] Figure 3 The illustration shows the corresponding embodiment of the present invention. Figure 2A and Figure 2B The diagram shows a comparison of the timing variations of the main electrical signals in the energy recovery circuit device applied to parasitic capacitance (the target load P is a piezoelectric ceramic air pump).

[0030] Figure 4A The illustration shows the corresponding embodiment of the present invention. Figure 2A The circuit structure diagram shown is of the first logic drive unit 401 of the logic drive circuit module DR applied to the energy recovery circuit device of parasitic capacitance.

[0031] Figure 4B The illustration shows the corresponding embodiment of the present invention. Figure 2A The circuit structure diagram shown is of the second logic drive unit 402 of the logic drive circuit module DR applied to the energy recovery circuit device of parasitic capacitance.

[0032] Figure 4C The illustration shows the corresponding embodiment of the present invention. Figure 2A The circuit structure diagram shown is of the third logic drive unit 403 of the logic drive circuit module DR applied to the energy recovery circuit device of parasitic capacitance.

[0033] Figure 4D The illustration shows the corresponding embodiment of the present invention. Figure 2A The circuit structure diagram shown is of the fourth logic drive unit 404 of the logic drive circuit module DR applied to the energy recovery circuit device of parasitic capacitance.

[0034] Figure 5 The illustration schematically depicts an application scenario of an energy recovery circuit device, control method, apparatus, medium, and program product for parasitic capacitance according to an embodiment of the present invention.

[0035] Figure 6 A flowchart illustrating a control method for an energy recovery circuit device applied to a parasitic capacitor according to an embodiment of the present invention is shown.

[0036] Figure 7 A block diagram of an electronic device according to an embodiment of the present invention is shown schematically, which is suitable for implementing a control method for an energy recovery circuit device applied to a parasitic capacitor.

[0037] The accompanying drawings mentioned above are part of the specification of embodiments of the present invention, illustrating exemplary embodiments of the invention. The drawings, together with the description in the specification, serve to illustrate the principles of the embodiments of the present invention. It should be understood that the above general description with reference to the drawings and the following detailed description are merely exemplary and illustrative, and do not limit the scope of the invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the spirit of the contents disclosed in the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the technology taught in the present invention without departing from the spirit and scope of the present invention.

[0039] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0040] The terms "first," "second," etc., used in this invention do not specifically refer to any order or sequence, nor are they intended to limit the invention; they are merely used to distinguish elements or operations described using the same technical terms.

[0041] The directional terms used in this invention, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this invention.

[0042] The terms “comprising,” “including,” “having,” “containing,” etc., used in this invention are all open-ended terms, meaning that they include but are not limited to.

[0043] The term "and / or" as used in this invention includes any or all combinations of the things mentioned.

[0044] In this invention, "multiple" includes "two" and "more than two"; in this invention, "multiple groups" includes "two groups" and "more than two groups".

[0045] The terms "approximately," "about," etc., used in this invention are intended to modify any quantity or error that may vary slightly, but these slight variations or errors do not change the essence of the quantity or error. Generally, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in some embodiments, 5% in some embodiments, or other values. Those skilled in the art should understand that the aforementioned values ​​can be adjusted according to actual needs and are not limited thereto.

[0046] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0047] When expressions such as "at least one of A, B, and C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When expressions such as "at least one of A, B, or C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). A person skilled in the art should also understand that any conjunction and / or phrase that substantially arbitrarily indicates two or more optional items, whether in the specification, claims, or drawings, should be understood to indicate the possibility of including one of these items, either of these items, or both items. For example, the phrase “A or B” should be understood as including the possibility of “A” or “B”, or “A and B”.

[0048] The principle of piezoelectric drive technology lies in the fact that piezoelectric ceramic elements undergo minute mechanical deformation under the influence of an external electric field. This mechanical deformation can be used to achieve direct output with nanometer precision within a microscale range, a process known as piezoelectric ceramic direct deformation braking. Furthermore, piezoelectric ceramic elements and metallic elastomers can form elastic composites of specific shapes. By applying specific signals to the piezoelectric ceramic elements, the stator elastomer can be excited to generate low-frequency motion / high-frequency vibration. Within the driving region of the stator elastomer, particles form motion trajectories (straight lines, oblique lines, rectangles, triangles, and ellipses, etc.) with a driving effect. The macroscopic motion output of the mover is further achieved through frictional coupling between the stator and mover. Therefore, compared to traditional precision drive technologies, piezoelectric drive technology offers advantages such as high displacement resolution, fast response speed, high output density, high thrust at low speeds, diverse configurations, self-locking upon power failure, no electromagnetic interference, good environmental adaptability, and diverse motion forms.

[0049] However, in the field of piezoelectric drives, especially in applications involving high-frequency square wave drives, piezoelectric ceramic air pumps (such as Piezo) are crucial. Figure 1 As shown, the load P, when driven, often generates a parasitic capacitance C0, leading to significant energy loss. Furthermore, during voltage step transitions, this can easily cause large current pulses, resulting in overcharging (which can easily damage the load and chip). Specifically... Figure 1 As shown, in the simplified electrical model of the equivalent circuit, the parasitic capacitance C0 and the corresponding parasitic resistance R0 can be connected in parallel across the load.

[0050] Traditional solutions to the energy loss caused by parasitic capacitance and the large current generated during voltage transitions across the capacitor in piezoelectric drive technology are mainly limited to three methods: direct dissipation, RC absorption circuits, and active clamping / energy recovery attempts.

[0051] 1) Direct dissipation: The on-resistance of the switching transistor and the line resistance inside the drive circuit naturally dissipate the energy of the parasitic capacitance C0 during charging and discharging. This is the simplest but least efficient method, and the energy is completely wasted. This wasted energy can reduce the overall efficiency of the drive circuit by at least 20%.

[0052] 2) RC snubber circuit: An RC snubber network is connected in parallel across the driver terminals or on the drive power rail. This circuit dissipates the energy released by the parasitic capacitance C0 through the resistor R. Although it can slow down the rate of voltage change and suppress some EMI, it also wastes energy, fails to recover energy, and the resistor itself consumes power.

[0053] 3) Active clamping / energy recovery attempts: Some more complex energy recovery schemes exist, such as using additional switched capacitor circuits or auxiliary switching transistors to transfer the energy of parasitic capacitance C0 to intermediate energy storage capacitors. However, these schemes usually require complex control logic and additional power devices, increasing system cost, size, and control difficulty, and may have limitations in terms of recovery efficiency and transient response.

[0054] In summary, the common drawback of existing technologies is that they cannot efficiently and cost-effectively recover the pulse energy released by the parallel parasitic capacitor C0 at the moment of drive switching, making it difficult to further improve system efficiency.

[0055] Addressing at least one of the technical problems in existing piezoelectric drive technology—namely, increased circuit energy consumption due to parasitic capacitance and the generation of large current pulses during voltage step transitions across the capacitor—this invention proposes an energy recovery circuit device for parasitic capacitance, along with its control method, equipment, medium, and product. This provides a simpler, more efficient, stable, and lower-cost novel parasitic capacitance energy recovery drive architecture. It can directly recover parasitic capacitance energy, which is easily dissipated by resistance during voltage switching, from target loads (such as piezoelectric ceramic air pumps based on RLC or RLC-like circuit models). This significantly improves the overall efficiency of the circuit system and effectively avoids energy waste and the danger of overcharging caused by parasitic capacitance during voltage switching in circuits such as piezoelectric actuators.

[0056] To enable those skilled in the art to have a clearer understanding of the energy recovery circuit device 100 and its control method applied to parasitic capacitance described in the embodiments of the present invention, further provisions are provided as follows: Figures 1-6 Explanation.

[0057] like Figures 1-2B As shown, another aspect of the present invention provides an energy recovery circuit device for parasitic capacitance. The energy recovery circuit device 100 for parasitic capacitance includes a bilateral delay circuit module DELAY, a logic drive circuit module DR, a full-bridge drive circuit module H, and a resonant inductor Lr.

[0058] The dual-sided delay circuit module DELAY is used to generate at least one timing control signal in response to a preset clock signal CLK_IN;

[0059] The logic drive circuit module DR is connected to at least one output terminal of the bilateral delay circuit module DELAY, and is used to generate at least one drive control signal according to at least one timing control signal.

[0060] The full-bridge drive circuit module H (such as H-Bridge) is connected to both ends of the target load P and at least one output terminal of the logic drive circuit module DR. It is used to connect to the preset input power supply VDD and update the drive electrical signal applied to the target load P according to at least one drive control signal.

[0061] The resonant inductor Lr and the target load P are connected in series between the two output terminals of the full-bridge drive circuit module H. During the window period when the drive signal is controlled and updated, the resonant inductor Lr and the target load P form an inductor-capacitor resonant circuit (LC resonant circuit) to realize the energy recovery of the parasitic capacitance C0 of the target load P.

[0062] The dual-sided delay circuit module DELAY can be implemented based on a dual-sided delay circuit, enabling precise delay processing of the input electrical signal and effectively achieving accurate timing control of system signals. The preset clock signal CLK_IN, as a timing control electrical signal, can serve as the working input signal or working start signal of the energy recovery circuit device 100. Specifically, it can be pre-adjusted based on the actual working requirements of the energy recovery device 100 and the expected energy recovery effect of parasitic capacitance. The dual-sided delay circuit module DELAY can provide at least one aspect of delay to the received preset clock signal CLK_IN (such as the forward time delay of signal propagation and the reverse time delay of signal return). Typically, the rising and falling edges of the preset clock signal CLK_IN need to be considered to ensure the accuracy and stability of the delay. At least one timing control signal is the clock signal generated by the dual-sided delay circuit module DELAY through the delay processing of the preset clock signal CLK_IN.

[0063] The logic driver circuit module DR primarily functions to generate the drive control signals required by the full-bridge driver circuit module H based on at least one timing control signal provided by the bilateral delay circuit module DELAY. The input terminal of the logic driver circuit module DR can be connected to the output terminal of the bilateral delay circuit module DELAY to receive at least one timing control signal. Furthermore, the logic driver circuit module DR can generate a corresponding number of drive control signals based on the at least one timing control signal, such that when these drive control signals are applied to the corresponding input terminals of the full-bridge driver circuit module H, the output electrical signals at the two output terminals of the full-bridge driver circuit module H can be updated, thereby further updating the drive electrical signals on the target load P.

[0064] The full-bridge drive circuit module H can be a load drive circuit implemented based on four control switching circuit elements, capable of precisely switching the polarity of the electrical signals across the load, thereby controlling the direction of the drive electrical signals. In this embodiment of the invention, the target load P can be a load device based on an RLC circuit model or a similar RLC circuit model, such as a piezoelectric ceramic air pump or a micro fan. Figure 1 and Figure 2B As shown, a piezoelectric ceramic air pump, acting as the target load P, typically has a resistor Rs, an inductor Ls, and a capacitor Cs connected in series. The target load P has its own inherent resonant frequency (i.e., intrinsic resonant frequency). Under a constant input voltage, the output power of the target load P is maximized when its actual operating frequency equals its intrinsic resonant frequency. The preset input power supply VDD can serve as the driving power supply for the target load P. By connecting to the full-bridge drive circuit module H, it provides the corresponding operating electrical signal, enabling the target load P to operate normally. The driving electrical signal can be understood as the current or voltage signal of the target load P under normal operating conditions. It can also reflect the corresponding parasitic capacitance C0 and parasitic resistance R0, specifically as follows... Figure 2B As shown.

[0065] The target load P is connected between the two output terminals (OUT+ and OUT-) of the full-bridge drive circuit module H. Simultaneously, the resonant inductor Lr is also connected between these two output terminals and is connected in series with the target load P. The update of the drive signal on the target load P can be controlled by at least one drive control signal to switch the polarity of the drive voltage between the two output terminals OUT+ and OUT- of the full-bridge drive circuit module H. To achieve energy recovery of the parasitic capacitor C0 during the polarity switching of the driving voltage, a resonant inductor Lr is introduced in series with the target load P between the output terminals OUT+ and OUT-. This allows the two to form an inductor-capacitor resonant circuit (i.e., an LC resonant circuit) during the polarity switching process (i.e., the switching window). At this time, the parasitic capacitor C0 can charge the resonant inductor Lr, storing the energy in the resonant inductor Lr. Then, the resonant inductor Lr can discharge the energy to the target load P in the reverse direction, realizing the polarity reversal of the driving voltage. This directly achieves energy recovery of the parasitic capacitor C0 connected in parallel on the target load (such as a piezoelectric driver), effectively avoiding the energy loss of the parasitic capacitor C0.

[0066] Specifically, such as Figures 2A-3 As shown, when the preset clock signal CLK_IN appears with a falling edge, the driving voltage between the output terminals OUT- and OUT+ of the full-bridge drive circuit module H will decrease from the preset input power supply VDD to 0V. At this time, the voltage Vx at the junction between the capacitor Cs and the resonant inductor Lr of the target load P will also decrease from VDD. At this time, the current flowing through the target load P (as the driving signal) rises from zero, changes in a shape close to a sine wave, and decreases after reaching its peak. The intrinsic resonant period T of the series resonance of this LC resonant circuit satisfies the following formula (1):

[0067]

[0068] Assuming that the voltage between the output terminals OUT+ and OUT- remains constant after resonance begins, and there are no additional losses, after a quarter cycle (T / 4), the node voltage Vx drops to 0V, and the current in the resonant inductor Lr rises to its peak value. After another quarter cycle, the node voltage Vx drops to -VDD, and the current in the resonant inductor Lr drops from its peak value to 0. If the voltage at the output terminal OUT+ is raised from 0V to the preset input power supply VDD at this moment, the node voltage Vx can rise from -VDD to 0V. Thus, the voltage difference across the parasitic capacitor C0 has switched from VDD to -VDD. This process recovers and reuses the energy on the parasitic capacitor C0 without consuming power from the power supply.

[0069] In summary, the energy recovery circuit device 100 applied to parasitic capacitance based on the embodiments of the present invention provides a novel and highly efficient energy recovery circuit architecture for the parasitic capacitance C0 of the target load (such as a piezoelectric actuator). The core of this architecture lies in introducing a resonant inductor Lr and cleverly controlling the voltage timing of OUT+ and OUT- outputs from the full-bridge drive circuit module. During the brief window of drive voltage switching, a highly efficient LC resonant circuit is formed, storing the energy of the parasitic capacitance C0 in the resonant inductor Lr. Then, the resonant inductor Lr discharges in the reverse direction to the parasitic capacitance C0, achieving a polarity reversal of the drive voltage and thus realizing ultra-low loss transfer of the energy stored in the parasitic capacitance C0. Therefore, it can directly recover the energy of the parasitic capacitance C0 that is dissipated by the resistor during drive voltage switching in traditional solutions (especially in high-speed, high-frequency piezoelectric applications, where this energy loss accounts for a very large proportion). With the help of this energy recovery circuit device, the overall drive efficiency of the circuit system can be significantly improved, reaching up to 20% (the specific value depends on the operating frequency, voltage amplitude, and capacitance value of the parasitic capacitance C0).

[0070] The energy recovery circuit device 100 described in this embodiment of the invention can be applied to the fields of integrated circuit chip technology and electronic circuit technology. Specifically, it can be applied to energy recovery in technologies such as piezoelectric drive technology. For example, it can efficiently and stably recover energy from the energy pulse generated by the parallel parasitic capacitor in the equivalent electrical model of the piezoelectric driver at the moment of square wave drive switching.

[0071] In summary, the energy recovery circuit device 100 of this embodiment provides a novel energy recovery architecture that realizes the charging and discharging of parasitic capacitors in the parallel load at the moment of waveform drive switching. Utilizing a highly efficient LC resonant circuit, energy is first stored in the resonant inductor at the moment the load drive voltage flips, and then discharged in reverse through the resonant inductor, achieving a polarity reversal of the drive voltage, thereby completing the energy recovery from the parallel parasitic capacitors in the target load (such as a piezoelectric actuator). Therefore, it can effectively overcome the energy waste and overcharge danger caused by the parallel parasitic capacitors in the equivalent circuit model of the target load (such as a piezoelectric actuator) during voltage switching, providing a simple and efficient energy recovery circuit solution.

[0072] It should be noted that, in the embodiments of the present invention, when the preset clock signal CLK_IN switches, the full-bridge drive circuit module H will respond by controlling the voltage switching between its output terminals OUT+ and OUT-. At this time, the parasitic capacitor C0 is charged and discharged, causing its voltage to change from VDD to -VDD (or from -VDD to VDD). The current for charging and discharging the parasitic capacitor C0 is much greater than the current in other parts of the electrical model of the target load P. Therefore, in the embodiments of the present invention, the current other than that of the parasitic capacitor C0 can be temporarily ignored. Similarly, for ease of analysis and technical explanation, the parasitic resistance R0 in the electrical model of the target load P can also be ignored, as can the on-resistance Rdson of each control switch (such as NM0, NM1, PM0, PM1 as described below) in the full-bridge drive circuit module H (i.e., H-Bridge) can also be ignored. Therefore, if it is necessary to provide a detailed description of the energy recovery circuit device 100 of the present invention in conjunction with actual product applications, it is also necessary to consider the current other than the parasitic capacitance C0 that has been ignored, the parasitic resistance R0, and the on-resistance Rdson of the full-bridge drive, etc., which will not be elaborated in detail.

[0073] like Figures 1-3 As shown, according to an embodiment of the present invention, the dual-sided delay circuit module DELAY operates to output a first delay signal CLK_IN_DELAY_R and a second delay signal CLK_IN_DELAY_F according to a preset clock signal CLK_IN, wherein:

[0074] The first delay signal CLK_IN_DELAY_R is a timing control signal formed by delaying the rising edge of the preset clock signal CLK_IN by a preset fixed time.

[0075] The second delay signal CLK_IN_DELAY_F is another timing control signal formed by delaying the falling edge of the preset clock signal CLK_IN by a preset fixed time. The preset fixed time Tdelay is half the series resonant period of the inductor-capacitor resonant circuit, i.e., T / 2. During the drive switching process of the full-bridge drive circuit module H (i.e., the pull-up and / or pull-down changes of each control switch), the charging and discharging process for the parasitic capacitance C0 (charging and discharging of the matching resonant inductor Lr) is completed. In other words, the charging and discharging process is completed within the preset fixed time T / 2.

[0076] Therefore, the dual-sided delay circuit module DELAY can delay the rising edge of the input preset clock signal CLK_IN by a preset fixed time to obtain the first delay signal CLK_IN_DELAY_R, and simultaneously delay the falling edge of the preset clock signal CLK_IN by a preset fixed time to obtain the second delay signal CLK_IN_DELAY_F. The timing diagrams for the first delay signal CLK_IN_DELAY_R and the second delay signal CLK_IN_DELAY_F are as follows: Figure 3 As shown.

[0077] In this way, the first delay signal CLK_IN_DELAY_R and the second delay signal CLK_IN_DELAY_F can be used as timing control signals to input to the logic drive circuit module DR to generate at least one drive control signal, thereby ultimately achieving precise timing control of the full-bridge drive circuit module H. This ensures the charging and discharging process of the parasitic capacitance C0 and the resonant inductor Lr during the drive switching window of the LC resonant circuit, and ensures that the energy recovery process of the LC resonant circuit is not affected by the drive voltage switching.

[0078] like Figures 1-4D As shown, according to an embodiment of the present invention, the logic driving circuit module DR includes a first logic driving unit 401, a second logic driving unit 402, a third logic driving unit 403, and a fourth logic driving unit 404.

[0079] The first logic driving unit 401 is used to output a first driving control signal HB_LG_OUT+ according to the first delay signal CLK_IN_DELAY_R;

[0080] The second logic drive unit 402 is used to output a second drive control signal HB_LG_OUT- based on the first delay signal CLK_IN_DELAY_R.

[0081] The third logic drive unit 403 is used to output a third drive control signal HB_HG_OUT- based on the first delay signal CLK_IN_DELAY_R.

[0082] The fourth logic drive unit 404 is used to output the fourth drive control signal HB_HG_OUT+ according to the second delay signal CLK_IN_DELAY_F;

[0083] Among them, the first drive control signal HB_LG_OUT+, the second drive control signal HB_LG_OUT-, the third drive control signal HB_HG_OUT-, and the fourth drive control signal HB_HG_OUT+ are simultaneously input to four different input terminals of the full-bridge drive circuit module H, and are used to update the drive electrical signal applied to the target load P according to the preset input power supply VDD.

[0084] The logic drive circuit module DR is mainly used to generate drive control signals that can control the various control switches of the full-bridge drive circuit module H based on the two timing control signals CLK_IN_DELAY_R and CLK_IN_DELAY_F generated by the bilateral delay circuit module DELAY. These signals are the first drive control signal HB_LG_OUT+, the second drive control signal HB_LG_OUT-, the third drive control signal HB_HG_OUT-, and the fourth drive control signal HB_HG_OUT+.

[0085] The full-bridge driver circuit module H can have four different input terminals, which are respectively used to connect the first drive control signal HB_LG_OUT+, the second drive control signal HB_LG_OUT-, the third drive control signal HB_HG_OUT-, and the fourth drive control signal HB_HG_OUT+ output from the aforementioned logic driver circuit module DR. In this way, the full-bridge driver circuit module H can achieve polarity reversal switching of the drive voltage between the output terminals OUT+ and OUT-, specifically by pulling up or down the output terminal OUT+ (corresponding to pulling down or up the output terminal OUT-). Therefore, the charging and discharging process of the parasitic capacitance C0 in the aforementioned LC resonant circuit can be realized during this drive voltage switching process.

[0086] Therefore, the logic drive circuit module DR can generate four drive control signals that match the full-bridge drive circuit module H based on the first delay signal CLK_IN_DELAY_R and the second delay signal CLK_IN_DELAY_F that match the preset clock signal, ensuring that the charging and discharging (i.e., energy recovery) process of the parasitic capacitor C0 in the above-mentioned LC resonant circuit is completed accurately within the preset fixed time of T / 2.

[0087] like Figure 2A , Figure 2B and Figure 4A As shown, according to an embodiment of the present invention, the first logic driving unit 401 includes a first latch unit 411. The source of the first transistor M1 of the first latch unit 411 is connected to a first preset reference power supply VIN. The source of the second transistor M2 of the first latch unit 411 is grounded to GND. The drains of the first transistor M1 and the drains of the second transistor M2 are connected to form the output terminal of the first latch unit 411, which is used to output a first drive control signal HB_LG_OUT+. The first delay signal CLK_IN_DELAY_R is processed by an inverter and then enters the first latch unit 411. After processing by the first latch unit 411, the first drive control signal HB_LG_OUT+ is generated.

[0088] like Figure 2A , Figure 2B and Figure 4B As shown, according to an embodiment of the present invention, the second logic driving unit 402 includes a second latch unit 421. The source of the third transistor M3 of the second latch unit 421 is connected to a first preset reference power supply VIN. The source of the fourth transistor M4 of the second latch unit 421 is grounded. The drains of the third transistor M3 and the drains of the fourth transistor M4 are connected to form the output terminal of the second latch unit 421, which is used to output the second drive control signal HB_LG_OUT-. The first delay signal CLK_IN_DELAY_R is processed by an inverter and then enters the second latch unit 421. After processing by the second latch unit 421, the second drive control signal HB_LG_OUT- is generated.

[0089] like Figure 2A , Figure 2B and Figure 4C As shown, according to an embodiment of the present invention, the third logic driving unit 403 includes a third latch unit 431 and a first level converter 432 connected in series therewith. The source of the fifth transistor M5 of the third latch unit 431 is connected to a preset input power supply VDD, the source of the sixth transistor M6 of the third latch unit 431 is connected to a second preset reference power supply VDD_5, and the drains of the fifth transistor M5 and the drains of the sixth transistor M6 are connected to form the output terminal of the third latch unit 431. The first level converter 432 is used to convert the first delay signal CLK_IN_DELAY_R input to the third latch unit 431 into a first high voltage domain signal, and the third latch unit 431 converts the first high voltage domain signal into a third drive control signal HB_HG_OUT-.

[0090] like Figure 2A , Figure 2B and Figure 4D As shown, according to an embodiment of the present invention, the fourth logic driving unit 404 includes a fourth latch unit 441 and a second level converter 442 connected in series therewith. The source of the seventh transistor M7 of the fourth latch unit 441 is connected to a preset input power supply VDD, the source of the eighth transistor M8 of the fourth latch unit 441 is connected to a second preset reference power supply VDD_5, and the drains of the seventh transistor M7 and the drains of the eighth transistor M8 are connected to form the output terminal of the fourth latch unit 441. The second level converter 442 is used to convert the second delay signal CLK_IN_DELAY_F input to the fourth latch unit 441 into a second high-voltage domain signal, and the fourth latch unit converts the second high-voltage domain signal into a fourth drive control signal HB_HG_OUT+.

[0091] like Figures 4A-4DAs shown, the first latch unit 401, the second latch unit 402, the third latch unit 403, and the fourth latch unit 404 can all use circuit elements such as SR latches to implement the corresponding drive control signal output. The structural design of the SR latch can be referenced as follows: Figures 4A-4D As shown, the generation mechanism and principle of the corresponding drive control signal will not be elaborated here.

[0092] Unlike the first latch unit 411 and the second latch unit 421, the third latch unit 431 and the fourth latch unit 441, in order to implement the third and fourth drive control signals, may have some differences in their circuit structure design. For example, the number of inverters and the connection method of related circuit components may be adjusted. Specifically, for example... Figures 4A-4D As shown.

[0093] In addition, to ensure the driving characteristics of the first driving control signal HB_LG_OUT+, the second driving control signal HB_LG_OUT-, the third driving control signal HB_HG_OUT-, and the fourth driving control signal HB_HG_OUT+ for each control switch of the full-bridge driving circuit module H, the relationship between the first preset reference power supply VIN, the second preset reference power supply VDD_5, and the preset input power supply VDD can satisfy the following formula (2):

[0094] VDD = VDD_5 + VIN (2)

[0095] In this embodiment of the invention, VDD can be used to represent the input voltage signal of a preset input power supply. Similarly, the expressions for VDD_5 and VIN are similar and will not be repeated here.

[0096] Accordingly, the first transistor M1, the second transistor M2, ..., the eighth transistor M8 can be metal-oxide-semiconductor field-effect transistors (MOSFETs), specifically N-type doped NMOS transistors or P-type doped PMOS transistors. In this embodiment of the invention, the first transistor M1, the third transistor M3, the fifth transistor M5, and the seventh transistor M7 can be P-type doped PMOS transistors; conversely, the second transistor M2, the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 can be N-type doped NMOS transistors, thereby enabling the corresponding latch units to realize the conversion and output of their respective drive control signals.

[0097] Furthermore, it should be noted that in this embodiment of the invention, in order to achieve effective and accurate driving of the full-bridge drive circuit module H, the third drive control signal HB_HG_OUT- and the fourth drive control signal HB_HG_OUT+ need to be considered as high-voltage domain drive control signals. Therefore, unlike the first logic drive unit 401 and the second logic drive unit 402, corresponding first level converters 432 and second level converters 442 can be set in the third logic drive unit 403 and the fourth logic drive unit 404. These first level converters 432 and second level converters 442 are used to convert the corresponding first delay signal CLK_IN_DELAY_R and second delay signal CLK_IN_DELAY_F into matching first and second high-voltage domain signals. The first and second high-voltage domain signals are respectively input to the third latch unit 431 and the fourth latch unit 441, thereby ultimately achieving matched output of the third drive control signal HB_HG_OUT- and the fourth drive control signal HB_HG_OUT+. The first level converter 432 and the second level converter 442 can be implemented by a level converter (LV_SHIFT), which is mainly used to convert the input signal from one voltage domain to another, thereby ensuring that electrical signals in different voltage domains can work normally, effectively avoiding signal mismatch caused by voltage domain differences, and ensuring the driving accuracy of the full-bridge drive circuit module H.

[0098] Before the first delay signal CLK_IN_DELAY_R and the second delay signal CLK_IN_DELAY_F are level-converted by the first level converter 432 and the second level converter 442, they can be inverted by at least one inverter to ensure that the control logic of the corresponding drive control signal meets the logic requirements of parasitic capacitance C0 energy recovery.

[0099] Therefore, the first drive control signal HB_LG_OUT+ and the second drive control signal HB_LG_OUT- can be directly driven by the first latch unit 411 of the first logic drive unit 401 and the second latch unit 421 of the second logic drive unit 402, respectively. Correspondingly, the third drive control signal HB_HG_OUT- and the fourth drive control signal HB_HG_OUT+ need to be directly driven by the first high-voltage domain signal and the second high-voltage domain signal generated by the first level converter 432 of the third logic drive unit 403 and the second level converter 442 of the fourth logic drive unit 404, respectively, through the third latch unit 431 and the fourth latch unit 441, respectively.

[0100] like Figures 1-4DAs shown, according to an embodiment of the present invention, the full-bridge drive circuit module H includes a first control switch NM0, a second control switch NM1, a third control switch PM1, and a fourth control switch PM0.

[0101] The gate of the first control switch NM0 is connected to the first drive control signal HB_LG_OUT+, its drain is connected to one end of the target load P, and its source is grounded to GND.

[0102] The gate of the second control switch NM1 is connected to the second drive control signal HB_LG_OUT-, its drain is connected to one end of the resonant inductor Lr, and its source is grounded to GND.

[0103] The gate of the third control switch PM1 is connected to the third drive control signal HB_HG_OUT-, and its drain is connected to the drain of the second control switch NM1 to form an output terminal of the full-bridge drive circuit module H. Its source is connected to the preset input power supply VDD.

[0104] The gate of the fourth control switch PM0 is connected to the fourth drive control signal HB_HG_OUT+, and its drain is connected to the drain of the first control switch NM0 to form another output terminal of the full-bridge drive circuit module H. Its source is connected to the preset input power supply VDD.

[0105] In one embodiment of the present invention, the first control switch NM0 and the second control switch NM1 of the full-bridge drive circuit module H can be NMOS switching transistors, and the third control switch PM1 and the fourth control switch PM0 can be PMOS switching transistors. Specifically, the MOS transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET), the PMOS transistor can be a P-type doped MOS transistor, and the NMOS transistor can be an N-type doped MOS transistor.

[0106] Specifically, for the first control switch NM0 and the second control switch NM1 of the NMOS transistor, when their gate voltage is high, they are in the ON state and current is flowing (i.e., on state); when their gate voltage is low, they are in the OFF state and current is not flowing (i.e., off state). Conversely, for the third control switch PM1 and the fourth control switch PM0 of the PMOS switching transistor, when their gate voltage is high, they are in the OFF state and current is not flowing (i.e., off state); when their gate voltage is low, they are in the ON state and current is flowing (i.e., on state).

[0107] Among them, such as Figure 2AAs shown, when the first control switch NM0 is on and grounded, the fourth control switch PM0 is off, the third control switch PM1 is on and connected to the preset input power supply VDD, and the second control switch NM1 is off, the output terminal OUT+ of the full-bridge drive circuit module H is pulled down, while its output terminal OUT- is pulled up. Conversely, when the first control switch NM0 is off, the fourth control switch PM0 is on and connected to the preset input power supply VDD, the third control switch PM1 is off, and the second control switch NM1 is on and grounded, the output terminal OUT+ of the full-bridge drive circuit module H is pulled up, while its output terminal OUT- is pulled down. In this way, the voltage polarity switching between the output terminals OUT+ and OUT- of the full-bridge drive circuit module H can be effectively achieved through the first drive control signal HB_LG_OUT+, the second drive control signal HB_LG_OUT-, the third drive control signal HB_HG_OUT-, and the fourth drive control signal HB_HG_OUT+.

[0108] Specifically, such as Figure 2A , Figure 2B and Figure 3 As shown, when the preset clock signal CLK_IN has a falling edge, the voltage at the output terminal OUT- of the full-bridge drive circuit module H drops from VDD to 0V. At this time, the voltage at the junction Vx between the capacitor Cs of the target load P and the resonant inductor Lr starts to decrease from VDD, and the corresponding current Ix rises from zero, changing in a shape close to a sine wave, and then decreases after reaching its peak. The intrinsic resonant period T of the series resonance of the LC resonant circuit satisfies the above formula (1). Assuming that the voltage between the output terminals OUT+ and OUT- does not change after the resonance starts, and there is no additional loss, then after a quarter of a cycle (T / 4), the junction voltage Vx drops to 0V, and the current Ix of the resonant inductor Lr rises to its peak value. After another quarter of a cycle (T / 4), the voltage at the junction Vx point drops to -VDD, and the current Ix of the resonant inductor Lr drops from its peak value to 0. At this moment, if the voltage at the output terminal OUT+ is allowed to rise from 0V to VDD, the junction voltage Vx can rise from -VDD to 0V. At this point, the voltage difference across the parasitic capacitor C0 has switched from VDD to -VDD. This process is precisely the recovery and reuse of energy on the parasitic capacitor C0, without requiring additional power consumption.

[0109] like Figure 3As shown, through the energy recovery logic control of the parasitic capacitor C0, the voltage switching waveform can be improved. Specifically, during the resonance process, the change of the voltage of the parasitic capacitor C0 (i.e., the voltage difference between the output terminal OUT+ and the node voltage Vx) is closer to a sinusoidal trajectory. Compared with the sharp voltage jump (dV / dt) generated by direct hard switching, the voltage waveform edge can be softened to a considerable extent, thereby effectively reducing voltage overshoot and ringing, making it safer for the piezoelectric element itself and the surrounding circuit, and reducing the impact of EMI radiation and noise.

[0110] like Figures 1-4D As shown, according to an embodiment of the present invention, the energy recovery circuit device 100 applied to parasitic capacitance further includes a zero-crossing comparator module ICMP.

[0111] The first input terminal of the zero-crossing comparator circuit module ICMP is connected to one end of the resonant inductor Lr (i.e., the output terminal OUT- of the full-bridge drive circuit module H) to detect the actual working electrical signal of the resonant inductor Lr; its second input terminal is grounded to GND, and its third input terminal is connected to the preset clock signal CLK_IN; its output terminal is connected to the dual-sided delay circuit module DELAY.

[0112] Among them, the zero-crossing comparator circuit module ICMP responds to the preset clock signal CLK_IN and outputs a delay control signal to the bilateral delay circuit module DELAY according to the change of the actual working electrical signal of the resonant inductor Lr.

[0113] The zero-crossing comparator (ICMP) circuit module can be implemented based on a zero-crossing comparator. Typically, one input of an integrated operational amplifier is grounded to GND, and the other input is connected to a detection signal. Signal comparison is performed, and the output voltage changes abruptly near the zero-crossing point of the detected signal. In this embodiment, the preset clock signal CLK_IN is equivalent to the operating input signal of the ICMP circuit module. The ICMP circuit module responds to the preset clock signal CLK_IN by detecting the actual operating signal of the resonant inductor Lr and outputs a delay control signal accordingly.

[0114] In this embodiment of the invention, the zero-crossing comparator module ICMP is mainly used to detect when the absolute value of the current Ix flowing through the resonant inductor Lr drops to 0A or close to 0A during the LC resonant time of the energy recovery process of the parasitic capacitance C0. During the LC resonant time of energy recovery, due to the switching timing design of the full-bridge drive circuit module H (i.e., H-Bridge), the current Ix of the resonant inductor Lr will definitely flow through the second control switch NM1, which can be considered as a small resistor after being turned on. Therefore, the absolute value of the current Ix of the resonant inductor Lr can be determined by detecting the small voltage difference between the output terminal OUT- and ground GND.

[0115] The delay control signal is mainly used to control the signal drive logic of the dual-sided delay circuit module DELAY, enabling the module to process the preset clock signal on both sides in accordance with the logic switching requirements. This improves the overall stability of the system circuit, ensures the energy recovery process of the parasitic capacitance C0, and prevents energy loss. The actual operating electrical signal can be the current signal flowing through the resonant inductor Lr.

[0116] like Figures 1-4D As shown, according to an embodiment of the present invention, the bilateral delay circuit module DELAY updates the first delay signal and / or the second delay signal according to the delay control signal, including:

[0117] After the rising edge of the preset clock signal CLK_IN, when the absolute value of the actual working electrical signal reaches a preset threshold, the preset clock signal CLK_IN is pulled high to generate the updated first delay signal within a preset fixed time; and / or

[0118] After the falling edge of the preset clock signal CLK_IN, when the absolute value of the actual working electrical signal reaches the preset threshold, the preset clock signal CLK_IN is pulled low to generate the updated second delay signal within a preset fixed time.

[0119] As mentioned above, to satisfy the output of the delay control signal of the zero-crossing comparator module ICMP, the preset threshold can be 0 or other values ​​close to 0. Specifically, after the rising edge of the preset clock signal CLK_IN, when the absolute value of the actual working electrical signal reaches the preset threshold, the bilateral delay circuit module DELAY can respond to the delay control signal by pulling the preset clock signal CLK_IN high to generate the updated first delay signal within a preset fixed time. At this time, it is no longer necessary to wait for the preset fixed time in the bilateral delay circuit module DELAY to end. Furthermore, after the falling edge of the preset clock signal CLK_IN, when the absolute value of the actual working electrical signal reaches the preset threshold, the bilateral delay circuit module DELAY can respond to the delay control signal by pulling the preset clock signal CLK_IN low to generate the updated second delay signal within a preset fixed time. At this time, it is also no longer necessary to wait for the preset fixed time in the bilateral delay circuit module DELAY to end.

[0120] Therefore, as Figure 2A , Figure 2B and Figure 3 As shown in this embodiment of the invention, when the preset clock signal CLK_IN appears with a rising edge, the voltage at the output terminal OUT- of the full-bridge drive circuit module H drops from VDD to 0V. At this time, the node voltage Vx will instantly drop from 0V to -VDD and then start to rise. The current Ix of the resonant inductor Lr also starts to rise. After half of the intrinsic resonance period of the LC resonant circuit (i.e., T / 2), the node voltage Vx rises to VDD. At this time, the current Ix on the resonant inductor Lr is 0. At this time, the zero-crossing comparator circuit module ICMP flips, controlling the logic switching in the logic drive circuit module DR and the full-bridge drive circuit module H, pulling the voltage at the output terminal OUT- from 0V to VDD, thereby completing the energy recovery and reuse on the parasitic capacitor C0. The preset fixed time Tdelay can also be the flip time of the zero-crossing comparator circuit module ICMP, i.e., Tdelay = T / 2.

[0121] As can be seen, the zero-crossing comparator module ICMP can accurately detect the zero-crossing point of the current Ix flowing through the resonant inductor Lr, which corresponds to the moment when energy recovery ends. Therefore, at the moment energy recovery ends, it can switch the corresponding control switch within the full-bridge drive circuit module H to complete the polarity reversal of the drive voltage, preventing further leakage of the recovered parasitic capacitance energy. Furthermore, the bilateral delay circuit module DELAY ensures that even if the zero-crossing comparator module ICMP does not flip, the logic switch will be completed after a fixed delay (a preset fixed time T / 2), greatly increasing the overall circuit reliability.

[0122] Specifically, such as Figures 2A-3As shown, when the preset clock signal CLK_IN appears with a falling edge, the driving voltage between the output terminals OUT- and OUT+ of the full-bridge drive circuit module H will decrease from the preset input power supply VDD to 0V. At this time, the voltage Vx at the junction between the capacitor Cs and the resonant inductor Lr of the target load P will also decrease from VDD. At this time, the current flowing through the target load P (as the driving signal) rises from zero, changes in a shape close to a sine wave, and decreases after reaching its peak. The period T of the series resonance of this LC resonant circuit satisfies the above formula (1): .

[0123] Assuming that the voltage between the output terminals OUT+ and OUT- remains constant after resonance begins, and there are no additional losses, after a quarter cycle (T / 4), the node voltage Vx drops to 0V, and the current in the resonant inductor Lr rises to its peak value. After another quarter cycle, the node voltage Vx drops to -VDD, and the current in the resonant inductor Lr drops from its peak value to 0. If the voltage at the output terminal OUT+ is raised from 0V to the preset input power supply VDD at this moment, the node voltage Vx can rise from -VDD to 0V. Thus, the voltage difference across the parasitic capacitor C0 has switched from VDD to -VDD. This process recovers and reuses the energy on the parasitic capacitor C0 without consuming power from the power supply.

[0124] like Figure 3 As shown Figure 2A and Figure 2B The waveform diagram and timing diagram of the key signals are shown. At time t1, the voltage at the output terminal OUT- of the full-bridge drive circuit module H drops from VDD to 0V. At this time, the voltage and current Ix waveforms at the node voltage Vx change as shown by the dashed and solid lines in the figure, respectively. The voltage difference between the output terminal OUT+ and the node voltage Vx at time t1 is -VDD.

[0125] It is known that the intrinsic resonant period T of the series resonance of an LC resonant circuit satisfies: Assuming that the voltages at the output terminals OUT+ and OUT- of the full-bridge drive circuit module H remain unchanged after the resonance begins, and there are no additional losses, then after half a cycle (i.e., T / 2), the node voltage Vx is -VDD. If the voltage at the output terminal OUT+ is raised from 0V to VDD at this moment, then the node voltage Vx can be raised from -VDD back to 0V at this moment, i.e., as shown below. Figure 3 The time t2 is shown.

[0126] Similarly, at time t3, the output terminal OUT+ changes from VDD to 0, and the node voltage Vx becomes -VDD. After half a resonant period (i.e., T / 2), the node voltage Vx changes back to VDD after energy conversion. At this time, the voltage at the output terminal OUT- rises from 0V to VDD, i.e., as shown below. Figure 3 The time t4 is shown.

[0127] Therefore, by precisely controlling the voltage switching times of the output terminals OUT+ and OUT-, and making the difference between t2-t1 and t4-t3 half of the series resonant period T (i.e., T / 2), the energy of the parasitic capacitor C0 can be recovered, thereby significantly saving energy in the power supply and improving the overall efficiency of the drive circuit.

[0128] It should also be noted that, if we consider Figure 2B The parasitic resistance R0 shown and as follows Figure 2A The on-resistance Rdson of each control switch transistor (i.e., power transistor) in the full-bridge drive circuit module H shown will cause some energy loss. The amplitude of the series LC resonant circuit during the resonance process will be slightly lower than VDD. Assuming that the actual resonance amplitude caused by the above parasitic resistance R0 is VDD1, the actual energy recovery efficiency satisfies the following formula (3):

[0129]

[0130] In summary, a series branch consisting of a resonant inductor Lr is directly connected in series across the target load P (such as a piezoelectric actuator). Utilizing the lossless resonance characteristic of this LC resonant circuit, the voltage across the parasitic capacitance C0 can be effectively switched from -VDD to VDD (or from VDD to -VDD), thereby greatly reducing energy waste.

[0131] The energy recovery circuit device and control method for parasitic capacitance provided in this invention can at least partially solve at least one of the technical problems in piezoelectric drive technology, namely, increased circuit energy consumption due to parasitic capacitance and the generation of large current pulses during voltage step transitions across the capacitor. Therefore, it can achieve at least one of the following technical effects:

[0132] 1. Significantly improve driving efficiency: Through the inductor-capacitor resonant circuit composed of the above-mentioned bilateral delay circuit module, logic drive circuit module, full-bridge drive circuit module and resonant inductor, the energy of parasitic capacitance dissipated by resistors during the switching of drive voltage in traditional piezoelectric drive design can be directly recovered (especially in high-speed, high-frequency switching piezoelectric applications, the energy loss caused by this part of parasitic capacitance accounts for a very large proportion). The recovery of parasitic capacitance energy can significantly improve the overall system efficiency (the efficiency can be improved by more than 20%, the specific value depends on the operating frequency and voltage amplitude).

[0133] 2. Improved voltage switching waveform: The resonance process of the inductor-capacitor resonant circuit can make the voltage change of the parasitic capacitance closer to a sinusoidal trajectory. Therefore, compared with the sharp voltage jump (dV / dt) generated by direct hard switching, the voltage waveform edge is softened to a certain extent, which effectively reduces the occurrence of overcharging and ringing. It is safer for the target load such as piezoelectric elements and surrounding circuits, and has less electromagnetic interference (EMI) radiation and noise impact.

[0134] 3. Simpler circuit structure: Compared with the traditional piezoelectric drive circuit design, the energy recovery circuit device of this invention adds only an inductor and its matching timing signal drive control module (such as a bilateral delay circuit module and a logic drive circuit module) as the core components. Compared with the existing complex active energy recovery schemes, the structure is simpler, the cost is lower, and it is easier to integrate into the existing piezoelectric drive architecture.

[0135] In summary, this invention provides an efficient, practical, and easy-to-implement energy recovery scheme for piezoelectric drive technology, effectively solving the core problem of energy waste caused by parallel parasitic capacitance in square wave drive processes of piezoelectric actuators, etc., and has significant practical value and economic benefits.

[0136] Therefore, the energy recovery circuit device and control method for parasitic capacitance described above in the embodiments of the present invention can be more widely adapted to the needs of small and high-efficiency scenarios. Even under the current chip manufacturing process level, it can be better applied to high-precision electronic products (such as micro heat sinks for automotive chips or mobile phone chips) or equipment (such as extreme ultraviolet light source chips for lithography machines), and has a very wide range of product applications.

[0137] Therefore, the energy recovery circuit device and control method for parasitic capacitors based on the embodiments of the present invention can provide a parasitic capacitor energy recovery technology that is more efficient, more stable, lower power consumption, lower cost, more practical, easier to implement and promote compared to existing energy recovery schemes. It can directly recover the energy of parasitic capacitors that are dissipated by resistors at the moment of driving voltage switching in traditional piezoelectric drive design schemes, significantly improve the working efficiency of circuit system, and has extremely important practical value and economic benefits.

[0138] Based on the above-described energy recovery circuit device for parasitic capacitance, the present invention also provides a control method for the energy recovery circuit device for parasitic capacitance. The following will be combined with... Figures 5-7 The control method is described in detail.

[0139] Figure 5The illustration schematically depicts an application scenario of a control method, apparatus, device, medium, and program product for an energy recovery circuit device for parasitic capacitance according to an embodiment of the present invention.

[0140] like Figure 5 As shown, application scenario 500 according to this embodiment may include terminal devices 501, 502, and 503, a network 504, and a server 505. Network 504 serves as a medium for providing a communication link between terminal devices 501, 502, and 503 and server 505. Network 504 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0141] Users can use terminal devices 501, 502, and 503 to interact with server 505 via network 504 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 501, 502, and 503, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0142] Terminal devices 501, 502, and 503 can be various electronic devices with displays that support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0143] Server 505 can be a server that provides various services, such as a backend management server that supports websites browsed by users using terminal devices 501, 502, and 503 (for example only). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0144] It should be noted that the control method for the energy recovery circuit device applied to parasitic capacitance provided in the embodiments of the present invention can generally be executed by server 505. Correspondingly, the control device for the energy recovery circuit device applied to parasitic capacitance provided in the embodiments of the present invention can generally be located in server 505. The control method for the energy recovery circuit device applied to parasitic capacitance provided in the embodiments of the present invention can also be executed by a server or server cluster that is different from server 505 and capable of communicating with terminal devices 501, 502, 503 and / or server 505. Correspondingly, the control device for the energy recovery circuit device applied to parasitic capacitance provided in the embodiments of the present invention can also be located in a server or server cluster that is different from server 505 and capable of communicating with terminal devices 501, 502, 503 and / or server 505.

[0145] It should be understood that Figure 5The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0146] The following will be based on Figure 5 The described scene, through Figure 6 The control method of the energy recovery circuit device applied to parasitic capacitors according to the disclosed embodiments will be described in detail.

[0147] like Figure 6 As shown, another aspect of the present invention provides a control method for the above-described energy recovery circuit device applied to parasitic capacitance, wherein the energy recovery circuit device applied to parasitic capacitance includes a resonant inductor connected in series with a target load to form an inductor-capacitor resonant circuit, and the control method includes operations S601 to S603.

[0148] In operation S601, at least one timing control signal is generated in response to the preset clock signal CLK_IN;

[0149] In operation S602, at least one drive control signal is generated based on at least one timing control signal; and

[0150] In operation S603, the drive electrical signal applied to the target load is updated according to at least one drive control signal.

[0151] During the window period when the driving electrical signal is updated, the inductor-capacitor resonant circuit is used to recover energy from the parasitic capacitance of the target load.

[0152] The control process and corresponding beneficial effects of the control method for the energy recovery circuit device 100 applied to the parasitic capacitor in the above embodiments of the present invention can be referred to the relevant description of the energy recovery circuit device 100 applied to the parasitic capacitor, and will not be repeated here.

[0153] Figure 7 A block diagram of an electronic device according to an embodiment of the present invention is shown schematically, which is suitable for implementing a control method for an energy recovery circuit device applied to a parasitic capacitor.

[0154] The electronic device provided in the embodiments of the present invention includes one or more processors and a memory, wherein the memory is used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to execute the control method applied to the energy recovery circuit device for parasitic capacitance.

[0155] like Figure 7As shown, an electronic device 700 according to an embodiment of the present invention includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage portion 708 into a random access memory (RAM) 703. The processor 701 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include onboard memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0156] RAM 703 stores various programs and data required for the operation of electronic device 700. Processor 701, ROM 702, and RAM 703 are interconnected via bus 704. Processor 701 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 702 and / or RAM 703. It should be noted that the programs may also be stored in one or more memories other than ROM 702 and RAM 703. Processor 701 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0157] According to an embodiment of the present invention, the electronic device 700 may further include an input / output (I / O) interface 705, which is also connected to a bus 704. The electronic device 700 may also include one or more of the following components connected to the I / O interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0158] The present invention also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the control method described above for an energy recovery circuit device applied to a parasitic capacitor.

[0159] The computer-readable storage medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0160] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 702 and / or RAM 703 and / or one or more memories other than ROM 702 and RAM 703 described above.

[0161] Embodiments of the present invention also include a computer program product comprising a computer program that, when executed by a processor, implements the control method described above for an energy recovery circuit device applied to a parasitic capacitor.

[0162] The computer program includes program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the methods provided in the embodiments of the present invention.

[0163] When the computer program is executed by the processor 701, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0164] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 709, and / or installed from a removable medium 711. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0165] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 709, and / or installed from the removable medium 711. When the computer program is executed by the processor 701, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0166] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0167] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0168] Furthermore, all actions involving the acquisition of information, signals, or data in this invention are carried out in compliance with the relevant data protection laws, regulations, and policies of the country where the invention is located, and with the authorization granted by the owner of the corresponding device.

[0169] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0170] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. An energy recovery circuit device applied to a parasitic capacitance, characterized by, include: A dual-sided delay circuit module is used to generate at least one timing control signal in response to a preset clock signal, wherein the at least one timing control signal includes a first delay signal and a second delay signal; the first delay signal is a timing control signal formed by delaying the rising edge of the preset clock signal by a preset fixed time; the second delay signal is another timing control signal formed by delaying the falling edge of the preset clock signal by the preset fixed time. A logic drive circuit module, connected to at least one output terminal of the bilateral delay circuit module, is used to generate at least one drive control signal according to the at least one timing control signal; A full-bridge drive circuit module is connected to both ends of the target load and at least one output terminal of the logic drive circuit module. It is used to connect to a preset input power supply and update the drive electrical signal applied to the target load according to the at least one drive control signal. A resonant inductor is connected in series with the target load between the two output terminals of the full-bridge drive circuit module. During the window period when the drive signal is controlled and updated, the resonant inductor and the target load form an inductor-capacitor resonant circuit, which charges the resonant inductor with the parasitic capacitance of the target load. Then, the resonant inductor discharges the target load in the reverse direction, thereby realizing the polarity reversal of the drive signal and realizing the energy recovery of the parasitic capacitance of the target load. The zero-crossing comparator module has a first input terminal connected to one end of the resonant inductor for detecting the actual operating electrical signal of the resonant inductor; its second input terminal is grounded, and its third input terminal is connected to the preset clock signal; its output terminal is connected to the bilateral delay circuit module. The zero-crossing comparator module responds to the preset clock signal and outputs a delay control signal to the bilateral delay circuit module based on the change in the actual operating electrical signal of the resonant inductor. The bilateral delay circuit module updates the first delay signal and the second delay signal according to the delay control signal, wherein the preset fixed time is the time when the zero-crossing comparison circuit module flips; and the preset fixed time is half of the series resonance period of the inductor-capacitor resonant circuit.

2. The energy recovery circuit device applied to parasitic capacitance according to claim 1, characterized in that, The logic driving circuit module includes: The first logic driving unit is used to output a first driving control signal according to the first delay signal; The second logic driving unit is used to output a second driving control signal according to the first delay signal; The third logic driving unit is used to output a third driving control signal according to the first delay signal; The fourth logic drive unit is used to output a fourth drive control signal according to the second delay signal; The first drive control signal, the second drive control signal, the third drive control signal, and the fourth drive control signal are simultaneously input to four different input terminals of the full-bridge drive circuit module to update the drive electrical signal applied to the target load according to the preset input power supply.

3. The energy recovery circuit device for parasitic capacitance according to claim 2, characterized in that: The first logic driving unit includes a first latch unit. The source of the first transistor of the first latch unit is connected to a first preset reference power supply. The source of the second transistor of the first latch unit is grounded. The drain of the first transistor and the drain of the second transistor are connected to form the output terminal of the first latch unit, which is used to output the first driving control signal. The second logic driving unit includes a second latch unit. The source of the third transistor of the second latch unit is connected to the first preset reference power supply, the source of the fourth transistor of the second latch unit is grounded, and the drains of the third transistor and the drains of the fourth transistor are connected to form the output terminal of the second latch unit, which is used to output the second driving control signal.

4. The energy recovery circuit device for parasitic capacitance according to claim 3, characterized in that: The third logic driving unit includes a third latch unit and a first level shifter connected in series therewith. The source of the fifth transistor of the third latch unit is connected to a preset input power supply, the source of the sixth transistor of the third latch unit is connected to a second preset reference power supply, and the drains of the fifth transistor and the sixth transistor are connected to form the output terminal of the third latch unit. The first level shifter is used to convert a first delayed signal input to the third latch unit into a first high-voltage domain signal, and the third latch unit converts the first high-voltage domain signal into a third driving control signal. The fourth logic drive unit includes a fourth latch unit and a second level shifter connected in series therewith. The source of the seventh transistor of the fourth latch unit is connected to the preset input power supply, the source of the eighth transistor of the fourth latch unit is connected to the second preset reference power supply, and the drains of the seventh transistor and the drains of the eighth transistor are connected to form the output terminal of the fourth latch unit. The second level shifter is used to convert the second delayed signal input to the fourth latch unit into a second high-voltage domain signal, and the fourth latch unit converts the second high-voltage domain signal into a fourth drive control signal.

5. The energy recovery circuit device for parasitic capacitance according to claim 2, characterized in that, The full-bridge drive circuit module includes: The first control switch has its gate connected to the first drive control signal, its drain connected to one end of the target load, and its source grounded. The second control switch has its gate connected to the second drive control signal, its drain connected to one end of the resonant inductor, and its source grounded. The third control switch has its gate connected to the third drive control signal, its drain connected to the drain of the second control switch to form an output terminal of the full-bridge drive circuit module, and its source connected to the preset input power supply. The fourth control switch has its gate connected to the fourth drive control signal, its drain connected to the drain of the first control switch to form another output terminal of the full-bridge drive circuit module, and its source connected to the preset input power supply.

6. The energy recovery circuit device applied to parasitic capacitance according to claim 2, characterized in that, The bilateral delay circuit module updates the first delay signal and / or the second delay signal according to the delay control signal, including: After the rising edge of the preset clock signal, when the absolute value of the actual working electrical signal reaches a preset threshold, the preset clock signal is pulled high to generate an updated first delay signal within the preset fixed time period; and / or After the falling edge of the preset clock signal, when the absolute value of the actual working electrical signal reaches a preset threshold, the preset clock signal is pulled low to generate an updated second delay signal within the preset fixed time period.

7. A control method for an energy recovery circuit device applied to parasitic capacitance according to any one of claims 1-6, characterized in that, An energy recovery circuit device for parasitic capacitance includes a resonant inductor connected in series with the target load to form an inductor-capacitor resonant circuit, and the control method includes: At least one timing control signal is generated in response to a preset clock signal; At least one drive control signal is generated based on the at least one timing control signal; and The drive electrical signal applied to the target load is updated according to the at least one drive control signal; During the window period when the driving electrical signal is controlled to be updated, the inductor-capacitor resonant circuit is used to realize the energy recovery of the parasitic capacitance of the target load.

8. An electronic device, comprising: One or more processors; Memory, used to store one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method of claim 7.

9. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method of claim 7.

10. A computer program product comprising a computer program that, when executed by a processor, implements the method of claim 7.

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