Frequency synthesis circuit and method
By using a power divider and a phase-locked loop (PLL) frequency multiplier in parallel processing in the frequency synthesis circuit, combined with signal synthesis in the synthesis control module, the problem of phase noise degradation in traditional frequency synthesis is solved, and the purity of the signal spectrum is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-15
AI Technical Summary
In traditional frequency synthesis techniques, phase noise deteriorates severely during the frequency multiplication process, making it impossible to break through the theoretical limit of 20lg(n)dB, which affects the spectral purity of the signal.
A power divider is used to distribute the reference clock signal into multiple sub-reference signals with consistent phase and equal power. After parallel processing through multiple phase-locked loop frequency multiplication channels, the signal is synthesized using a synthesis control module to ensure signal phase correlation and improve the signal-to-noise ratio.
By using parallel processing and synthesis control of multiple phase-locked loop frequency multiplication channels, the overall output phase noise performance is improved, the spectral purity of the signal is enhanced, and the phase noise limit of traditional technologies is broken.
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Figure CN122052785A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of frequency synthesis technology, and in particular to a frequency synthesis circuit and method. Background Technology
[0002] As a core component of modern electronic systems, the spectral purity of the output signal of a frequency synthesizer directly affects the performance of the entire system. Phase noise is a key indicator for measuring the spectral purity of a frequency synthesizer, directly determining the bit error rate of a communication system, the range resolution of a radar system, and the accuracy of measuring instruments.
[0003] Traditional frequency synthesis techniques, including direct analog synthesis, phase-locked loop synthesis, and direct digital synthesis, have fundamental theoretical limitations when performing frequency conversion. Specifically, when a signal is multiplied by n, its phase noise theoretically deteriorates by 20lg(n) dB. In actual circuits, the deterioration of phase noise is often even more severe due to factors such as additional noise from active devices, power supply disturbances, vibration, and temperature changes.
[0004] To improve phase noise performance, existing technologies typically employ ultra-low noise fundamental frequency reference sources, increase circuit operating power to enhance the signal-to-noise ratio, and suppress noise introduction by optimizing circuit layout and component types. However, these methods have consistently failed to overcome the theoretical degradation limit of 20lg(n) dB. Furthermore, while multi-channel signal synthesis technology is widely used to enhance output power, traditional power synthesis methods still suffer from high phase noise during the synthesis process, thus affecting the spectral purity of the output signal. Summary of the Invention
[0005] This invention provides a frequency synthesis circuit and method to solve the technical problem of phase noise degradation in traditional frequency multiplication technology and improve the spectral purity of the signal.
[0006] According to one aspect of the present invention, a frequency synthesis circuit is provided, comprising:
[0007] A power divider, wherein a reference clock signal is connected to its input terminal, and the power divider is used to divide the reference clock signal into multiple sub-reference signals, and output the multiple sub-reference signals through the corresponding output terminal of the power divider; wherein the multiple sub-reference signals have the same phase and equal power.
[0008] Multiple phase-locked frequency multiplier channels are provided, with the input terminal of each phase-locked frequency multiplier channel connected to the output terminal of the power divider. The phase-locked frequency multiplier channel is used to generate a first frequency signal after performing phase-locked frequency multiplication processing based on the corresponding sub-reference signal.
[0009] A synthesis control module is provided, the input of which is connected to the output of multiple phase-locked frequency multiplication channels. The synthesis control module is used to synthesize multiple first frequency signals to generate a final output signal.
[0010] Optionally, the phase-locked loop frequency multiplier channel includes a phase-locked loop, a frequency multiplier unit, and an amplitude and phase adjustment unit;
[0011] The first input terminal of the phase-locked loop (PLL) is connected to the output terminal of the power divider, and the second input terminal of the PLL is connected to the first output terminal of the PLL. The PLL is used to generate a second frequency signal based on a corresponding sub-reference signal. The input terminal of the frequency multiplier unit is connected to the second output terminal of the PLL. The frequency multiplier unit is used to multiply the second frequency signal to generate a third frequency signal. The input terminal of the amplitude-phase adjustment unit is connected to the output terminal of the frequency multiplier unit, and the output terminal of the amplitude-phase adjustment unit is connected to the input terminal of the synthesis control module. The amplitude-phase adjustment unit is used to adjust the amplitude and phase of the third frequency signal under the control of the synthesis control module to obtain the first frequency signal.
[0012] Optionally, the phase-locked loop includes a phase detector, a first filter, an oscillator, and a feedback phase compensation network;
[0013] The first input terminal of the phase detector is connected to the output terminal of the power divider, the second input terminal of the phase detector is connected to the output terminal of the feedback phase compensation network, and the output terminal of the phase detector is connected to the input terminal of the first filter. The phase detector is used to output a phase detection error signal based on the sub-reference signal and the feedback signal. The input terminal of the feedback phase compensation network is connected to the first output terminal of the oscillator, and the feedback phase compensation network is used to compensate for the phase of the feedback signal. The output terminal of the first filter is connected to the input terminal of the oscillator, and the first filter is used to filter the phase detection error signal and output a tuning voltage signal. The second output terminal of the oscillator is connected to the input terminal of the frequency multiplier unit, and the oscillator is used to output a second frequency signal to the frequency multiplier unit based on the tuning voltage signal, and to output the feedback signal to the phase detector.
[0014] Optionally, the feedback phase compensation network includes a programmable delay chip, which is used to compensate for the phase deviation of each channel to keep the feedback signals of the phase detector in phase for all channels.
[0015] Optionally, the amplitude and phase adjustment unit includes a vector modulator, the input of which is connected to the output of the frequency multiplication unit, and the output of which is connected to the input of the synthesis control module. The vector modulator is used to receive external control signals and to perform amplitude adjustment and phase alignment on the obtained first frequency signal.
[0016] Optionally, the synthesis control module includes a programmable routing matrix and a synthesis control unit;
[0017] The programmable routing matrix is connected to the output of the phase-locked frequency multiplier channel and the synthesis control unit, respectively. The programmable routing matrix is used to group multiple first frequency signals under the control of the synthesis control unit, perform a first-level synthesis, and then perform a second synthesis on the multiple first-level synthesized outputs to form a hierarchical synthesis structure. The synthesis control unit is connected to the output of the phase-locked frequency multiplier channel and is used to control the synthesis and grouping of the first frequency signals according to the multiple first frequency signals.
[0018] Optionally, the synthesis control module further includes a synthesis efficiency monitoring unit, which is connected to the output of the phase-locked frequency multiplication channel and the synthesis control unit, respectively. The synthesis efficiency monitoring unit is used to monitor the synthesis efficiency of multiple first frequency signals; the synthesis control unit is used to control the synthesis and grouping of the first frequency signals according to the multiple first frequency signals and the synthesis efficiency fed back by the synthesis efficiency monitoring unit.
[0019] Optionally, the phase-locked loop frequency multiplier channel further includes a second filter, the input of which is connected to the output of the frequency multiplier unit, and the output of which is connected to the input of the amplitude and phase adjustment unit. The second filter is used to filter the third frequency signal.
[0020] Optionally, the frequency synthesis circuit further includes a third filter, which is connected to the output of the synthesis control module and is used to filter the generated final output signal.
[0021] According to another aspect of the present invention, a frequency synthesis method is also provided, which is performed using a frequency synthesis circuit as described in any embodiment of the present invention. The frequency synthesis method includes:
[0022] The power divider divides the reference clock signal into multiple sub-reference signals; and outputs the multiple sub-reference signals through the corresponding output terminals of the power divider; wherein the multiple sub-reference signals have the same phase and equal power.
[0023] Multiple phase-locked frequency multiplication channels generate multiple first frequency signals after performing phase-locked frequency multiplication processing based on the corresponding sub-reference signals;
[0024] The synthesis control module synthesizes multiple first frequency signals to generate the final output signal.
[0025] The technical solution of this invention divides the reference clock signal into multiple phase-coordinated and power-coordinated sub-reference signals using a power divider, ensuring phase consistency of the signals fed into each channel. By setting multiple phase-locked loop (PLL) frequency multiplication channels, the phase noise generated by the multiple parallel PLL channels is uncorrelated, while the generated first frequency signals are correlated. By setting a synthesis control module, the multiple first frequency signals can be synthesized in the synthesis control module, which can improve the signal-to-noise ratio and improve the overall output phase noise performance. The technical solution of this invention improves the spectral purity of the signal by generating signals with the same frequency and phase correlation through multiple PLL frequency multiplication channels.
[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of the structure of a frequency synthesis circuit provided in an embodiment of the present invention;
[0029] Figure 2 This is a schematic diagram of another frequency synthesis circuit provided in an embodiment of the present invention;
[0030] Figure 3 This is a schematic diagram of another frequency synthesis circuit provided in an embodiment of the present invention;
[0031] Figure 4 This is a schematic diagram of another frequency synthesis circuit provided in an embodiment of the present invention;
[0032] Figure 5 This is a flowchart of a frequency synthesis method provided in an embodiment of the present invention. Detailed Implementation
[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0035] Figure 1 This is a schematic diagram of a frequency synthesis circuit provided in an embodiment of the present invention. This embodiment is applicable to fields with strict requirements for spectral purity and signal stability, such as satellite communication, radar systems, high-precision testing instruments, quantum computing, and wireless communication base stations. Figure 1 As shown, the frequency synthesis circuit includes:
[0036] The power divider 110 has a reference clock signal REF connected to its input terminal. It is used to divide the reference clock signal REF into multiple sub-reference signals and output the multiple sub-reference signals through the corresponding output terminals of the power divider 110. The multiple sub-reference signals have the same phase and equal power.
[0037] Multiple phase-locked frequency multiplier channels 120 are provided. The input terminal of each phase-locked frequency multiplier channel 120 is connected to the output terminal of the power divider 110. The phase-locked frequency multiplier channel 120 is used to generate a first frequency signal after performing phase-locked frequency multiplication processing according to the corresponding sub-reference signal.
[0038] The synthesis control module 130 has its input terminal connected to the output terminals of multiple phase-locked frequency multiplication channels 120. The synthesis control module 130 is used to synthesize multiple first frequency signals to generate the final output signal Rf.
[0039] The power divider 110 divides the input reference clock signal REF into multiple sub-reference signals. These sub-reference signals have consistent phase and equal power, ensuring consistent starting conditions for subsequent processing channels and reducing errors introduced by phase or amplitude differences. Each phase-locked loop (PLL) frequency multiplier channel 120 receives one sub-reference signal and performs PLL processing on it to generate a first frequency signal. The PLL channel 120 may include a phase-locked loop and a frequency multiplier for PLL-multiplying the sub-reference signals. Each PLL channel 120 processes its corresponding sub-reference signal, allowing for parallel operation, improved processing speed, and enhanced phase noise performance. The synthesis control module 130 synthesizes the first frequency signals output from the multiple PLL channels 120 into a final output signal Rf. The synthesis control module 130 may employ a power synthesizer. Hierarchical synthesis can be used, where signals are combined step-by-step like a tree structure. For example, signals can be synthesized in pairs, and the result can be combined with the next signal until the final output.
[0040] Specifically, the reference clock signal REF is input to the power divider 110 and divided into multiple sub-reference signals with consistent phase and equal power. Each sub-reference signal is sent to a corresponding phase-locked loop (PLL) frequency multiplier channel 120 to generate its own first frequency signal. All first frequency signals are then processed by the synthesis control module 130 to generate the desired final output signal Rf. In a traditional system, when a signal is multiplied by n in a single channel, its phase noise theoretically deteriorates by 20lg(n) dB. In the multiple PLL frequency multiplier channels 120 of this invention, the sub-reference signals of all channels are from the same source and in phase, and the phase noise in the output signals of all channels is uncorrelated. When uncorrelated noise sources are combined, the power is added, and the power of N noise sources becomes N times, which is logarithmically an increase of 10lg(N) dB. When correlated signals are combined, the amplitude is added, and the amplitude of N signals becomes N times, which is logarithmically an increase of 20lg(N) dB. Since the signals are in phase and correlated, and the noise sources are uncorrelated, the phase noise relative to the carrier is ideally improved by 10lg(N) dB. When the synthesis control module 130 performs synthesis, the phase noise performance of the final output signal Rf is made better than that of a single channel.
[0041] The technical solution of this invention divides the reference clock signal into multiple sub-reference signals with consistent phase and equal power using a power divider, ensuring phase consistency of the signals fed into each channel. By setting multiple phase-locked loop (PLL) frequency multiplication channels, the phase noise generated by the multiple parallel PLL channels is uncorrelated, while the generated first frequency signals are correlated. By setting a synthesis control module, the signal-to-noise ratio can be improved and the overall output phase noise performance can be enhanced when the multiple first frequency signals are synthesized in the synthesis control module. The technical solution of this invention improves the spectral purity of the signal by generating signals with the same frequency and phase correlation through multiple PLL frequency multiplication channels.
[0042] Figure 2 This is a schematic diagram of another frequency synthesis circuit provided in an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 2 As shown, the phase-locked loop frequency multiplier channel 120 includes a phase-locked loop 121, a frequency multiplier unit 122, and an amplitude and phase adjustment unit 123;
[0043] The first input terminal of phase-locked loop 121 is connected to the output terminal of power divider 110, and the second input terminal of phase-locked loop 121 is connected to the output terminal of phase-locked loop 121. Phase-locked loop 121 is used to generate a second frequency signal based on the corresponding sub-reference signal. The input terminal of frequency multiplier unit 122 is connected to the output terminal of phase-locked loop 121. Frequency multiplier unit 122 is used to multiply the second frequency signal to generate a third frequency signal. The input terminal of amplitude-phase adjustment unit 123 is connected to the output terminal of frequency multiplier unit 122, and the output terminal of amplitude-phase adjustment unit 123 is connected to the input terminal of synthesis control module 130. Amplitude-phase adjustment unit 123 is used to adjust the amplitude and phase of the third frequency signal under the control of synthesis control module 130 to obtain a first frequency signal.
[0044] The phase-locked loop (PLL) 121 receives a sub-reference signal from the power divider 110 at its first input and a feedback signal from its own output at its second input. The PLL 121 continuously compares the phase difference between the feedback signal and the sub-reference signal, generates an error voltage based on the comparison result, and controls the oscillation frequency until the feedback signal and the sub-reference signal are completely synchronized, generating a second frequency signal which is then output to the frequency multiplier unit 122. The PLL 121 ensures that the second frequency signals of all parallel channels maintain a strict phase relationship with the reference clock signal REF at their source. The frequency multiplier unit 122 can multiply the frequency of the second frequency signal using a nonlinear circuit, thereby generating a higher-frequency third frequency signal. For example, the frequency multiplier unit 122 can use a Schottky diode-based frequency doubler, such as multiplying 500MHz to 1000MHz. The frequency multiplication process simultaneously degrades phase noise, theoretically by 20lg2dB. The PLL 121 ensures a low-phase-noise output second frequency signal, guaranteeing that the noise performance of the multiplied third frequency signal remains within acceptable limits. The amplitude and phase adjustment unit 123 can be a programmable or adjustable circuit. The amplitude and phase adjustment unit 123 can be used to finely adjust the amplitude and phase of the output signal of the frequency multiplier unit 122, so that the synthesis control module 130 can achieve high-efficiency synthesis, while avoiding power cancellation caused by phase inconsistency.
[0045] Figure 3 This is a schematic diagram of another frequency synthesis circuit provided in an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 3 As shown, the phase-locked loop 121 includes a phase detector 1211, a first filter 1212, an oscillator 1213, and a feedback phase compensation network 1214;
[0046] The first input terminal of the phase detector 1211 is connected to the output terminal of the power divider 110, the second input terminal of the phase detector 1211 is connected to the output terminal of the feedback phase compensation network 1214, and the output terminal of the phase detector 1211 is connected to the input terminal of the first filter 1212. The phase detector 1211 is used to output a phase detection error signal based on the sub-reference signal and the feedback signal. The input terminal of the feedback phase compensation network 1214 is connected to the first output terminal of the oscillator 1213. The feedback phase compensation network 1214 is used to compensate for the phase of the feedback signal. The output terminal of the first filter 1212 is connected to the input terminal of the oscillator 1213. The first filter 1212 is used to filter the phase detection error signal and output a tuning voltage signal. The second output terminal of the oscillator 1213 is connected to the input terminal of the frequency multiplier unit 122. The oscillator 1213 is used to output a second frequency signal to the frequency multiplier unit 122 based on the tuning voltage signal, and to output a feedback signal to the phase detector 1211.
[0047] The phase detector 1211 receives a sub-reference signal from the power divider 101 at its first input and a feedback signal from the oscillator 1213 at its second input. The phase detector 1211 continuously compares the phase difference between these two input signals and outputs a phase error signal. A feedback phase compensation network 1214 is located between the oscillator 1213 and the phase detector 1211. The feedback phase compensation network 1214 adjusts the phase of the feedback signal, ensuring that the phase detector 1211 always operates in a region where the phase error is close to zero, thereby optimizing the loop dynamic performance and ensuring the phase accuracy of the feedback path. The first filter 1212 can be a loop filter. The first filter 1212 receives the phase error signal from the phase detector 1211, filters out high-frequency noise and spurious components in the phase error signal, and prevents interference with the oscillator 1213. After filtering the phase error signal, the first filter 1212 outputs a tuning voltage signal. The oscillator 1213 can be a voltage-controlled oscillator. The oscillator 1213 can receive the tuning voltage signal from the first filter 1212, adjust its own oscillation frequency according to the tuning voltage signal, and output a second frequency signal to the frequency multiplier unit 122 and the phase detector 1211.
[0048] Specifically, the phase detector 1211 outputs a phase detection error signal based on the sub-reference signal from the power divider 101 and the feedback signal from the oscillator 1213. The first filter 1212 filters the phase detection error signal to generate a tuning voltage signal. The oscillator 1213 can change its own oscillation frequency according to the received tuning voltage signal to generate a second frequency signal, and sends a portion of the second frequency signal back to the phase detector 1211 as a feedback signal, forming a dynamic feedback system.
[0049] In some optional embodiments of the present invention, the feedback phase compensation network includes a programmable delay chip, which is used to compensate for the phase deviation of each channel to keep the feedback signals of the phase detectors of all channels in phase.
[0050] The programmable delay chip can be an integrated circuit whose internal signal propagation delay time can be controlled by digital signals. Ideally, all channels are in phase due to the reference clock signal REF. However, in reality, there is a phase difference between the third frequency signals output by the frequency multiplier units of each channel. By adjusting the programmable delay chip of each channel, a specific delay can be introduced into the feedback path to cancel out the phase difference of that channel. In some embodiments, the feedback phase compensation network can be an adjustable delay line, which can continuously fine-tune the physical delay time of the signal on the transmission path by changing the control voltage or current. The adjustable delay line can use a microstrip line as the delay line and be calibrated by a vector network analyzer to ensure that the electrical lengths of the multiple feedback signals to the phase detector are equal.
[0051] In some optional embodiments of the present invention, the amplitude and phase adjustment unit includes a vector modulator, the input of which is connected to the output of the frequency multiplication unit, and the output of which is connected to the input of the synthesis control module. The vector modulator is used to adjust the amplitude and align the phase of the third frequency signal under the control of the synthesis control module.
[0052] The vector modulator can precisely control the amplitude and phase of the input signal. It receives a third frequency signal output from the frequency multiplier unit and a control signal from the synthesis control module. Based on the control signal from the synthesis control module, the vector modulator adjusts the amplitude and aligns the phase of the third frequency signal, outputting a first frequency signal to the synthesis control module. Amplitude adjustment can increase or decrease the signal power to achieve equal output amplitude across all channels. Phase alignment can advance or delay the signal phase to achieve phase consistency across all channels. In some optional embodiments, the amplitude and phase adjustment unit may further include a digitally controlled attenuator and a digitally controlled phase shifter. The digitally controlled attenuator can be used to adjust the amplitude. It can be a variable resistor network controlled by a digital signal to increase signal loss along the transmission path in fixed steps. By setting the attenuation value for each channel, all channels achieve equal power. The digitally controlled phase shifter can be used to adjust the phase. It can change the phase of the signal in fixed steps by altering the electrical length of the signal path. By setting the phase offset value for each channel, all channels achieve phase synchronization.
[0053] Figure 4 This is a schematic diagram of another frequency synthesis circuit provided in an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 4 As shown, the synthesis control module 130 includes a programmable routing matrix 131 and a synthesis control unit 132;
[0054] The programmable routing matrix 131 is connected to the output of the phase-locked frequency multiplier channel 120 and the synthesis control unit 132 respectively. The programmable routing matrix 131 is used to group multiple first frequency signals, perform first-level synthesis, and then perform a second synthesis on the multiple first-level synthesized outputs to form a hierarchical synthesis structure. The synthesis control unit 132 is connected to the output of the phase-locked frequency multiplier channel 120. The synthesis control unit 132 is used to control the synthesis and grouping of the first frequency signals according to the multiple first frequency signals.
[0055] The programmable routing matrix 131 can divide multiple first-frequency signals into several groups according to the instructions of the synthesis control unit 132, and route signals from the same group to the first-stage power combiner for synthesis. Then, it routes the multiple first-stage synthesized outputs to the second-stage power combiner for final synthesis, generating the final output signal Rf. The synthesis control unit 132 can be a microcontroller. The synthesis control unit 132 can receive the basic parameters of the first-frequency signals of each channel, and send control commands to the programmable routing matrix 131 according to the control algorithm built into the synthesis control unit 132 to change the synthesis routing and grouping strategy. At the same time, the synthesis control unit 132 can send calibration commands to the amplitude and phase adjustment units 123 of each phase-locked loop channel 120. For example, if the efficiency of a synthesis node is found to be lower than a preset threshold, it can be determined that the amplitude and phase deviation of a certain signal in that group is large. The synthesis control unit 132 can fine-tune the amplitude and phase adjustment units 123 of the corresponding channel of that group. If the synthesis efficiency is still lower than the threshold after adjustment, regrouping can be performed, and intact channels can be merged into another group, so that the programmable routing matrix 131 always works in the optimal state.
[0056] In some optional embodiments, the synthesis control module 132 may further include a digital twin calibration unit. The digital twin calibration unit includes a channel characteristic model, a real-time parameter sensing unit, and a predictive control unit. The channel characteristic model can be a pre-stored mathematical model, or a mathematical model obtained through machine learning training, showing the amplitude-frequency response, phase-frequency response, and nonlinear characteristics of each channel as a function of temperature, frequency, and power. The real-time parameter sensing unit can collect parameters such as temperature, output power, and phase detector error voltage for each channel. The predictive control unit can predict the required amplitude-phase adjustment for each channel based on the channel characteristic model and the real-time sensed parameters, and issue pre-compensation commands to the amplitude-phase adjustment unit 123 in advance. Simultaneously, combined with real-time feedback on synthesis efficiency, an adaptive algorithm is used to fine-tune the model parameters and control commands online, forming a closed-loop optimization system.
[0057] In some alternative embodiments of the present invention, reference continues to be made. Figure 4 The synthesis control module 130 also includes a synthesis efficiency monitoring unit 133, which is connected to the output terminal of the phase-locked frequency multiplication channel 120 and the synthesis control unit 132. The synthesis efficiency monitoring unit 133 is used to monitor the synthesis efficiency of multiple first frequency signals. The synthesis control unit 132 is used to control the synthesis and grouping of the first frequency signals according to the multiple first frequency signals and the synthesis efficiency fed back by the synthesis efficiency monitoring unit 133.
[0058] The synthesis efficiency monitoring unit 133 can monitor the input power, output power, and relative phase between each input signal in each synthesis path. The synthesis efficiency monitoring unit 133 can calculate the synthesis efficiency based on the ratio of the total output power to the sum of each power. It can also collect parameters such as the temperature, output power, and phase detection error of each channel. When there is amplitude mismatch or phase misalignment between signals, the synthesis efficiency is low. When the synthesis efficiency is low, the synthesis control unit 132 can send calibration commands to the amplitude and phase adjustment units 123 of each phase-locked loop frequency multiplier channel 120. If the synthesis efficiency is still lower than the threshold after adjustment, regrouping can be performed. The synthesis control unit 132 sends control commands to the programmable routing matrix 131 to change the synthesis routing and grouping strategy.
[0059] The technical solution of this invention, through the setting of a programmable routing matrix, a synthesis control unit, and a synthesis efficiency monitoring unit, allows the programmable routing matrix, under the control of the synthesis control unit, to group multiple first-frequency signals, perform a first-level synthesis, and then perform a second synthesis on the multiple first-level synthesized outputs to form a hierarchical synthesis structure. Hierarchical synthesis reduces signal loss and interference along the synthesis path, improving synthesis efficiency. The synthesis efficiency monitoring unit monitors the synthesis efficiency in real time and can determine the phase and amplitude alignment of the multiple signals. Based on the multiple first-frequency signals and the synthesis data fed back by the synthesis efficiency monitoring unit, the synthesis control unit dynamically optimizes the synthesis routing and grouping strategy to automatically isolate faulty channels and maximize efficiency.
[0060] In some alternative embodiments of the present invention, reference continues to be made. Figure 4 The phase-locked frequency multiplier channel 120 also includes a second filter 124. The input terminal of the second filter 124 is connected to the output terminal of the frequency multiplier unit 122, and the output terminal of the second filter 124 is connected to the input terminal of the amplitude and phase adjustment unit 123. The second filter 124 is used to filter the third frequency signal.
[0061] In this process, when the frequency multiplier unit 123 performs frequency multiplication, the output signal contains not only the required third frequency signal, but also the fundamental frequency, other harmonics, and spurious components. The second filter 124 can be a bandpass filter to filter the output signal of the frequency multiplier unit 123, removing harmonics and spurious components generated by the frequency multiplication nonlinearity and purifying the spectrum.
[0062] In some optional embodiments of the present invention, the frequency synthesis circuit further includes a third filter 140, which is connected to the output terminal of the synthesis control module 130 and is used to filter the generated final output signal Rf.
[0063] The third filter 140 is connected to the output of the synthesis control module 130 and can filter the final output signal Rf. The third filter 140 can be a bandpass filter.
[0064] Working principle of the invention: (Refer to) Figure 4 The power divider 110 divides the reference clock signal REF into multiple sub-reference signals with consistent phase and equal power. These sub-reference signals are then output to the phase detector 1211 of the phase-locked loop 121 via their respective output terminals. The phase detector 1211 can also receive feedback signals from the oscillator 1213. It continuously compares the phase difference between the sub-reference signals and the feedback signal, outputting a phase error signal to the first filter 1212. The first filter 1212 filters the phase error signal and outputs a tuning voltage signal to the oscillator 1213. The oscillator 1213 adjusts its oscillation frequency based on the tuning voltage signal, outputting a second frequency signal to the frequency multiplier unit 122 and the feedback phase compensation network 1214. The frequency multiplier unit 122 multiplies the second frequency signal to generate a third frequency signal. The second filter 124 filters the third frequency signal before transmitting it to the amplitude and phase adjustment unit 123. The amplitude and phase adjustment unit 123 adjusts the amplitude and phase of the third frequency signal to obtain the first frequency signal. Multiple first frequency signals are fed into the programmable routing matrix 131 of the synthesis control module 130. The programmable routing matrix 131, according to instructions from the synthesis control unit 132, divides the multiple first frequency signals into several groups and routes signals from the same group to the first-stage power combiner for synthesis. Then, the multiple first-stage synthesized outputs are routed to the second-stage power combiner for final synthesis, generating the final output signal Rf. The third filter 140 can filter the final output signal Rf. The synthesis efficiency monitoring unit 133 can calculate the synthesis efficiency based on the ratio of the total output power to the sum of each power. When the synthesis efficiency is low, the synthesis control unit 132 can send calibration commands to the amplitude and phase adjustment units 123 of each phase-locked loop frequency multiplier channel 120. If the synthesis efficiency is still below the threshold after adjustment, regrouping can be performed. The synthesis control unit 132 sends control commands to the programmable routing matrix 131 to change the synthesis routing and grouping strategy.
[0065] Figure 5 This is a flowchart of a frequency synthesis method provided by an embodiment of the present invention, executed using the frequency synthesis circuit described in any embodiment of the present invention, such as... Figure 4 and Figure 5 As shown, the frequency synthesis method includes:
[0066] S210 and power divider 110 divide the reference clock signal REF into multiple sub-reference signals, and output the multiple sub-reference signals through the corresponding output terminals of power divider 110; wherein the multiple sub-reference signals have the same phase and equal power;
[0067] S220: Multiple phase-locked frequency multiplication channels 120 perform phase-locked frequency multiplication processing according to the corresponding sub-reference signals to generate multiple first frequency signals;
[0068] S230 and the synthesis control module 130 synthesize multiple first frequency signals to generate the final output signal Rf.
[0069] The reference clock signal REF is input to the power divider 110 and split into multiple sub-reference signals with consistent phase and equal power. Each sub-reference signal is sent to a corresponding phase-locked loop frequency multiplier channel 120 to generate its own first frequency signal. All first frequency signals are then processed by the synthesis control module 130 to generate the desired final output signal Rf.
[0070] This invention achieves a breakthrough improvement in phase noise by introducing multiple phase-locked loop (PLL) frequency multiplication channels and utilizing the different characteristics of signal and noise during synthesis. The theoretical basis is as follows:
[0071] Assuming the power of a single output signal is The noise power spectral density is Then single-channel phase noise ;
[0072] After N-channel synthesis, the signal voltages are superimposed in phase, and the total signal power is... ;
[0073] After N-channel synthesis, the noise powers are added together, and the total noise power spectral density is: ;
[0074] The synthesized phase noise is ;
[0075] Logarithmically, the phase noise improvement value is... ;
[0076] For example, refer to Figure 4In this embodiment of the invention, the target frequency of synthesizing 1GHz is set to 4 channels, and the reference signal is 100MHz. The power divider 110 can be a four-channel power divider. The oscillator 1213 can be a 500MHz cryogenic oscillator based on a surface acoustic wave (SAW) resonator. The feedback phase compensation network 1214 can use a microstrip line as a delay line and be calibrated using a vector network analyzer to ensure that the electrical lengths of the four 500MHz feedback signals to the phase detector 1211 are equal. The frequency multiplier 122 can be a frequency doubler composed of Schottky diodes to multiply the 500MHz to 1000MHz. The second filter 124 can be a SAW filter with a center frequency of 1000MHz to suppress spurious signals generated by frequency multiplication. The amplitude and phase adjustment unit 123 can be adjusted in a closed loop by a microcontroller based on the synthesis efficiency feedback to ensure that the four signals achieve equal amplitude and phase.
[0077] First, each phase-locked loop 121 can be independently debugged to ensure it locks and outputs a stable 500MHz signal. Then, using an external coherent receiver or vector signal analyzer, the relative amplitude and phase difference between the four 1000MHz signals are measured. Based on the measurement results, the synthesis control module 130 sends adjustment commands to the amplitude and phase adjustment units 123 of each channel until the synthesis efficiency is greater than 95%. Finally, the phase noise data measured at the 1GHz output frequency is shown in Table 1. Compared with the traditional single-channel frequency multiplication scheme, the phase noise is improved by more than 5dB in the frequency deviation range of 1kHz to 1MHz, which is consistent with the theoretical prediction.
[0078] Table 1
[0079] Frequency deviation (Hz) The theoretical limit of conventional frequency doubling (dBc / Hz) The actual measurement of this invention (dBc / Hz) Increase (dBc) 1k -150 -155.7 5.7 10k -157 -162.5 5.5 100k -163 -168.7 5.7
[0080] This invention effectively breaks through the classical theoretical limit of phase noise degradation in frequency synthesis, providing a key high-quality frequency source solution for high-performance electronic systems.
[0081] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0082] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A frequency synthesis circuit, characterized in that, include: A power divider, wherein a reference clock signal is connected to its input terminal, and the power divider is used to divide the reference clock signal into multiple sub-reference signals, and output the multiple sub-reference signals through the corresponding output terminal of the power divider; wherein the multiple sub-reference signals have the same phase and equal power. Multiple phase-locked frequency multiplier channels are provided, with the input terminal of each phase-locked frequency multiplier channel connected to the output terminal of the power divider. The phase-locked frequency multiplier channel is used to generate a first frequency signal after performing phase-locked frequency multiplication processing based on the corresponding sub-reference signal. A synthesis control module is provided, the input of which is connected to the output of multiple phase-locked frequency multiplication channels. The synthesis control module is used to synthesize multiple first frequency signals to generate a final output signal.
2. The frequency synthesis circuit according to claim 1, characterized in that, The phase-locked frequency multiplication channel includes a phase-locked loop, a frequency multiplication unit, and an amplitude and phase adjustment unit; The first input terminal of the phase-locked loop (PLL) is connected to the output terminal of the power divider, and the second input terminal of the PLL is connected to the first output terminal of the PLL. The PLL is used to generate a second frequency signal based on a corresponding sub-reference signal. The input terminal of the frequency multiplier unit is connected to the second output terminal of the PLL. The frequency multiplier unit is used to multiply the second frequency signal to generate a third frequency signal. The input terminal of the amplitude-phase adjustment unit is connected to the output terminal of the frequency multiplier unit, and the output terminal of the amplitude-phase adjustment unit is connected to the input terminal of the synthesis control module. The amplitude-phase adjustment unit is used to adjust the amplitude and phase of the third frequency signal under the control of the synthesis control module to obtain the first frequency signal.
3. The frequency synthesis circuit according to claim 2, characterized in that, The phase-locked loop includes a phase detector, a first filter, an oscillator, and a feedback phase compensation network; The first input terminal of the phase detector is connected to the output terminal of the power divider, the second input terminal of the phase detector is connected to the output terminal of the feedback phase compensation network, and the output terminal of the phase detector is connected to the input terminal of the first filter. The phase detector is used to output a phase detection error signal based on the sub-reference signal and the feedback signal. The input terminal of the feedback phase compensation network is connected to the first output terminal of the oscillator, and the feedback phase compensation network is used to compensate for the phase of the feedback signal; the output terminal of the first filter is connected to the input terminal of the oscillator, and the first filter is used to filter the phase detection error signal and output a tuning voltage signal; the second output terminal of the oscillator is connected to the input terminal of the frequency multiplier unit, and the oscillator is used to output a second frequency signal to the frequency multiplier unit according to the tuning voltage signal, and to output the feedback signal to the phase detector.
4. The frequency synthesis circuit according to claim 3, characterized in that, The feedback phase compensation network includes a programmable delay chip, which is used to compensate for the phase deviation of each channel to keep the feedback signals of the phase detector in phase for all channels.
5. The frequency synthesis circuit according to claim 2, characterized in that, The amplitude and phase adjustment unit includes a vector modulator. The input of the vector modulator is connected to the output of the frequency multiplication unit, and the output of the vector modulator is connected to the input of the synthesis control module. The vector modulator is used to adjust the amplitude and align the phase of the third frequency signal under the control of the synthesis control module.
6. The frequency synthesis circuit according to claim 1, characterized in that, The synthesis control module includes a programmable routing matrix and a synthesis control unit; The programmable routing matrix is connected to the output of the phase-locked frequency multiplier channel and the synthesis control unit, respectively. The programmable routing matrix is used to group multiple first frequency signals under the control of the synthesis control unit, perform a first-level synthesis, and then perform a second synthesis on the multiple first-level synthesized outputs to form a hierarchical synthesis structure. The synthesis control unit is connected to the output of the phase-locked frequency multiplier channel and is used to control the synthesis and grouping of the first frequency signals according to the multiple first frequency signals.
7. The frequency synthesis circuit according to claim 6, characterized in that, The synthesis control module further includes a synthesis efficiency monitoring unit, which is connected to the output of the phase-locked frequency multiplication channel and the synthesis control unit. The synthesis efficiency monitoring unit is used to monitor the synthesis efficiency of multiple first frequency signals. The synthesis control unit is used to control the synthesis and grouping of the first frequency signals based on the multiple first frequency signals and the synthesis efficiency fed back by the synthesis efficiency monitoring unit.
8. The frequency synthesis circuit according to claim 2, characterized in that, The phase-locked frequency multiplier channel also includes a second filter. The input of the second filter is connected to the output of the frequency multiplier unit, and the output of the second filter is connected to the input of the amplitude and phase adjustment unit. The second filter is used to filter the third frequency signal.
9. The frequency synthesis circuit according to claim 1, characterized in that, It also includes a third filter, which is connected to the output of the synthesis control module and is used to filter the generated final output signal.
10. A frequency synthesis method, characterized in that, The frequency synthesis method is performed using the frequency synthesis circuit as described in any one of claims 1-9, and the frequency synthesis method includes: The power divider divides the reference clock signal into multiple sub-reference signals and outputs the multiple sub-reference signals through the corresponding output terminals of the power divider; wherein the multiple sub-reference signals have the same phase and equal power. Multiple phase-locked frequency multiplication channels generate multiple first frequency signals after performing phase-locked frequency multiplication processing based on the corresponding sub-reference signals; The synthesis control module synthesizes multiple first frequency signals to generate the final output signal.