Adaptive playback of packets in peripheral interface link

Abstract

Systems, methods, and circuitry for adaptive playback of data link packets in a peripheral interface are described. A data link layer according to a peripheral interface protocol may include a replay buffer memory to simultaneously support sequential replay and selective replay in response to packet errors. In response to detecting an error packet, the receiver may determine an adaptive threshold for selecting a playback mode based on a set of link operating parameters, and then select between a selective playback mode and a sequential playback mode by comparing a fill level of a playback buffer to the adaptive threshold determined for the packet error.

Description

Technical Field

[0001] This disclosure generally relates to data link layer communication via peripheral interfaces, and more specifically to the use of adaptive replay to dynamically select replay modes to handle packet errors. Background Technology

[0002] PCIe (Fast Peripheral Component Interconnect) is a high-speed serial computer expansion bus standard widely used in computer systems to connect various components and peripheral devices, such as data storage devices. As data transfer rates continue to increase, maintaining reliable communication between devices becomes increasingly challenging. PCIe incorporates error detection and correction mechanisms, including packet replay, to ensure data integrity. However, traditional replay methods can sometimes lead to inefficient bandwidth utilization and increased latency, especially when only a small portion of the transmitted data is affected by errors. For example, in many cases, selective packet replay can be more efficient than sequential replay of all packets, but selective replay can be constrained by the size of the replay buffer on the receive side of the PCIe interface's data link layer. Under certain operating conditions, actively choosing between selective and sequential replay may be advantageous. As computing systems demand increasingly higher performance and lower latency, there is a growing need for more sophisticated and adaptive methods for managing packet replay in PCIe communications.

[0003] Therefore, there is still a need for more sophisticated and adaptive methods for managing data link packet replay in PCIe communications that can improve bandwidth utilization and reduce latency while maintaining data integrity. Summary of the Invention

[0004] This paper describes various aspects of adaptive replay of data link packets in the peripheral interface. More specifically, the replay logic dynamically determines an adaptive threshold based on link operation parameters and selects between selective and sequential replay modes by comparing the replay buffer fill level with the adaptive threshold. This enables efficient handling of packet errors while optimizing buffer usage and system performance.

[0005] One general aspect includes an apparatus comprising a peripheral interface configured to connect to a host system using a peripheral interface protocol. The peripheral interface protocol includes a data link layer configured to transmit and receive data link packets, and the peripheral interface includes: a replay buffer configured to store received data link packets after erroneous packets to support a selective replay mode; and replay logic configured to: determine errors in data link packets received via the peripheral interface; dynamically determine an adaptive threshold for selecting a replay mode based on a set of link operation parameters; select a replay mode based on a comparison of a fill level of the replay buffer with the adaptive threshold, the replay mode being selected from: a selective replay mode for requesting retransmission of only the erroneous data link packet; and a sequential replay mode for requesting retransmission of the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet; and transmit a replay request to the host system based on the selected replay mode.

[0006] The implementation may include one or more of the following features. The replay logic circuitry may be further configured to, in response to the selective replay mode: store error-free sequential data link packets received after the erroneous data link packet in the replay buffer; sequentially transmit the transaction layer content of the error-free version of the erroneous data link packet and the error-free sequential data link packets in the replay buffer in response to receiving an error-free version of the erroneous data link packet from the host system; and clear the error-free sequential data link packets from the replay buffer. The replay logic circuitry may be further configured to, in response to the sequential replay mode: discard sequential data link packets received after the erroneous data link packet; and sequentially transmit the error-free version of the erroneous data link packet and the transaction layer content of the retransmitted sequential data link packets in response to receiving the error-free version of the erroneous data link packet and retransmitted sequential data link packets received after the error-free version of the erroneous data link packet. The replay buffer may have a buffer size corresponding to the total number of data link packets that can be stored in the replay buffer at one time. The fill level may correspond to the current number of data link packets stored in the replay buffer for pending selective replay requests. The adaptive threshold may correspond to a maximum fill level smaller than the buffer size of the replay buffer. The replay logic may be further configured to periodically determine the adaptive threshold based on a set of link operation parameters from multiple maximum fill levels. The peripheral interface protocol may support flow control modes configured to change the memory size and format of these data link packets. The replay logic may be further configured to: determine that the flow control mode is active; determine the fill level of the replay buffer based on the memory size and format of these data link packets under the flow control mode; and dynamically determine the adaptive threshold based on the flow control mode. The replay logic may be further configured to recalculate the adaptive threshold based on the current set of link operation parameters in response to each detection of an erroneous data link packet, to dynamically determine the adaptive threshold for the erroneous data link packet. The replay logic circuitry can be further configured to dynamically determine the adaptive threshold by processing the set of link operation parameters through a statistical model. This statistical model includes the set of link operation parameters and corresponding weighting factors, which are configured to balance the probability of successfully recovering the erroneous data link packet with the data link layer latency. The set of link operation parameters may include at least one link connection parameter selected from: current link speed; number of channels; and the bit error rate of the current link speed and number of channels. The set of link operation parameters may also include at least one link workload parameter selected from: current data link packet workload; historical host system workload; and predicted workload.The peripheral interface protocol supports a skip-order set mode, which is configured to periodically resynchronize the data link layer by introducing idle time between fixed periods of transaction layer packet processing. The link set of operating parameters may include a counter for the fixed periods of these transaction layer packet processing. In response to the skip-order set mode, dynamically determining the adaptive threshold may include compensating for the predicted idle time based on the counter. The device may be a data storage device, comprising: a non-volatile storage medium configured to store data for the host system; and a peripheral interface connector configured to connect to a peripheral interface bus for storage communication with the host system using the peripheral interface protocol.

[0007] Another general aspect includes a computer-implemented method comprising: receiving data link packets from a host system via a peripheral interface using a peripheral interface protocol; determining errors in the data link packets received via the peripheral interface; dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operation parameters; selecting a replay mode based on a comparison of a replay buffer fill level with the adaptive threshold, the replay mode being selected from: a selective replay mode for requesting retransmission of only the erroneous data link packet; and a sequential replay mode for requesting retransmission of the erroneous data link packet and subsequent data link packets sent after the erroneous data link packet; and transmitting a replay request to the host system based on the selected replay mode.

[0008] The implementation may include one or more of the following features. The computer-implemented method may include, in response to the selective replay mode: storing error-free sequential data link packets received after the erroneous data link packet in the replay buffer; sequentially transmitting the error-free version of the erroneous data link packet and the transaction layer content of these error-free sequential data link packets in the replay buffer in response to receiving an error-free version of the erroneous data link packet from the host system; and clearing these error-free sequential data link packets from the replay buffer. The computer-implemented method may also include, in response to the sequential replay mode: discarding sequential data link packets received after the erroneous data link packet; and sequentially transmitting the error-free version of the erroneous data link packet and the transaction layer content of these retransmitted sequential data link packets in response to receiving the error-free version of the erroneous data link packet and retransmitted sequential data link packets received after the error-free version of the erroneous data link packet. The computer-implemented method may include periodically determining the adaptive threshold based on a set of link operation parameters from multiple maximum fill levels, wherein: the replay buffer has a buffer size corresponding to the total number of data link packets that can be stored in the replay buffer at one time; the fill level corresponds to the current number of data link packets stored in the replay buffer for pending selective replay requests; and the adaptive threshold corresponds to a maximum fill level smaller than the buffer size of the replay buffer. The computer-implemented method may include: determining that a flow control mode is active, wherein the peripheral interface protocol supports the flow control mode configured to change the memory size and format of these data link packets; determining the fill level of the replay buffer based on the memory size and format of these data link packets under the flow control mode; and dynamically determining the adaptive threshold based on the flow control mode. The computer-implemented method may include recalculating the adaptive threshold based on the current set of link operation parameters in response to each detection of an erroneous data link packet to dynamically determine the adaptive threshold for the erroneous data link packet. The computer-implemented method may include processing the set of link operation parameters through a statistical model, the statistical model including the set of link operation parameters and corresponding weighting factors, the weighting factors being configured to balance the probability of successfully recovering the erroneous data link packet and the data link layer latency. The set of link operation parameters may include at least one link connection parameter selected from: current link speed; number of channels; and the bit error rate of the current link speed and number of channels. The set of link operation parameters may include at least one link workload parameter selected from: current data link packet workload; historical host system workload; and predicted workload.The peripheral interface protocol can support a skip ordered set mode, which is configured to periodically resynchronize the data link layer by introducing idle time between fixed periods of transaction layer packet processing; the link set of operating parameters may include counters for the fixed periods of these transaction layer packet processing; and in response to the skip ordered set mode, dynamically determining the adaptive threshold includes compensating for the predicted idle time based on the counters.

[0009] Another general aspect includes a peripheral interface circuit comprising: a data link layer configured to receive data link packets from a host system; a replay buffer configured to store received data link packets after erroneous packets to support a selective replay mode; means for determining errors in data link packets received from the host system; means for dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operation parameters; means for selecting a replay mode based on a comparison of the fill level of the replay buffer with the adaptive threshold, the replay mode being selected from: a selective replay mode for requesting retransmission of only erroneous data link packets; and a sequential replay mode for requesting retransmission of the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet; and means for transmitting a replay request to the host system based on the selected replay mode.

[0010] Various implementations advantageously apply the teachings of the peripheral bus interface to computer peripherals to improve the functionality of computer systems including those peripherals. These implementations include operations designed to overcome or at least reduce problems previously encountered in computer systems using the peripheral interface, and thus to be more reliable and / or efficient than other computing systems. Specifically, the various implementations disclosed herein include hardware and / or software features that improve the link latency and reliability of the peripheral interface, such as by using adaptive thresholds based on link operation parameters to select between selective replay and sequential replay modes. Therefore, the implementations disclosed herein provide various improvements to storage networks and / or storage systems.

[0011] It should be understood that the language used in this disclosure is chosen primarily for readability and guidance purposes, rather than to limit the scope of the topics disclosed herein. Attached Figure Description

[0012] Figure 1 This schematically illustrates a system that uses a peripheral interface with an adaptive replay mode selector for data storage and communication at the data link layer.

[0013] Figure 2A system for data communication is schematically illustrated, focusing on the data link layer's transmitting and receiving components that support adaptive replay mode selection.

[0014] Figure 3 The diagram schematically illustrates a data link layer receive circuit used to manage packet replay in a peripheral interface of a computing device.

[0015] Figure 4 This is a flowchart of an exemplary method for dynamically selecting the replay mode in the data link layer of a receiver in a PCIe system.

[0016] Figure 5 This is a flowchart of an exemplary method for handling packet replay in the data link layer of a PCIe system transmitter.

[0017] Figure 6 This is a flowchart of an exemplary method for determining parameters related to a replay buffer in a peripheral interface of a computing device based on a flow control mode.

[0018] Figure 7 This is a flowchart of an exemplary method for adjusting an adaptive threshold for packet replay modes based on skipping ordered set modes.

[0019] Figure 8 This is a flowchart of an exemplary method for determining an adaptive threshold for packet replay in a peripheral interface of a computing device. Detailed Implementation

[0020] This disclosure relates to an adaptive replay system for peripheral interfaces. In some examples, the adaptive replay system can dynamically select between a selective replay mode and a sequential replay mode to handle packet errors in data link layer communications. The adaptive replay system can utilize a set of link operation parameters to determine an adaptive threshold for selecting the appropriate replay mode.

[0021] Peripheral interfaces can use peripheral interface protocols to connect devices to host systems. Peripheral interface protocols may include data link layers configured to send and receive data link packets. A replay buffer can be implemented to store received data link packets after erroneous packets, thereby supporting selective replay modes.

[0022] The replay logic can be configured to identify errors in data link packets received through a peripheral interface. The replay logic can dynamically determine an adaptive threshold for selecting a replay mode based on a set of link operation parameters. For example, link operation parameters may include current link speed, number of channels, bit error rate, current workload, and historical behavior of the host system.

[0023] The replay logic circuitry selects a replay mode by comparing the fill level of the replay buffer with an adaptive threshold. The replay modes may include: a selective replay mode for requesting the retransmission of only the erroneous data link packet; and a sequential replay mode for requesting the retransmission of both the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet.

[0024] The adaptive replay system can periodically recalculate the adaptive threshold based on the current link operating parameters. This dynamic approach allows the system to adapt to changing conditions and error modes, potentially improving overall system performance and reliability. Peripheral interface protocols can support additional features that can influence the determination of the adaptive threshold. For example, flow control modes can be supported, which can modify the memory size and format of data link packets, and / or skip ordered set modes can be supported, which can limit processing cycles and scheduled idle cycles to support data link layer resynchronization. The replay logic can adjust its calculations based on the active flow control mode and / or skip ordered set mode.

[0025] Adaptive replay systems can be implemented in a variety of devices that utilize peripheral interfaces. For example, the system can be incorporated into data storage devices, network interface cards, or other computer peripherals that communicate with the host system using peripheral interface protocols such as PCIe.

[0026] Figure 1 An embodiment of an exemplary data storage system 100 having multiple data storage devices 120 interconnected by a peripheral interface bus 108 is shown. While some exemplary features are shown, various other features are not shown for the sake of brevity and to avoid obscuring relevant aspects of the exemplary embodiments disclosed herein. Therefore, as a non-limiting example, the data storage system 100 includes one or more data storage devices 120 (sometimes also referred to as information storage devices, storage devices, disk drives, or drives). In some embodiments, the storage devices 120 may be configured in servers or storage array blades or similar storage units for use in data center storage racks or chassis. The storage devices 120 may interface with one or more hosts 102 and provide data storage and retrieval capabilities to or through those host systems. In some embodiments, the storage devices 120 may be configured in a storage tier that includes storage nodes, storage controllers, and / or other intermediate components between the storage devices 120 and the hosts 102. For example, each storage device may include peripheral interface circuitry and a corresponding peripheral interface connector for connecting to the peripheral interface bus 108, and one or more intermediate systems or components may act as a host system and / or root complex for peripheral interface bus communication.

[0027] In the illustrated embodiments, multiple storage devices 120 are attached to a common peripheral interface bus 108 for host communication. For example, storage devices 120 may include multiple drives arranged in a storage array, such as storage devices in a shared rack, cell, or blade configuration in a data center, or solid-state drives (SSDs) in an all-flash array. In some embodiments, storage devices 120 may share a backplane network, network switches, and / or other hardware and software components accessed via the peripheral interface bus 108. For example, storage devices 120 may be connected to the peripheral interface bus 108 via multiple physical port connections, which define physical, link, and other logical channels for establishing communication with different components and sub-components, thereby establishing a communication channel to host 102. In some embodiments, the peripheral interface bus 108 may be configured as a storage interface bus and provide a primary host interface for storage device management and host data transfer.

[0028] In some implementations, storage device 120 may be configured to perform peer-to-peer communication between storage devices 120 via peripheral interface bus 108, with or without the assistance of host 102. For example, storage device 120 may be configured to use one or more direct memory access protocols, such as Fast Non-Volatile Memory (NVMe), Remote Direct Memory Access (RDMA), NVMe over Network Architecture (NVMeOF), etc., to provide command messaging and data transfer between storage devices using a high-bandwidth storage interface and storage interface bus 108. In these cases, storage device 120 may be configured to act as both an initiator and an endpoint device for peripheral interface communication, thereby allowing one storage device to act as a host system for initiating communication with another storage device via peripheral interface bus 108.

[0029] In some embodiments, data storage device 120 is or includes a solid-state drive (SSD). Each data storage device 120.1-120.n may include a non-volatile memory (NVM) or device controller 130 based on computing resources (processor and memory) and multiple NVMs or media devices 140 for data storage (e.g., one or more NVM devices, such as one or more flash memory devices). In some embodiments, a respective data storage device 120 in one or more data storage devices includes one or more NVM controllers, such as flash memory controllers or channel controllers (e.g., for a storage device having NVM devices in multiple memory channels). In some embodiments, data storage devices 120 may each be encapsulated in a housing, such as a multi-part sealed housing having a defined form factor and ports and / or connectors for interconnection with a peripheral interface bus 108.

[0030] In some embodiments, the corresponding data storage device 120 may include a single media device, while in other embodiments, the corresponding data storage device 120 includes multiple media devices to provide non-volatile storage media for storing host data. In some embodiments, the media device includes NAND flash memory or NOR flash memory. In some embodiments, the data storage device 120 may include one or more hard disk drives (HDDs). In some embodiments, the data storage device 120 may include flash memory devices, which in turn include one or more flash dies, one or more flash packages, one or more flash channels, etc. However, in some embodiments, one or more data storage devices in the data storage device 120 may have other types of non-volatile data storage media (e.g., phase-change random access memory (PCRAM), resistive random access memory (ReRAM), spin-transfer torque random access memory (STT-RAM), magnetoresistive random access memory (MRAM), etc.).

[0031] In some embodiments, each storage device 120 includes a device controller 130, which includes one or more processing units (sometimes also referred to as CPUs, processors, microprocessors, or microcontrollers) configured to execute instructions in one or more programs. In some embodiments, the one or more processors are shared by one or more components within the device controller and, in some cases, beyond the functionality of the device controller. Media devices 140 are coupled to the device controller 130 via connections that typically transmit commands in addition to data, and optionally transmit metadata, error correction information, and / or other information in addition to data values ​​to be stored in the media device and data values ​​read from the media device 140. Media devices 140 may include any number (i.e., one or more) of memory devices, including but not limited to non-volatile semiconductor memory devices such as flash memory devices.

[0032] In some implementations, the media device 140 in storage device 120 is divided into multiple addressable and individually selectable blocks, sometimes referred to as erase blocks. In some implementations, an individually selectable block is the smallest erasable cell in a flash memory device. In other words, each block contains the minimum number of memory cells that can be erased simultaneously (i.e., in a single erase operation). Typically, each block is further divided into multiple pages and / or word lines, where each page or word line is typically an instance of the smallest individually accessible (readable) portion of the block. However, in some implementations (e.g., using some types of flash memory), the smallest individually accessible unit of a dataset is a sector or codeword, which is a subunit of a page. That is, a block comprises multiple pages, each page contains multiple sectors or codewords, and each sector or codeword is the smallest unit of data used to read data from the flash memory device.

[0033] Data units can describe any size allocation of data, such as host blocks, data objects, sectors, pages, multiplane pages, erase / program blocks, media devices / packages, etc. Storage locations can include physical and / or logical locations on storage device 120 and can be described and / or allocated at different granularity levels depending on the storage medium, storage device / system configuration, and / or context. For example, a storage location can be allocated based on host logical block address (LBA) data unit size and addressability for host read / write purposes, but in other contexts managed as a page with storage device addressing managed in the media flash translation layer (FTL). Media segments can include physical storage locations on storage device 120, which may also correspond to one or more logical storage locations. In some embodiments, media segments can include contiguous series of physical storage locations, such as adjacent data units on a storage medium, and for flash devices, may correspond to one or more media erase or program blocks. Logical data groups can contain multiple logical data units that can be grouped logically, regardless of storage location, such as data objects, files, or other logical data structures composed of multiple host blocks.

[0034] The host system 102, or a corresponding host in a system with multiple hosts, can be any suitable computer device, such as a computer, computer server, laptop computer, tablet computer, netbook, internet kiosk, personal digital assistant, mobile phone, smartphone, gaming device, or any other computing device. The host system 102 is sometimes referred to as a host, client, or client system. In some embodiments, the host system 102 is a server system (such as a server system in a data center) or a storage system (such as a storage array in a data center). In some embodiments, one or more host systems 102 are one or more host devices distinct from the storage controller or storage nodes that house the multiple storage devices 120. One or more host systems 102 can be configured to store and access data in the multiple storage devices 120.

[0035] The host system 102 may include one or more central processing units (CPUs) 104 for performing computational operations or instructions to access storage devices 120 via peripheral interface bus 108. In some embodiments, the CPU 104 may include a host processor and be associated with an operational memory 106 for performing both storage operations and a storage interface protocol compatible with peripheral interface bus 108 and storage device 120. In some embodiments, memory 106 may include one or more dynamic random access memory (DRAM) devices for storage device 120 to use for command, management parameters, and / or host data storage and transfer. In some embodiments, storage device 120 may be configured for direct memory access (DMA) via peripheral interface bus 108, such as using a remote direct memory access (RDMA) protocol, to access and use host memory buffers allocated to the storage device. Memory 106 may also include an operating system (not shown), firmware, and / or software applications for performing various functions of the host system 102. In some configurations, memory 106 may include a host basic input / output system (BIOS) 106.1 for establishing basic communication between components of the host system 102 during startup. In some implementations, the host BIOS 106.1 may be configured to establish communication with the storage device 120 via the peripheral interface bus 108 during startup.

[0036] In some configurations, the peripheral interface bus 108 may interface with a common bus shared by other components of the host system 102, such as the CPU 104 and memory 106. In other configurations, the host system 102 may include interface ports for connecting to the peripheral interface bus 108. For example, the host system 102 may include a peripheral bus interface 108.1 for physical connection to the peripheral interface bus 108. The host 102, the peripheral interface bus 108, and / or the storage interface unit may include a root complex 110 for peripheral interface protocols, which uses the peripheral interface switch 112 to manage connectivity and communication through the peripheral interface bus 108. For example, the root complex 110 may be configured to connect the CPU and memory subsystems to a PCIe root complex of a PCIe switch network architecture consisting of various endpoints, including storage device 120, the host system 102, and other devices connected to the peripheral interface bus 108. In some embodiments, the host system 102 may provide processor and memory resources to support the root complex 110. From the perspective of storage device 120, peripheral interface bus 108 may be referred to as host interface bus and provides a host data path between storage device 120 and host 102, as well as other endpoints of the host system that can be used to initiate communication through peripheral interface bus 108.

[0037] System 100 may include a peripheral interface protocol 150 configured to connect a peripheral interface bus 108 and various endpoints connected to the peripheral interface bus 108 (such as host 102 and storage device 120) for storage communication. Peripheral interface protocol 150 may be based on a transaction layer 152, a data link layer 154, and a physical layer 156. Transaction layer 152 may handle higher-level protocol operations, such as read and write requests, and manage transaction layer packet (TLP) flows between host 102 and storage devices 120.1, 120.2, and 120.n. Transaction layer 152 may handle TLP formation, routing, ordering, and flow control. Data link layer 154 may be responsible for reliable data delivery of transaction layer 152 through physical layer 156. For example, data link layer 154 may allocate the contents of transaction layer packets to data link packets for transmission through physical layer 156. Data link layer 154 may include a replay mode selector 154.1, which may be configured to dynamically select between different replay modes for handling packet errors. Data link layer 154 manages data link packets (DLLPs) and implements error detection and correction mechanisms to ensure accurate transmission of transaction layer data between the sending and receiving sides of the corresponding endpoints of data link layer 154. Physical layer 156 is responsible for the actual transmission and reception of data through the physical medium of peripheral interface bus 108. In some cases, physical layer 156 may include peripheral interface connectors 156.1 for connecting to each endpoint of peripheral interface bus 108, as well as the wires and switches therein. Physical layer 156 can handle tasks such as signal encoding, timing, and electrical specifications for data transmission.

[0038] In some embodiments, the data storage system 100 includes one or more processors, one or more types of memory, a display and / or other user interface components (such as a keyboard, touchscreen display, mouse, trackpad) and / or any number of additional devices to add functionality. In some embodiments, the data storage system 100 does not have a display and other user interface components.

[0039] refer to Figure 2 The diagram illustrates a block diagram of a system 200 for data communication, with a particular focus on the data link layer of a peripheral interface protocol. System 200 may include a transaction layer 206, data link layer transmitting circuitry 202, data link layer receiving circuitry 204, and a physical layer 208. Devices implementing peripheral interface protocols (such as PCIe endpoints) may include both transmitting and receiving components, but any given transaction will occur between the transmitting portion of one device and the receiving portion of another. Additionally, more complex peripheral interface bus connections may include intermediate components for routing packets between multiple endpoints, such as switches and corresponding root complexes.

[0040] Data link layer transmitting circuit 202 can process transaction layer content 214, including transaction layer packet (TLP) information 216 received from transaction layer 206. For example, transaction layer 206 can determine the transaction layer packet of the destination endpoint and generate corresponding transmit data 212 (TLP packet payload) and packet information 210 (TLP packet header and parameters for TLP packet processing). In some configurations, the peripheral interface protocol can implement flow control modes, such as FLIT in PCIe. For example, transaction layer content 214 can be formatted as 236 bytes of TLP information 216. Note that data link packets may not have a one-to-one mapping with transaction layer packets, and more or fewer transaction layer packets may be appropriate for a data link packet depending on the relative size and consistency of transaction layer packets to data link packets. The data link layer can transmit sequential data link packets of transaction layer content 214 across physical layer 208 and receive and reassemble sequential data link packets at data link layer receiving 204 to return the corresponding transaction layer content 252 to transaction layer 206 at the receiving device. The transaction layer content 214 can then be processed by the data link packet (DLP) formatter 218 to package the TLP information 216 for transmission according to the link layer protocol. For example, the DLP formatter 218 can add a DLP header and error check data to the TLP information 216, thereby producing a data link packet 220. In some configurations, the data link packet 220 may contain an additional 6 bytes of DLP parameters 222, such as a 2-byte DLP header and a 4-byte Cyclic Redundancy Check (CRC) for a 242-byte DLP or FLIT packet. The DLP 220 is then passed to the physical layer transmitter 224 for transmission over the peripheral interface bus to the destination endpoint (via any switches and root complexes that may need to reach there).

[0041] In some protocols, the data link layer may generate additional packets for maintaining reliable link communication, such as acknowledgments and replay requests, as well as flow control and power management messages. These management packets for the data link layer may be referred to as Data Link Layer Packets (DLLPs) 226. DLLPs 226 may include DLLP parameter data 228, such as message type and information. These DLLPs 226 may also receive DLP parameters 222 (header and CRC) from the DLP formatter 218 before being transmitted through the physical layer transmitter 224. DLLPs 226 including flow control information may receive the flow control information 238 from the corresponding data link layer receiver 204, which may include receivers at the destination endpoint and / or intermediate receivers, such as switches.

[0042] In some configurations, the data link layer transmitting circuitry 202 may include a transmit replay or retry buffer 232 for storing data that may need to be retransmitted. The transmit retry buffer 232 may be configured to store a variable number of transaction layer packets to be replayed in response to a replay request from the data link layer receiver circuitry 204, depending on current operating conditions and protocol settings. In some configurations, the size of the transmit retry buffer 232 may be set and managed to store all transaction layer packet information 216 of TLPs that have been transmitted but not acknowledged by the corresponding DLLP. The data link layer transmitting circuitry 202 may use a multiplexer 230 with path selection logic to select between a new TLP received from the transaction layer 206 and replays of TLPs from the transmit retry buffer 232. For example, when a replay request is pending, the multiplexer 230 may select replay packets from the transmit retry buffer 232 in a first-in-first-out (FIFO) selection to help clear older TLPs from the transmit replay buffer 232. In some configurations, the storage interface protocol can also support No-Operation (NOP) packets from transaction layer 206, as No-Operation Data Content 234 and corresponding TLP information 236. These TLPs can be processed similarly to regular TLPs, but given different priorities by multiplexer 230. In some instances, NOP packets can be transmitted when no other packets are available to help maintain link connectivity and operational parameters.

[0043] On the receiving side, the data link layer receiving circuit 204 can process incoming data link packets 242 received from a transmitter of another device (such as a host system or another endpoint) via the physical layer receiver 240. Data link packets 242 may include TLP information 244 and DLP parameters 246, corresponding to TLP information 216 and DLP parameters 222 transmitted by the sending side and subjected to errors caused by any transmission. The DLP processor 248 can parse the DLP 242 and use the DLP parameters 246 for packet identification and error detection. For example, the DLP header can identify the DLP packet and its contents, and a CRC can be used to determine whether one or more errors exist in the data link packet. Data link packets without errors can have their DLP parameters removed and be stored in the receive replay or retry buffer 250. For example, TLP or FLIT data corresponding to the original 236 bytes in the transaction layer content 214 and TLP information 216 can be stored as the corresponding DLP unit in the receive retry buffer 250. Error-prone data link packets can generate a replay request to be transmitted back to the transmitter in the DLLP. The replay mode selector 260 can dynamically and adaptively select whether to use selective or sequential replay mode for a replay request, such as regarding... Figure 3 Further description: Erroneous data link packets may be dropped, and the processing of previous and / or subsequent sequential packets associated with the same TLP may be determined by the selected replay mode.

[0044] When error-free packets are received and aggregated in the receive retry buffer 250, the transaction layer content 252 corresponding to the TLP information 244 can be reassembled into a TLP and returned to the transaction layer 206 as received data 254 (transaction packet payload) and packet information (transaction packet parameters) for further processing. When the TLP is completed and returned to the transaction layer 206, an acknowledgment of the TLP can be transmitted to the transmitter using a DLLP, and the data link transmission circuit 202 and the data link layer receiving circuit 204 can clear the corresponding transaction layer content from their respective transmit retry buffer 232 and receive retry buffer 250. The DLP processor 248 can also update the flow control information 238 and transmit the corresponding flow control DLLP to the transmitter.

[0045] Figure 3 The selected module of the data link layer receiver circuit 300 is schematically illustrated, which is configured to dynamically adjust an adaptive threshold for selecting between playback modes. For example, the data link layer receiver circuit 300 may embody... Figure 1 and Figure 2 This is part of the data link layer functionality described for peripheral interfaces, such as PCIe interfaces for communication between data storage devices and host systems. The endpoint device including the receiving circuitry 300 may include components from... Figure 1 and Figure 2 Other components support a wider range of functions for transmitting, receiving, and managing flow control, as well as other features of the peripheral interfaces and peripheral interface protocols implemented therein. For example, the receive circuit 300 may also include components such as an interface to a physical layer receiver, a DLP processor, TLP logic for reassembling TLP packets from error-free data link packets in the receive replay buffer 350 or another receive buffer, flow control logic, and connections to transmit circuit components such as a DLLP generator for transmitting replay requests and acknowledgments.

[0046] The receiving circuit 300 may include a bus 310 interconnecting at least one processor 312, at least one memory 314, and other components of the receiving circuit 300. The bus 310 may include one or more wires allowing communication between components of the receiving circuit 300 and / or other components of its peripheral interface. The processor 312 may include any type of processor or microprocessor that interprets and executes instructions or operations, and may include multiple processors or processor cores configured to operate individually or in combination. The memory 314 may include random access memory (RAM) or another type of dynamic storage device storing information and instructions for execution by the processor 312 and / or read-only memory (ROM) or another type of static storage device storing static information and instructions for use by the processor 312. The memory 314 may include one or more memory devices and may include memory devices of different types and configurations. In some configurations, some or all other components of the receiving circuit 300 may be instantiated in the memory 314 for execution by the processor 312. For example, parameter register 360 and replay buffer 350 may be embodied in data structures allocated within memory 314, and replay logic 320 and data link state machine 380 may be instantiated by a set of instructions and data structures in memory 314 for execution by processor 312 to implement the described functions. In some configurations, one or more components may be instantiated in hardware circuitry, including its own logic and memory circuitry for performing the described functions, and processor 312 and memory 314 may provide coordination and management of the functions performed by those hardware circuits via bus 310.

[0047] The receiving circuitry 300 may include replay logic circuitry 320, which includes logic for processing errors detected in received data link packets, managing the capacity of the replay buffer 350, and dynamically selecting between replay modes in response to detected packet errors. The replay logic circuitry 320 may include an error detector 322 for identifying errors in received data packets. For example, the error detector 322 may extract a CRC value from each DLP and perform a CRC check on the received DLP to determine if a transmission-induced error exists in the DLP. The error detector 322 may include CRC processing logic based on the payload size (FLIT data) and a CRC code added by the transmitter to determine if the packet contains an error and requires replay to successfully return the TLP data in the DLP.

[0048] The receiving circuitry 300 may include a replay mode selector 324 within replay logic circuitry 320, configured to determine whether to use sequential replay mode 326 or selective replay mode 328 based on various factors. In some configurations, the receiving circuitry may include a static threshold for selecting between sequential replay mode 326 and selective replay mode 328. For example, the receiving circuitry 300 may default to selective replay mode 328 until the fill level of the replay buffer 350 meets a static threshold for triggering sequential replay mode 326. The use of a static threshold allows the receiver to utilize both modes, but its use is not optimized due to the dynamic nature of the data link connection and varying workloads of the peripheral interface. Therefore, the replay mode selector 324 may be configured with a dynamic model for determining an adaptive threshold that is periodically adjusted based on a set of link operating parameters. For example, the statistics engine 330 may implement one or more statistical models for changing the adaptive threshold in response to changing link operating conditions and current and / or predicted workloads. In some configurations, the statistics engine 330 can calculate a new adaptive threshold each time the error detector 322 detects an erroneous packet. The replay logic circuitry 320 can recalculate the adaptive threshold 330.1 based on the current set of link operation parameters to dynamically determine the adaptive threshold for each erroneous data link packet. For example, whenever the error detector 322 identifies a packet error, the statistics engine 330 can analyze the current link speed 364, number of channels 366, bit error rate 368, and other relevant parameters to recalculate the appropriate adaptive threshold 330.1 for that specific error instance. In other configurations, threshold adaptation can be triggered based on periodic scheduling (such as time, packet count, skip ordered set (SKPOS) resynchronization, or another operating cycle). Other triggering conditions are also possible, such as based on a bit error rate (BER) threshold, a link speed change threshold, etc.

[0049] Sequential replay mode 326 may include a regular linked replay mode, configured to restart the DLP sequence of the current and future TLPs without storing the TLP data from error-free DLPs in the sequence in replay buffer 350. This mode can be used when replay buffer 350 is full or otherwise unavailable, and can be selectively used to allow previous packet errors requested using selective replay mode 328 to be cleared. Sequential replay mode may be triggered in response to error detection by error detector 322, such as when a packet with a failed integrity check using an error detection mechanism (such as CRC) is received. Error notification can be provided to the transmitter by transmitting a replay request indicating that the entire TLP (which may include multiple TLPs) should be retransmitted. When a replay request is received, the transmitting device can locate the TLP in its transmit retransmission buffer and generate a DLP for retransmitting the TLP sequence. Once the receiving device receives the error packet (and other TLPs for retransmission to complete the TLP), the TLP can be reassembled and returned to the transaction layer, with acknowledgment sent from the receiver to the transmitter.

[0050] Selective replay mode 328 may include selectively replaying only erroneous DLPs to avoid retransmitting other DLPs in the TLP sequence. Selective replay mode may be based on storing error-free DLPs in replay buffer 350 to select and rearrange DLPs to complete the TLP. Selective replay mode 328 may be initiated based on the selection of error detector 322 and replay mode selector 324. A replay request sent to the transmitter may indicate selective replay mode and identify erroneous DLP packets. The transmitting device retransmits only the requested packets. The receiving circuit 300 continues to receive and process good packets received after the erroneous packets in the DLP sequence (and the corresponding TLP sequence). Selective replay mode 328 uses replay buffer 350 as a reordering buffer to store good packets until the erroneous packets are retransmitted by the transmitter and received without errors. The receiving device acknowledges the retransmitted packets and / or thereby completes the TLP transmission to the transaction layer.

[0051] The statistical engine 330 within the playback logic circuit 320 may be configured with one or more statistical models for determining an adaptive threshold 330.1. The adaptive threshold 330.1 may include a threshold that, when met, triggers a change in playback mode from selective playback mode 328 to sequential playback mode 326, and may trigger a return to selective playback mode when the threshold is no longer met. For example, the adaptive threshold 330.1 may correspond to a fill level of playback buffer 350, and more specifically, to a maximum fill level at or above which sequential playback mode is selected to reduce stress on playback buffer 350. The adaptive threshold 330.1 may vary within a range of maximum fill level values ​​less than the total capacity of playback buffer 350. The adaptive threshold 330.1 may correspond to a maximum fill level less than the buffer size of playback buffer memory 350. For example, for a given operating cycle, the adaptive threshold 330.1 may be set to 80% of the total buffer size 362 and then adapted to allow for variable buffer headroom as link operating parameters change. In some configurations, the padding level and adaptive threshold 330.1 can be incremented in steps corresponding to the packet size of error-free packets stored in the replay buffer 350. For example, the FLIT size can be used and the number of packets can be used to represent the capacity, padding level, and / or adaptive threshold 330.1.

[0052] The statistical model used by the statistics engine 330 may be based on a set of link operation parameters 330.2. For example, the statistics engine 330 may be configured to represent a set of link operation parameters and workload, and these parameters may be correlated to determine thresholds that should be adapted to changing conditions. In some configurations, the statistics engine 330 may determine, request, or access operation parameter values ​​from the parameter register 360. The parameter register 360 may include combinations of link connectivity parameters (such as current link speed 364, number of channels 366, and bit error rate 368) and link workload parameters (such as current workload 370 and host workload history 372). In a simple statistical model, the selected operation parameters may be included as individual terms in the model, and each term may include correlation operators and weighting factors 330.3 to represent the relationships and trade-offs between the different parameters. In some configurations, the statistics engine 330 may be configured to balance completion target 330.4 to determine the probability that erroneous packets (and / or their contributing TLPs or TLP sequences) will be successfully replayed and received without errors, and to balance latency target 330.5 to determine changes in data link layer latency based on changes in replay mode. In some configurations, completion target 330.4 may be based on a completion risk threshold, such as a 90% probability of recovering erroneous packets in the next attempt, and latency target 330.5 may be based on an allowable latency change threshold, such as a 5% increase in link latency. FLIT compensation 330.6 may include factors in the statistical model or logic in the statistics engine 330, responding to the enabling of flow control modes and accompanying changes in packet size and format, and their impact on the replay buffer 350 and the reordering or completion logic for the corresponding TLPs. SKPOS compensation 330.7 may include factors in the statistical model or logic in the statistical engine 330, which responds to the enabling of skip ordered set mode and provides predictable interruptions in DLP packet processing and supports catching up on relevant processing cycles and idle times of error backlog. The statistical engine 330 can be configured to compensate for any number of operating parameters and / or operating modes or combinations thereof that affect link operation.

[0053] The replay logic circuit 320 may include a replay request interface 332 for initiating packet retransmission via a replay request to the transmitting device, such as initiating a DLLP message identifying the erroneous packet and the requested replay mode. The replay logic circuit 320 may include reordering logic 334 for reassembling the DLP and TLP sequences in response to error-free packets received in the replay buffer 350 and / or in response to the replay request, and for returning the completed TLP to the transaction layer in response to an error-free version of the erroneous packet that is the subject of the replay request. The replay logic circuit 320 may include an acknowledgment interface 336 for confirming successful transmission, such as initiating a DLLP message indicating that a DLP packet was received error-free and / or that a TLP was completed error-free. The replay logic circuit 320 may include a buffer monitor 338 for tracking the state of the replay buffer 350, and more specifically, determining the current padding level based on the completion of the sequences waiting for them stored in the replay buffer 350 and the corresponding error-free TLPs returned to the transaction layer. Playback logic circuitry 320 can be configured to select a playback mode based on comparing the fill level of playback buffer memory 350 with an adaptive threshold. For example, buffer monitor 338 can track the current fill level of playback buffer 350, and playback mode selector 324 can compare this fill level with an adaptive threshold 330.1 to determine whether to use sequential playback mode 326 or selective playback mode 328.

[0054] The replay buffer 350 may include one or more memory devices configured to store data link packets 352.1, 352.2, 352.3, up to 352.n. The replay buffer 350 may be configured as a FIFO buffer with a total capacity based on the allocated device memory size and the packet size of packet 352. In some configurations, the replay buffer 350 may be indexed to allow reordering of packets based on their expected order (as determined at the transmitter) and indicated in the header parameters of the DLP and / or TLP mapped data. The replay buffer 350 may be configured to store received error-free data link layer packets after erroneous packets to support selective replay modes and to reassemble the order of packets once a corrected erroneous packet is received. In some configurations, the replay buffer 350 may have a buffer size corresponding to the total number of data link packets that can be stored in the replay buffer 350 at one time. For example, the buffer size 362 stored in parameter register 360 may indicate the maximum capacity of the replay buffer 350. The fill level of the replay buffer 350 corresponds to the current number of data link packets stored in the replay buffer 350 for pending selective replay requests. The buffer monitor 338 tracks this fill level in real time as packets are added to and removed from the replay buffer 350.

[0055] Parameter register 360 may include one or more memory devices configured to store various link operation parameters. Exemplary link operation parameters that may be included in parameter register 360 include: replay buffer size 362, current link speed 364, number of channels 366, BER 368 (for current link speed and number of channels), current data link packet workload 370, host system history 372 (historical workload for a specific host system / transmitter), FLIT mode indicator 374, and SKPOS counter 376. Replay logic circuitry 320 may use some or all of these parameters to determine an adaptive threshold 330.1 and dynamically select between or within replay modes. For example, statistics engine 330 may use a set of link operation parameters, including link connectivity parameters selected from link speed 364, number of channels 366, and BER 368, to model link latency and error probability. In another example, the statistics engine 330 may use a set of link operation parameters, including link workload parameters selected from workload 370, host history 372, and / or predicted workload based on the current workload, host history, and a predictive model that infers changes in the current workload over a future period. In some configurations, one or more parameter values ​​in the parameter register 360 may be determined by the data link state machine 380. For example, the data link state machine 380 may monitor link speed 364, channel connectivity 366, BER 368, current workload, and various modes (including FLIT and SKPOS modes) to maintain link operation at the desired level of performance. In some configurations, the parameter register 360 may include a set of memory registers associated with or connected to the data link state machine 380 and / or other functions within or connected to the receiver circuitry 300, which may be updated and accessed to provide the current value for each parameter.

[0056] In some configurations, the replay logic circuitry 320 can be configured to determine whether a flow control mode is active. For example, the FLIT mode parameter 374 in parameter register 360 can indicate whether a flow control mode such as FLIT (Flow Control Unit) is currently in use. When FLIT mode is active, the replay logic circuitry 320 can adjust its calculation and decision-making processes to take into account the different packet sizes and formats used in FLIT mode. The statistics engine 330 can employ various compensation mechanisms to fine-tune the adaptive threshold 330.1. For example, when FLIT mode is active, FLIT compensation 330.6 can adjust the calculation to take into account the specific characteristics of FLIT mode.

[0057] Similarly, SKPOS compensation 330.7 can modify the threshold based on the frequency and time of skipped ordered sets, as indicated by SKPOS counter 376. Replay mode selector 324 can consider the distance to the SKPOS time window or the current packet processing window. In some configurations, SKPOS are periodic markers inserted into the data stream to maintain synchronization between the transmitter and receiver, introducing idle time to allow for resynchronization at the data link layer. Parameter register 360 can include SKPOS counter 376 to track the time and frequency of these SKPOS occurrences. SKPOS counter 376 provides information about the time of skipped ordered sets, which can affect packet transmission patterns. Replay mode selector 324 can use this information to adjust its replay mode selection strategy. SKPOS compensation 330.7 can use the value from SKPOS counter 376 to adjust the adaptive threshold 330.1 or influence replay mode selection. For example, if SKPOS counter 376 indicates an impending SKPOS, replay logic circuitry 320 can adjust its decision-making process to avoid initiating sequential replay operations that might conflict with the upcoming SKPOS. If a packet error occurs close to the upcoming SKPOS window, the replay mode selector 324 can increase the adaptive threshold 330.1 and rely on the idle time provided by SKPOS resynchronization to receive packet retransmissions before the next processing window is initiated, rather than interrupting sequential replay.

[0058] Figure 4 A flowchart of a method 400 for dynamically selecting a replay mode in a PCIe system is shown. Method 400 can be executed by receiving circuitry in a data storage device or other peripheral device connected to the host system via a PCIe interface. Method 400 can effectively handle packet errors while optimizing buffer usage and system performance. Generally, method 400 can dynamically select between a selective replay mode and a sequential replay mode based on the replay buffer fill level and an adaptive threshold.

[0059] At box 410, packets can be received from the transmitter. For example, the receiving circuitry can receive data link packets from the host system via a PCIe interface.

[0060] At box 412, errors in the received packet can be identified. For example, the receiving circuitry can perform a cyclic redundancy check on the received packet to detect any transmission errors.

[0061] At box 414, an adaptive threshold can be determined. For example, the receiving circuitry can calculate the threshold based on current link operating parameters such as link speed, number of channels, and bit error rate.

[0062] At box 416, the fill level of the replay buffer can be determined. For example, the receiving circuitry can check the memory allocation in its replay buffer, which is used to store good packets waiting to be replayed during selective replay of erroneous packets.

[0063] At box 418, a decision can be made based on whether the fill level meets a threshold. For example, the receiving circuitry can compare the current playback buffer fill level with a calculated adaptive threshold.

[0064] At box 420, if the fill level does not meet the threshold, a selective playback mode can be selected. For example, if sufficient buffer space is available, the receiving circuitry can choose to use selective playback.

[0065] At box 422, a replay request can be sent for an erroneous packet. For example, the receiving circuit can send a data link layer packet (DLLP) to the host system, requesting the retransmission of a specific erroneous packet and specifying a selective replay mode.

[0066] At box 424, sequential packets can be stored in a replay buffer. For example, the receiving circuit can continue to receive and buffer subsequent error-free packets while waiting for erroneous packets to be retransmitted.

[0067] At box 426, replay packets can be received without errors. For example, the receiving circuitry can accept retransmitted packets from the host system and verify their integrity to confirm the error-free version.

[0068] At box 428, transaction layer content from replay packets and stored packets can be transmitted to the transaction layer. For example, the receiving circuitry can forward one or more transaction layer packets (including error-free versions of erroneous packets) corresponding to the corrected packet sequence to a higher protocol layer for further processing.

[0069] At box 430, transmitted packets can be cleared from the replay buffer. For example, receiving circuitry can remove successfully processed packets from its buffer to free up space.

[0070] At box 440, a sequential playback mode can be selected if the fill level meets a threshold (which may include being equal to or exceeding an adaptive threshold). For example, if buffer space is limited and operating conditions indicate that selective playback is unlikely to be successful or more efficient, the receiving circuitry may choose to use sequential playback.

[0071] At box 442, a replay request can be sent for the erroneous packet. For example, the receiving circuitry can send a DLLP to the host system, requesting a retransmission starting from the erroneous packet.

[0072] At box 444, packets following an error can be discarded. For example, the receiving circuitry can ignore any subsequent packets received after an error is detected.

[0073] At box 446, replay packets can be received without errors. For example, the receiving circuitry can accept retransmitted packets from the host system and verify their integrity.

[0074] At box 448, transaction layer content from the replay packet can be transmitted to the transaction layer. For example, the receiving circuitry can forward the transaction layer packet corresponding to the corrected packet to a higher protocol layer for further processing.

[0075] At box 450, transaction layer content from sequential packets can be received and sent to the transaction layer. For example, the receiving circuitry can accept and forward the remaining sequence of retransmitted packets to complete one or more transaction layer packets that include and / or follow content from the corrected packets.

[0076] Figure 5 A flowchart of a method 500 for handling packet replay in the data link layer of a transmitter in a PCIe system is shown. Method 500 can be executed by transmitting circuitry in a data storage device or other peripheral device connected to a host system via a PCIe interface. Method 500 can effectively handle packet errors by dynamically selecting between a selective replay mode and a sequential replay mode. In general, method 500 provides a structured approach to error handling in data transmission, allowing for flexible selection of the most appropriate replay mode based on the specific circumstances of the error.

[0077] At box 510, packets can be transmitted to the receiver. For example, the transmitting circuitry can transmit data link packets to the host system via a PCIe interface.

[0078] At box 512, a replay request can be received. For example, the transmitting circuit can receive a data link layer packet (DLLP) from the host system indicating that an error occurred during the transmission of a previously transmitted packet.

[0079] At box 514, a specific erroneous packet can be identified. For example, the transmitting circuitry can analyze the replay request to identify which packet needs to be retransmitted based on the data link packet identifier from the header of the erroneous packet.

[0080] At box 516, the playback mode to be used can be determined. For example, the transmitting circuit can determine the playback mode parameter value based on a playback request set by a receiver that has detected an error.

[0081] At box 518, a decision can be made regarding whether selective replay should be used. For example, the transmitting circuitry can determine whether the replay mode parameter value indicates selective replay mode or sequential replay mode.

[0082] At box 520, if selective replay is indicated, the packet sequence can be interrupted. For example, the transmitting circuitry can pause the current transmission sequence to prepare for retransmission of a specific erroneous packet.

[0083] At box 522, erroneous packets can be retransmitted out of order. For example, the transmitting circuit can retrieve the erroneous packet from its transmit buffer and transmit it immediately, regardless of its original position in the sequence.

[0084] At box 524, the packet sequence can be resumed from the point of interruption. For example, after a packet retransmission, the transmitting circuitry can return to transmitting packets with the new packet sequence in progress, without repeating the packets that initially followed the retransmission.

[0085] At box 530, if selective replay is not indicated, the current packet sequence can be terminated. For example, the transmitting circuitry can stop the ongoing transmission and prepare to retransmit all packets from the point of error.

[0086] At box 532, erroneous packets can be retransmitted. For example, the transmitting circuit can retrieve the erroneous packet from its transmit buffer and retransmit from that point.

[0087] At box 534, the packet sequence can be recovered from the erroneous packet. For example, the transmitting circuit can continue transmitting all subsequent packets in the sequence, thereby effectively retransmitting the portion of the data stream that started with the erroneous packet and continues forward.

[0088] Figure 6 A flowchart of a method 600 for determining parameters associated with a replay buffer in a peripheral interface of a computing device based on flow control modes is shown. Method 600 can be performed by replay logic circuitry in a data storage device or other peripheral device connected to a host system via the peripheral interface. Method 600 can accurately determine replay buffer parameters that account for variations in packet size and format due to flow control modes. Generally, method 600 can dynamically adjust the replay buffer parameters to optimize error handling and data transmission efficiency in different flow control scenarios.

[0089] At box 610, the buffer size of the replay buffer can be determined. For example, the replay logic circuitry can access a parameter register to retrieve the total memory capacity allocated to the replay buffer.

[0090] At box 612, the flow control mode can be determined. For example, the playback logic can check the current state of the peripheral interface protocol to identify whether a specific flow control mode, such as the FLIT (Flow Control Unit) mode, is active.

[0091] At box 614, packet size and format, as well as replay buffer packet capacity, can be determined based on the flow control mode. For example, if FLIT mode is active, the replay logic can calculate new packet sizes and formats according to the FLIT specification, and then determine how many of these packets can be stored in the replay buffer.

[0092] At box 616, the fill level of the replay buffer can be determined based on the packet size and format of the current flow control mode. For example, the replay logic can count the number of packets currently stored in the replay buffer and multiply that by the packet size to calculate the current occupancy of the buffer.

[0093] Figure 7 A flowchart is shown for a method 700 for adjusting an adaptive threshold for packet replay patterns based on skipped ordered set patterns. Method 700 can be executed by replay logic circuitry in a data storage device or other peripheral device connected to a host system via a peripheral interface. Method 700 can induce an optimized adaptive threshold adjustment that takes into account periodic resynchronization events in the data link layer. Generally, method 700 can dynamically adjust the adaptive threshold based on the processing cycle and predicted idle time to improve the efficiency of packet replay decisions.

[0094] At box 710, the skip ordered set mode can be determined. For example, the replay logic circuitry can check the current state of the peripheral interface protocol to identify whether the skip ordered set mode is active.

[0095] At box 712, the processing cycles and idle times used for resynchronization can be determined. For example, the replay logic can retrieve configuration values ​​for fixed cycles of transaction layer packet processing and the scheduled or predicted idle times between these cycles.

[0096] At box 714, packets can be received from the transmitter. For example, the replay logic circuitry can accept input data link packets from the host system via a peripheral interface.

[0097] At block 716, a counter used for processing cycles can be incremented. For example, replay logic can update an internal counter that tracks the process within the current processing cycle.

[0098] At box 718, the current idle count can be determined. For example, the replay logic can calculate the remaining time or packet count before the next scheduled idle period based on the current counter value and the known processing cycle duration.

[0099] At block 720, an adaptive threshold can be adjusted based on the current idle count. For example, the replay logic can modify the adaptive threshold used to select between replay modes, potentially increasing the threshold as the system approaches an idle period to take advantage of upcoming resynchronization opportunities.

[0100] Figure 8A flowchart is shown of a method 800 for determining an adaptive threshold for packet replay in a peripheral interface of a computing device. Method 800 can be executed by replay logic circuitry in a data storage device or other peripheral device connected to a host system via the peripheral interface. Method 800 can generate a dynamically adjusted adaptive threshold that optimizes the selection between replay modes based on current system conditions. Generally, method 800 analyzes various system parameters and historical data to calculate an adaptive threshold that balances effective error handling with system performance.

[0101] At box 810, a statistical model can be determined. For example, the playback logic circuit can select or configure a statistical model that incorporates relevant system parameters and their relationships for threshold calculation.

[0102] At box 812, the completion target can be determined. For example, the replay logic circuitry can set a target percentage for successful packet transmission completion based on system requirements and historical performance data.

[0103] At box 814, a delay target can be determined. For example, the replay logic can establish the maximum acceptable delay for packet retransmission to maintain overall system responsiveness.

[0104] At box 816, the parameter types and weighting factors can be determined. For example, the replay logic circuit can identify key system parameters such as link speed and bit error rate, and assign appropriate weighting factors to each based on their relative importance in the statistical model.

[0105] At box 820, packet errors can be detected. For example, replay logic can identify cyclic redundancy check (CRC) failures in received data link layer packets.

[0106] At box 822, the current link speed can be determined. For example, the replay logic can query the physical layer to obtain the current operating speed of the peripheral interface link.

[0107] At box 824, the number of channels can be determined. For example, replay logic can check the current link configuration to identify the number of active channels in the peripheral interface connection.

[0108] At box 826, the bit error rate can be determined. For example, the replay logic can calculate or retrieve the current bit error rate based on recent transmission statistics.

[0109] At box 828, packet workload can be determined. For example, replay logic can measure the current rate of packet transmission and reception on the peripheral interface.

[0110] At box 830, the host's historical workload can be determined. For example, replay logic can access stored data about past workload patterns of the connected host system.

[0111] At box 832, the predicted workload can be determined. For example, playback logic circuits can use machine learning algorithms or statistical analysis to predict the expected workload based on current trends and historical data.

[0112] At box 834, an adaptive threshold can be calculated based on the collected parameters and factors. For example, the replay logic circuitry can input all determined values ​​into a statistical model to calculate a new adaptive threshold for selecting between replay modes specifically designed for detected erroneous packets.

[0113] While at least one exemplary embodiment has been presented in the foregoing detailed description of this technology, it should be understood that numerous variations are possible. It should also be understood that one or more exemplary embodiments are examples and are not intended to limit the scope, applicability, or configuration of this technology in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing exemplary embodiments of this technology, and it should be understood that various modifications may be made to the function and / or arrangement of the elements described in the exemplary embodiments without departing from the scope of this technology as set forth in the appended claims and their legal equivalents.

[0114] As will be appreciated by those skilled in the art, various aspects of this technology may be embodied in a system, method, or computer program product. Therefore, some aspects of this technology may take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or a combination of hardware and software aspects, all of which are collectively referred to herein as circuits, modules, systems, and / or networks. Furthermore, various aspects of this technology may take the form of a computer program product embodied in one or more computer-readable media, including computer-readable program code embodied thereon.

[0115] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a physical computer-readable storage medium. A physical computer-readable storage medium can be, for example, but not limited to, electronic, magnetic, optical, crystal, polymer, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination thereof. Non-limiting examples of physical computer-readable storage media may include, but are not limited to, electrical connections comprising one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, optical fiber, CD-ROM, optical processors, magnetic processors, or any suitable combination thereof. In the context of this document, a computer-readable storage medium can be any tangible medium that can contain or store programs or data for use by or in connection with an instruction execution system, apparatus, and / or device.

[0116] Computer code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, radio frequency (RF), or any suitable combination thereof. The computer code used to perform various aspects of this technology may be written in any statically typed language, such as the C programming language or other similar programming languages. The computer code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the latter case, the remote computing device may be connected to the user's computing device via any type of network or communication system, including but not limited to a local area network (LAN) or wide area network (WAN), an integrated network, or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0117] The foregoing description of various aspects of the art can be made with reference to flowchart illustrations and / or block diagrams of methods, apparatus, systems, and computer program products. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing apparatus (processor) of a general-purpose computer, special-purpose computer, or other programmable data processing device to produce a machine, such that instructions executable by the processing apparatus or other programmable data processing device create means for implementing the operations / actions specified in the blocks of the flowchart illustrations and / or block diagrams.

[0118] Some computer program instructions may also be stored in a computer-readable medium that directs a computer, other programmable data processing apparatus, or other device to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the operations / actions specified in the frames of a flowchart and / or block diagram. Some computer program instructions may also be loaded onto a computing device, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computing device, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which are executable by the computer or other programmable apparatus, provide one or more processes for implementing the operations / actions specified in the frames of a flowchart and / or block diagram.

[0119] The flowcharts and / or block diagrams in the above figures illustrate the architecture, functionality, and / or operation of possible embodiments of apparatus, systems, methods, and / or computer program products according to various aspects of the present technology. In this regard, boxes in flowcharts or block diagrams may represent modules, segments, or code portions, which may include one or more executable instructions for implementing one or more specified logical functions. It should also be noted that in some alternative aspects, some functions marked in the boxes may occur in a different order than indicated in the figures. For example, two boxes shown consecutively may actually be executed substantially concurrently, or the boxes may sometimes be executed in reverse order, depending on the operations involved. It will also be noted that boxes or combinations of boxes in block diagrams and / or flowcharts may be implemented by a system based on dedicated hardware, or a combination of dedicated hardware and computer instructions, capable of performing one or more specified operations or actions.

[0120] Although one or more aspects of the present technology have been described and discussed in detail, those skilled in the art will understand that modifications and / or adaptations may be made to each aspect without departing from the scope of the present technology as set forth in the appended claims.

Claims

1. A device comprising a peripheral interface configured to connect to a host system using a peripheral interface protocol, wherein: The peripheral interface protocol includes a data link layer configured to send and receive data link packets; and The peripheral interface includes: A replay buffer, configured to store received data link packets after erroneous packets to support selective replay mode; and The replay logic circuit is configured as follows: Identify errors in the data link packets received through the peripheral interface; An adaptive threshold for selecting the replay mode is dynamically determined based on a set of link operation parameters. The replay mode is selected based on a comparison between the fill level of the replay buffer and the adaptive threshold, wherein the replay mode is selected from: Selective replay mode, which is used to request the retransmission of only erroneous data link packets; and A sequential replay mode, wherein the sequential replay mode is used to request the retransmission of the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet; and The replay request is transmitted to the host system based on the selected replay mode.

2. The device according to claim 1, wherein the replay logic circuit is further configured as follows: In response to the selective replay mode: The replay buffer stores error-free sequential data link packets received after the erroneous data link packet. In response to receiving an error-free version of the erroneous data link packet from the host system, the error-free version of the erroneous data link packet and the transaction layer content of the error-free sequential data link packet in the replay buffer are transmitted sequentially. as well as Clear the error-free sequential data link packets from the replay buffer; as well as In response to the sequential replay mode: Discard sequential data link packets received after the erroneous data link packet; as well as In response to receiving the error-free version of the erroneous data link packet and a retransmitted sequential data link packet received after the error-free version of the erroneous data link packet, the transaction layer content of the error-free version of the erroneous data link packet and the retransmitted sequential data link packet is transmitted sequentially.

3. The device according to claim 1, wherein: The replay buffer has a buffer size corresponding to the total number of data link packets that can be stored in the replay buffer at one time; The fill level corresponds to the current number of data link packets stored in the replay buffer for pending selective replay requests; The adaptive threshold corresponds to the maximum fill level that is smaller than the buffer size of the replay buffer memory; and The replay logic circuit is further configured to periodically determine the adaptive threshold based on the set of link operation parameters using multiple maximum fill levels.

4. The device according to claim 3, wherein: The peripheral interface protocol supports flow control modes that can be configured to change the memory size and format of the data link packets; and The replay logic circuit is further configured as follows: It is determined that the flow control mode is active; The fill level of the replay buffer memory is determined based on the memory size and format of the data link packets in the flow control mode; as well as The adaptive threshold is dynamically determined based on the flow control mode.

5. The apparatus of claim 1, wherein the replay logic circuitry is further configured to recalculate the adaptive threshold based on a current set of link operation parameters in response to each detection of an erroneous data link packet, so as to dynamically determine the adaptive threshold for the erroneous data link packet.

6. The device of claim 1, wherein the replay logic circuit is further configured to dynamically determine the adaptive threshold by processing the set of link operation parameters through a statistical model, the statistical model including the set of link operation parameters and corresponding weighting factors, the weighting factors being configured to balance the probability of successfully recovering the erroneous data link packet and the data link layer latency.

7. The device of claim 1, wherein the set of link operation parameters includes at least one link connection parameter selected from: Current link speed; Number of channels; and The bit error rate of the current link speed and number of channels.

8. The device of claim 1, wherein the set of link operation parameters includes at least one link workload parameter selected from the following: Current data link packet workload; Historical workload of the host system; and Predict workload.

9. The device according to claim 1, wherein: The peripheral interface protocol supports a skip ordered set mode, which is configured to periodically resynchronize the data link layer by introducing idle time between fixed periods of transaction layer packet processing. The link set of operation parameters includes a fixed-period counter for processing the transaction layer packets; and In response to the skip ordered set mode, dynamically determining the adaptive threshold includes compensating for the predicted idle time based on the counter.

10. The device according to claim 1, wherein the device is a data storage device, and the device further comprises: A non-volatile storage medium configured to store data for the host system; and A peripheral interface connector configured to connect to a peripheral interface bus for storage communication with the host system using the peripheral interface protocol.

11. A computer-implemented method, the method comprising: Use the peripheral interface protocol to receive data link packets from the host system through the peripheral interface; Identify errors in the data link packets received through the peripheral interface; An adaptive threshold for selecting the replay mode is dynamically determined based on a set of link operation parameters. The replay mode is selected based on a comparison between the fill level of the replay buffer and the adaptive threshold, wherein the replay mode is selected from: Selective replay mode, which is used to request the retransmission of only erroneous data link packets; and Sequential replay mode, which is used to request the retransmission of the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet; as well as The replay request is transmitted to the host system based on the selected replay mode.

12. The computer-implemented method according to claim 11, further comprising: In response to the selective replay mode: The replay buffer stores error-free sequential data link packets received after the erroneous data link packet. In response to receiving an error-free version of the erroneous data link packet from the host system, the error-free version of the erroneous data link packet and the transaction layer content of the error-free sequential data link packet in the replay buffer are transmitted sequentially. as well as Clear the error-free sequential data link packets from the replay buffer; as well as In response to the sequential replay mode: Discard sequential data link packets received after the erroneous data link packet; as well as In response to receiving the error-free version of the erroneous data link packet and a retransmitted sequential data link packet received after the error-free version of the erroneous data link packet, the transaction layer content of the error-free version of the erroneous data link packet and the retransmitted sequential data link packet is transmitted sequentially.

13. The computer-implemented method according to claim 11, further comprising: The adaptive threshold is determined periodically from multiple maximum fill levels based on the aforementioned set of link operation parameters, wherein: The replay buffer has a buffer size corresponding to the total number of data link packets that can be stored in the replay buffer at one time; The fill level corresponds to the current number of data link packets stored in the replay buffer for pending selective replay requests; and The adaptive threshold corresponds to the maximum fill level that is smaller than the size of the buffer in the replay buffer memory.

14. The computer-implemented method according to claim 13, further comprising: It is determined that the flow control mode is active, wherein the peripheral interface protocol supports the flow control mode that can be configured to change the memory size and format of the data link packets; The fill level of the replay buffer memory is determined based on the memory size and format of the data link packets in the flow control mode; as well as The adaptive threshold is dynamically determined based on the flow control mode.

15. The computer-implemented method of claim 11, further comprising each detection in response to an erroneous data link packet: The adaptive threshold is recalculated based on the current set of link operation parameters to dynamically determine the adaptive threshold for the erroneous data link packet.

16. The computer-implemented method of claim 11, further comprising: The set of link operation parameters is processed by a statistical model, which includes the set of link operation parameters and corresponding weighting factors. The weighting factors are configured to balance the probability of successfully recovering the erroneous data link packet and the data link layer latency.

17. The computer-implemented method of claim 11, wherein the set of link operation parameters includes at least one link connection parameter selected from: Current link speed; Number of channels; and The bit error rate of the current link speed and number of channels.

18. The computer-implemented method of claim 11, wherein the set of link operation parameters includes at least one link workload parameter selected from: Current data link packet workload; Historical workload of the host system; and Predict workload.

19. The computer-implemented method according to claim 11, wherein: The peripheral interface protocol supports a skip ordered set mode, which is configured to periodically resynchronize the data link layer by introducing idle time between fixed periods of transaction layer packet processing. The link set of operation parameters includes a fixed-period counter for processing the transaction layer packets; and In response to the skip ordered set mode, dynamically determining the adaptive threshold includes compensating for the predicted idle time based on the counter.

20. A peripheral interface circuit, the peripheral interface circuit comprising: A data link layer configured to receive data link packets from a host system; A replay buffer is configured to store received data link packets after erroneous packets to support selective replay mode; A means for determining errors in data link packets received from the host system; A device for dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operation parameters; A means for selecting a playback mode based on a comparison of the fill level of the playback buffer memory with the adaptive threshold, wherein the playback mode is selected from: Selective replay mode, which is used to request the retransmission of only erroneous data link packets; and Sequential replay mode, which is used to request the retransmission of the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet; and A means for transmitting a replay request to the host system based on a selected replay mode.

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