Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The manufacturing method of the semiconductor device comprises the following steps: manufacturing a first electrode on one side of a substrate; manufacturing a second electrode; the second electrode is insulated from the first electrode; manufacturing a semiconductor layer by adopting a deposition process based on a first oxidation source, and manufacturing a gate insulating layer and a gate to obtain a transistor; the semiconductor layer is electrically connected with the first electrode and the second electrode, and the gate insulating layer is located between the semiconductor layer and the gate; at least one parameter value of the concentration, the pulse time and the power of the first oxidation source is smaller than a corresponding parameter value of a conventional deposition process. According to the invention, the contact resistance between the first electrode and the semiconductor layer and between the second electrode and the semiconductor layer is reduced, and the on-state current and other performances of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development and progress of semiconductor technology, semiconductor devices are constantly evolving towards lower energy consumption, while also facing problems and challenges from performance and process aspects. Summary of the Invention

[0003] This application proposes a semiconductor device and its manufacturing method, as well as an electronic device, to solve the technical problem of high source-drain contact resistance in related technologies.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: A first electrode is fabricated on one side of the substrate; Fabricate a second electrode; the second electrode is insulated from the first electrode; A semiconductor layer is fabricated using a deposition process based on a first oxide source, and a gate insulating layer and a gate are fabricated to obtain a transistor; the semiconductor layer is electrically connected to a first electrode and a second electrode, respectively, and the gate insulating layer is located between the semiconductor layer and the gate; at least one of the following parameters of the first oxide source—concentration, pulse time, and power—is less than the corresponding parameter value of a conventional deposition process.

[0005] In some optional embodiments of this application, a deposition process based on a second oxide source is used to fabricate the gate insulating layer and / or the gate; Among them, at least one of the parameters of the second oxidation source concentration, pulse time, and power is greater than the corresponding parameter value of the conventional deposition process.

[0006] In some optional embodiments of this application, before forming the first electrode on one side of the substrate, the method further includes: forming a first insulating layer on one side of the substrate; In addition, a first electrode is fabricated on one side of the substrate, including: fabricating a first electrode that covers a portion of the first insulating layer; In addition, after the first electrode is fabricated on one side of the substrate and before the second electrode is fabricated, the method further includes: fabricating a second insulating layer covering the first electrode and the first insulating layer; And, fabricating the second electrode includes: fabricating a second electrode covering a portion of the second insulating layer; the orthographic projections of the second electrode and the first electrode on the substrate at least partially intersect; And, after fabricating the second electrode and before fabricating the semiconductor layer using a deposition process based on the first oxide source, the process further includes: Fabricate a third insulating layer that covers the second electrode and the second insulating layer; A first through-hole is formed, penetrating the third insulating layer, the second electrode, and the second insulating layer, and extending to the first electrode.

[0007] In some optional embodiments of this application, a semiconductor layer is fabricated using a deposition process based on a first oxide source, including: An initial semiconductor layer is deposited using ozone with a first concentration or a first pulse time, or oxygen plasma with a first power, as a first oxidation source, to obtain an initial semiconductor layer that conformally covers a first via and a third insulating layer; the first concentration or the first pulse time is 5% to 80% of the concentration or pulse time of ozone in a conventional deposition process, and the first power is 5% to 80% of the power of oxygen plasma in a conventional deposition process.

[0008] In some optional embodiments of this application, a gate insulating layer and a gate are fabricated using a deposition process based on a second oxide source to obtain a transistor, including: An initial gate insulating layer and an initial gate are sequentially deposited to form a conformal covering initial semiconductor layer and fill the first via; the initial gate insulating layer and / or the initial gate are deposited using ozone with a second concentration or a second pulse time, or oxygen plasma with a second power, as a second oxidation source, wherein the second concentration or the second pulse time is 100% to 300% of the concentration or pulse time of ozone in a conventional deposition process, and the second power is 100% to 300% of the power of oxygen plasma in a conventional deposition process; At least a portion of the initial semiconductor layer, at least a portion of the initial gate insulating layer, and at least a portion of the initial gate located on the side of the third insulating layer away from the substrate are removed to obtain the semiconductor layer, the gate insulating layer, and the gate.

[0009] In some optional embodiments of this application, before fabricating the first electrode on one side of the substrate, the method further includes: A first dielectric layer is fabricated on one side of the substrate; Fabricate a stacked structure covering a first dielectric layer; the stacked structure includes a first sacrificial layer and a second dielectric layer that are alternately distributed in sequence. Fabricate a first sacrificial pillar and a second sacrificial pillar that penetrate the stacked structure; the first sacrificial pillar and the second sacrificial pillar are distributed along a first direction parallel to the substrate; In addition, a first electrode is fabricated on one side of the substrate, including replacing a multilayer first sacrificial layer located on the side of the first sacrificial pillar away from the second sacrificial pillar with a plurality of first electrodes; In addition, the fabrication of the second electrode includes replacing the multilayer first sacrificial layer located around the second sacrificial pillar with a plurality of second electrodes.

[0010] In some optional embodiments of this application, fabricating a first sacrificial pillar and a second sacrificial pillar that penetrate the laminated structure includes: Multiple second through-holes and multiple third through-holes are formed, which penetrate the stacked structure and are distributed in an array; the multiple second through-holes and multiple third through-holes are alternately distributed in pairs along the first direction, and each is sequentially distributed along the second direction; the second direction is parallel to the substrate and intersects the first direction; The first sacrificial pillar and the second sacrificial pillar are respectively made in the second through hole and the third through hole; And, replacing the multilayer first sacrificial layer located on the side of the first sacrificial pillar away from the second sacrificial pillar with multiple first electrodes, including: A trench is formed that penetrates the stacked structure and extends along the second direction; the trench is located between two adjacent first sacrificial pillars; Through trenches, the multiple first sacrificial layers are etched laterally until the first sacrificial pillar is exposed, forming multiple first channels; the first channels extend along the second direction. Fabricate a first electrode that conformally covers the first channel; In addition, after fabricating the first electrode on one side of the substrate, the process also includes: A first conductive layer is fabricated to cover the first electrode and fill the first channel.

[0011] In some optional embodiments of this application, the multilayer first sacrificial layer located around the second sacrificial pillar is replaced with a plurality of second electrodes, including: Remove the second sacrificial pillar; Through the third through-hole, the multi-layer first sacrificial layer is etched laterally until the first sacrificial pillar is exposed, forming a multi-layer second channel; the second channel is annular. Fabricate a second electrode that conformally covers the second channel; In addition, after fabricating the second electrode, the following also includes: A second conductive layer is fabricated to cover the second electrode in a conformal shape and fill the second channel.

[0012] In some optional embodiments of this application, after replacing the multilayer first sacrificial layer located around the second sacrificial pillar with a plurality of second electrodes, and before fabricating the semiconductor layer using a deposition process based on the first oxide source, and fabricating the gate insulating layer and the gate to obtain the transistor, the method further includes: Remove the first sacrificial pillar; Through the second via, the multilayer second dielectric layer and the first dielectric layer are etched laterally to expose at least part of the bottom wall and at least part of the top wall of each first electrode and each second electrode, forming a multilayer third channel; the third channel is annular. Create a second sacrificial layer within the third passage.

[0013] In some optional embodiments of this application, a semiconductor layer is fabricated using a deposition process based on a first oxide source, and a gate insulating layer and a gate are fabricated to obtain a transistor, including: An initial semiconductor layer is deposited using ozone with a first concentration or a first pulse duration, or oxygen plasma with a first power, as a first oxidation source, to obtain a conformal covering of a second via and a stacked structure; wherein the first concentration or the first pulse duration is 5% to 80% of the concentration or pulse duration of ozone in a conventional deposition process, and the first power is 5% to 80% of the power of oxygen plasma in a conventional deposition process; An initial gate insulating layer and an initial conductive structure are sequentially deposited to form a conformal covering initial semiconductor layer and fill the second via. The initial gate insulating layer and / or the initial conductive structure are deposited using ozone with a second concentration or a second pulse time, or oxygen plasma with a second power, as a second oxidation source. The second concentration or the second pulse time is 100% to 300% of the concentration or pulse time of ozone in a conventional deposition process, and the second power is 100% to 300% of the power of oxygen plasma in a conventional deposition process. The initial conductive structure, initial gate insulating layer, and initial semiconductor layer located on the side of the stacked structure away from the substrate are removed to obtain a conductive pillar and a gate insulating layer and semiconductor layer surrounding the conductive pillar; the semiconductor layer includes multiple channels electrically connected to multiple first electrodes and multiple second electrodes respectively, and the conductive pillar includes multiple gates corresponding to the multiple channels one by one.

[0014] Secondly, embodiments of this application provide a semiconductor device, including a transistor; Transistors include: The first electrode is disposed on one side of the substrate; The second electrode is insulated from the first electrode; The semiconductor layer is electrically connected to the first electrode and the second electrode, respectively. A gate insulating layer and a gate, wherein the gate insulating layer is disposed between the semiconductor layer and the gate; The semiconductor layer is fabricated using a deposition process based on a first oxide source; The on-state current of a transistor is more than twice that of a transistor fabricated using a conventional deposition process.

[0015] In some optional embodiments of this application, at least one of the following parameters—concentration of the first oxidation source, pulse time, and power—is less than the corresponding parameter values ​​of conventional deposition processes.

[0016] In some optional embodiments of this application, the semiconductor device includes at least one of the following: The gate insulating layer and / or the gate are fabricated using a deposition process based on a second oxide source; at least one of the following parameters of the second oxide source—concentration, pulse time, and power—is greater than the corresponding parameter value of a conventional deposition process. The semiconductor layer extends along a direction perpendicular to the substrate and is disposed around the periphery of the gate. The semiconductor device includes a multilayer memory cell array, multiple first conductive layers, and multiple conductive pillars. Each memory cell array includes multiple memory cells distributed in an array. Each memory cell includes a transistor. The transistors of the multiple memory cells distributed sequentially along a second direction in each memory cell array share a first conductive layer. The transistors of the multilayer memory cells distributed sequentially along a direction perpendicular to the substrate in the multilayer memory cell array share a conductive pillar.

[0017] Thirdly, embodiments of this application provide an electronic device, including: A semiconductor device manufactured using the semiconductor device manufacturing method described above; or, Semiconductor devices as described above.

[0018] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, a first electrode is first fabricated on one side of the substrate; then a second electrode insulated from the first electrode is fabricated; subsequently, a semiconductor layer, a gate insulating layer, and a gate are fabricated to obtain a transistor. The semiconductor layer is fabricated using a deposition process with a first oxide source whose concentration, pulse time, and power are all lower than the corresponding parameters of the oxide source in conventional deposition processes. The semiconductor layer is electrically connected to both the first and second electrodes. Compared to the oxide source in conventional deposition processes, the first oxide source has a lower oxidation effect and degree on both the first and second electrodes. The interface layers formed between the first electrode and the semiconductor layer, and between the second electrode and the semiconductor layer, are thinner, thereby reducing the contact resistance between the first electrode and the semiconductor layer, and between the second electrode and the semiconductor layer, thus improving the on-state current and other performance characteristics of the device.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 2 The gate voltage of the transistor (V) GS ) and drain current (I D The current-voltage characteristic curve of ) Figures 3 to 10 This is a schematic diagram of the structure of a specific example of a semiconductor device manufacturing method provided in this application at different processes; Figures 11 to 35 This is a schematic diagram of the structure of another specific example of a semiconductor device manufacturing method provided in the embodiments of this application during different processes.

[0021] Figure label: 10-Substrate; 20 - Transistor; 21 - First electrode; 211 - First initial electrode layer; 22 - Second electrode; 221 - Second initial electrode layer; 23 - Semiconductor layer; 231 - Initial semiconductor layer; 232 - Channel; 24 - Gate insulating layer; 241 - Initial gate insulating layer; 25 - Gate; 251 - Initial gate; 26 - First through hole; 31 - First insulating layer; 32 - Second insulating layer; 33 - Third insulating layer; 34 - Fourth insulating layer; 41-First interconnect structure; 411-Interconnection section; 412-Electrode section; 42-Second interconnect structure; 43-Third interconnect structure; 51 - First dielectric layer; 50 - Layered structure; 52 - First sacrificial layer; 53 - Second dielectric layer; 54 - Second Sacrificial Layer; 61 - First sacrificial pillar; 62 - Second sacrificial pillar; 63 - Second through hole; 64 - Third through hole; 71-Trench; 72-First channel; 73-Second channel; 74-Third channel; 81-First conductive layer; 811-First initial conductive layer; 82-Second conductive layer; 821-Second initial conductive layer; 83-Initial conductive structure; 84-Conductive pillar; 91 - First isolation structure; 92 - Second isolation structure. Detailed Implementation

[0022] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0023] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, and / or components, but does not exclude implementation as other features, information, data, steps, operations, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] In related technologies, ozone (O3) or oxygen plasma (O-plasma) are commonly used oxidation sources in the process of growing metal oxide semiconductor channel materials by ALD (Atomic Layer Deposition). Both are strong oxidants, and they usually also produce a certain degree of oxidation on the deposited substrate during the growth of the target material.

[0026] For device structures where source and drain electrodes are preferentially deposited, during the growth of channel materials, O3 or O-plasma oxide sources may cause oxidation of the surface materials of the source and drain electrodes, resulting in an increase in the source and drain contact resistance and a decrease in the on-state current, thereby limiting the improvement of device performance.

[0027] This application addresses the problem that O3 or O-plasma oxide sources may cause oxidation of source and drain electrode materials in semiconductor device structures where source and drain electrodes are preferentially deposited, during the subsequent growth of channel materials via ALD process. It provides semiconductor devices, their manufacturing methods, and electronic devices, aiming to solve the aforementioned technical problems in related technologies.

[0028] This application embodiment can effectively regulate the oxidation effect of the deposition process on the substrate by adjusting the concentration or pulse time of O3 or the power of O-plasma during the deposition growth process. This can reduce the oxidation degree of the source and drain electrodes during the channel material deposition growth process, reduce the source and drain contact resistance, and at the same time ensure sufficient oxygen content in the channel layer film and prevent degradation of properties such as sheet resistance of the channel layer film, thereby improving the on-state current and other performance of the device.

[0029] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0030] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the structural schematic diagrams of the semiconductor device manufacturing method at different processes are as follows: Figures 3 to 10 as well as Figures 11 to 35 As shown, the method for manufacturing this semiconductor device includes: S101. A first electrode 21 is fabricated on one side of the substrate 10.

[0031] S102, Fabricate the second electrode 22; the second electrode 22 is insulated from the first electrode 21.

[0032] S103. A semiconductor layer 23 is fabricated using a deposition process based on a first oxide source, and a gate insulating layer 24 and a gate 25 are fabricated to obtain a transistor 20. The semiconductor layer 23 is electrically connected to the first electrode 21 and the second electrode 22, respectively, and the gate insulating layer 24 is located between the semiconductor layer 23 and the gate 25. At least one of the following parameters of the first oxide source—concentration, pulse time, and power—is less than the corresponding parameter value of a conventional deposition process.

[0033] In this embodiment, substrate 10 is used to carry transistor 20.

[0034] In this embodiment, a first electrode 21 is first fabricated on one side of the substrate 10; then a second electrode 22, which is insulated from the first electrode 21, is fabricated; subsequently, a semiconductor layer 23, a gate insulating layer 24, and a gate 25 are fabricated to obtain a transistor 20. The semiconductor layer 23 is fabricated using a deposition process with a first oxide source, where at least one parameter value (concentration, pulse time, or power) is less than the corresponding parameter value of the oxide source in a conventional deposition process. The semiconductor layer 23 is electrically connected to the first electrode 21 and the second electrode 22, respectively. Compared to the oxide source in a conventional deposition process, the first oxide source has a lower oxidation effect and degree on the first electrode 21 and the second electrode 22. The thickness of the interface layer formed between the first electrode 21 and the semiconductor layer 23, and between the second electrode 22 and the semiconductor layer 23, is thinner. This reduces the contact resistance between the first electrode 21 and the semiconductor layer 23, and between the second electrode 22 and the semiconductor layer 23, thereby improving the on-state current and other performance of the device.

[0035] It should be noted that, in the embodiments of this application, the first electrode 21 is one of the source and drain of the transistor 20, and the second electrode 22 is the other of the source and drain of the transistor 20.

[0036] The semiconductor device manufacturing method provided in this application embodiment can reduce the oxidation effect and degree of the growth process on the source and drain electrode materials and reduce the interface layer thickness between the source and drain electrode materials and the semiconductor layer materials without increasing the process complexity or photomask. This can achieve the effect of reducing the source and drain contact resistance of the device and improving the on-state current and other performance of the device.

[0037] It should be noted that, in the embodiments of this application, the oxidation source for the conventional deposition process refers to the conventional oxidation source used in existing production. The concentration, pulse time, and power parameters of the conventional oxidation source are the commonly used concentration, pulse time, and power parameters of the oxidation source used in existing production.

[0038] Optionally, in this embodiment, the deposition process based on the first oxidation source employs atomic layer deposition (ALD). Of course, in other optional embodiments, processes such as chemical vapor deposition (CVD), direct oxidation deposition (LANXIDE), and chemical solution deposition (CSD) can also be used as needed.

[0039] In the embodiments of this application, Figure 2 The transistor's gate voltage (V) is shown. GS ) and drain current (I D The current-voltage characteristic curve of V GS I represents the gate voltage of a transistor. D The base line represents the drain current of the transistor, and the base line represents the gate voltage (V) of the transistor fabricated using conventional deposition processes to create the semiconductor layer. GS ) and drain current (I D The current-voltage characteristic curve of the transistor is used as the baseline; the model line represents the gate voltage (V) of the transistor fabricated using the deposition process of the first oxide source to create the semiconductor layer. GS ) and drain current (I D The current-voltage characteristic curve of ).

[0040] like Figure 2 As shown, the transistor device fabricated by forming a semiconductor layer based on a deposition process using a first oxide source has an on-state current that is more than 1 times that of a transistor device fabricated by forming a semiconductor layer based on a conventional deposition process.

[0041] The source-drain electrode resistivity of the transistor fabricated using the deposition process based on the first oxide source is more than 30% of that of the transistor fabricated using the conventional deposition process; the carrier concentration of the semiconductor layer fabricated using the deposition process based on the first oxide source is more than 5 times that of the semiconductor layer fabricated using the conventional deposition process.

[0042] In some optional embodiments of this application, the gate insulating layer 24 and / or the gate 25 are fabricated using a deposition process based on a second oxide source; wherein at least one of the parameters of the concentration, pulse time, and power of the second oxide source is greater than the corresponding parameter values ​​of a conventional deposition process.

[0043] In this embodiment, the semiconductor layer 23 is fabricated using a deposition process with a first oxide source whose concentration, pulse time, and power are all lower than the corresponding parameters of the oxide source in a conventional deposition process. At least one of the gate insulating layer 24 and the gate 25 is fabricated using a deposition process with a second oxide source whose concentration, pulse time, and power are all higher than the corresponding parameters of the oxide source in a conventional deposition process. Compared to the oxide source in a conventional deposition process, the second oxide source enhances the oxidation effect on the semiconductor layer 23, thereby ensuring sufficient oxygen content in the semiconductor layer 23 and preventing degradation of properties such as sheet resistance of the semiconductor layer 23, thus improving the on-state current and other performance of the device.

[0044] Optionally, the semiconductor device manufacturing method provided in this application embodiment can be used to fabricate horizontal channel transistors and multilayer stacked semiconductor devices, vertical channel transistors and multilayer stacked semiconductor devices, etc. The following description uses a vertical channel transistor as an example.

[0045] Optionally, the vertical channel transistor can be used in 2T (Transistor) 0C (Capacitor) memory cells or 1T1C memory cells. The vertical channel transistor can be a horizontal source-drain vertical channel transistor, and can also be applied to multi-layer stacked semiconductor devices, such as DRAM (Dynamic Random Access Memory) devices.

[0046] In some optional embodiments of this application, such as Figure 3 As shown, before fabricating the first electrode 21 on one side of the substrate 10, the method further includes: fabricating a first insulating layer 31 on one side of the substrate 10. The first insulating layer 31 is located on one side of the substrate 10 and can separate the substrate 10 from the subsequently fabricated conductive components (such as the first electrode 21), thereby achieving electrical isolation between the substrate 10 and the subsequently fabricated conductive components and preventing leakage.

[0047] Optionally, the material of the first insulating layer 31 includes an insulating dielectric. The insulating dielectric is grown on the substrate 10 to form the first insulating layer 31.

[0048] In some optional embodiments of this application, such as Figure 3 As shown, a first electrode 21 is fabricated on one side of the substrate 10, including: fabricating a first electrode 21 that covers a portion of the first insulating layer 31.

[0049] Optionally, the material of the first electrode 21 includes a conductive material, which includes, but is not limited to, one or more combinations of TiN (titanium nitride), W (tungsten), Mo (molybdenum), Ni (nickel), TiAl (titanium aluminum alloy), and ITO (indium tin oxide).

[0050] Optionally, in this embodiment, the first electrode 21 serves as the drain electrode (or drain).

[0051] In some optional embodiments of this application, such as Figure 4 As shown, after fabricating the first electrode 21 on one side of the substrate 10 and before fabricating the second electrode 22, the process further includes fabricating a second insulating layer 32 that covers the first electrode 21 and the first insulating layer 31. The second insulating layer 32 covers the first electrode 21, which can separate the first electrode 21 from the subsequently fabricated conductive components (such as the second electrode 22), thereby achieving electrical isolation between the first electrode 21 and the subsequently fabricated conductive components and preventing leakage.

[0052] Optionally, the material of the second insulating layer 32 includes an insulating dielectric. The insulating dielectric is grown on the side of the first electrode 21 away from the substrate 10 and planarized to form the second insulating layer 32.

[0053] Optionally, planarization can be achieved using a CMP (Chemical Mechanical Polishing) process.

[0054] In some optional embodiments of this application, such as Figure 5 As shown, fabricating the second electrode 22 includes: fabricating a second electrode 22 covering a portion of the second insulating layer 32; the orthographic projections of the second electrode 22 and the first electrode 21 on the substrate 10 at least partially intersect.

[0055] Optionally, the material of the second electrode 22 includes a conductive material, which includes, but is not limited to, one or more combinations of TiN, W, Mo, Ni, TiAl, ITO, etc.

[0056] Optionally, in this embodiment, the second electrode 22 serves as the source electrode (or source pole).

[0057] In some optional embodiments of this application, such as Figure 6 and Figure 7 As shown, after fabricating the second electrode 22 and before fabricating the semiconductor layer 23 using a deposition process based on the first oxide source, the process further includes: like Figure 6 As shown, a third insulating layer 33 is fabricated to cover the second electrode 22 and the second insulating layer 32. The third insulating layer 33 covers the second electrode 22, which can separate the second electrode 22 from the conductive components (such as the gate 25) that are subsequently fabricated, thereby achieving electrical isolation between the second electrode 22 and the conductive components that are subsequently fabricated and preventing leakage.

[0058] Optionally, the material of the third insulating layer 33 includes an insulating dielectric. The insulating dielectric is grown on the side of the second electrode 22 away from the substrate 10 and planarized to form the third insulating layer 33.

[0059] Next, as Figure 7 As shown, a first through-hole 26 is formed, penetrating the third insulating layer 33, the second electrode 22, and the second insulating layer 32, and extending to the first electrode 21. The inner wall of the first through-hole 26 exposes the second electrode 22 and the first electrode 21, facilitating the subsequent fabrication of a semiconductor layer 23 that is electrically connected to the second electrode 22 and the first electrode 21, respectively.

[0060] Optionally, in this embodiment of the application, a first through hole 26 can be formed by photolithography and etching processes. The first through hole 26 passes through the third insulating layer 33, the second electrode 22 and the second insulating layer 32, and stops on the first electrode 21.

[0061] Optionally, such as Figure 7 As shown in the embodiment of this application, the first through hole 26 does not penetrate the first electrode 21. The side of the first through hole 26 exposes the third insulating layer 33, the second electrode 22, the second insulating layer 32 and the first electrode 21, and the bottom of the first through hole 26 exposes the first electrode 21.

[0062] Of course, in some alternative embodiments of this application, the first through hole 26 may penetrate the first electrode 21 as needed. The side of the first through hole 26 exposes the third insulating layer 33, the second electrode 22, the second insulating layer 32 and the first electrode 21, and the bottom exposes the first insulating layer 31.

[0063] In some optional embodiments of this application, such as Figure 8 and Figure 9 As shown, a semiconductor layer 23 is fabricated using a deposition process based on a first oxide source, and a gate insulating layer 24 and a gate 25 are fabricated to obtain a transistor 20, comprising: like Figure 8 As shown, an initial semiconductor layer 231 is deposited using ozone with a first concentration or a first pulse time, or oxygen plasma with a first power, as the first oxidation source, to obtain an initial semiconductor layer 231 that conformally covers the first via 26 and the third insulating layer 33; the first concentration or the first pulse time is 5% to 80% of the concentration or pulse time of ozone in a conventional deposition process, and the first power is 5% to 80% of the power of oxygen plasma in a conventional deposition process.

[0064] In this embodiment, the initial semiconductor layer 231 is conformally covered by the first through hole 26 and the third insulating layer 33. The initial semiconductor layer 231 is electrically connected to the second electrode 22 and the first electrode 21 exposed on the inner wall of the first through hole 26, respectively.

[0065] In this embodiment of the application, during the deposition of the initial semiconductor layer 231, ozone with a first concentration of 5% to 80% (proportion) of the ozone concentration of the conventional deposition process or a first pulse time of 5% to 80% (proportion) of the ozone pulse time of the conventional deposition process is used as the first oxidation source, or oxygen plasma with a first power of 5% to 80% (proportion) of the oxygen plasma power of the conventional deposition process is used as the first oxidation source to grow the semiconductor layer material. This can reduce the oxidation effect and degree of the first oxidation source on the source and drain electrode materials, thereby reducing the source and drain contact resistance and improving the on-state current and other performance of the device.

[0066] Optionally, the semiconductor layer material includes, but is not limited to, metal oxide materials. The metal oxide material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of transistor 20 is relatively small (leakage current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO (indium tungsten oxide), ZnOx, InOx (indium oxide), In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the transistor leakage current meets the requirements. Specific adjustments can be made according to the actual situation.

[0067] Optionally, in this embodiment, the semiconductor layer material includes one or more combinations of common oxide semiconductor materials such as IGZO, ITO, IWO, and InO. Optionally, in this embodiment, the semiconductor layer material is grown using ALD growth.

[0068] Next, as Figure 8As shown, an initial gate insulating layer 241 and an initial gate 251, which conformally cover the initial semiconductor layer 231 and fill the first via 26, are sequentially deposited. The initial gate insulating layer 241 and / or the initial gate 251 are deposited using ozone with a second concentration or a second pulse time, or oxygen plasma with a second power, as the second oxidation source. The second concentration or the second pulse time is 100% to 300% of the concentration or pulse time of ozone in a conventional deposition process, and the second power is 100% to 300% of the power of oxygen plasma in a conventional deposition process.

[0069] In this embodiment, the initial gate insulating layer 241 conformally covers the initial semiconductor layer 231, and the initial gate 251 conformally covers the initial gate insulating layer 241 and fills the first via 26. The initial gate insulating layer 241 is located between the initial semiconductor layer 231 and the initial gate 251 and electrically isolates them.

[0070] In this embodiment, during the deposition of at least one of the initial gate insulating layer 241 and the initial gate 251, ozone with a second concentration of 100% to 300% (proportion) of the ozone concentration in the conventional deposition process or a second pulse time of 100% to 300% (proportion) of the ozone pulse time in the conventional deposition process is used as the second oxidation source, or oxygen plasma with a second power of 100% to 300% (proportion) of the oxygen plasma power in the conventional deposition process is used as the second oxidation source to grow at least one of the initial gate insulating layer 241 and the initial gate 251. This can enhance the oxidation effect of the second oxidation source on the semiconductor layer material, thereby ensuring sufficient oxygen content in the initial semiconductor layer 231 film and preventing degradation of properties such as sheet resistance of the initial semiconductor layer 231 film, and improving the on-state current and other performance of the device.

[0071] Optionally, the material of the initial gate insulating layer 241 includes, but is not limited to, high-k (dielectric constant) materials such as HfO2 (hafnium oxide), Al2O3 (aluminum oxide), HfAlO (hafnium aluminum oxide), and HfLaO (hafnium lanthanum oxide), where the dielectric constant of the high-k materials is greater than that of SiO (3.9). Optionally, the initial gate insulating layer 241 is grown by ALD (Alternating Current Deposition).

[0072] Optionally, the material of the initial gate 251 includes, but is not limited to, conductive materials such as IZO (indium zinc oxide), ITO, TiN, and W. Optionally, the initial gate 251 is grown by ALD growth.

[0073] Next, as Figure 9As shown, at least a portion of the initial semiconductor layer 231, at least a portion of the initial gate insulating layer 241, and at least a portion of the initial gate 251 located on the side of the third insulating layer 33 away from the substrate 10 are removed to obtain the semiconductor layer 23, the gate insulating layer 24, and the gate 25.

[0074] In this embodiment, the remaining unremoved initial semiconductor layer 231, initial gate insulating layer 241, and initial gate 251 serve as semiconductor layer 23, gate insulating layer 24, and gate 25, respectively, and the first electrode 21, second electrode 22, semiconductor layer 23, gate insulating layer 24, and gate 25 form transistor 20.

[0075] Optionally, in this embodiment of the application, a semiconductor layer material, a gate dielectric material, and a gate material are sequentially grown according to the above deposition method to obtain an initial semiconductor layer 231, an initial gate insulating layer 241, and an initial gate 251; then, a gate pattern is formed by photolithography and etching processes to obtain a semiconductor layer 23, a gate insulating layer 24, and a gate 25, thereby forming a vertical channel metal-oxide-semiconductor transistor device.

[0076] In this embodiment, the semiconductor layer material uses low-concentration or unsaturated pulse time or subsaturated pulse time O3, or low-power O-plasma as a weak oxidation source (as the first oxidation source) for ALD growth. This can reduce the oxidation effect and degree of the first oxidation source on the source and drain electrode materials, thereby reducing the source and drain contact resistance. At the same time, at least one of the gate insulating material and the gate electrode material can use high-concentration or oversaturated pulse time O3, or high-power O-plasma as an excessive strong oxidation source (as the second oxidation source) for ALD growth. This can enhance the oxidation effect of the second oxidation source on the semiconductor layer material, thereby ensuring sufficient oxygen content in the semiconductor layer film and preventing degradation of properties such as sheet resistance of the semiconductor layer film, thereby improving the on-state current and other performance of the device.

[0077] In some optional embodiments of this application, such as Figure 10 As shown, after the gate insulating layer 24 and the gate 25 are fabricated sequentially, the process further includes: like Figure 10 As shown, a fourth insulating layer 34 is fabricated covering the third insulating layer 33, the semiconductor layer 23, the gate insulating layer 24, and the gate 25. The fourth insulating layer 34 covers the gate 25, which can isolate the gate 25 from the subsequently fabricated conductive components (such as the first interconnect structure 41 and the third interconnect structure 43), thereby achieving electrical isolation between the gate 25 and the subsequently fabricated conductive components and preventing leakage.

[0078] Optionally, the material of the fourth insulating layer 34 includes an insulating dielectric. The insulating dielectric is grown on the side of the gate 25 away from the substrate 10 to form the fourth insulating layer 34.

[0079] Next, as Figure 10 As shown, a first interconnect structure 41 is fabricated that penetrates the fourth insulating layer 34, the third insulating layer 33, and the second insulating layer 32, and is electrically connected to the first electrode 21.

[0080] Optionally, fabricating the first interconnect structure 41 includes: fabricating a first via through the fourth insulating layer 34, the third insulating layer 33, and the second insulating layer 32, with the bottom of the first via exposing the first electrode 21; then, fabricating the first interconnect structure 41 within the first via, with one end of the first interconnect structure 41 electrically connected to the first electrode 21 and the other end used for electrical connection to other conductive components (such as capacitors, bit lines, or another transistor).

[0081] Optionally, such as Figure 10 As shown, the first interconnection structure 41 includes an interconnection portion 411 and an electrode portion 412. One end of the interconnection portion 411 is electrically connected to the first electrode 21, and the other end of the interconnection portion 411 is electrically connected to the electrode portion 412. The electrode portion 412 is used for electrical connection with other conductive components.

[0082] Next, as Figure 10 As shown, a second interconnect structure 42 is fabricated that penetrates the fourth insulating layer 34 and is electrically connected to the gate 25. One end of the second interconnect structure 42 is electrically connected to the gate 25, and the other end is used for electrical connection to other conductive components (such as word lines).

[0083] Next, as Figure 10 As shown, a third interconnect structure 43 is fabricated that penetrates the fourth insulating layer 34 and the third insulating layer 33 and is electrically connected to the second electrode 22. One end of the third interconnect structure 43 is electrically connected to the second electrode 22, and the other end is used for electrical connection to other conductive components (such as capacitors, bit lines, or another transistor).

[0084] It should be noted that in the embodiments of this application, the manufacturing methods and structures of the second interconnect structure 42 and the third interconnect structure 43 are similar to those of the first interconnect structure 41, and will not be described again here.

[0085] Optionally, in this embodiment of the application, an interconnection process is used to form metal leads to obtain a first interconnection structure 41, a second interconnection structure 42, and a third interconnection structure 43.

[0086] In other alternative embodiments of this application, such as Figure 11 As shown, before fabricating the first electrode 21 on one side of the substrate 10, the method further includes fabricating a first dielectric layer 51 on one side of the substrate 10. The first dielectric layer 51 is used to electrically isolate the substrate 10 from subsequently fabricated conductive components (such as transistor 20, first conductive layer 81, and second conductive layer 82) to prevent leakage.

[0087] Optionally, the material of the first dielectric layer 51 includes an insulating medium, which includes, but is not limited to, oxides such as silicon oxide (SiO). The first dielectric layer 51 can be obtained by depositing SiO using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.

[0088] Next, as Figure 11 As shown, a stacked structure 50 covering the first dielectric layer 51 is fabricated; the stacked structure 50 includes a first sacrificial layer 52 and a second dielectric layer 53 that are alternately distributed in sequence.

[0089] Optionally, a first sacrificial layer 52 and a second dielectric layer 53 are sequentially and alternately fabricated on the side of the first dielectric layer 51 away from the substrate 10 to obtain a stacked structure 50.

[0090] Optionally, the material of the first sacrificial layer 52 includes an insulating medium, which includes, but is not limited to, nitrides, such as silicon nitride (Si3N4). Si3N4 can be deposited using PECVD or LPCVD (Low Pressure Chemical Vapor Deposition) processes to obtain the first sacrificial layer 52.

[0091] Optionally, the material and manufacturing process of the second dielectric layer 53 may be the same as or similar to those of the first dielectric layer 51, and will not be described in detail here.

[0092] Next, as Figures 12 to 14 As shown, a first sacrificial pillar 61 and a second sacrificial pillar 62 are fabricated through the stacked structure 50; the first sacrificial pillar 61 and the second sacrificial pillar 62 are distributed along a first direction parallel to the substrate 10.

[0093] In this embodiment, the first sacrificial post 61 defines the location of the transistor to be formed, the second sacrificial post 62 defines the location of the effective device to be formed, and the first sacrificial post 61 and the second sacrificial post 62 define the location and region of the memory cell to be formed. Optionally, the effective device can be a capacitor, in which case the memory cell includes a transistor 20 and a capacitor, forming a 1T1C structure; the effective device can also be another transistor, in which case the memory cell includes two transistors, forming a 2T0C structure.

[0094] In some optional embodiments of this application, such as Figures 12 to 14 As shown, the fabrication of the first sacrificial pillar 61 and the second sacrificial pillar 62 penetrating the laminated structure 50 includes: like Figure 12 and Figure 13 As shown (where Figure 13 for Figure 12(Cross-sectional view in the middle aa direction) forms a plurality of second through holes 63 and a plurality of third through holes 64 that respectively penetrate the stacked structure 50 and are arranged in an array; the plurality of second through holes 63 and the plurality of third through holes 64 are alternately distributed in pairs along the first direction, and each is sequentially distributed along the second direction; the second direction is parallel to the substrate 10 and intersects with the first direction.

[0095] In this embodiment, the second through-hole 63 and the third through-hole 64 can be formed by a patterning process. A plurality of second through-holes 63 are arrayed along a first direction and a second direction, each penetrating the stacked structure 50 and exposing the first dielectric layer 51 at their bottom; a plurality of third through-holes 64 are arrayed along the first direction and a second direction, each penetrating the stacked structure 50 and exposing the first dielectric layer 51 at their bottom. The plurality of second through-holes 63 and the plurality of third through-holes 64 are alternately distributed in pairs along the first direction, and the plurality of second through-holes 63 are sequentially distributed along the second direction, and the plurality of third through-holes 64 are sequentially distributed along the second direction.

[0096] Optionally, the second direction is perpendicular to the first direction.

[0097] Next, as Figure 14 As shown, a first sacrificial post 61 and a second sacrificial post 62 are respectively made in the second through hole 63 and the third through hole 64.

[0098] In this embodiment of the application, the first sacrificial post 61 is filled with the second through hole 63, and the second sacrificial post 62 is filled with the third through hole 64.

[0099] Multiple first sacrificial pillars 61 are arrayed along a first direction and a second direction; multiple second sacrificial pillars 62 are arrayed along the first direction and the second direction. The multiple first sacrificial pillars 61 and the multiple second sacrificial pillars 62 are distributed alternately in pairs along the first direction, and the multiple first sacrificial pillars 61 are distributed sequentially along the second direction, and the multiple second sacrificial pillars 62 are distributed sequentially along the second direction.

[0100] Optionally, the material of the first sacrificial pillar 61 includes, but is not limited to, silicon, which may be polycrystalline silicon. The material of the second sacrificial pillar 62 includes, but is not limited to, silicon, which may be polycrystalline silicon.

[0101] In other alternative embodiments of this application, such as Figures 15 to 22 As shown, a first electrode 21 is fabricated on one side of the substrate 10, including replacing the multilayer first sacrificial layer 52 located on the side of the first sacrificial pillar 61 away from the second sacrificial pillar 62 with the multilayer first electrode 21.

[0102] In this embodiment, the multilayer first electrode 21 serves as the source or drain of the multilayer transistor 20 stacked sequentially along the direction perpendicular to the substrate 10.

[0103] In some optional embodiments of this application, such as Figures 15 to 22As shown, the multilayer first sacrificial layer 52 located on the side of the first sacrificial pillar 61 away from the second sacrificial pillar 62 is replaced with a plurality of first electrodes 21, including: like Figure 15 and Figure 16 As shown, a groove 71 is formed that penetrates the stacked structure 50 and extends along the second direction; the groove 71 is located between two adjacent first sacrificial pillars 61.

[0104] Optionally, in this embodiment, the laminated structure 50 is patterned to form a plurality of grooves 71. The plurality of grooves 71 are spaced apart along a first direction and each extends along a second direction.

[0105] Optionally, the stacked structure 50 is patterned to form multiple trenches 71, including: fabricating a mask structure on the side of the stacked structure 50 away from the substrate 10, the mask structure covering the stacked structure 50, multiple first sacrificial pillars 61, and multiple second sacrificial pillars 62, and patterning the mask structure to give it a preset pattern, using the preset pattern to define the shape and position of multiple trenches to be formed that are spaced apart along a first direction and each extends along a second direction; each trench 71 is located between two adjacent first sacrificial pillars 61 and on the side of the first sacrificial pillar 61 away from the second sacrificial pillar 62. Then, based on the mask structure with the preset pattern, the stacked structure 50 is etched to form multiple trenches 71, exposing the first dielectric layer 51 at the bottom.

[0106] Next, as Figure 17 and Figure 18 As shown (where Figure 18 for Figure 17 Middle Figure 15 (As shown in the cross-sectional view along the bb direction), the multilayer first sacrificial layer 52 is laterally etched through the trench 71 until the first sacrificial pillar 61 is exposed, forming a multilayer first channel 72; the first channel 72 extends along the second direction. The multilayer first channel 72 is distributed sequentially at intervals along the direction perpendicular to the substrate 10, and each extends along the second direction, and all multilayer first channels 72 are connected to the trench 71.

[0107] Next, as Figure 19 and Figure 21 As shown, a first electrode 21 is fabricated to conformally cover the first channel 72. The side of the first channel 72 exposes the first sacrificial pillar 61. The first electrode 21 conformally covers the first sacrificial pillar 61 exposed by the first channel 72, which facilitates the electrical connection between the first electrode 21 and the subsequently fabricated semiconductor layer 23.

[0108] In this embodiment, multiple first electrodes 21 are fabricated one-to-one within the multilayer first channel 72. The multilayer first electrodes 21 are spaced apart along a direction perpendicular to the substrate 10 and each extends along a second direction. Multiple transistors 20 sequentially distributed along the second direction in each memory cell share a single first electrode 21.

[0109] In other alternative embodiments of this application, such as Figure 20 and Figure 21 As shown, after fabricating the first electrode 21 on one side of the substrate 10, the process further includes: fabricating a first conductive layer 81 that conformally covers the first electrode 21 and fills the first channel 72. The first conductive layer 81 is electrically connected to the first electrode 21.

[0110] In this embodiment, multiple first conductive layers 81 are fabricated one-to-one within the multilayer first channel 72. The multiple first conductive layers 81 are spaced apart along a direction perpendicular to the substrate 10 and each extends along a second direction. Multiple transistors 20 arranged sequentially along the second direction in each memory cell share a single first conductive layer 81.

[0111] Optionally, in this embodiment, the material of the first electrode 21 includes a conductive material, which includes, but is not limited to, ITO. The conductive material can be deposited using an ALD process to fabricate the first electrode 21.

[0112] Optionally, in this embodiment, the material of the first conductive layer 81 includes, but is not limited to, metallic materials, such as TiN and W. Metallic materials can be deposited to fabricate the first conductive layer 81.

[0113] Optionally, such as Figures 19 to 21 As shown, in this embodiment of the application, fabricating the first electrode 21 and fabricating the first conductive layer 81 includes: like Figure 19 As shown, a conductive material is deposited to form a first initial electrode layer 211 that conformally covers multiple layers of first channels 72, trenches 71, stacked structures 50, multiple first sacrificial pillars 61 and multiple second sacrificial pillars 62.

[0114] Next, as Figure 20 As shown, a metallic material is deposited to form a conformal covering first initial electrode layer 211, and a first initial conductive layer 811 is filled with multiple first channels 72 and trenches 71.

[0115] Next, as Figure 21 As shown, the first initial electrode layer and the first initial conductive layer on the side of the stacked structure 50 away from the substrate 10 and in the trench 71 are removed, and the remaining first initial electrode layer and the first initial conductive layer in the multilayer first channel 72 are disconnected. The remaining first initial electrode layer and the first initial conductive layer in the multilayer first channel 72 are respectively used as the multilayer first electrode 21 and the multilayer first conductive layer 81.

[0116] Optionally, in this embodiment, the first electrode 21 serves as the drain of the transistor 20. The first conductive layer 81 serves as the bit line (BL).

[0117] Optionally, such as Figure 23 and Figure 24 As shown in the embodiment of this application, after fabricating the first conductive layer 81 and before fabricating the second electrode 22, the method further includes: fabricating a first isolation structure 91, wherein the first isolation structure 91 fills the trench 71. The material of the first isolation structure 91 includes polycrystalline silicon.

[0118] In other alternative embodiments of this application, such as Figures 23 to 28 As shown, the fabrication of the second electrode 22 includes replacing the multilayer first sacrificial layer 52 located around the second sacrificial pillar 62 with a plurality of second electrodes 22.

[0119] In this embodiment, the multilayer second electrode 22 serves as the drain or source of the multilayer transistor 20 stacked sequentially along the direction perpendicular to the substrate 10.

[0120] In other alternative embodiments of this application, such as Figures 23 to 28 As shown, the multi-layered first sacrificial layer 52 located around the second sacrificial pillar 62 is replaced with multiple second electrodes 22, including: like Figure 23 and Figure 24 As shown, the second sacrificial pillar 62 is removed. The second sacrificial pillar 62 fills the third through hole 64. After removing the second sacrificial pillar 62, the third through hole 64 is opened, exposing multiple layers of the first sacrificial layer 52 and multiple layers of the second dielectric layer 53 on the side, and exposing the first dielectric layer 51 at the bottom.

[0121] Optionally, the second sacrificial pillar 62 can be removed by an etching process to open up a storage region (such as the capacitor CAP region).

[0122] Next, as Figure 25 As shown, the multilayer first sacrificial layer 52 is etched laterally through the third via 64 until the first sacrificial pillar 61 is exposed, forming a multilayer second channel 73; the second channel 73 is annular. The multilayer second channels 73 are distributed sequentially at intervals along the direction perpendicular to the substrate 10, and each is annularly arranged around the third via 64, and all multilayer second channels 73 are connected to the third via 64.

[0123] Next, as Figure 26 and Figure 28As shown, a second electrode 22 is fabricated to conformally cover the second channel 73. The side of the second channel 73 exposes the first sacrificial pillar 61. The second electrode 22 conformally covers the first sacrificial pillar 61 exposed by the second channel 73, which facilitates the electrical connection between the second electrode 22 and the subsequently fabricated semiconductor layer 23.

[0124] In this embodiment, each third via 64 corresponds to a multilayer second channel 73, and a multilayer second electrode 22 is fabricated in each of the multilayer second channels 73. The multilayer second electrodes 22 are stacked along a direction perpendicular to the substrate 10, and adjacent layers of second electrodes 22 are electrically isolated through a second dielectric layer 53.

[0125] In other alternative embodiments of this application, such as Figure 27 and Figure 28 As shown, after fabricating the second electrode 22, the process further includes: fabricating a second conductive layer 82 that conforms to the shape of the second electrode 22 and fills the second channel 73. The second conductive layer 82 is electrically connected to the second electrode 22.

[0126] In this embodiment, multiple second conductive layers 82 are fabricated one-to-one within the multiple second channels 73. The multiple second conductive layers 82 are spaced apart along a direction perpendicular to the substrate 10, and each is arranged in a ring around the periphery of the third through hole 64.

[0127] Optionally, in this embodiment, the material of the second electrode 22 includes a conductive material, which includes, but is not limited to, ITO. The conductive material can be deposited using an ALD process to fabricate the second electrode 22.

[0128] Optionally, in this embodiment, the material of the second conductive layer 82 includes, but is not limited to, metallic materials, such as TiN and W. Metallic materials can be deposited to fabricate the second conductive layer 82.

[0129] Optionally, such as Figures 26 to 28 As shown, in this embodiment of the application, fabricating the second electrode 22 and the second conductive layer 82 includes: like Figure 26 As shown, a conductive material is deposited to form a second initial electrode layer 221 that conformally covers multiple layers of second channels 73, multiple third vias 64, a stacked structure 50, multiple first sacrificial pillars 61 and a first isolation structure 91.

[0130] Next, as Figure 27 As shown, a metallic material is deposited to form a conformal covering second initial electrode layer 221, and a second initial conductive layer 821 is filled with multiple second channels 73 and multiple third vias 64.

[0131] Next, as Figure 28As shown, the second initial electrode layer and the second initial conductive layer on the side of the stacked structure 50 away from the substrate 10 and in the plurality of third vias 64 are removed, and the second initial electrode layer and the second initial conductive layer remaining in the multilayer second channel 73 are disconnected. The second initial electrode layer and the second initial conductive layer remaining in the multilayer second channel 73 corresponding to each third via 64 are respectively used as the multilayer second electrode 22 and the multilayer second conductive layer 82.

[0132] Optionally, in this embodiment, the second electrode 22 serves as the source of the transistor 20. The second conductive layer 82 serves as a storage node (SN).

[0133] Optionally, such as Figure 29 and Figure 30 As shown in this embodiment, after fabricating the second conductive layer 82 and before removing the first sacrificial pillar 61, the method further includes: fabricating a second isolation structure 92, which fills the third via 64. The material of the second isolation structure 92 includes polycrystalline silicon.

[0134] Optionally, the second isolation structure 92 can be removed as needed, and a capacitor can be fabricated in the third through hole 64 (optionally, the structure and fabrication method of this capacitor can be the same as or similar to the structure and fabrication method of conventional capacitors in the art, and will not be described in detail here). The capacitor and the transistor 20 in this embodiment form a 1T1C structure memory cell, or another transistor can be fabricated in the third through hole 64 (the structure and fabrication method of this transistor can be the same as or similar to the structure and fabrication method of transistor 20 in this embodiment, and will not be described in detail here). This transistor and the transistor 20 in this embodiment form a 2T0C structure memory cell.

[0135] In other alternative embodiments of this application, such as Figures 29 to 32 As shown, after fabricating the second electrode 22, the second conductive layer 82, and the second isolation structure 92, and before fabricating the semiconductor layer 23 using a deposition process based on the first oxide source, and fabricating the gate insulating layer 24 and the gate 25 to obtain the transistor 20, the process further includes: like Figure 29 and Figure 30 As shown, the first sacrificial post 61 is removed. The first sacrificial post 61 fills the second through hole 63. After the first sacrificial post 61 is removed, the second through hole 63 is opened, and the multilayer second dielectric layer 53, the multilayer first electrode 21 and the multilayer second electrode 22 are exposed on the side, and the first dielectric layer 51 is exposed at the bottom.

[0136] Optionally, the first sacrificial pillar 61 can be removed by an etching process to open the transistor region.

[0137] Next, as Figure 31 As shown, the second through-hole 63 is used to etch the multilayer second dielectric layer 53 and the first dielectric layer 51 laterally, exposing at least part of the bottom wall and at least part of the top wall of each first electrode 21 and each second electrode 22, forming a multilayer third channel 74; the third channel 74 is annular.

[0138] In this embodiment, the multilayer third channels 74 are distributed sequentially at intervals along the direction perpendicular to the substrate 10, and each is arranged in a ring around the second through hole 63. All the multilayer third channels 74 are connected to the second through hole 63.

[0139] Next, as Figure 32 As shown, a second sacrificial layer 54 is fabricated within the third channel 74. Multiple second sacrificial layers 54 are fabricated one-to-one within the multiple third channels 74, and the second sacrificial layers 54 fill the corresponding third channels 74.

[0140] Optionally, the material of the second sacrificial layer 54 includes, but is not limited to, polysilicon (Poly), to facilitate subsequent process steps. Optionally, in this embodiment, the fabrication of the second sacrificial layer 54 within the third channel 74 includes: depositing Poly to form an initial sacrificial layer (not shown); the initial sacrificial layer fills the multilayer third channel 74, the second via 63, and covers the stacked structure 50, the first isolation structure 91, and the second isolation structure 92; removing the initial sacrificial layer located on the side of the stacked structure 50 away from the substrate 10 and within the second via 63; separating the remaining initial sacrificial layers within the multilayer third channel 74; and using the remaining initial sacrificial layers within the multilayer third channel 74 as the multilayer second sacrificial layers 54.

[0141] In other alternative embodiments of this application, such as Figures 33 to 35 As shown, a semiconductor layer 23 is fabricated using a deposition process based on a first oxide source, and a gate insulating layer 24 and a gate 25 are fabricated to obtain a transistor 20, comprising: like Figure 33 As shown, an initial semiconductor layer 231 is deposited using ozone with a first concentration or a first pulse time, or oxygen plasma with a first power, as the first oxidation source, to obtain a conformal covering of the second via 63 and the stacked structure 50; wherein the first concentration or the first pulse time is 5% to 80% of the concentration or pulse time of ozone in a conventional deposition process, and the first power is 5% to 80% of the power of oxygen plasma in a conventional deposition process.

[0142] In this embodiment, the initial semiconductor layer 231 conformally covers the second via 63 and the stacked structure 50. The initial semiconductor layer 231 is electrically connected to the stacked multilayer first electrode 21 and multilayer second electrode 22 exposed on the inner wall of the second via 63.

[0143] In this embodiment of the application, during the deposition of the initial semiconductor layer 231, ozone with a first concentration of 5% to 80% (proportion) of the ozone concentration in the conventional deposition process or a first pulse time of 5% to 80% (proportion) of the ozone pulse time in the conventional deposition process is used as the first oxidation source, or oxygen plasma with a first power of 5% to 80% (proportion) of the oxygen plasma power in the conventional deposition process is used as the first oxidation source to grow the semiconductor layer material. This can reduce the oxidation effect and degree of the first oxidation source on the source and drain electrode materials, thereby reducing the source and drain contact resistance and improving the on-state current and other performance of the device.

[0144] Optionally, the semiconductor layer material includes, but is not limited to, metal oxide materials. The metal oxide material can be IGZO. When the metal oxide material is IGZO, the leakage current of transistor 20 is relatively small (leakage current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO, IZOx, etc., as long as the transistor leakage current meets the requirements. Specific adjustments can be made according to the actual situation.

[0145] Optionally, in this embodiment, the semiconductor layer material includes one or more combinations of common oxide semiconductor materials such as IGZO, ITO, IWO, and InO. Optionally, in this embodiment, the semiconductor layer material is grown using ALD growth.

[0146] Next, as Figure 34 As shown, an initial gate insulating layer 241 and an initial conductive structure 83 are sequentially deposited to cover the initial semiconductor layer 231 and fill the second via 63. The initial gate insulating layer 241 and / or the initial conductive structure 83 are deposited using ozone with a second concentration or a second pulse time, or oxygen plasma with a second power, as the second oxidation source. The second concentration or the second pulse time is 100% to 300% of the concentration or pulse time of ozone in a conventional deposition process, and the second power is 100% to 300% of the power of oxygen plasma in a conventional deposition process.

[0147] In this embodiment, the initial gate insulating layer 241 conformally covers the initial semiconductor layer 231, and the initial conductive structure 83 conformally covers the initial gate insulating layer 241 and fills the second via 63. The initial gate insulating layer 241 is located between the initial semiconductor layer 231 and the initial conductive structure 83 and electrically isolates them.

[0148] In this embodiment, during the deposition of at least one of the initial gate insulating layer 241 and the initial conductive structure 83, ozone with a second concentration of 100% to 300% (proportion) of the ozone concentration in a conventional deposition process or a second pulse time of 100% to 300% (proportion) of the ozone pulse time in a conventional deposition process is used as the second oxidation source, or oxygen plasma with a second power of 100% to 300% (proportion) of the oxygen plasma power in a conventional deposition process is used as the second oxidation source to grow at least one of the initial gate insulating layer 241 and the initial conductive structure 83. This can enhance the oxidation effect of the second oxidation source on the semiconductor layer material, thereby ensuring sufficient oxygen content in the initial semiconductor layer 231 film and preventing degradation of properties such as sheet resistance of the initial semiconductor layer 231 film, and improving the on-state current and other performance of the device.

[0149] Optionally, the material of the initial gate insulating layer 241 includes, but is not limited to, high-k materials such as HfO2, Al2O3, HfAlO, and HfLaO. Optionally, the initial gate insulating layer 241 is grown by ALD growth.

[0150] Optionally, the material of the initial gate 251 includes, but is not limited to, conductive materials such as IZO, ITO, TiN, and W. Optionally, the initial gate 251 is grown by ALD growth.

[0151] Next, as Figure 35 As shown, the initial conductive structure, initial gate insulating layer and initial semiconductor layer located on the side of the stacked structure 50 away from the substrate 10 are removed to obtain a conductive pillar 84 and a gate insulating layer 24 and a semiconductor layer 23 surrounding the conductive pillar 84; the semiconductor layer 23 includes a multilayer channel 232 that is electrically connected to the stacked multilayer first electrode 21 and multilayer second electrode 22 respectively, and the conductive pillar 84 includes a plurality of gates 25 that correspond one-to-one with the multilayer channel 232.

[0152] In this embodiment, the initial conductive structure, initial gate insulating layer and initial semiconductor layer located on the side of the stacked structure 50 away from the substrate 10 are removed, and the remaining initial conductive structure, initial gate insulating layer and initial semiconductor layer in the plurality of second vias 63 are separated. The remaining initial conductive structure, initial gate insulating layer and initial semiconductor layer in each second via 63 are respectively used as conductive pillar 84, gate insulating layer 24 and semiconductor layer 23.

[0153] In this embodiment, the semiconductor layer 23 extends along a direction perpendicular to the substrate 10. The semiconductor layer 23 includes a multilayer channel 232 that is electrically connected to the stacked multilayer first electrode 21 and multilayer second electrode 22 respectively. The conductive pillar 84 includes a multilayer gate 25 that corresponds one-to-one with the multilayer channel 232. The gate insulating layer 24 is located between the channel 232 and the gate 25. The multilayer first electrode 21, multilayer second electrode 22, multilayer channel 232, gate insulating layer 24 and multilayer gate 25 form a stacked multilayer transistor 20.

[0154] In this embodiment, the conductive post 84 extends in a direction perpendicular to the substrate 10, serving as a word line (WL). A gate insulating layer 24 is wound around the conductive post 84, and a semiconductor layer is wound around the gate insulating layer 24. The multilayer transistors 20 stacked sequentially in the multilayer memory cell along a direction perpendicular to the substrate 10 share a single conductive post 84 (i.e., share a single word line).

[0155] Optionally, in this embodiment, a semiconductor layer material, a gate dielectric material, and a gate material are sequentially grown according to the above deposition method to obtain an initial semiconductor layer 231, an initial gate insulating layer 241, and an initial conductive structure 83; then, the initial conductive structure, the initial gate insulating layer, and the initial semiconductor layer located on the side of the stacked structure 50 away from the substrate 10 are removed to obtain a semiconductor layer 23, a gate insulating layer 24, and a gate 25, forming a vertical channel metal-oxide-semiconductor transistor device.

[0156] In this embodiment, the semiconductor layer material uses low-concentration or unsaturated pulse time or subsaturated pulse time O3, or low-power O-plasma as a weak oxidation source (as the first oxidation source) for ALD growth. This can reduce the oxidation effect and degree of the first oxidation source on the source and drain electrode materials, thereby reducing the source and drain contact resistance. At the same time, at least one of the gate insulating material and the gate electrode material can use high-concentration or oversaturated pulse time O3, or high-power O-plasma as an excessive strong oxidation source (as the second oxidation source) for ALD growth. This can enhance the oxidation effect of the second oxidation source on the semiconductor layer material, thereby ensuring sufficient oxygen content in the semiconductor layer film and preventing degradation of properties such as sheet resistance of the semiconductor layer film, thereby improving the on-state current and other performance of the device.

[0157] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned using a patterning process to fabricate the respective film layers.

[0158] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.

[0159] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the thin film does not require patterning during the entire fabrication process, the thin film can be called a layer. If the thin film requires patterning during the entire fabrication process, the "layer" after patterning includes at least one "pattern".

[0160] The semiconductor device manufacturing method provided in this application can be applied to the field of semiconductor device fabrication and can be used to manufacture metal-oxide-semiconductor transistor devices. Based on the same inventive concept, this application also provides a semiconductor device, the structural schematic of which is shown below. Figure 9 , Figure 10 and Figure 35 As shown, the semiconductor device includes a transistor 20.

[0161] The transistor 20 includes: a first electrode 21 disposed on one side of the substrate 10, a second electrode 22 insulated from the first electrode 21, a semiconductor layer 23 electrically connected to the first electrode 21 and the second electrode 22 respectively, a gate insulating layer 24 and a gate 25, wherein the gate insulating layer 24 is disposed between the semiconductor layer 23 and the gate 25; the semiconductor layer 23 is fabricated using a deposition process based on a first oxide source, wherein at least one of the parameters of the concentration, pulse time and power of the first oxide source is less than the corresponding parameter values ​​of conventional deposition processes.

[0162] In this embodiment, the substrate 10 is used to support the transistor 20. The transistor 20 includes a first electrode 21, a second electrode 22 insulated from the first electrode 21, a semiconductor layer 23 electrically connected to the first electrode 21 and the second electrode 22 respectively, a gate 25 for controlling the transistor 20 to be turned on or off, and a gate insulating layer 24 located between the semiconductor layer 23 and the gate 25. The semiconductor layer 23 and the gate 25 are electrically isolated by the gate insulating layer 24.

[0163] In this embodiment, the semiconductor layer 23 is fabricated using a deposition process with a first oxide source whose concentration, pulse time, and power values ​​are lower than the corresponding parameter values ​​of the oxide source in conventional deposition processes. Compared to the oxide source in conventional deposition processes, the first oxide source has a lower oxidation effect and degree on the first electrode 21 and the second electrode 22. The thickness of the interface layer formed between the first electrode 21 and the semiconductor layer 23 and between the second electrode 22 and the semiconductor layer 23 is thinner, thereby reducing the contact resistance between the first electrode 21 and the semiconductor layer 23 and between the second electrode 22 and the semiconductor layer 23, and improving the on-state current and other performance of the device.

[0164] Optionally, in this embodiment of the application, the semiconductor layer material is deposited using ozone with a first concentration or a first pulse time, or oxygen plasma with a first power as the first oxidation source; the first concentration or the first pulse time is 5% to 80% of the concentration or pulse time of ozone in a conventional deposition process, and the first power is 5% to 80% of the power of oxygen plasma in a conventional deposition process.

[0165] In this embodiment of the application, during the deposition of semiconductor layer material, ozone with a first concentration of 5% to 80% (proportion) of the ozone concentration in the conventional deposition process or a first pulse time of 5% to 80% (proportion) of the ozone pulse time in the conventional deposition process is used as the first oxidation source, or oxygen plasma with a first power of 5% to 80% (proportion) of the oxygen plasma power in the conventional deposition process is used as the first oxidation source to grow semiconductor layer material. This can reduce the oxidation effect and degree of the first oxidation source on the source and drain electrode materials, thereby reducing the source and drain contact resistance and improving the on-state current and other performance of the device.

[0166] In some optional embodiments of this application, the gate insulating layer 24 and / or the gate 25 are fabricated using a deposition process based on a second oxide source; at least one of the parameters of the concentration, pulse time, and power of the second oxide source is greater than the corresponding parameter values ​​of a conventional deposition process.

[0167] In this embodiment, the semiconductor layer material is fabricated using a deposition process with a first oxide source, where at least one of the parameters of concentration, pulse time, and power is less than the corresponding parameter of the oxide source in a conventional deposition process. At least one of the gate insulating layer 24 and the gate 25 is fabricated using a deposition process with a second oxide source, where at least one of the parameters of concentration, pulse time, and power is greater than the corresponding parameter of the oxide source in a conventional deposition process. Compared to the oxide source in a conventional deposition process, the second oxide source enhances the oxidation effect on the semiconductor layer 23, thereby ensuring sufficient oxygen content in the semiconductor layer 23 and preventing degradation of properties such as sheet resistance of the semiconductor layer 23, thus improving the on-state current and other performance of the device.

[0168] Optionally, in the embodiments of this application, the gate insulating material and / or the gate material are deposited using ozone with a second concentration or a second pulse time, or oxygen plasma with a second power as the second oxidation source. The second concentration or the second pulse time is 100% to 300% of the concentration or pulse time of ozone in a conventional deposition process, and the second power is 100% to 300% of the power of oxygen plasma in a conventional deposition process.

[0169] In this embodiment, during the deposition of gate insulating material and / or gate material, ozone with a second concentration of 100% to 300% (proportion) of the ozone concentration in a conventional deposition process or a second pulse duration of 100% to 300% (proportion) of the ozone pulse duration in a conventional deposition process is used as a second oxidation source, or oxygen plasma with a second power of 100% to 300% (proportion) of the oxygen plasma power in a conventional deposition process is used as a second oxidation source to grow gate insulating material and / or gate material. This can enhance the oxidation effect of the second oxidation source on the semiconductor layer material, thereby ensuring sufficient oxygen content in the semiconductor layer 23 film and preventing degradation of properties such as sheet resistance of the semiconductor layer 23 film, and improving the on-state current and other performance of the device.

[0170] In some optional embodiments of this application, such as Figure 9 , Figure 10 and Figure 35 As shown, the semiconductor layer 23 extends entirely in a direction perpendicular to the substrate 10 and is disposed around the periphery of the gate 25. The semiconductor layer 23 includes a vertical channel, and the transistor 20 is a vertical channel transistor.

[0171] In some optional embodiments of this application, such as Figure 35 As shown, the semiconductor device includes a multilayer memory cell array, multiple first conductive layers 81, and multiple conductive pillars 84. Each memory cell array includes multiple memory cells distributed in an array. Each memory cell includes a transistor 20. The transistors 20 of the multiple memory cells distributed sequentially along a second direction in each memory cell array share a first conductive layer 81. The transistors 20 of the multilayer memory cells distributed sequentially along a direction perpendicular to the substrate 10 in the multilayer memory cell array share a conductive pillar 84.

[0172] In this embodiment, a multilayer memory cell array is stacked along a direction perpendicular to the substrate 10. Each layer of the memory cell array includes multiple memory cells arranged in an array, and each memory cell includes a transistor 20. A first conductive layer 81 serves as a bit line (BL). Multiple first conductive layers 81 are stacked along a direction perpendicular to the substrate 10 and each extends along a second direction. The transistors 20 of the multiple memory cells arranged sequentially along the second direction in each layer of the memory cell array share one first conductive layer 81. Conductive pillars 84 serve as word lines (WL). Multiple conductive pillars 84 are arranged in an array in a plane parallel to the substrate 10 and each extends along a direction perpendicular to the substrate 10. The transistors 20 of the multilayer memory cells arranged sequentially along a direction perpendicular to the substrate 10 in the multilayer memory cell array share one conductive pillar 84. This reduces the number of traces (including word lines and bit lines), which is beneficial for layout design, improving structural density, and enhancing practicality.

[0173] It should be noted that the semiconductor devices in the embodiments of this application can be manufactured using the manufacturing method of the semiconductor devices provided in the embodiments of this application. Therefore, the semiconductor devices in the embodiments of this application also have the above-mentioned beneficial effects of the manufacturing method of the semiconductor devices provided in the embodiments of this application, which will not be repeated here.

[0174] In some optional embodiments of this application, the semiconductor device includes, but is not limited to, random access memory, specifically static random access memory or dynamic random access memory, and of course, flash memory, etc.

[0175] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a semiconductor device manufactured using the semiconductor device manufacturing method described above; or, a semiconductor device as described above.

[0176] It should be noted that since the electronic devices in the embodiments of this application include semiconductor devices manufactured using the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, which will not be repeated here.

[0177] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0178] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In this embodiment, a first electrode is first fabricated on one side of the substrate; then a second electrode insulated from the first electrode is fabricated; subsequently, a semiconductor layer, a gate insulating layer, and a gate are fabricated to obtain a transistor. The semiconductor layer is fabricated using a deposition process with a first oxide source whose concentration, pulse time, and power are all lower than the corresponding parameters of the oxide source in conventional deposition processes. The semiconductor layer is electrically connected to both the first and second electrodes. Compared to the oxide source in conventional deposition processes, the first oxide source has a lower oxidation effect and degree on both the first and second electrodes. The interface layers formed between the first electrode and the semiconductor layer, and between the second electrode and the semiconductor layer, are thinner, thereby reducing the contact resistance between the first electrode and the semiconductor layer, and between the second electrode and the semiconductor layer, thus improving the on-state current and other performance characteristics of the device.

[0179] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0180] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A first electrode is fabricated on one side of the substrate; Fabricate the second electrode; The second electrode is insulated from the first electrode; A semiconductor layer is fabricated using a deposition process based on a first oxide source, and a gate insulating layer and a gate are fabricated to obtain a transistor; the semiconductor layer is electrically connected to the first electrode and the second electrode respectively, and the gate insulating layer is located between the semiconductor layer and the gate; at least one of the following parameters of the first oxide source—concentration, pulse time, and power—is less than the corresponding parameter value of a conventional deposition process.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The gate insulating layer and / or the gate are fabricated using a deposition process based on a second oxide source; Wherein, at least one of the parameters of the second oxidation source, such as concentration, pulse time, and power, is greater than the corresponding parameter value of the conventional deposition process.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, Before fabricating the first electrode on one side of the substrate, the method further includes: fabricating a first insulating layer on one side of the substrate; In addition, a first electrode is fabricated on one side of the substrate, including: fabricating the first electrode covering a portion of the first insulating layer; In addition, after fabricating the first electrode on one side of the substrate and before fabricating the second electrode, the method further includes: fabricating a second insulating layer covering the first electrode and the first insulating layer; And, fabricating a second electrode includes: fabricating a second electrode that covers a portion of the second insulating layer; the orthographic projections of the second electrode and the first electrode on the substrate at least partially intersect; And, after fabricating the second electrode and before fabricating the semiconductor layer using a deposition process based on the first oxide source, the process further includes: Fabricate a third insulating layer covering the second electrode and the second insulating layer; A first through-hole is formed, penetrating the third insulating layer, the second electrode, and the second insulating layer and extending to the first electrode.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The semiconductor layer is fabricated using a deposition process based on a first oxide source, including: An initial semiconductor layer is deposited using ozone with a first concentration or a first pulse time, or oxygen plasma with a first power, as the first oxidation source, to obtain an initial semiconductor layer that conformally covers the first via and the third insulating layer; the first concentration or the first pulse time is 5% to 80% of the concentration or pulse time of ozone in a conventional deposition process, and the first power is 5% to 80% of the power of oxygen plasma in a conventional deposition process.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, A gate insulating layer and a gate are fabricated using a deposition process based on a second oxide source to obtain a transistor, including: An initial gate insulating layer and an initial gate are sequentially deposited to conformally cover the initial semiconductor layer and fill the first via; the initial gate insulating layer and / or the initial gate are deposited using ozone with a second concentration or a second pulse time, or oxygen plasma with a second power, as a second oxidation source, wherein the second concentration or the second pulse time is 100% to 300% of the concentration or pulse time of ozone in a conventional deposition process, and the second power is 100% to 300% of the power of oxygen plasma in a conventional deposition process; At least a portion of the initial semiconductor layer, at least a portion of the initial gate insulating layer, and at least a portion of the initial gate located on the side of the third insulating layer away from the substrate are removed to obtain the semiconductor layer, the gate insulating layer, and the gate.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, Before fabricating the first electrode on one side of the substrate, the process also includes: A first dielectric layer is formed on one side of the substrate; A stacked structure covering the first dielectric layer is fabricated; the stacked structure includes a first sacrificial layer and a second dielectric layer that are alternately distributed in sequence. A first sacrificial pillar and a second sacrificial pillar are fabricated that penetrate the stacked structure; the first sacrificial pillar and the second sacrificial pillar are distributed along a first direction parallel to the substrate; In addition, a first electrode is fabricated on one side of the substrate, including replacing the multilayer of the first sacrificial layer located on the side of the first sacrificial pillar away from the second sacrificial pillar with a plurality of the first electrodes; In addition, fabricating a second electrode includes replacing the multiple layers of the first sacrificial layer located around the second sacrificial pillar with a plurality of second electrodes.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, Fabricating a first sacrificial pillar and a second sacrificial pillar that penetrate the stacked structure includes: A plurality of second through-holes and a plurality of third through-holes are formed, which respectively penetrate the stacked structure and are arranged in an array; the plurality of second through-holes and the plurality of third through-holes are alternately distributed in pairs along the first direction, and are each sequentially distributed along the second direction; the second direction is parallel to the substrate and intersects the first direction; The first sacrificial post and the second sacrificial post are respectively fabricated in the second through hole and the third through hole; And, replacing the multiple first sacrificial layers located on the side of the first sacrificial pillar away from the second sacrificial pillar with a plurality of first electrodes, including: A trench is formed that penetrates the stacked structure and extends along the second direction; the trench is located between two adjacent first sacrificial pillars; Through the trench, the multiple layers of the first sacrificial layer are etched laterally until the first sacrificial pillar is exposed, forming multiple layers of the first channel; the first channel extends along the second direction. Fabricate the first electrode that conformally covers the first channel; In addition, after fabricating the first electrode on one side of the substrate, the process also includes: A first conductive layer is fabricated to conformally cover the first electrode and fill the first channel.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, Replacing the multiple layers of the first sacrificial layer located around the second sacrificial pillar with multiple second electrodes, including: Remove the second sacrificial column; Through the third through-hole, the multilayer first sacrificial layer is laterally etched until the first sacrificial pillar is exposed, forming a multilayer second channel; the second channel is annular. Fabricate a second electrode that conformally covers the second channel; In addition, after fabricating the second electrode, the following also includes: A second conductive layer is fabricated to conformally cover the second electrode and fill the second channel.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, After replacing the multiple first sacrificial layers located around the second sacrificial pillar with a plurality of second electrodes, and before fabricating the semiconductor layer using a deposition process based on the first oxide source, and fabricating the gate insulating layer and the gate to obtain the transistor, the process further includes: Remove the first sacrificial column; Through the second via, the multilayer second dielectric layer and the first dielectric layer are laterally etched to expose at least a portion of the bottom wall and at least a portion of the top wall of each first electrode and each second electrode, forming a multilayer third channel; the third channel is annular; A second sacrificial layer is created within the third channel.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, A semiconductor layer is fabricated using a deposition process based on a first oxide source, and a gate insulating layer and a gate are fabricated to obtain a transistor, including: An initial semiconductor layer is deposited using ozone with a first concentration or a first pulse duration, or oxygen plasma with a first power, as the first oxidation source, to obtain a conformally conformally covering the second via and the stacked structure; wherein the first concentration or the first pulse duration is 5% to 80% of the concentration or pulse duration of ozone in a conventional deposition process, and the first power is 5% to 80% of the power of oxygen plasma in a conventional deposition process; An initial gate insulating layer and an initial conductive structure are sequentially deposited to conformally cover the initial semiconductor layer and fill the second via; the initial gate insulating layer and / or the initial conductive structure are deposited using ozone with a second concentration or a second pulse time, or oxygen plasma with a second power, as a second oxidation source, wherein the second concentration or the second pulse time is 100% to 300% of the concentration or pulse time of ozone in a conventional deposition process, and the second power is 100% to 300% of the power of oxygen plasma in a conventional deposition process; The initial conductive structure, initial gate insulating layer, and initial semiconductor layer located on the side of the stacked structure away from the substrate are removed to obtain a conductive pillar and a gate insulating layer and the semiconductor layer surrounding the conductive pillar; the semiconductor layer includes a plurality of channels electrically connected to a plurality of first electrodes and a plurality of second electrodes respectively, and the conductive pillar includes a plurality of gates corresponding one-to-one with the plurality of channels.

11. A semiconductor device, characterized in that, Including transistors; The transistor includes: The first electrode is disposed on one side of the substrate; The second electrode is insulated from the first electrode; A semiconductor layer is electrically connected to the first electrode and the second electrode, respectively; A gate insulating layer and a gate, wherein the gate insulating layer is disposed between the semiconductor layer and the gate; The semiconductor layer is fabricated using a deposition process based on a first oxide source; The on-state current of the transistor is more than 1 times that of a transistor fabricated using a conventional deposition process.

12. The semiconductor device according to claim 11, characterized in that, The concentration, pulse time, and power of the first oxidation source are at least one parameter value that is less than the corresponding parameter value of a conventional deposition process.

13. The semiconductor device according to claim 12, characterized in that, Includes at least one of the following: The gate insulating layer and / or the gate are fabricated using a deposition process based on a second oxide source; at least one of the following parameters of the second oxide source—concentration, pulse time, and power—is greater than the corresponding parameter value of a conventional deposition process. The semiconductor layer extends entirely in a direction perpendicular to the substrate and is disposed around the periphery of the gate. The semiconductor device includes a multilayer memory cell array, multiple first conductive layers, and multiple conductive pillars. Each layer of the memory cell array includes multiple memory cells arranged in an array. Each memory cell includes a transistor. The transistors of the multiple memory cells arranged sequentially along a second direction in each layer of the memory cell array share a first conductive layer. The transistors of the multilayer memory cells arranged sequentially along a direction perpendicular to the substrate in the multilayer memory cell array share a conductive pillar.

14. An electronic device, characterized in that, include: A semiconductor device manufactured using the manufacturing method of any one of claims 1 to 10; or, The semiconductor device as described in any one of claims 11 to 13.

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