Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device capable of mitigating or minimizing interference between storage node contacts and a method of manufacturing the same are disclosed. The semiconductor device includes: a semiconductor substrate; a plurality of bit line structures disposed over the semiconductor substrate; island-like storage node contacts spaced apart from each other between adjacent bit line structures of the plurality of bit line structures; a plurality of plug isolation layers disposed between the island-like storage node contacts; and contact spacers disposed between each of the storage node contacts and each of the plurality of plug isolation layers, each of the contact spacers having different thicknesses at a central portion and both ends thereof.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0160881, filed on November 13, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure relate to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including storage node contacts and a method for manufacturing the same. Background Technology

[0004] As the integration density of semiconductor devices increases and their size decreases, the size of contact plugs also decreases. The smaller the contact plugs become, the larger the aspect ratio of the contact holes.

[0005] However, during the etching process used to form contact holes with high aspect ratios, misalignment and incomplete contact hole formation may occur.

[0006] Thus, the electrical characteristics of semiconductor devices may deteriorate due to defects in high aspect ratio contact holes, and the process for forming contact plugs becomes more difficult. Therefore, there is a need to develop a method to mitigate this difficulty. Summary of the Invention

[0007] Embodiments of this disclosure relate to a semiconductor device capable of mitigating or minimizing interference between contacts of a storage node, and a method of manufacturing the semiconductor device.

[0008] According to one embodiment of the present disclosure, a semiconductor device includes: a semiconductor substrate; a plurality of bit line structures disposed on the semiconductor substrate; island-shaped memory node contacts spaced apart from each other among adjacent bit line structures in the plurality of bit line structures; a plurality of plug isolation layers disposed between the island-shaped memory node contacts; and contact spacers disposed between each memory node contact and each of the plurality of plug isolation layers, each contact spacer having a different thickness at its central portion and at both ends.

[0009] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a plurality of bit line structures on a semiconductor substrate; forming island-shaped memory node contacts spaced apart from each other between adjacent bit line structures in the plurality of bit line structures; replacing the surface of each memory node contact with a contact spacer; and forming a plug isolation layer to gap fill the space between adjacent memory node contacts in the island-shaped memory node contacts. Attached Figure Description

[0010] Figure 1A This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 1B and Figure 1C This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 2 through 10 illustrate methods for manufacturing semiconductor devices according to embodiments of the present disclosure. Detailed Implementation

[0013] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure more comprehensive and complete, and to fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in various figures and embodiments.

[0014] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0015] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated in order to clearly illustrate the features of the embodiments. When referring to a first layer being "on" a second layer or a substrate, it means not only that the first layer is formed directly on the second layer or substrate, but also that a third layer exists between the first layer and the second layer or substrate.

[0016] Figure 1A This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1B and Figure 1C This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The cross-sectional view taken by line A-A' in the diagram, and Figure 1C For along Figure 1A A cross-sectional view of the section cut by line B-B' in the diagram.

[0017] refer to Figures 1A to 1C A semiconductor device may include multiple memory cells. Each memory cell may include a unit transistor, which includes a buried gate structure BG, a bit line structure BL, and a memory element ME.

[0018] An isolation layer 102 and active regions 103 can be formed in the substrate 10. Multiple active regions 103 can be defined by the isolation layer 102. Each active region 103 can be strip-shaped, having a long axis and a short axis. The active regions 103 can be spaced apart from each other by a predetermined distance.

[0019] Substrate 101 may be formed of a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. Substrate 101 may also include other semiconductor materials, such as germanium (Ge). Substrate 101 may also include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 101 may also include an SOI (silicon-on-insulator) substrate. The isolation layer 102 may be formed using a shallow trench isolation (STI) process.

[0020] A linear buried gate structure BG extending along a first direction D1 can be formed in the substrate 101. The buried gate structure BG may include a gate dielectric layer 106 formed on the surface of the gate trench 105, and a gate electrode 107 and a gate capping layer 108 formed on the gate dielectric layer 106 to fill the gate trench 105.

[0021] Specifically, a linear gate trench 105 may be formed on a substrate 101 along a first direction D1 through the active region 103 and the isolation layer 102. The gate trench 105 may be formed to have a predetermined depth in a region defined by a hard mask layer 104 formed on the surface of the substrate 101. The bottom surface of the gate trench 105 may be disposed at a level higher than the bottom surface of the isolation layer 102. The depth of the gate trench 105 may be shallower than that of the isolation layer 102. According to another embodiment of the present disclosure, the bottom of the gate trench 105 may have curvature. According to another embodiment of the present disclosure, the isolation layer 102 may be etched to a predetermined depth in the direction in which the gate trench 105 extends to form fins in the active region 103.

[0022] A gate dielectric layer 106 may be formed on the surface of a gate trench 105. A gate electrode 107, partially filling the gate trench 105, may be formed on the gate dielectric layer 106. A gate capping layer (as a sealing layer) 108 may be formed on the gate electrode 107 to fill the remaining portion of the gate trench 105. The upper surface of the gate capping layer 108 may be disposed at the same level as the upper surface of the hard mask layer 104. The upper surface of the gate electrode 107 may be disposed at a lower level than the upper surface of the substrate 101. The gate electrode 107 may comprise a low-resistance metal material. The gate electrode 107 may comprise a combination or stacked structure of at least one of a metal material, a metal nitride, and polysilicon. For example, the gate electrode 107 may be formed by sequentially stacking titanium nitride and tungsten. According to another embodiment of this disclosure, the gate electrode 107 may be formed solely of titanium nitride (TiN only). According to another embodiment of this disclosure, the gate electrode 107 may comprise a stacked structure of a metal material and polysilicon.

[0023] The first impurity region 109 and the second impurity region 110 can be formed in the substrate 101. The first impurity region 109 and the second impurity region 110 can be referred to as "junction regions" or "source / drain regions". The first impurity region 109 and the second impurity region 110 can be separated from each other by a gate trench 105. Therefore, the gate electrode 107 and the first impurity region 109 and the second impurity region 110 can constitute a single-cell transistor. This single-cell transistor can improve the short-channel effect because the gate electrode 107 has a buried gate structure.

[0024] Bit line contact 111 can be formed on substrate 101. Bit line contact 111 can be coupled to first impurity region 109. Bit line contact 111 can be disposed within bit line contact hole BH. Bit line contact hole BH can expose first impurity region 109. Lower surface of bit line contact 111 can be lower than upper surface of substrate 101. Bit line contact 111 can be formed of polysilicon or metal. Linewidth of a portion of bit line contact 111 can be smaller than diameter of bit line contact hole BH. Therefore, a gap can be formed on each side of bit line contact 111. The gap can be formed independently on each side of bit line contact 111. As a result, a bit line contact 111 and a pair of gaps can be disposed in bit line contact hole BH, and the pair of gaps can be isolated by bit line contact 111.

[0025] The bitline structure BL can be formed on the bitline contact 111. The bitline contact 111 can couple the bitline structure BL to the active region. The bitline structure BL may include a bitline 112 and a bitline hard mask 113 located on the bitline 112. Referring to FIG1, the bitline structure BL may be linear and extend along a direction intersecting the buried gate structure BG (i.e., the second direction D2). A portion of the bitline 112 may be coupled to the bitline contact 111.

[0026] The bit line 112 and the bit line contact 111 may have the same line width. The bit line 112 may extend along the second direction D2 and cover the upper surface of the bit line contact 111. The bit line 112 may include a metallic material. The bit line hard mask 113 may include a dielectric material.

[0027] Bit line spacer 114 can be formed on the sidewall of bit line contact 111 and bit line structure BL. Bit line spacer 114 can extend along the contour of bit line structure BL in a second direction D2. Bit line spacer 114 can extend from the sidewall of bit line structure BL to bit line contact 111. Bit line spacer 114 can fill the gap between bit line contact 111 and bit line contact hole BH.

[0028] Bit line spacer 114 may include a single-layer or multi-layer structure. Bit line spacer 114 may include a dielectric material. Bit line spacer 114 may include at least one of silicon oxide, silicon nitride, and low-k materials, or a combination of one or more thereof.

[0029] Storage node contacts 115 can be formed between adjacent bit line structures BL. Each storage node contact 115 can be coupled to a second impurity region 110.

[0030] The storage node contacts 115 may be island-shaped and spaced apart in a first direction D1 and a second direction D2. The storage node contacts 115 may be spaced apart in the first direction D1 by a bit line structure BL. The storage node contacts 115 may be spaced apart in the second direction D2 by a plug isolation layer 117.

[0031] A contact spacer 116 may be disposed between the storage node contact 115 and the plug isolation layer 117. The contact spacer 116 may be a portion of the surface of each storage node contact 115 that has been converted to a predetermined thickness through an oxidation process. From a top viewpoint, see reference... Figure 1A The contact spacer 116 may have different thicknesses at its center and at both ends. The thickness of the center portion of the contact spacer 116 may be less than the thickness of the two ends of the contact spacer 116.

[0032] Both the contact spacer 116 and the plug isolation layer 117 may contain a dielectric material. For example, the contact spacer 116 may contain silicon oxide. For example, the plug isolation layer 117 may contain silicon nitride, but the embodiments of this disclosure are not limited thereto.

[0033] A storage element ME may be formed on the storage node contact 115. The storage element ME may include a capacitor containing the storage node. The storage node may be cylindrical. Although not shown in the figure, a dielectric layer and a plate-like node may also be formed on the storage node. The storage node may have a cylindrical shape other than a cylindrical shape.

[0034] As described above, according to this embodiment of the present disclosure, by applying contact spacer 116 (where the surface of the storage node contact 115 is converted to oxide), the peak of the storage node contact 115 can be eliminated, and interference between the storage node contacts 115 can be mitigated or minimized. Therefore, the parasitic capacitance of the cell transistor can be reduced, and the sensing margin can be improved.

[0035] Figures 2 through 10 illustrate methods for manufacturing semiconductor devices according to embodiments of the present disclosure. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A, Figure 8A , Figure 9A and Figure 10A It's a floor plan. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B It is along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A A cross-sectional view taken from line A-A'. Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C and 10C It is along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A The cross-sectional view taken by line B-B'. Figure 8D It is along Figure 8C The planar view intercepted by line C-C'.

[0036] refer to Figures 2A to 2C An isolation layer 12 can be formed on the substrate 11. Active regions 13 can be defined by the isolation layer 12. Each active region 13 can be elongated and strip-shaped. Multiple active regions 13 can be spaced apart from each other by a predetermined interval.

[0037] The isolation layer 12 can be formed using a shallow trench isolation (STI) process. The STI process can be performed as follows: The substrate 11 can be etched to form isolation trenches (the reference numerals are omitted). The isolation trenches can be filled with a dielectric material, thus forming the isolation layer 12. The isolation layer 12 can include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes can be used to fill the isolation trenches with the dielectric material. Additionally, planarization processes such as chemical mechanical polishing (CMP) can be used.

[0038] Subsequently, a buried gate structure BG can be formed in the substrate 11. The buried gate structure BG may have a linear shape extending along the first direction D1. The buried gate structure BG may be referred to as a "buried word line structure". The buried gate structure BG may include a gate trench 15, a gate dielectric layer 16 covering the bottom surface and sidewalls of the gate trench 15, a gate electrode 17 partially filling the gate trench 15 above the gate dielectric layer 16, and a gate capping layer 18 formed above the gate electrode 17.

[0039] The method for forming the buried grid structure BG can be performed as follows.

[0040] First, a gate trench 15 can be formed in the substrate 11. The gate trench 15 can be linear, traversing the active region 13 and the isolation layer 12. The gate trench 15 can be formed by forming a mask pattern (not shown) on the substrate 11 and performing an etching process using the mask pattern as an etching mask. To form the gate trench 15, a hard mask layer 14 can be used as an etching barrier. The hard mask layer 14 may contain TEOS, but embodiments of this disclosure are not limited thereto. The gate trench 15 can be formed shallower than the isolation trench. The bottom surface of the gate trench 15 can be set at a level higher than the bottom surface of the isolation layer 12. The depth of the gate trench 15 can be deep enough to increase the average cross-sectional area of ​​the gate electrode 17. Therefore, the resistance of the gate electrode 17 can be reduced. According to another embodiment of this disclosure, the bottom edge of the gate trench 15 can have curvature. By forming the bottom edge of the gate trench 15 with curvature, the unevenness of the bottom of the gate trench 15 can be minimized, thus making it easier to fill the gate electrode 17.

[0041] According to another embodiment of this disclosure, a fin region may also be formed after the gate trench 15 is formed. This fin region can be formed by recessing a portion of the isolation layer 12.

[0042] Subsequently, a gate dielectric layer 16 can be formed on the bottom surface and sidewalls of the gate trench 15. Before forming the gate dielectric layer 16, etching damage on the surface of the gate trench 15 can be repaired. For example, a sacrificial oxide can be formed by a thermal oxidation process, and then the sacrificial oxide can be removed.

[0043] The gate dielectric layer 16 can be formed by a thermal oxidation process. For example, the bottom and sidewalls of the gate trench 15 can be oxidized to form the gate dielectric layer 16.

[0044] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed by a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 may include a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium oxynitride, or a combination thereof. According to another embodiment of this disclosure, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium oxynitride, aluminum oxide, or a combination thereof. Other known high-k materials may be selectively used as high-k materials.

[0045] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed by depositing a pad polysilicon layer and then subjecting the pad polysilicon layer to free radical oxidation.

[0046] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed by forming a pad silicon nitride layer and then subjecting the pad silicon nitride layer to free radical oxidation.

[0047] Subsequently, a gate electrode 17 can be formed on the gate dielectric layer 16. To form the gate electrode 17, a conductive layer (not shown) can be formed to fill the gate trench 15, and then a recess process can be performed. For the recess process, an etch-back process can be performed, or a chemical mechanical polishing (CMP) process and an etch-back process can be performed sequentially. The gate electrode 17 can have a recessed shape that partially fills the gate trench 15. The upper surface of the gate electrode 17 can be disposed at a level below the upper surface of the substrate 11. The gate electrode 17 can include a metal, a metal nitride, or a combination thereof. For example, the gate electrode 17 can be formed of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). Titanium nitride / tungsten (TiN / W) can have a structure formed by conformally forming titanium nitride and then partially filling the gate trench 15 using tungsten. Titanium nitride can be used alone as the gate electrode 17, which can be referred to as a gate electrode 17 having a "TiN-only" structure. According to another embodiment of this disclosure, the gate electrode 17 can include a stacked structure of metal and polysilicon.

[0048] Subsequently, a gate capping layer 18 may be formed over the gate electrode 17. The gate capping layer 18 may include a dielectric material. The remaining portion of the gate trench 15 may be filled over the gate electrode 17 with the gate capping layer 18. The gate capping layer 18 may include silicon oxide. According to another embodiment of this disclosure, the gate capping layer 18 may have a NON (nitride-oxide-nitride) structure. The upper surface of the gate capping layer 18 may be at the same level as the upper surface of the hard mask layer 14. For this purpose, a chemical mechanical polishing (CMP) process may be performed when forming the gate capping layer 18 by using the upper surface of the hard mask layer 14 as an etch stop target.

[0049] After forming the buried gate structure as described above, a first junction region 19 and a second junction region 20 can be formed. The first junction region 19 and the second junction region 20 can be formed by a doping process (such as an implantation process). The first junction region 19 and the second junction region 20 can have the same depth. According to another embodiment of this disclosure, the first junction region 19 can be deeper than the second junction region 20. The first junction region 19 can be the region to which bit line contacts are to be coupled. The second junction region 20 can be the region to which memory node contacts are to be coupled.

[0050] The unit transistor of the memory cell can be formed by the gate electrode 17, the first junction region 19, and the second junction region 20.

[0051] Subsequently, a bitline structure BL coupled to the first junction region 19 can be formed. The bitline structure BL may include a stacked structure of bitlines 22 and bitline hard masks 23. The bitline structure BL may have a linear shape extending along a second direction D2 perpendicular to the first direction D1.

[0052] The method for forming a bitline structure (BL) can be performed as follows.

[0053] First, the hard mask layer 14 can be etched to form the bit line contact hole BH. (See reference) Figure 3A The bit line contact hole BH can be circular or elliptical. A portion of the substrate 11 can be exposed by the bit line contact hole BH. The bit line contact hole BH can have a diameter controlled to a predetermined linewidth. The bit line contact hole BH can expose a portion of the active region 13. For example, the bit line contact hole BH can expose the first junction region 19. The bit line contact hole BH can have a diameter greater than the width of the minor axis of the active region 13. Therefore, in the etching process used to form the bit line contact hole BH, a portion of the first junction region 19, the isolation layer 12, and the gate capping layer 18 can be etched. The gate capping layer 18, the first junction region 19, and the isolation layer 12 located below the bit line contact hole BH can be recessed to a predetermined depth. Therefore, the bottom of the bit line contact hole BH can extend into the interior of the substrate 11. As the bit line contact hole BH extends, the first junction region 19 can be recessed, and the upper surface of the first junction region 19 can be lower than the upper surface of the second junction region 20.

[0054] Subsequently, a preliminary plug (not shown) for gap filling the bit line contact hole BH can be formed. This preliminary plug can be formed using a selective epitaxial growth (SEG) process. For example, the preliminary plug may include SEG SiP, but embodiments of this disclosure are not limited thereto. Thus, a gapless preliminary plug can be formed using the selective epitaxial growth (SEG) process. According to another embodiment of this disclosure, the preliminary plug can be formed using a polysilicon deposition process and a chemical mechanical polishing (CMP) process. The preliminary plug can fill the bit line contact hole BH. The upper surface of the preliminary plug can be disposed at the same level as the upper surface of the hard mask layer 14.

[0055] Subsequently, a conductive layer (not shown) and a hard mask material layer (not shown) can be stacked on the hard mask layer 14 containing the initial plug. The conductive layer and the hard mask material layer can be sequentially stacked on the initial plug and the hard mask layer 14. The conductive layer may include a metal-containing material. The conductive layer may include a metal, a metal nitride, a metal silicide, or a combination thereof. According to this embodiment of the present disclosure, the conductive layer may include tungsten (W). According to another embodiment of the present disclosure, the conductive layer may include a stack of titanium nitride and tungsten (TiN / W). Here, titanium nitride can be used as a barrier. The hard mask material layer may be formed of a dielectric material having etch selectivity relative to the conductive layer and the initial plug. The hard mask material layer may include silicon oxide or silicon nitride.

[0056] Subsequently, a bit line mask layer (not shown) can be formed on top of the hard mask material layer. The bit line mask layer can be formed of a material that has etching selectivity relative to the conductive layer and the hard mask material layer. The bit line mask layer may include a photosensitive layer pattern. The bit line mask layer can be formed by patterning methods such as SPT or DPT.

[0057] Subsequently, the hard mask material layer, conductive layer, and preliminary plug can be etched sequentially. This forms the bit line contact 21, bit line 22, and bit line hard mask 23. The stacked structure of bit line 22 and bit line hard mask 23 can be called the "bit line structure BL".

[0058] The linewidth of the bitline structure BL can be smaller than the diameter of the bitline contact hole BH. Therefore, a gap G can be formed in the peripheral region of the bitline contact 21. The gap G does not need to be a surrounding shape around the bitline contact 21, but can be formed independently on the two sidewalls of the bitline contact 21. Therefore, one bitline contact 21 and a pair of gaps G can be disposed in the bitline contact hole BH, and the pair of gaps G can be separated by the bitline contact 21. The bottom surface of the gap G can be disposed at the same level as the recessed upper surface of the first junction region 19. According to another embodiment of this disclosure, the bottom surface of the gap G can extend into the interior of the isolation layer 12. The bottom surface of the gap G can be disposed at a level lower than the recessed upper surface of the first junction region 19.

[0059] refer to Figures 3A to 3C Bit line spacers 24 can be formed on the two side walls of the bit line structure BL.

[0060] Bit line spacer 24 can extend along bit line structure BL in the second direction D2. Bit line spacer 24 can extend from bit line structure BL to bit line contact 21. Bit line spacer 24 can fill the gap G between bit line contact hole BH and bit line contact 21.

[0061] Bit line spacer 24 may include a single-layer structure or a multi-layer structure. Bit line spacer 24 may contain a dielectric material. For example, bit line spacer 24 may contain a combination of at least one of silicon oxide, silicon nitride, and low-k materials. Here, low-k material may refer to a material with a dielectric constant higher than that of silicon oxide and a dielectric constant lower than that of silicon nitride.

[0062] Subsequently, the hard mask layer 14 exposed between the bit line spacers 24 can be etched to form the memory node contact hole SH that exposes the second junction region 20.

[0063] The memory node contact hole SH can extend into the interior of the substrate 11. The bottom surface of the memory node contact hole SH can be positioned at a level lower than the upper surface of the bit line contact 21. Alternatively, the bottom surface of the memory node contact hole SH can be positioned at a level higher than the bottom surface of the bit line contact 21.

[0064] The storage node contact hole SH can have a linear shape extending along the second direction D2.

[0065] refer to Figures 4A to 4C A plug material layer 25A can be formed to fill the linear memory node contact holes SH. The plug material layer 25A can be formed to gap fill all linear memory node contact holes SH exposed by the bit line structure BL and the bit line spacer 24. The plug material layer 25A may include a conductive material. For example, the plug material layer 25A may include polysilicon.

[0066] refer to Figures 5A to 5C A mask pattern 26 can be formed on the plug material layer 25A and the bit line structure BL.

[0067] The mask pattern 26 may be a line extending along a first direction D1. The mask pattern 26 may be spaced apart in a second direction D2. The mask pattern 26 may include a dielectric material with etching selectivity relative to the plug material layer 25A and the bit line hard mask 23.

[0068] refer to Figures 6A to 6C It can etch the plug material layer 25A exposed by the mask pattern 26 (see Figure 5B The storage node contacts 25 are formed by forming a plug isolation portion IH between the storage node contacts 25. Each storage node contact 25 is electrically connected to the second junction region 20. The plug isolation portion IH can isolate the storage node contacts 25 in the second direction D2. The storage node contacts 25 can be island-shaped, separated by a bit line structure BL in the first direction D1, and separated by the plug isolation portion IH in the second direction D2.

[0069] When the etching process is performed to form the storage node contact 25, a natural oxide layer 27 can be formed on the sidewall.

[0070] Each memory node contact 25 may have a peak PK, which is formed due to incomplete etching at the corner where the mask pattern 26 and the bit line spacer 24 intersect. Specifically, the exposed surface may be small because it is blocked at the material boundary. Therefore, a peak may form due to insufficient etching as it approaches the bit line spacer 24.

[0071] refer to Figures 7A to 7C It can remove the natural oxide layer 27 (see Figure 6B The natural oxide layer 27 can be removed by a cleaning process CN. The cleaning process CN can be carried out using wet chemicals. For example, HF or BOE can be used as wet chemicals. However, the embodiments of this disclosure are not limited thereto, and all wet chemicals capable of removing the oxide layer can be applied.

[0072] Therefore, the sidewalls of each storage node contact 25 can be exposed.

[0073] By removing the native oxide layer 27 via a cleaning process and exposing the sidewalls of each storage node contact 25, subsequent oxidation processes can be performed smoothly. As a comparison, when subsequent processes are performed without a cleaning process, a potential problem is that the native oxide layer 27 may cover the storage node contact 25, preventing additional oxidation, or even if additional oxidation occurs, its thickness may be so thin that it is difficult to use as a spacer.

[0074] refer to Figures 8A to 8D Contact spacers 28 can be formed on the sidewall of each storage node contact 25.

[0075] Contact spacer 28 may refer to a portion of the surface of each storage node contact 25 that has been oxidized to a thickness. Contact spacer 28 can be formed by an oxidation process (OP). For example, the oxidation process may include an oxygen treatment process using O2 plasma.

[0076] According to another embodiment of this disclosure, the oxidation process may include a thermal oxidation process or a wet oxidation process utilizing H2O.

[0077] Because a portion of the surface of each storage node contact 25 is replaced by the contact spacer 28 during the oxidation process OP, the peak PK of each storage node contact 25 (see...) Figure 6A This can be mitigated or minimized. Specifically, the oxidation process (OP) can be performed on exposed surfaces that can react with oxygen, and more oxidation is likely to occur in areas with more exposed surface. Since the portion where the peak PK is set is etched less, it can have a larger surface area exposed to the outside. Therefore, more oxidation may occur there.

[0078] Therefore, refer to Figure 8D The thickness of the contact spacer 28 can increase as it approaches the corner where the mask pattern 26 and the bit line spacer 24 intersect. The thickness of the contact spacer 28 can increase from the center portion toward both ends. In the contact spacer 28, the thickness of the center portion can be less than the thickness at one end.

[0079] Specifically, according to embodiments of this disclosure, by applying an oxygen treatment process utilizing O2 plasma as an oxidation process, the process difficulty and cost can be reduced.

[0080] refer to Figures 9A to 9C This can form a plug isolation layer 29 that fills the plug isolation portion IH.

[0081] The plug isolation layer 29 can be formed by a process of filling the gaps in the plug isolation portion IH with a dielectric material. The plug isolation layer 29 can be formed by two or more gap-filling processes. Specifically, the plug isolation layer 29 can be formed by repeatedly performing the process of filling the gaps in the plug isolation portion IH with a dielectric material and etching the portion of the dielectric material on the upper part of the plug isolation portion IH.

[0082] According to another embodiment of this disclosure, the plug isolation layer 29 can be formed by a gap filling process performed once.

[0083] The plug isolation layer 29 may include a dielectric material. For example, the plug isolation layer 29 may include silicon nitride. According to another embodiment of this disclosure, the plug isolation layer 29 may include silicon oxide.

[0084] Contact spacer 28 and plug isolation layer 29 can be used to isolate storage node contact 25.

[0085] refer to Figures 10A to 10C Storage elements ME can be formed on each storage node contact 25.

[0086] The storage element ME may include a capacitor containing a storage node. The storage node may be cylindrical. Although not shown, a dielectric layer and plate-like nodes may also be formed on top of the storage node. The storage node may be cylindrical in shape other than cylindrical.

[0087] According to another embodiment of this disclosure, prior to forming the memory element ME, an interlayer dielectric layer including landing pads may also be included on each memory node contact 25.

[0088] According to embodiments of this disclosure, interference between adjacent storage nodes can be improved.

[0089] According to embodiments of this disclosure, the parasitic capacitance of the unit transistor can be reduced, and the sensing margin can be improved.

[0090] According to embodiments of this disclosure, the reliability of semiconductor devices can be improved.

[0091] While the present invention has been described in conjunction with specific embodiments, those skilled in the art will understand that various changes and modifications can be made without departing from the spirit and scope of the embodiments as defined in the claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; Multiple bit line structures are disposed on the semiconductor substrate; Island-shaped memory node contacts, which are spaced apart from each other between adjacent bit line structures in the plurality of bit line structures; Multiple plug isolation layers are disposed between the island-shaped storage node contacts; as well as A contact spacer is disposed between each of the storage node contacts and each of the plurality of plug isolation layers, each contact spacer having a different thickness at its center and at both ends.

2. The semiconductor device according to claim 1, wherein: The plurality of bit line structures are spaced apart from each other in a first direction; as well as Each of the plurality of bitline structures has a line shape extending along a second direction orthogonal to the first direction.

3. The semiconductor device according to claim 1, wherein, The island-shaped storage node contacts and the plurality of plug isolation layers are alternately arranged in the second direction.

4. The semiconductor device according to claim 1, wherein, The thickness of each contact spacer in the central portion is thinner than that at both ends.

5. The semiconductor device according to claim 1, wherein, Each contact spacer includes an oxide.

6. The semiconductor device according to claim 5, wherein, The oxide is obtained by oxidizing the surface of the island-shaped storage node contact.

7. The semiconductor device according to claim 1, wherein, The contact spacer comprises silicon oxide.

8. The semiconductor device according to claim 1, wherein, The plurality of plug isolation layers comprise silicon nitride.

9. The semiconductor device according to claim 1, further comprising: Bit line spacers are disposed between the plurality of bit line structures and the island-shaped memory node contacts.

10. The semiconductor device according to claim 9, wherein, The bit line spacers extend along the two sidewalls of each bit line structure.

11. The semiconductor device according to claim 1, further comprising: A buried gate structure disposed within the semiconductor substrate; as well as The first and second junction regions are separated from each other by the buried gate structure.

12. The semiconductor device according to claim 11, wherein, Each bitline structure is coupled to the first junction region, and each island memory node contact is coupled to the second junction region.

13. The semiconductor device according to claim 1, further comprising: Bit line contacts are suitable for coupling between the semiconductor substrate and the bit line structure.

14. The semiconductor device according to claim 1, further comprising: A storage element is located on and coupled to the island-shaped storage node contact.

15. A method for manufacturing a semiconductor device, the method comprising: Multiple bit line structures are formed on a semiconductor substrate; Island-shaped memory node contacts are formed between adjacent bit line structures in the plurality of bit line structures, spaced apart from each other. Convert the surface of each storage node contact into a contact spacer; and A plug isolation layer is formed to fill the gap between adjacent storage node contacts in the island-shaped storage node contacts.

16. The method according to claim 15, wherein, The island-shaped storage node contact includes: Bit line spacers are formed on the two sidewalls of each of the plurality of bit line structures; Storage node contact holes that expose the semiconductor substrate are formed between adjacent bit line structures in the plurality of bit line structures; A plug material layer is formed to fill the contact holes of the storage node; A mask pattern is formed over the plurality of bit line structures and the plug material layer; and The island-shaped storage node contacts are formed by etching the plug material layer.

17. The method of claim 15, further comprising: After forming the island-shaped storage node contacts, the native oxides formed on the sidewalls of the island-shaped storage node contacts are removed.

18. The method according to claim 15, wherein, Converting the surface of each storage node contact into the contact spacer includes subjecting the surface of the island-shaped storage node contact to an oxygen treatment process, a thermal oxidation process, or a wet oxidation process.

19. The method according to claim 15, wherein, The oxygen treatment process utilizes O2 plasma.

20. The method of claim 15, wherein, The thickness of the contact spacer at the center is thinner than that at both ends.

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