Semiconductor device, imaging device, radiation imaging system, apparatus, and semiconductor device manufacturing method

Abstract

The invention provides a semiconductor device, an imaging device, a radiation imaging system, an apparatus, and a semiconductor device manufacturing method. The semiconductor device includes: a semiconductor layer; an insulating layer stacked on the semiconductor layer; a conductive through hole penetrating through the semiconductor layer, extending into the insulating layer, and having a recess at an end portion of a side adjacent to the insulating layer; and a conductive connection member disposed in the insulating layer and having a side surface partially in contact with an inner side surface of the recess of the through hole. The portion of the side surface of the connecting member, which is in contact with the through hole, extends from the insulating layer side to the semiconductor layer side with respect to an extension line of an interface between the insulating layer and the semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, methods for manufacturing semiconductor devices, etc. Background Technology

[0002] JP2019-62183A discloses a technique for improving the reliability of an image sensor including an organic photoelectric conversion layer. The image sensor described in JP2019-62183A includes a contact hole penetrating a substrate and a lower contact plug penetrating a portion of an interlayer insulating layer and protruding into the contact hole. The lower contact plug protruding into the contact hole has a structure such that the lower contact plug contacts the contact hole only on the substrate side relative to the boundary surface between the substrate and the interlayer insulating layer.

[0003] In semiconductor devices, such as image sensors, it is necessary to reduce the resistance at the connection points between conductive components, such as holes and plugs. The image sensor described in JP2019-62183A has a structure in which the lower contact plug protrudes into the contact via only on the substrate side relative to the boundary between the substrate and the interlayer insulating layer, and there is a need for technology that can further reduce the resistance at the connection points. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor device includes: a semiconductor layer; an insulating layer stacked on the semiconductor layer; a conductive via penetrating the semiconductor layer and extending into the insulating layer, having a recess at an end adjacent to the insulating layer; and a conductive connecting member disposed in the insulating layer, having a side surface that partially contacts the inner side surface of the recess of the via. The portion of the side surface of the connecting member that contacts the via extends from the insulating layer side to the semiconductor layer side relative to an extension of the interface between the insulating layer and the semiconductor layer.

[0005] According to a second aspect of this disclosure, a method of manufacturing a semiconductor device includes: preparing a second substrate, the second substrate including a semiconductor layer on which semiconductor elements are formed, an element isolation region isolating the semiconductor elements, and an insulating layer configured to cover the semiconductor layer and the element isolation region; forming a first opening in the second substrate, the first opening penetrating the insulating layer and reaching a portion of the element isolation region; forming a conductive connection member by filling the first opening with a conductive material; forming a second opening in the second substrate, the second opening penetrating the semiconductor layer and the element isolation region, reaching a portion of the insulating layer, and exposing a portion of the connection member; and forming a conductive via by filling the second opening with the conductive material. An electrical connection structure is formed in which the via and the connection member engage with each other, the via penetrating the semiconductor layer, extending into the insulating layer, and having a recess at an end adjacent to the insulating layer, the connection member being disposed in the insulating layer and a portion of its side surface contacting the inner side surface of the recess of the via.

[0006] The features of this disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings. The following description of the embodiments is given by way of example. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view illustrating the stacked structure of the photoelectric conversion device according to the first embodiment.

[0008] Figure 2 This is a schematic enlarged cross-sectional view showing the vicinity of the connection between the through hole and the connecting member.

[0009] Figure 3 This is a schematic enlarged cross-sectional view showing the vicinity of the connection between the through hole and the connecting member in the first modified example.

[0010] Figure 4 This is a schematic enlarged cross-sectional view showing the vicinity of the connection between the through hole and the connecting member in the second modified example.

[0011] Figure 5 This is a schematic enlarged cross-sectional view showing the vicinity of the connection between the through hole and the connecting member in the third modified example.

[0012] Figure 6 It is a schematic cross-sectional view used to describe one stage of the process of manufacturing the first circuit board.

[0013] Figure 7 It is a schematic cross-sectional view used to describe the process of forming connecting components.

[0014] Figure 8 This is a schematic cross-sectional view used to describe the process of forming a wiring structure including the bonding electrode E12.

[0015] Figure 9 It is a schematic cross-sectional view used to describe the process of bonding the first circuit board and the sensor board.

[0016] Figure 10 This is a schematic cross-sectional view used to describe the process of thinning the second semiconductor substrate SL2SUB as needed to form the second semiconductor layer SL2.

[0017] Figure 11 It is a schematic cross-sectional view used to describe the formation process of the opening TH used to form the through hole.

[0018] Figure 12 It is a schematic cross-sectional view used to describe the process of forming an insulating film to cover the sidewalls of the opening TH.

[0019] Figure 13 It is a schematic cross-sectional view used to describe the process of filling the opening TH with conductive material to form a through hole.

[0020] Figure 14 This is a schematic cross-sectional view used to describe the process of forming the bonding electrode E21 on the through hole.

[0021] Figure 15 It is a schematic cross-sectional view used to describe the process of integrating three substrates (sensor substrate 11, first circuit substrate 21 and second circuit substrate 31).

[0022] Figure 16A This is a schematic diagram used to describe the device according to the second embodiment.

[0023] Figure 16B This is a schematic diagram illustrating an example of a photoelectric conversion system according to a second embodiment.

[0024] Figure 16C This is a schematic diagram illustrating an example of an in-vehicle photoelectric conversion system according to a second embodiment.

[0025] Figure 17A This is a schematic diagram illustrating an apparatus used as a radiation imaging system according to a third embodiment.

[0026] Figure 17B This is a schematic diagram illustrating the configuration of a transmission electron microscope used as a radiographic imaging system according to a third embodiment. Detailed Implementation

[0027] Semiconductor devices, methods of manufacturing semiconductor devices, etc., according to embodiments of the present disclosure will be described with reference to the accompanying drawings. The embodiments described below are merely examples, and detailed configurations can be appropriately modified and implemented by those skilled in the art without departing from the spirit of the present disclosure.

[0028] In the accompanying drawings referenced in the following embodiments and descriptions, unless otherwise stated, elements indicated by the same reference numerals have similar functions. In the drawings, where multiple identical elements are arranged, reference numerals and their descriptions may be omitted.

[0029] Furthermore, for ease of explanation and description, the accompanying drawings may be schematic; therefore, the shape, size, and arrangement of elements in the drawings may not strictly match the actual shape, size, and arrangement of elements. Additionally, unless otherwise stated, "above XX and below YY" or "XX to YY" indicating a numerical range means a numerical range including endpoints XX (lower limit) and YY (upper limit). When describing numerical ranges by stages, the upper and lower limits of each numerical range can be arbitrarily combined.

[0030] In the following description, for example, the +X direction indicates the same direction as indicated by the X-axis arrow in the illustrated orthogonal coordinate system, and the -X direction indicates a direction 180 degrees opposite to the direction indicated by the X-axis arrow in the illustrated orthogonal coordinate system. Additionally, the direction simply referred to as the X-direction is a direction parallel to the X-axis regardless of its difference from the direction indicated by the X-axis arrow. This also applies to directions other than the X-direction. In the following description, terms indicating specific directions or positions (such as "up," "down," "right," "left," and other terms including these terms) are used as needed. These terms are used to facilitate understanding of the embodiments with reference to the accompanying drawings, and the technical scope of this disclosure is not limited by the meaning of these terms.

[0031] In the following description, the terms “layer” and “film” may be used as in the same way as insulating layer and insulating film, but unless otherwise stated, these terms do not imply any technical difference.

[0032] The term "substantially equal" will be used in the following description. Even when the design relationships are equal, slight differences may occur due to manufacturing errors. The term "substantially equal" includes slight differences caused by such manufacturing errors. First Embodiment Configuration of photoelectric conversion device

[0033] The configuration of the photoelectric conversion device according to the first embodiment will be described with reference to the accompanying drawings. Figure 1This is a schematic cross-sectional view illustrating the stacked structure of the photoelectric conversion device according to the first embodiment. The photoelectric conversion device 100, as an example, is implemented as a stacked photoelectric conversion device. The photoelectric conversion device 100 can be, for example, a back-illuminated photoelectric conversion device, but the photoelectric conversion device according to this disclosure can be implemented as a front-illuminated photoelectric conversion device.

[0034] The photoelectric conversion device 100 is implemented by, for example, stacking multiple substrates including a sensor substrate 11, a first circuit substrate 21, and a second circuit substrate 31 and electrically connecting the multiple substrates.

[0035] Each substrate in the sensor substrate 11, the first circuit substrate 21, and the second circuit substrate 31 can be a chip cut from a wafer, but the substrate is not limited to a chip. For example, each substrate can be a wafer. Multiple substrates can be stacked in a wafer state and then cut, or multiple substrates can be cut into multiple chips and then the multiple chips can be stacked or bonded.

[0036] The sensor substrate 11 has a pixel array region in which a plurality of photoelectric conversion elements 201 are arranged. The sensor substrate 11 includes a first semiconductor layer SL1 having the photoelectric conversion elements 201 and an insulating layer IL11 having a multilayer wiring structure. The insulating layer IL11 may be formed as an interlayer insulating layer having a multilayer wiring structure electrically connected to the photoelectric conversion elements 201.

[0037] The first circuit board 21 includes a second semiconductor layer SL2, in which a plurality of semiconductor elements (e.g., transistors) included in a circuit such as a first signal processing unit are arranged, as well as element isolation regions 210 that isolate the semiconductor elements. Furthermore, the first circuit board 21 includes an insulating layer IL12 having a multilayer wiring structure and an insulating layer IL21 containing the wiring structure.

[0038] The insulating layer IL12 can be formed as an interlayer insulating layer having a multilayer wiring structure electrically connecting the sensor substrate 11 and the first signal processing unit. The insulating layer IL12 includes an insulating film 216 and an insulating layer 218. The insulating layer IL21 can be formed as an interlayer insulating layer having a wiring structure electrically connecting the first signal processing unit and the second circuit substrate 31. The insulating layers IL12 and IL21 are stacked on opposite sides of the second semiconductor layer SL2. The second semiconductor layer SL2 includes a silicide layer 211 at the interface with the insulating layer IL12 (insulating layer 218).

[0039] The first circuit board 21 includes a through-hole 219 configured to penetrate the second semiconductor layer SL2 to electrically connect a wiring pattern 217 formed in the insulating layer IL12 and wiring included in the second circuit board 31. The through-hole 219, made of a conductive material, penetrates at least a portion of the insulating layer IL21 and the second semiconductor layer SL2 and extends into at least a portion (interior) of the insulating layer IL12. The wiring pattern 217 and the through-hole 219 are connected by a connecting member 215 made of a conductive material. The connecting member 215 penetrates at least a portion of the insulating layer IL12 and extends into a recess in the through-hole 219. The connection between the through-hole 219 and the connecting member 215 and its surrounding structure are described in detail below.

[0040] The second circuit board 31 has a second circuit region in which circuits such as a second signal processing unit, a vertical scanning circuit, a horizontal scanning circuit, and a readout circuit are arranged. Furthermore, the second circuit board 31 includes a third semiconductor layer SL3 and an insulating layer IL22. The third semiconductor layer SL3 has multiple semiconductor elements (e.g., transistors) arranged in the circuits such as the second signal processing unit. The insulating layer IL22 has a multilayer wiring structure. The insulating layer IL22 may be formed as an interlayer insulating layer having a multilayer wiring structure electrically connected to the first circuit board 21.

[0041] A first insulating layer IL1 is inserted between a first semiconductor layer SL1 of the sensor substrate 11 and a second semiconductor layer SL2 of the first circuit substrate 21. In the first insulating layer IL1, insulating layers IL11 and IL12 are connected. A second insulating layer IL2 is inserted between a second semiconductor layer SL2 of the first circuit substrate 21 and a third semiconductor layer SL3 of the second circuit substrate 31. In the second insulating layer IL2, insulating layers IL21 and IL22 are connected.

[0042] The sensor substrate 11 and the first circuit substrate 21 are joined such that the first insulating layer IL11 and the insulating layer IL12 are adjacent to each other. At the junction between the sensor substrate 11 and the first circuit substrate 21, the bonding electrode E11 arranged in the insulating layer IL11 and the bonding electrode E12 arranged in the insulating layer IL12 form a metal bond, electrically and mechanically connecting the sensor substrate 11 and the first circuit substrate 21 to each other. That is, a wiring structure (electrical connection structure) is formed in the first insulating layer IL1 to electrically connect the photoelectric conversion element 201 formed in the first semiconductor layer SL1 to the first circuit region formed in the first circuit substrate 21.

[0043] The first circuit board 21 includes an insulating layer IL21 formed on the side of the semiconductor layer SL2 opposite to the insulating layer IL12. At the junction between the first circuit board 21 and the second circuit board 31, a bonding electrode E21 arranged in the insulating layer IL21 and a bonding electrode E22 arranged in the insulating layer IL22 form a metal bond, electrically and mechanically connecting the first circuit board 21 and the second circuit board 31 to each other. That is, a wiring structure (electrical connection structure) is formed in the second insulating layer IL2 to electrically connect the first circuit region formed in the first circuit board 21 and the second circuit region formed in the second circuit board 31. Through holes and connecting components

[0044] Next, the feature portion of this embodiment will be described, namely the structure for reducing the connection resistance between the through hole 219 and the connecting member 215. Figure 2 This is a schematic enlarged cross-sectional view showing the connection between the through hole 219 and the connecting member 215 and its vicinity. Figure 2 In the first circuit substrate 21 or the second semiconductor layer SL2, the main surface is parallel to the XY plane, and the normal direction relative to the main surface of the first circuit substrate 21 or the second semiconductor layer SL2 is the Z direction. Figure 2 The layered structure schematically shown can be confirmed by observing a cross-sectional sample of the photoelectric conversion device 100 or the first circuit board 21 using an appropriate analyzer or appropriate analytical method, such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

[0045] In the first circuit board 21, through-holes 219 and connecting members 215 electrically connect the wiring pattern 217 arranged in the insulating layer IL12 and the bonding electrode E21 arranged in the insulating layer IL21. The wiring pattern 217 can be formed of, for example, copper or aluminum, and can also be formed of other materials.

[0046] The via 219 can be formed of, for example, tungsten, and can also be formed of other conductive materials such as aluminum or copper. The via 219 can be formed as a double-layer structure comprising a conductive core material 2192 and a conductive cover material 2191 covering the core material 2192. The core material 2192, which serves as the center or base of the via 219, can be formed of a metallic material or other alloy material such as tungsten, aluminum, or copper, and the cover material 2191 can be formed as a barrier metal such as Ti or TiN.

[0047] A silicide layer 211 is formed on the surface of the second semiconductor layer SL2 on the +Z direction side (insulating layer IL12 side). A device isolation region 210 for isolating semiconductor devices can be disposed on the portion of the second semiconductor layer SL2 where the silicide layer 211 is not disposed. Although vias 219 need to be disposed while avoiding the silicide layer 211, as... Figure 2 The arrangement of via 219 as penetrating the component isolation region 210 is advantageous in terms of simplifying circuit layout and manufacturing process.

[0048] The connecting member 215, which connects the wiring pattern 217 and the through-hole 219 to each other, can be formed as a two-layer structure including a conductive core material 2152 and a conductive cover material 2151 covering the core material 2152. The core material 2152, which serves as the center or base of the connecting member 215, can be formed from a metallic material such as tungsten, aluminum, or copper, or other alloy materials, and the cover material 2151 can be formed as a barrier metal, such as Ti or TiN. The connecting member 215 can be, for example, a plug.

[0049] For ease of explanation, the dimension of the through hole 219 in the Z direction is called the height of the through hole 219, and the diameter of the through hole 219 in a section parallel to the XY plane is called the width of the through hole 219. The dimension of the connecting member 215 in the Z direction is called the height of the connecting member 215, and the diameter of the connecting member 215 in a section parallel to the XY plane is called the width of the connecting member 215.

[0050] By configuring the via 219 to be electrically connected to the wiring pattern 217 via the connecting member 215, the height of the via 219 can be reduced; in other words, the depth of the through-hole used to form the via 219 can be reduced. This facilitates the stable formation of the fine via 219. Furthermore, such a structure is advantageous because the wiring pattern 217 is not etched and damaged when the through-hole used to form the via 219 is formed by etching. To reduce the height of the via 219, the thickness of the second semiconductor layer SL2 can be less than the thickness of the other semiconductor layers. For example, the thickness of the second semiconductor layer SL2 can be less than the thickness of either the first semiconductor layer SL1 or the third semiconductor layer SL3.

[0051] The through hole 219 may have a tapered shape, with its width decreasing towards the connecting member. Similarly, the connecting member 215 may also have a tapered shape, with its width decreasing towards the through hole. At the connection between the through hole 219 and the connecting member 215, the width of the through hole 219 is greater than the width of the connecting member 215. This configuration reduces the requirements for alignment accuracy between the through hole 219 and the connecting member 215 during manufacturing.

[0052] A recessed portion in the -Z direction is formed at the upper end (end in the +Z direction) of the through hole 219, and the lower end (end in the -Z direction) of the connecting member 215 extends into the recessed portion, thereby firmly connecting the through hole 219 and the connecting member 215 to each other. That is, the side surface of the recessed portion of the through hole 219 and the side surface of the lower end of the connecting member 215 engage with each other, and the bottom surface of the recessed portion of the through hole 219 and the distal surface of the lower end of the connecting member 215 engage with each other.

[0053] As shown in the figure, in the normal direction (Z direction) relative to the main surface of the first circuit substrate 21 or the second semiconductor layer SL2, the upper end of the through hole 219 is located at P1, the boundary surface between the insulating layer IL12 and the second semiconductor layer SL2 is located at P2, and the lower end of the connecting member 215 is located at P3.

[0054] As can be clearly seen from the positional relationship between P1 and P2, the upper end of the via 219 is located closer to the insulating layer IL12 than the extension of the boundary between the insulating layer IL12 and the second semiconductor layer SL2. That is, the via 219 penetrates the second semiconductor layer SL2 and extends at least partially into the insulating layer IL12.

[0055] As can be seen from the positional relationship between P2 and P3, the lower end of the connecting member 215 is located on the side of the second semiconductor layer SL2 relative to the extension of the boundary surface between the insulating layer IL12 and the second semiconductor layer SL2. That is, the connecting member 215 penetrates a portion of the insulating layer IL12 and extends at least partially into the second semiconductor layer SL2.

[0056] According to this embodiment, the side surface of the recess of the through-hole 219 and the side surface of the lower end of the connecting member 215 are joined to each other over a wide area from P1 in the insulating layer IL12 to P3 in the second semiconductor layer SL2. That is, the side surfaces of the through-hole 219 and the connecting member 215 are joined to each other over a wide area to hold the boundary surface (P2) between the insulating layer IL12 and the second semiconductor layer SL2. In other words, the portion of the side surface of the connecting member 215 that contacts the through-hole 219 extends from the insulating layer IL12 to the semiconductor layer SL2 relative to the extension line of P2, where P2 is the interface between the insulating layer IL12 and the semiconductor layer SL2.

[0057] As described above, not only do the distal faces of the through hole 219 and the distal faces of the connecting member 215 engage with each other over a wide area, but the inner side surface of the recess of the through hole 219 and the side surface of the lower end portion of the connecting member 215 also engage with each other over a wide area. Therefore, according to this embodiment, conduction faults and resistance variations at the connection between the connecting member 215 and the through hole 219 can be significantly reduced.

[0058] The cover material 2151 included in the connecting member 215 can be formed, for example, by chemical vapor deposition (CVD), a film-forming technique (film-forming method) with low anisotropy in deposition rate. Furthermore, the cover material 2191 included in the via 219 can be formed, for example, by sputtering, a film-forming technique with high anisotropy in deposition rate (material orientation). According to this manufacturing method, the film thickness of each part can satisfy the relationships TB12>TB22>TS22 and TB12>TS12. TS12 is the thickness of the cover material 2151 on the side surface of the connecting member 215, and TB22 is the thickness of the cover material 2191 on the upper surface of the via 219, i.e., the portion in contact with the insulating layer 218. TS22 is the thickness of the cover material 2191 on the side surface of the via 219. TB12 is the total film thickness of the cover material 2151 and cover material 2191 on the bottom surface of the recess of the via 219. As an example, the film thickness TS12 can be from 5 nm to 30 nm, the film thickness TS22 can be from 5 nm to 60 nm, the film thickness TB22 can be from 5 nm to 90 nm, and the film thickness TB12 can be from 10 nm to 120 nm.

[0059] As described above, the connecting member 215 includes a conductive core material 2152 and a conductive covering material 2151 covering the core material 2152. The thickness TS12 of the covering material 2151 on the side of the covering core material 2152 is substantially equal to the thickness (TB12-TB22) of the covering material on the end face of the covering core material 2152 adjacent to the through hole 219. The through hole 219 includes a conductive core material 2192 and a conductive covering material 2191 covering the core material 2192. The thickness TS22 of the covering material 2191 on the side of the covering core material 2192 is less than the thickness TB22 of the covering material 2191 on the distal end face of the covering core material 2192 adjacent to the bottom surface of the insulating layer 218 or the recess.

[0060] The manufacturing methods and configurations of the covering material 2151 of the connecting member 215 and the covering material 2191 of the through hole 219 can be different. Modifications will be described below. First variation

[0061] Figure 3 This is a schematic enlarged cross-sectional view showing the connection between the through hole 219 and the connecting member 215 in the first modified example, and its vicinity. (The details will be omitted.) Figure 2 The embodiments shown are described in terms of common aspects.

[0062] The cover material 2151 included in the connecting member 215 is formed, for example, by CVD, a film-forming technique with small anisotropy in deposition rate. The cover material 2191 of the through-hole 219 is formed, for example, by CVD, a film-forming technique with small anisotropy in deposition rate. According to this manufacturing method, the film thickness of each part can satisfy the relationships TB13>TB23≈TS23 and TB13>TS13. TS13 is the thickness of the cover material 2151 on the side surface of the connecting member 215, and TB23 is the thickness of the cover material 2191 on the upper surface of the through-hole 219, i.e., the portion in contact with the insulating layer 218. TS23 is the thickness of the cover material 2191 on the side surface of the through-hole 219. TB13 is the total film thickness of the cover material 2151 and cover material 2191 on the bottom surface of the recess of the through-hole 219. As an example, the film thickness TS13 can be from 5 nm to 30 nm, the film thickness TS23 can be from 5 nm to 30 nm, the film thickness TB23 can be from 5 nm to 30 nm, and the film thickness TB13 can be from 10 nm to 60 nm. Second variation

[0063] Figure 4 This is a schematic enlarged cross-sectional view showing the connection between the through hole 219 and the connecting member 215 in the second modified example, and its vicinity. (The details will be omitted.) Figure 2 The description of common matters in the aspects shown.

[0064] The cover material 2151 of the connecting member 215 is formed by increasing the deposition rate (material orientation) in the Z direction, for example by sputtering, a film formation technique with anisotropic deposition rate. The cover material 2191 of the via 219 is formed by, for example, CVD, a film formation technique with small anisotropy in deposition rate. According to this manufacturing method, the film thickness of each part can satisfy the relationships TB14>TB24≈TS24 and TB14>TS14. TS14 is the thickness of the cover material 2151 on the side surface of the connecting member 215, and TB24 is the thickness of the cover material 2191 on the upper surface of the via 219, i.e., the portion in contact with the insulating layer 218. TS24 is the thickness of the cover material 2191 on the side surface of the via 219. TB14 is the total film thickness of the cover material 2151 and cover material 2191 on the bottom surface of the recess of the via 219. As an example, the film thickness TS14 can be 5nm to 60nm, the film thickness TS24 can be 5nm to 30nm, the film thickness TB24 can be 5nm to 30nm, and the film thickness TB14 can be 10nm to 120nm. Third variation

[0065] Figure 5This is a schematic enlarged cross-sectional view showing the connection between the through hole 219 and the connecting member 215 in the third modified example, and its vicinity. (The details will be omitted.) Figure 2 The description of common matters in the aspects shown.

[0066] The cover material 2151 of the connecting member 215 is formed by increasing the deposition rate in the Z direction, for example by sputtering, a film formation technique with anisotropic deposition rate. The cover material 2191 of the through-hole 219 is formed by increasing the deposition rate in the Z direction, for example by sputtering, a film formation technique with anisotropic deposition rate. According to this manufacturing method, the film thickness of each part can satisfy the relationship TB15>TB25>TS25 and TB15>TS15. TS15 is the thickness of the cover material 2151 on the side surface of the connecting member 215, and TB25 is the thickness of the cover material 2191 on the upper surface of the through-hole 219, i.e., the portion in contact with the insulating layer 218. TS25 is the thickness of the cover material 2191 on the side surface of the through-hole 219. TB15 is the total film thickness of the cover material 2151 and cover material 2191 on the bottom surface of the recess of the through-hole 219. As an example, the film thickness TS15 can be 5nm to 60nm, the film thickness TS25 can be 5nm to 60nm, the film thickness TB25 can be 5nm to 90nm, and the film thickness TB15 can be 10nm to 180nm. Manufacturing method

[0067] Reference Figures 6 to 15 A method for manufacturing a photoelectric conversion device according to this embodiment is described. Figures 6 to 15 This is a schematic cross-sectional view used to describe the various stages of the manufacturing process of a photoelectric conversion device. First, the first circuit board 21 will be described... Figure 1 The manufacturing process of ).

[0068] like Figure 6 As shown, for example, a device isolation region 210 with an oxide film embedded in a groove and a transistor including a silicide layer 211 are formed in a second semiconductor substrate SL2SUB for forming a second semiconductor layer SL2. Furthermore, an insulating layer 218 and an insulating film 216 are sequentially formed on the second semiconductor substrate SL2SUB. The insulating layer 218 may be, for example, a silicon nitride film. The insulating film 216 may be, for example, a silicon oxide film. The thickness of the insulating layer 218 may be from 10 nm to 100 nm. An insulating film (not shown) may be further formed between the insulating layer 218 and the second semiconductor substrate SL2SUB.

[0069] Next step, such as Figure 7As shown, the insulating film 216 is etched to form a first opening OP21 and a second opening OP22. The first opening OP21 penetrates the insulating layer 218 and reaches a predetermined depth in the component isolation region 210. Figure 2 (P3 in the middle), but adjust the etching conditions of the second opening OP22 so that etching stops at the location where the silicide layer 211 is exposed.

[0070] Subsequently, the first opening OP21 is filled with conductive material to form the connecting member 215, and the second opening OP22 is filled with conductive material to form the contact plug 230. Figure 1 Here, the connecting member 215 is formed to penetrate the insulating layer 218 and reach a predetermined depth in the component isolation region 210. Figure 2 (P3 in the text).

[0071] The connecting member 215 and the contact plug 230 can be formed of a barrier metal such as Ti or TiN and tungsten, and can also be formed of other materials such as aluminum or copper or combinations thereof. The connecting member 215 connected to the through hole 219 can be formed simultaneously with the contact plug 230 connected to the transistor, etc. Furthermore, after forming the first opening OP21, a second opening OP22 connected to the transistor, etc., can be formed to form the connecting member 215 and the contact plug 230.

[0072] At this point, it is desirable that the diameter of the first opening OP21 is equal to or greater than the diameter of the second opening OP22. Due to the circuit layout, it is desirable that the diameter of the second opening OP22, which is used to form the contact plug 230 connected to the transistor, is small. On the other hand, from the viewpoint of facilitating alignment with the through hole 219 to be connected later and reducing connection resistance, it is desirable that the diameter of the first opening OP21, which is used to form the connecting member 215, is equal to or greater than the diameter of the second opening OP22.

[0073] Next, as Figure 8 As shown, a wiring structure, further including a wiring layer, is formed on the connecting member 215 and the contact plug 230. In the uppermost layer of the wiring structure, the bonding electrode E12 is formed to expose the upper surface of the insulating layer IL12. In this way, a portion of the first circuit board 21 is formed.

[0074] Next, as Figure 9 As shown, a portion of the first circuit board 21 and the separately prepared sensor board 11 are joined together. Figure 9 In relation to Figure 8 The image is shown in a vertically reversed configuration. At this time, the bonding electrode E11 formed in the sensor substrate 11 and the bonding electrode E12 formed in the first circuit substrate 21 are bonded to each other, and the sensor substrate 11 and the first circuit substrate 21 are electrically and mechanically connected to each other.

[0075] Next, as Figure 10 As shown, the second semiconductor substrate SL2SUB is thinned as needed to form the second semiconductor layer SL2. Furthermore, an insulating layer IL21 is formed on the second semiconductor layer SL2.

[0076] Next step, such as Figure 11 As shown, an opening TH is formed. This is achieved by penetrating the insulating layer IL21, the second semiconductor layer SL2, and the device isolation region 210, and further excavating through etching. Figure 2 A portion of the insulating layer 218 to P1 is used to form the opening TH. A portion of the connecting member 215 protrudes from the insulating layer 218 at the bottom of the opening TH.

[0077] Next, as Figure 12 As shown, an insulating film is formed to cover the sidewalls of the opening TH. For example, the insulating film can be formed to cover the inner surface of the opening, and then the portion of the insulating film located at the bottom of the opening TH can be removed by using a back etching process or the like.

[0078] Next step, such as Figure 13 As shown, a reference is formed, for example, by filling the opening TH with a conductive material. Figure 2 The described via 219. That is, a via 219 is formed that penetrates the second semiconductor layer SL2 and connects to the connecting member 215. For example... Figure 2 As shown, the distal end of the via 219 is located at P1 in the insulating layer 218. For example, the via 219 can be formed of a barrier metal such as Ti or TiN and tungsten, or it can be formed of other materials such as aluminum or copper.

[0079] Next step, such as Figure 14 As shown, a bonding electrode E21 is formed on the via 219. Although not shown here, a wiring structure including a wiring layer may also be formed between the via 219 and the bonding electrode E21.

[0080] Next, as Figure 15 As shown, the separately prepared second circuit board 31 is bonded to Figure 14 The first circuit board 21 and the sensor board 11 formed in the process. Figure 15 In relation to Figure 14 The vertical inversion method is shown. At this time, the bonding electrode E21 of the first circuit substrate 21 and the bonding electrode E22 of the second circuit substrate 31 are bonded to each other, and the first circuit substrate 21 and the second circuit substrate 31 are electrically and mechanically connected to each other. As a result, the three substrates, including the sensor substrate 11, the first circuit substrate 21, and the second circuit substrate 31, are integrated and electrically and mechanically connected to each other. Thereafter, the first semiconductor layer SL1 is thinned as needed, and the process is completed. Figure 1 The photoelectric conversion device 100 shown.

[0081] According to the above manufacturing method, such as Figure 7 As shown, the connecting member 215 is formed to penetrate the insulating layer 218 and reach a predetermined depth in the component isolation region 210. Figure 2 (P3 in the text). Then, as... Figure 13 As shown, a through-hole 219 is formed, which penetrates the second semiconductor layer SL2, has a distal end located in the insulating layer 218, and is connected to the connecting member 215.

[0082] As a result, one end of the via 219 is located on the side of the insulating layer IL12 relative to the extension of the boundary surface between the insulating layer IL12 and the second semiconductor layer SL2. That is, the via 219 penetrates the second semiconductor layer SL2 and extends at least partially into the insulating layer IL12.

[0083] One end of the connecting member 215 is located on the second semiconductor layer SL2 side relative to the extension of the boundary surface between the insulating layer IL12 and the second semiconductor layer SL2. That is, the connecting member 215 penetrates a portion of the insulating layer IL12 and extends at least partially into the second semiconductor layer SL2.

[0084] According to this embodiment, the inner side surface of the recess of the through-hole 219 and the side surface of the end of the connecting member 215 are joined to each other over a wide area from P1 in the insulating layer IL12 to P3 in the second semiconductor layer SL2. In other words, the side surfaces of the through-hole 219 and the connecting member 215 are joined to each other over a wide area to hold the boundary surface (P2) between the insulating layer IL12 and the second semiconductor layer SL2. As described above, not only are the bottom surface of the recess of the through-hole 219 and the distal end surface of the end of the connecting member 215 joined to each other over a wide area, but the inner side surface of the recess of the through-hole 219 and the side surface of the end of the connecting member 215 are also joined to each other over a wide area. Therefore, in this embodiment, the connection resistance at the connection between the connecting member 215 and the through-hole 219 can be reduced, and the occurrence of conductivity failures and resistance changes can be significantly reduced. Second Embodiment

[0085] As a second embodiment, an apparatus including a semiconductor device (solid-state camera device) according to the above embodiments will be described. Figure 16A This is a schematic diagram illustrating an apparatus 9191 including the semiconductor device 930 according to the above embodiments. The apparatus 9191 including the semiconductor device 930 will be described in detail.

[0086] Semiconductor device 930 includes semiconductor device 910, in which a first chip serving as a photoelectric conversion device and a second chip including at least one of memory circuitry and logic circuitry are integrated. In addition to semiconductor device 910, semiconductor device 930 may also include package 920 for housing semiconductor device 910. Package 920 may include a substrate to which semiconductor device 910 is fixed and a cover such as glass facing semiconductor device 910. Package 920 may also include bonding members such as bonding wires or bumps for connecting terminals disposed on the substrate and terminals disposed on semiconductor device 910.

[0087] Device 9191 may include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, shutter, or mirror disposed corresponding to the semiconductor device 930, and includes an optical system for guiding light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an application-specific integrated circuit (ASIC).

[0088] Processing device 960 processes signals output from semiconductor device 930. Processing device 960 is a semiconductor device such as a central processing unit (CPU) or ASIC used to configure an analog front-end (AFE) or digital front-end (DFE). Display device 970 is an EL display device or liquid crystal display device that displays information (images) obtained by semiconductor device 930. Storage device 980 is a magnetic or semiconductor device that stores information (images) obtained by semiconductor device 930. Storage device 980 is volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM), or non-volatile memory such as flash memory or hard disk drive.

[0089] Mechanical device 990 includes a movable unit or propulsion unit such as a motor or engine. In device 9191, signals output from semiconductor device 930 are displayed on display device 970 or transmitted to the outside via a communication device (not shown) included in device 9191. Therefore, device 9191 may also include a storage device 980 and a processing device 960, separate from the storage and processing circuits of semiconductor device 930. Mechanical device 990 can be controlled based on signals output from semiconductor device 930.

[0090] Furthermore, device 9191 is suitable for electronic devices such as information terminals with camera functionality (e.g., smartphones or wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, camcorders, or surveillance cameras). Mechanical devices 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, mechanical devices 990 in the camera can move the semiconductor device 930 for vibration-damping operation.

[0091] Furthermore, device 9191 can be a transportation device such as a vehicle, ship, or aircraft. The mechanical device 990 within the transportation device can function as a mobile device. Device 9191, used as a transportation device, is suitable for transporting the semiconductor device 930 and for assisting and / or automating driving (steering) via camera functionality. The processing device 960 for assisting and / or automating driving (steering) can perform processing for operating the mechanical device 990, which functions as a mobile device, based on information obtained from the semiconductor device 930. Alternatively, device 9191 can be a medical device such as an endoscope, a measuring device such as a distance measurement sensor, an analytical device such as an electron microscope, an office device such as a photocopier, or an industrial device such as a robot. According to the above embodiment, since the resistance at the connection between conductive components such as holes and plugs is reduced in the imaging element or circuit section, images with good characteristics can be stably acquired.

[0092] Therefore, if the semiconductor device 930 according to this embodiment is used in the device 9191, the value of the device can also be increased. For example, when the semiconductor device 930 is installed on a transport device and performs external imaging or external environment measurement, excellent performance can be obtained. Therefore, when manufacturing and selling transport devices, it is advantageous to determine that the semiconductor device according to this embodiment is installed on the transport device to enhance the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained by the semiconductor device to perform driving assistance and / or automatic driving of the transport device. The implementation in vehicles, ships, aircraft, etc. is not limited to devices actually used for transportation purposes, but can also be suitably applied to drones, etc., that perform aerial imaging for various purposes (including inspecting buildings and agricultural facilities, monitoring natural phenomena, etc.).

[0093] Reference Figure 16B and Figure 16C This embodiment describes a photoelectric conversion system and a moving body. Figure 16BAn example of a photoelectric conversion system associated with a vehicle-mounted camera is shown. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device used as the electronic component described in the above embodiments. The photoelectric conversion system 8 includes: an image processing unit 801 that performs image processing on multiple image data acquired by the photoelectric conversion device 80; and a disparity acquisition unit 802 that calculates disparity (phase difference of the disparity image) from the multiple image data acquired by the photoelectric conversion system 8. Furthermore, the photoelectric conversion system 8 includes: a distance acquisition unit 803 that calculates the distance to a target object based on the calculated disparity; and a collision determination unit 804 that determines the possibility of a collision based on the calculated distance. Here, the disparity acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition units that acquire distance information to a target object. That is, the distance information is information about disparity, defocus, distance to the target object, etc. The collision determination unit 804 can determine the possibility of a collision by using any of these distance information. The distance information acquisition unit can be implemented by dedicated hardware or by a software module. Alternatively, the distance information acquisition unit can be implemented using a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or the like.

[0094] The photoelectric conversion system 8 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Additionally, the photoelectric conversion system 8 is connected to the electronic control unit (ECU) 820, which is a control device that outputs control signals to generate braking force on the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to a warning device 830, which issues a warning to the driver based on the judgment result of the collision judgment unit 804. For example, if the collision judgment unit 804 indicates a high probability of collision, the control ECU 820 controls the vehicle to avoid a collision and reduce damage by applying brakes, reversing the accelerator, or reducing engine output. The warning device 830 warns the user by emitting warnings such as sounds, displaying warning information on a screen such as a car navigation system, or providing vibrations to the seat belt or steering wheel.

[0095] In this embodiment, the photoelectric conversion system 8 captures images of the vehicle's surroundings (e.g., the area in front of or behind the vehicle). Figure 16C The photoelectric conversion system is shown in the case of capturing images of an area in front of the vehicle (camera range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. With this configuration, the accuracy of distance measurement can be further improved.

[0096] The above description has described examples of control to prevent collisions with other vehicles; however, this technology is also applicable to autonomous driving control such as following other vehicles and maintaining lane departure. Furthermore, the photoelectric conversion system is not limited to vehicles such as automobiles, but can be applied to mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. Moreover, this technology can be applied not only to mobile bodies but also to devices that widely utilize object recognition, such as Intelligent Transportation Systems (ITS). According to the above embodiments, images with good characteristics can be stably acquired. Third Embodiment

[0097] As a third embodiment, reference will be made to Figure 17A and Figure 17B An example of a radiation imaging system is described, in which the semiconductor device described in the first embodiment is used as a radiation detector, and the radiation detector is incorporated into the radiation imaging system.

[0098] Figure 17A A device EQP is shown for use as a radiation imaging system including a radiation detector 1000. In addition to the imaging element 101 (a photoelectric conversion element capable of detecting radiation) which is a semiconductor device, the radiation detector 1000 also includes a package PKG for mounting the imaging element 101.

[0099] The package PKG may include: a substrate to which the imaging element 101 is fixed; a cover, such as glass, facing the imaging element 101; and connecting members, such as bonding wires or bumps, connecting terminals disposed on the substrate and terminals disposed on the imaging element 101. The imaging element 101 includes a pixel array 102 and a peripheral region surrounding the pixel array 102, in which pixels 103 are arranged in a matrix. Peripheral circuitry (e.g., vertical scan circuitry and DFE) may be provided in the peripheral region.

[0100] The device EQP may also include at least one of the following: an optical system OPT, a control unit CTRL, a processing unit PRCS, a display unit DSPL, a storage unit MMRY, and a mechanical device MCHN. The optical system OPT forms an image of radiation on the radiation detector 1000 and is, for example, a lens, shutter, or mirror. The optical system OPT can form an image of a particle beam, such as an electron beam or a proton beam, on the radiation detector 1000, depending on the type of radiation to be processed. The control unit CTRL controls the radiation detector 1000 and is, for example, an ASIC. The processing unit PRCS processes the signals output from the radiation detector 1000 and is a device such as a CPU or ASIC for configuring the analog front-end (AFE) or digital front-end (DFE). The display unit DSPL is an electroluminescent (EL) display device or a liquid crystal display device that displays information obtained by the radiation detector 1000 in the form of a visual image. The storage unit MMRY is a magnetic or semiconductor device that stores information obtained by the radiation detector 1000. Storage devices (MMRY) are volatile memory such as SRAM or DRAM, or non-volatile memory such as flash memory or hard disk drives. Mechanical devices (MCHN) include movable units such as motors.

[0101] The device EQP displays the signal output from the radiation detector 1000 on the display device DSPL, or transmits the signal to an external device via a communication device (not shown) included in the device EQP. Therefore, the device EQP may also include a storage device MMRY and a processing device PRCS, separate from the storage and processing circuits of the radiation detector 1000. The mechanical device MCHN can be controlled based on the signal output from the radiation detector 1000.

[0102] Figure 17A The device EQP shown can be a medical device such as an endoscope or radiological diagnostic equipment, a measuring device such as a distance measuring sensor, or an analytical device such as an electron microscope.

[0103] Figure 17B This is a schematic diagram illustrating the configuration of a transmission electron microscope (TEM) as an example of an EQP device. The EQP device used as an electron microscope includes an electron beam source 1202 (electron gun), an application lens 1204, a vacuum chamber 1201 (scope tube), an objective lens 1206, a magnifying lens system 1207, and a camera 1209 serving as a radiation detector 1000.

[0104] An electron beam 1203, an energy beam emitted from an electron beam source 1202 (radiation source), is focused by an application lens 1204 and applied to a sample S, which serves as an analytical target (imaging target) held by a sample holder. The space through which the electron beam 1203 passes is formed by a vacuum chamber 1201 (lens barrel), and this space is maintained in a vacuum. A radiation detector 1000 is arranged to face the vacuum space through which the electron beam 1203 passes. The electron beam 1203, which transmits through the sample S, is magnified by an objective lens 1206 and a magnifying lens system 1207 and projected onto the radiation detector 1000. The electron optical system used to apply the electron beam to the sample S is called the application optical system, and the electron optical system used to form an image of the electron beam transmitting through the sample S on the radiation detector 1000 is called the imaging optical system.

[0105] Electron beam source 1202 is controlled by electron beam source control device 1211. Application lens 1204 is controlled by application lens control device 1212. Objective lens 1206 is controlled by objective lens control device 1213. Magnifying lens system 1207 is controlled by magnifying lens system control device 1214. Sample holder control mechanism 1205 is controlled by holder control device 1215, which controls the drive mechanism of the sample holder.

[0106] The electron beam 1203 transmitted through the sample S is detected by the direct electron detector 1200 of the camera 1209. The output signal from the direct electron detector 1200 is processed by the signal processing unit 1216 and the image processing unit 1218, which serve as processing devices PRCS, to generate an image signal. The generated image signal (transmission electron image) is displayed on the image display monitor 1220 and the analysis monitor 1221, which correspond to the display device DSPL.

[0107] Camera 1209 is disposed at the bottom of device EQP. Camera 1209 includes direct electronic detector 1200. Direct electronic detector 1200 corresponds to imaging element 101. Direct electronic detector 1200 is disposed in camera 1209 such that at least a portion of camera 1209 is exposed to the vacuum space formed by vacuum chamber 1201.

[0108] Each of the devices in the electron beam source control device 1211, the application lens control device 1212, the objective lens control device 1213, the magnifying lens system control device 1214, and the holder control device 1215 is connected to the image processing device 1218. Therefore, they can exchange data to set the imaging conditions of the electron microscope. For example, the electron beam application rate can be set to 0.5 electron / pix / frm (electron / pixel / frame) or less. In this case, the electron beam source control device 1211 and the image processing device 1218 act as control units for controlling the radiation application rate. The drive control of the sample holder and the observation conditions of each lens can be set via signals from the image processing device 1218.

[0109] The operator prepares the sample S to be imaged and sets the imaging conditions using the input device 1219 connected to the image processing device 1218. Predetermined data is input to each of the electron beam source control device 1211, the application lens control device 1212, the objective lens control device 1213, and the magnifying lens system control device 1214 to obtain the desired acceleration voltage, magnification, and observation mode. Additionally, the operator inputs conditions such as the number of consecutive field-of-view images, the imaging start position, and the moving speed of the sample holder to the image processing device 1218 using the input device 1219, such as a mouse, keyboard, or touch panel. Alternatively, the image processing device 1218 can automatically set the conditions, independent of operator input. The radiation imaging system described in the embodiments is merely an example, and the semiconductor device described in the first embodiment can be applied to other systems. Modified embodiments

[0110] This disclosure is not limited to the above embodiments and variations, and many modifications can be made within the technical concept of this disclosure. For example, all or some of the different embodiments and variations described above can be combined and implemented.

[0111] For example, the semiconductor device described in the embodiments can be applied to detectors using single-photon avalanche diodes (SPADs) and camera systems including such detectors.

[0112] The applications of the semiconductor devices described in the embodiments are not limited to photography. For example, the semiconductor devices described in the embodiments are also applicable to distance measuring devices (devices for focus detection, distance measurement using time-of-flight (TOF), etc.), light measuring devices (devices for measuring incident light, etc.).

[0113] The photoelectric conversion device disclosed herein is not limited to a specific form and can be, for example, any of a front-illuminated sensor and a back-illuminated sensor. Alternatively, the photoelectric conversion device can be a stacked photoelectric conversion device, in which semiconductor chips including light-receiving units and semiconductor chips including electrical circuits such as logic circuits are stacked.

[0114] Various types of devices, including semiconductor devices according to embodiments, are also included in the embodiments of this disclosure. A device according to this embodiment may have at least one of six devices: an optical device corresponding to the semiconductor device, a control device for controlling the semiconductor device, a processing device for processing information obtained from the semiconductor device, a display device for displaying the information obtained from the semiconductor device, a storage device for storing the information obtained from the semiconductor device, and a mechanical device for operating based on the information obtained from the semiconductor device.

[0115] According to this disclosure, a technique can be provided that is beneficial for reducing the resistance at the connection between conductive components such as holes and plugs in a semiconductor device. (Other embodiments)

[0116] While this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. A semiconductor device comprising: Semiconductor layer; An insulating layer, which is stacked on the semiconductor layer; A conductive via penetrating the semiconductor layer and extending into the insulating layer, having a recess at its end adjacent to the insulating layer; and A conductive connecting member is disposed in the insulating layer and has a side portion that contacts the inner side surface of the recess in the through-hole. Wherein, the portion of the side of the connecting member that contacts the through hole extends from the insulating layer side to the semiconductor layer side relative to the extension line of the interface between the insulating layer and the semiconductor layer.

2. The semiconductor device according to claim 1, further comprising: The first substrate includes a first semiconductor layer and a first insulating layer. The insulating layer and the semiconductor layer are included in the second substrate, and The first substrate and the second substrate are bonded to each other, such that the first insulating layer and the insulating layer are adjacent to each other.

3. The semiconductor device according to claim 2, wherein, The first semiconductor layer includes a photoelectric conversion element, and the second substrate includes circuitry for processing signals output from the first substrate.

4. The semiconductor device according to claim 1, further comprising: The third substrate includes a third semiconductor layer and a third insulating layer. The insulating layer and the semiconductor layer are included in a second substrate, the second substrate further comprising a second insulating layer formed on the semiconductor layer on the side opposite to the insulating layer, and The third substrate and the second substrate are bonded to each other, such that the second insulating layer and the third insulating layer are adjacent to each other.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The through-hole includes a first core material with electrical conductivity, and The first covering material is conductive and covers the first core material.

6. The semiconductor device according to claim 5, wherein, The thickness of the first covering material covering the side surface of the first core material is substantially equal to the thickness of the first covering material covering the bottom surface of the recess of the first core material.

7. The semiconductor device according to claim 5, wherein, The thickness of the first covering material covering the side surface of the first core material is less than the thickness of the first covering material covering the bottom surface of the recess of the first core material.

8. The semiconductor device according to any one of claims 1 to 4, wherein, The connecting member includes a conductive second core material and a conductive second covering material, the second covering material covering the second core material.

9. The semiconductor device according to claim 8, wherein, The thickness of the second covering material covering the side of the second core material is substantially equal to the thickness of the second covering material covering the end face of the second core material on the side adjacent to the through hole.

10. The semiconductor device according to claim 8, wherein, The thickness of the second covering material covering the side of the second core material is less than the thickness of the second covering material covering the end face of the second core material on the side adjacent to the through hole.

11. A camera device comprising: The semiconductor device according to any one of claims 1 to 10; as well as An optical device corresponding to the semiconductor device.

12. A radiation imaging system, comprising: The semiconductor device according to any one of claims 1 to 10; as well as It is configured as a radiation source to apply radiation to the camera target.

13. An apparatus comprising a semiconductor device according to any one of claims 1 to 10 and a device selected from the group consisting of: Optical devices corresponding to the semiconductor device; A control device that controls the semiconductor device; A processing device that processes information obtained from the semiconductor device; A display device that displays information obtained from the semiconductor device; A storage device that stores information obtained from the semiconductor device; as well as A mechanical device that operates based on information obtained from the semiconductor device.

14. A method for manufacturing a semiconductor device, comprising: Prepare a second substrate, the second substrate including a semiconductor layer on which semiconductor elements are formed, an element isolation region that isolates the semiconductor elements, and an insulating layer configured to cover the semiconductor layer and the element isolation region; A first opening is formed in the second substrate, the first opening penetrating the insulating layer and reaching a portion of the element isolation region; A conductive connecting member is formed by filling the first opening with a conductive material; A second opening is formed in the second substrate, the second opening penetrating the semiconductor layer and the element isolation region, reaching a portion of the insulating layer, and exposing a portion of the connection member; as well as A conductive through-hole is formed by filling the second opening with the conductive material. The via and the connecting member are connected to each other in an electrical connection structure. The via penetrates the semiconductor layer, extends into the insulating layer, and has a recess at its end on the side adjacent to the insulating layer. The connecting member is disposed in the insulating layer and a portion of its side surface contacts the inner side surface of the recess of the via.

15. The method for manufacturing a semiconductor device according to claim 14, wherein, The portion of the side of the connecting member that contacts the through hole extends from the insulating layer side to the semiconductor layer side relative to the extension line of the interface between the insulating layer and the semiconductor layer.

16. The semiconductor device manufacturing method according to claim 14, further comprising: Prepare a first substrate comprising a first semiconductor layer and a first insulating layer; as well as The second substrate and the first substrate are bonded together such that the first insulating layer and the insulating layer are adjacent to each other.

17. The semiconductor device manufacturing method according to claim 14, further comprising: Prepare a third substrate comprising a third semiconductor layer and a third insulating layer; as well as The third substrate and the second substrate are bonded together such that the second insulating layer and the third insulating layer are adjacent to each other. The second substrate includes a second insulating layer formed on the semiconductor layer on the side opposite to the insulating layer.

18. The method for manufacturing a semiconductor device according to any one of claims 14 to 17, wherein, The formation of the through hole includes: A first conductive covering material is formed in the second opening; and A first core material with conductivity is formed in the second opening where the first covering material is formed.

19. The method for manufacturing a semiconductor device according to claim 18, wherein, In the formation of the first covering material The first covering material is formed such that the thickness of the first covering material covering the side of the first core material is substantially equal to the thickness of the first covering material covering the end face of the first core material on the side adjacent to the insulating layer.

20. The method for manufacturing a semiconductor device according to claim 18, wherein, In the formation of the first covering material The first covering material is formed such that the thickness of the first covering material covering the side of the first core material is less than the thickness of the first covering material covering the end face of the first core material on the side adjacent to the insulating layer.

21. The method for manufacturing a semiconductor device according to any one of claims 14 to 17, wherein, The formation of the connecting member includes: A second covering material is formed in the first opening; and A second core material with conductivity is formed in the first opening where the second covering material is formed.

22. The semiconductor device manufacturing method according to claim 21, wherein, In the formation of the second covering material The second covering material is formed such that the thickness of the second covering material covering the side of the second core material is substantially equal to the thickness of the second covering material covering the end face of the second core material on the side adjacent to the through hole.

23. The semiconductor device manufacturing method according to claim 21, wherein, In the formation of the second covering material The second covering material is formed such that the thickness of the second covering material covering the side of the second core material is less than the thickness of the second covering material covering the end face of the second core material on the side adjacent to the through hole.

Images