Display panel and display device

Abstract

The display panel comprises a first thin film transistor and a capacitor which are located in a pixel opening area, the capacitor comprises at least three electrode plates which are stacked and arranged at intervals, and the first thin film transistor and the capacitor are arranged on the basis of the face, close to an anode, of a substrate. The difference between the height of the first thin film transistor and the height of the capacitor is smaller than 4500 angstroms. Through the arrangement of the at least three layers of polar plates, the capacitance is improved, the terrain of the capacitance area is raised, the terrain of the first thin film transistor and the terrain of the capacitor tend to be similar, and the flatness of the pixel opening area is improved.

Description

[0001] This application is a divisional application. The original application has the application number 202510122905.4 and the original application date is January 24, 2025. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0003] In an organic light-emitting display panel printed with inkjet ink, the flatness of the pixel aperture area of ​​the driving backplane determines the uniformity of the film layer after ink curing. In addition, due to the increase in the resolution of the display panel, the area of ​​the compensation capacitor is reduced, thereby reducing the capacitance of the compensation capacitor. Furthermore, due to the increase in the resolution of the display panel, the driving thin-film transistor and the compensation capacitor are located in the pixel aperture area, so the terrain of the driving thin-film transistor and the compensation capacitor will affect the flatness of the pixel aperture area. Summary of the Invention

[0004] This application provides a display panel and a display device that can improve the capacitance of capacitors and the flatness of the pixel aperture area.

[0005] This application provides a display panel, which includes: substrate; A first thin-film transistor is disposed on the substrate; A capacitor is disposed on the substrate and located on one side of the first thin-film transistor; An anode is disposed on the side of the first thin-film transistor and the capacitor away from the substrate; and A pixel definition layer is disposed on the side of the anode away from the substrate, and the pixel definition layer has pixel openings that expose the anode; The first thin-film transistor and the capacitor respectively partially overlap with the anode. The capacitor includes at least three stacked and spaced-apart plates. With the side of the substrate closest to the anode as a reference, the difference in height between the first thin-film transistor and the capacitor is less than 4500 angstroms.

[0006] Optionally, in some embodiments of this application, the display panel further includes a light-shielding portion, a buffer layer and an interlayer dielectric layer, the first thin-film transistor includes a first active portion, a first gate insulating portion, a first gate, a first electrode and a second electrode, and the capacitor includes a first electrode plate, a second electrode plate and a third electrode plate; The first electrode plate is disposed in the same layer as the light-shielding part, the buffer layer covers the first electrode plate and the light-shielding part, the second electrode plate is disposed in the same layer as the first active part, the first gate insulating part is disposed on the side of the first active part away from the substrate, the first gate is disposed on the side of the first gate insulating part away from the substrate, the interlayer dielectric layer covers the first gate and the capacitor, and the first electrode and the second electrode are disposed on the side of the interlayer dielectric layer away from the substrate. In the thickness direction of the display panel, the third electrode plate is located on one side of the first electrode plate, and the one of the first electrode plate and the second electrode plate that is farther away from the third electrode plate is electrically connected to the third electrode plate.

[0007] Optionally, in some embodiments of this application, the display panel further includes a first insulating layer and a transition portion. The first insulating layer covers the first gate and the second electrode plate. The third electrode plate is disposed on the side of the first insulating layer away from the substrate. The interlayer dielectric layer covers the first insulating layer and the third electrode plate. The transition portion, the first electrode, and the second electrode are disposed in the same layer. The transition portion connects the first electrode plate and the third electrode plate.

[0008] Optionally, in some embodiments of this application, in the display panel viewed from above, the light-shielding portion is connected to the first electrode plate, the second electrode plate is spaced apart from the first active portion, the second electrode plate includes a connected first sub-portion and a second sub-portion, the first sub-portion extends along a first direction, the second sub-portion extends along a second direction intersecting the first direction, the first sub-portion is located on the side of the first active portion in the second direction, the second sub-portion is located on the side of the first active portion in the first direction, and both the first sub-portion and the second sub-portion overlap with the first electrode plate.

[0009] Optionally, in some embodiments of this application, in the display panel viewed from above, the third electrode plate includes a third sub-part and a fourth sub-part connected together, the third sub-part extending along a first direction, the fourth sub-part extending along a second direction intersecting the first direction, the third sub-part overlapping the first sub-part, and the fourth sub-part overlapping the second sub-part.

[0010] Optionally, in some embodiments of this application, in the display panel viewed from above, the adapter covers a portion of the fourth sub-part and at least a portion of the third sub-part, and the adapter is connected to the second electrode.

[0011] Optionally, in some embodiments of this application, the display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The second active portion is disposed on the side of the buffer layer away from the substrate, the second gate insulating portion is disposed on the side of the second active portion away from the substrate, the second gate is disposed on the side of the second gate insulating portion away from the substrate, the first insulating layer and the interlayer dielectric layer sequentially cover the second gate, and the third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

[0012] Optionally, in some embodiments of this application, the first gate insulation portion includes a first sublayer and a second sublayer stacked together; The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a protective portion, a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The protective portion is disposed on the side of the buffer layer away from the substrate. The second active portion is disposed on the side of the protective portion away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The first insulating layer and the interlayer dielectric layer sequentially cover the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

[0013] Optionally, in some embodiments of this application, the display panel further includes a first insulating layer and a transition portion, the third electrode plate is disposed on the side of the first electrode plate near the substrate, the first insulating layer covers the third electrode plate and the substrate, the buffer layer covers the first insulating layer, the transition portion is disposed in the same layer as the first electrode on the side of the interlayer dielectric layer away from the substrate, and the transition portion connects the second electrode plate and the third electrode plate.

[0014] Optionally, in some embodiments of this application, the display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The second active portion is disposed on the side of the buffer layer away from the substrate, the second gate insulating portion is disposed on the side of the second active portion away from the substrate, the second gate is disposed on the side of the second gate insulating portion away from the substrate, the interlayer dielectric layer sequentially covers the second gate, and the third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

[0015] Optionally, in some embodiments of this application, the first gate insulation portion includes a first sublayer and a second sublayer stacked together; The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a protective portion, a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The protective portion is disposed on the side of the buffer layer away from the substrate. The second active portion is disposed on the side of the protective portion away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The interlayer dielectric layer covers the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

[0016] Optionally, in some embodiments of this application, the display panel further includes a first planarization layer and a second planarization layer that sequentially cover the first thin-film transistor and the capacitor, wherein the anode is disposed on the side of the second planarization layer away from the substrate.

[0017] Accordingly, this application also provides a display device, which includes a display panel as described in any of the above embodiments.

[0018] The display panel and display device of this application embodiment include a first thin-film transistor and a capacitor located in the pixel aperture region. The capacitor includes at least three stacked and spaced-apart plates. With the side of the substrate closest to the anode as a reference, the height difference between the first thin-film transistor and the capacitor is less than 4500 angstroms. By using at least three layers of plates, this application not only increases the capacitance but also raises the terrain of the capacitor region, making the topography of the first thin-film transistor and the capacitor more similar, thus improving the flatness of the pixel aperture region. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application; Figure 2 This is a partial top view of the display panel provided in an embodiment of this application; Figure 3 yes Figure 2 A schematic diagram of the film layer containing the central light-shielding section and the first electrode plate; Figure 4 Based on Figure 3 A planar schematic diagram of the film layer containing the first active part and the second electrode plate is added; Figure 5 Based on Figure 4 A planar schematic diagram of the film layer containing the first gate electrode; Figure 6 Based on Figure 5 A planar schematic diagram of the membrane layer containing the third electrode plate; Figure 7 Based on Figure 6 A planar schematic diagram of the membrane layer containing the first electrode, the second electrode, and the transition section is added; Figure 8 This is another structural schematic diagram of the display panel provided in the embodiments of this application; Figure 9 This is another structural schematic diagram of the display panel provided in the embodiments of this application; Figure 10 This is another structural schematic diagram of the display panel provided in the embodiments of this application; Figure 11 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0021] This application provides a display panel and a display device, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0022] Please refer to Figure 1 and Figure 2 This application provides a display panel 100, which includes a substrate 101, a first thin-film transistor t1, a capacitor c1, an anode 201 and a pixel definition layer 202.

[0023] A first thin-film transistor t1 is disposed on a substrate 101. A capacitor c1 is disposed on the substrate 101 and located on one side of the first thin-film transistor t1. An anode 201 is disposed on the side of the first thin-film transistor t1 and the capacitor c1 away from the substrate 101. A pixel definition layer 202 is disposed on the side of the anode 201 away from the substrate 101, and the pixel definition layer 202 has a pixel opening 2a that exposes the anode 201.

[0024] The first thin-film transistor t1 and the capacitor c1 partially overlap with the anode 201. The capacitor c1 includes at least three stacked and spaced electrodes. With the side of the substrate 101 closest to the anode 201 as a reference, the height difference gd between the first thin-film transistor t1 and the capacitor c1 is less than 4500 angstroms.

[0025] The display panel 100 of this application embodiment includes a first thin film transistor t1 and a capacitor c1 located in the pixel opening 2a region. By setting at least three electrode plates, this application not only increases the capacitance but also raises the terrain of the capacitor c1 region, so that the terrain difference between the first thin film transistor t1 and the capacitor c1 is less than 4500 angstroms and the two tend to be similar, thereby improving the flatness of the pixel opening 2a region.

[0026] It is understandable that, in the thickness direction of the display panel 100, the height difference gd between the first thin-film transistor t1 and the capacitor c1 is less than 4500 angstroms. For example, the height difference between the two is 4400 angstroms, 4300 angstroms, 4200 angstroms, 4100 angstroms, 4000 angstroms, 3900 angstroms, 3800 angstroms, 3700 angstroms, 3600 angstroms, 3500 angstroms, 3400 angstroms, 3300 angstroms, 3200 angstroms, 3100 angstroms, 3000 angstroms, 2900 angstroms, 2800 angstroms, 2700 angstroms, 2600 angstroms, 2500 angstroms. 00 angstroms, 2400 angstroms, 2300 angstroms, 2200 angstroms, 2100 angstroms, 2000 angstroms, 1900 angstroms, 1800 angstroms, 1700 angstroms, 1600 angstroms, 1500 angstroms, 1400 angstroms, 1300 angstroms, 1200 angstroms, 1100 angstroms, 1000 angstroms, 900 angstroms, 800 angstroms, 700 angstroms, 600 angstroms, 500 angstroms, 400 angstroms, 300 angstroms, 200 angstroms, 10 angstroms or 0 angstroms.

[0027] It is understandable that the more layers of plates capacitor C1 has, the higher its elevation, and the closer it is to the elevation of the first thin-film transistor t1, resulting in a higher flatness of the pixel opening 2a region.

[0028] The first thin-film transistor t1 serves as the driving thin-film transistor and is located in the display area. The first thin-film transistor t1 is connected to the anode 201.

[0029] Optionally, the display panel 100 further includes a light-emitting functional layer disposed on the anode 201. The light-emitting functional layer is formed by multiple layers including one or more emitting layers, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. When the light-emitting functional layer includes all of the above layers, the hole injection layer may be located on the anode 201, and the hole transport layer, emitting layer, electron transport layer, and electron injection layer may be sequentially laminated on the hole injection layer.

[0030] Optionally, in some embodiments of this application, the display panel 100 further includes a light-shielding portion 102, a buffer layer 103, and an interlayer dielectric layer 109. The first thin-film transistor t1 includes a first active portion 104, a first gate insulating portion 105, a first gate 106, a first electrode 107, and a second electrode 108. The capacitor c1 includes a first electrode c01, a second electrode c02, and a third electrode c03.

[0031] The first electrode plate c01 is disposed in the same layer as the light-shielding portion 102. A buffer layer 103 covers the first electrode plate c01 and the light-shielding portion 102. The second electrode plate c02 is disposed in the same layer as the first active portion 104. A first gate insulating portion 105 is disposed on the side of the first active portion 104 away from the substrate 101. A first gate electrode 106 is disposed on the side of the first gate insulating portion 105 away from the substrate 101. An interlayer dielectric layer 109 covers the first gate electrode 106 and the capacitor c1. A first electrode 107 and a second electrode 108 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0032] In the thickness direction of the display panel 100, the third electrode plate c03 is located on one side of the first electrode plate c01, and the one of the first electrode plate c01 and the second electrode plate c02 that is farther away from the third electrode plate c03 is electrically connected to the third electrode plate c03.

[0033] Understandably, the conductive film layer of the first thin-film transistor t1 is relatively thick, thus significantly affecting its topography. Therefore, the first electrode c01 is disposed on the same layer as the light-shielding portion 102, and the second electrode c02 is disposed on the same layer as the first active portion 104 to offset the topography difference between the two conductive film layers. Furthermore, the capacitor c1 uses a third electrode c03 to offset the topography difference of the first gate 106 of the first thin-film transistor t1, thereby reducing the height difference between the first thin-film transistor t1 and the capacitor c1 and improving flatness.

[0034] Optionally, in some embodiments of this application, the display panel 100 further includes a first planarization layer 111 and a second planarization layer 112 that sequentially cover the first thin-film transistor t1 and the capacitor c1, with the anode 201 disposed on the side of the second planarization layer 112 away from the substrate 101.

[0035] It is understandable that the planarization layer has a certain degree of leveling, and due to the process limitations of existing equipment, there is an upper limit to the leveling of the terrain by a single planarization layer. Therefore, based on the fact that the terrain height difference between the first thin-film transistor t1 and the capacitor c1 is less than 4500 angstroms, the embodiments of this application compensate for the terrain height difference between the first thin-film transistor t1 and the capacitor c1 by setting a first planarization layer 111 and a second planarization layer 112, thereby improving the flatness of the pixel opening 2a region and thus improving the flatness of the anode 201.

[0036] Optionally, in some embodiments, based on the terrain height difference gd between the first thin-film transistor t1 and the capacitor c1 being less than or equal to 2600 angstroms, embodiments of this application improve the flatness of the pixel opening 2a region by setting a first flattening layer 111 and a second flattening layer 112 to completely level the terrain height difference between the first thin-film transistor t1 and the capacitor c1, thereby improving the flatness of the anode 201.

[0037] In some embodiments, the display panel 100 further includes a third planarization layer 113, which is disposed on the side of the second planarization layer 112 away from the substrate 101. It is understood that in the pixel opening 2a region, in addition to the terrain where the first thin-film transistor t1 and capacitor c1 are disposed, there is also a terrain formed by stacked inorganic insulating layers. The inorganic stacked terrain formed by the inorganic insulating layers is lower than the terrain of the first thin-film transistor t1, making it impossible for the first planarization layer 111 and the second planarization layer 112 to fully compensate for the height difference between the first thin-film transistor t1 and the inorganic stacked terrain. Therefore, this embodiment of the application provides a third planarization layer 113 to further compensate for the height difference between the first thin-film transistor t1 and the inorganic stacked terrain, thereby improving the flatness of the pixel opening 2a region and consequently improving the flatness of the anode 201.

[0038] Optionally, the inorganic stacked terrain includes a buffer layer 103 and an interlayer dielectric layer 109.

[0039] Optionally, in some embodiments of this application, the display panel 100 further includes a first insulating layer 114 and a transition portion 115. The first insulating layer 114 covers the first gate electrode 106 and the second electrode 02. The third electrode 03 is disposed on the side of the first insulating layer 114 away from the substrate 101. An interlayer dielectric layer 109 covers the first insulating layer 114 and the third electrode 03. The transition portion 115, the first electrode 107, and the second electrode 108 are disposed in the same layer, and the transition portion 115 connects the first electrode 01 and the third electrode 03.

[0040] It is understandable that the third electrode plate c03 is placed on the side of the second electrode plate c02 away from the substrate 101, so that the transition part 115 is closer to the third electrode plate c03, in order to reduce the depth of the via.

[0041] Optionally, the adapter 115 is connected to the third electrode 03 through a first via g1, and the second electrode 108 is connected to the first active part 104 through another first via g1. The adapter 115 is connected to the first electrode 01 through a second via g2.

[0042] Optionally, the thicknesses of the first gate 106 and the third electrode c03 are equal, the thicknesses of the first active portion 104 and the second electrode c02 are the same, and the thicknesses of the light-shielding portion 102 and the first electrode c01 are equal, but this is not limited to these. For example, the thickness of the first gate 106 can be less than the thickness of the third electrode c03, the thicknesses of the first active portion 104 and the second electrode c02 can be the same, and the thicknesses of the light-shielding portion 102 and the first electrode c01 can be equal, in order to further reduce the topographic height difference between the first thin-film transistor t1 and the capacitor c1.

[0043] Optionally, in some embodiments, the light-shielding part 102 and the first electrode plate c01 are formed using the same photomask, and the second electrode plate c02 and the first active part 104 are formed using the same photomask.

[0044] Optional, please refer to Figures 2 to 7 In some embodiments of this application, in the display panel 100 viewed from above, the light-shielding portion 102 is connected to the first electrode plate c01, and the second electrode plate c02 is spaced apart from the first active portion 104. The second electrode plate c02 includes a first sub-portion c21 and a second sub-portion c22 connected together. The first sub-portion c21 extends along a first direction F1, and the second sub-portion c22 extends along a second direction F2 intersecting the first direction F1. The first sub-portion c21 is located on one side of the first active portion 104 in the second direction F2, and the second sub-portion c22 is located on one side of the first active portion 104 in the first direction F1. Both the first sub-portion c21 and the second sub-portion c22 overlap with the first electrode plate c01.

[0045] Optionally, the first direction F1 is perpendicular to the second direction F2, but it is not limited to this; for example, the first direction F1 and the second direction F2 may not be perpendicular and may intersect. Optionally, the second direction F2 is the extension direction of the data line d1.

[0046] It is understandable that the light-shielding part 102 and the first electrode plate c01 are connected to form a whole, which not only reduces the manufacturing difficulty, but also is equivalent to increasing the layout area of ​​the first electrode plate c01.

[0047] Secondly, the first sub-part c21 and the second sub-part c22 are connected to form a shape that semi-encloses the first active part 104, which increases the overlap area of ​​the second electrode c02 and the first electrode c01 in a limited space, thereby increasing the capacitance of the capacitor c1 and raising the area of ​​the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0048] Optionally, in some embodiments of this application, in the display panel 100 viewed from above, the third electrode plate c03 includes a third sub-part c33 and a fourth sub-part c34 connected together. The third sub-part c33 extends along a first direction F1, and the fourth sub-part c34 extends along a second direction F2 intersecting the first direction F1. The third sub-part c33 overlaps with the first sub-part c21, and the fourth sub-part c34 overlaps with the second sub-part c22.

[0049] Understandably, the third sub-part c33 of the third electrode c03 overlaps with the first sub-part c21, and the fourth sub-part c34 of the third electrode c03 overlaps with the second sub-part c22. This increases the overlap area of ​​the second electrode c02 and the third electrode c03 within a limited space, thereby increasing the capacitance of capacitor c1 and raising the area of ​​the pixel opening 2a region to better provide flatness to the pixel opening 2a region.

[0050] Optionally, in some embodiments of this application, in the display panel 100 viewed from above, the adapter 115 covers a portion of the fourth sub-part c34 and at least a portion of the third sub-part c33. The adapter 115 is connected to the second electrode 108.

[0051] Understandably, by having the adapter 115 cover the portion of the third electrode plate c03, the influence of the signal line on the side of capacitor c1 furthest from the substrate 101 on capacitor c1 can be reduced. Secondly, by having the adapter 115 cover the third electrode plate c03, the topography of the capacitor c1 region is increased, thereby reducing the height difference between the first thin-film transistor t1 region and capacitor c1 and improving flatness.

[0052] Optionally, in some embodiments of this application, the adapter 115 extends beyond the third electrode c03 and the second electrode c02. The extended portion 15a of the adapter 115 is connected to the second electrode 108. The extended portion 15a of the adapter 115 is connected to the second electrode 108 to form a compensation electrode c04, and the compensation electrode c04 and the light-shielding portion 102 are partially overlapped to form a compensation capacitor.

[0053] Understandably, the compensation plate c04 and the light-shielding part 102 form a compensation capacitor, which can not only increase the capacitance of capacitor c1, but also increase the area of ​​the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0054] Optionally, in some embodiments of this application, the second electrode plate c02 further includes a first protrusion c23 connecting the intersection of the first sub-part c21 and the second sub-part c22 and near the first active part 104, the first protrusion c23 overlapping the first electrode plate c01. The third electrode plate c03 further includes a second protrusion c35 connecting the intersection of the third sub-part c33 and the fourth sub-part c34 and near the first active part 104, the second protrusion c35 overlapping the first protrusion c23.

[0055] Understandably, the arrangement of the first protrusion c23 and the second protrusion c35 not only increases the capacitance of capacitor c1, but also raises the area of ​​the pixel opening 2a region to better provide flatness to the pixel opening 2a region.

[0056] Optionally, in some embodiments, the display panel 100 further includes a connecting portion 116 disposed on the same layer as the adapter portion 115 and spaced apart. The connecting portion 116 connects the first gate 106 and the second electrode plate c02 through the third via g3.

[0057] Optionally, in some embodiments of this application, the display panel 100 further includes a second thin-film transistor t2 located in the gate driving circuit region. The second thin-film transistor t2 includes a second active portion 121, a second gate insulating portion 122, a second gate 123, a third electrode 124, and a fourth electrode 125. The second active portion 121 is disposed on the side of the buffer layer 103 away from the substrate 101. The second gate insulating portion 122 is disposed on the side of the second active portion 121 away from the substrate 101. The second gate 123 is disposed on the side of the second gate insulating portion 122 away from the substrate 101. The first insulating layer 114 and the interlayer dielectric layer 109 sequentially cover the second gate 123. The third electrode 124 and the fourth electrode 125 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0058] Optionally, the second active portion 121 and the first active portion 104 are disposed on the same layer and formed using the same photomask. The second gate insulating portion 122 and the first gate insulating portion 105 are disposed on the same layer and formed using the same photomask. The second gate 123 and the first gate 106 are disposed on the same layer and formed using the same photomask. The third electrode 124, the fourth electrode 125, the first electrode 107 and the second electrode 108 are disposed on the same layer and formed using the same photomask.

[0059] The display panel 100 also includes an outer peripheral trace 131 located in the gate drive circuit region. The outer peripheral trace 131 is located on the side of the second thin-film transistor t2 away from the substrate 101. The outer peripheral trace 131 is electrically connected to the second thin-film transistor t2.

[0060] Optionally, the display panel 100 further includes a passivation layer 110 covering the first electrode 107, the second electrode 108, the third electrode 124, and the fourth electrode 125, and a first planarization layer 111 covering the passivation layer 110. A peripheral trace 131 is disposed on the side of the first planarization layer 111 away from the substrate 101. A second planarization layer 112 covers the peripheral trace 131 and the first planarization layer 111.

[0061] The gate drive circuit area is located on the outer peripheral trace 131 to reduce the bezel width. One outer peripheral trace 131 is connected to the second gate 123, and another outer peripheral trace 131 is connected to the fourth electrode 125.

[0062] Optionally, the outer peripheral trace 131 connecting the second gate 123 is a clock signal line, and the outer peripheral trace connecting the fourth electrode 125 is a power supply line or a reset signal line.

[0063] Optionally, the display panel 100 further includes a line-changing section 132 located in the display area. The line-changing section 132 and the outer peripheral trace 131 are disposed on the same layer of the first planarization layer 111 on the side away from the substrate 101. The second electrode 108 of the first thin-film transistor t1 is connected to the anode 201 through the line-changing section 132.

[0064] Figure 8 This is a schematic diagram illustrating another structural design of the display panel 100 according to an embodiment of this application. Figure 8 The following will describe the parts that differ from the above embodiments in order to avoid redundancy.

[0065] exist Figure 8 In some embodiments of this application, the first gate insulation portion 105 includes a first sublayer 051 and a second sublayer 052 stacked together.

[0066] The display panel 100 also includes a second thin-film transistor t2 located in the gate driving circuit region. The second thin-film transistor t2 includes a protective portion 120, a second active portion 121, a second gate insulating portion 122, a second gate 123, a third electrode 124, and a fourth electrode 125. The protective portion 120 is disposed on the side of the buffer layer 103 away from the substrate 101. The second active portion 121 is disposed on the side of the protective portion 120 away from the substrate 101, the second gate insulating portion 122 is disposed on the side of the second active portion 121 away from the substrate 101, the second gate 123 is disposed on the side of the second gate insulating portion 122 away from the substrate 101, the first insulating layer 114 and the interlayer dielectric layer 109 sequentially cover the second gate 123, and the third electrode 124 and the fourth electrode 125 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0067] It should be noted that, Figure 8 The display panel 100 in the corresponding embodiment differs from the one described above in that the first gate insulating portion 105 includes a first sublayer 051 and a second sublayer 052 stacked together, and the second thin-film transistor t2 further includes a protective portion 120. The carrier mobility of the first thin-film transistor t1 is less than that of the second thin-film transistor t2.

[0068] Optionally, the first sublayer 051 and the protective portion 120 are formed using the same photomask process, and both have the same material and thickness. The second sublayer 052 and the second gate insulating portion 122 are formed using the same photomask process, and both have the same material and thickness.

[0069] in, Figure 8 The planar layout structure of the display panel 100 in the corresponding embodiment is similar to or the same as the planar layout structure of the display panel 100 in the above embodiment. For details, please refer to... Figures 2 to 7 The explanation will not be repeated here.

[0070] Figure 9 This is a schematic diagram illustrating yet another structural configuration of the display panel 100 according to an embodiment of this application. Figure 9 The following will describe the parts that differ from the above embodiments in order to avoid redundancy.

[0071] exist Figure 9 In some embodiments of this application, the display panel 100 further includes a first insulating layer 114 and a transition portion 115. A third electrode plate c03 is disposed on the side of the first electrode plate c01 near the substrate 101. The first insulating layer 114 covers the third electrode plate c03 and the substrate 101. A buffer layer 103 covers the first insulating layer 114. The transition portion 115 is disposed in the same layer as the first electrode 107 on the side of the interlayer dielectric layer 109 away from the substrate 101, and the transition portion 115 connects the second electrode plate c02 and the third electrode plate c03.

[0072] Optionally, the adapter 115 is connected to the second electrode plate c02 through the first through hole g1, and the adapter 115 is connected to the third electrode plate c03 through the second through hole g2.

[0073] Compared to the display panel 100 in the above embodiments, Figure 9 In the corresponding embodiment, the display panel 100 places the third electrode plate c03 on the side of the first electrode plate c01 near the substrate 101 to save overhead wiring space and facilitate wiring. That is, the third electrode plate c03 is placed on the side of the first electrode plate c01 closest to the substrate 101. Figure 1 The film layer containing the third electrode plate c03 is transferred to the side of the film layer containing the light-shielding part 102 that is closer to the substrate 101.

[0074] Optionally, in some embodiments of this application, the display panel 100 further includes a second thin-film transistor t2 located in the gate driving circuit region. The second thin-film transistor t2 includes a second active portion 121, a second gate insulating portion 122, a second gate 123, a third electrode 124, and a fourth electrode 125. The second active portion 121 is disposed on the side of the buffer layer 103 away from the substrate 101. The second gate insulating portion 122 is disposed on the side of the second active portion 121 away from the substrate 101. The second gate 123 is disposed on the side of the second gate insulating portion 122 away from the substrate 101. An interlayer dielectric layer 109 sequentially covers the second gate 123, and the third electrode 124 and the fourth electrode 125 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0075] Optionally, the second active part 121, the second electrode plate c02, and the first active part 104 are disposed on the same layer and formed using the same photomask. The second gate insulating part 122 and the first gate insulating part 105 are disposed on the same layer and formed using the same photomask. The second gate 123 and the first gate 106 are disposed on the same layer and formed using the same photomask. The third electrode 124, the fourth electrode 125, the first electrode 107, and the second electrode 108 are disposed on the same layer and formed using the same photomask.

[0076] The display panel 100 also includes an outer peripheral trace 131 located in the gate drive circuit area. The outer peripheral trace 131 is located on the side of the second thin film transistor t2 away from the substrate 101 and is electrically connected to the second thin film transistor t2.

[0077] The gate drive circuit area is located on the outer peripheral trace 131 to reduce the bezel width. One outer peripheral trace 131 is connected to the second gate 123, and another outer peripheral trace 131 is connected to the fourth electrode 125. Optionally, the outer peripheral trace 131 connected to the second gate 123 is a clock signal line, and the outer peripheral trace connected to the fourth electrode 125 is a power supply line or a reset signal line.

[0078] Optionally, the third electrode, c03, can be a black electrode to enhance the overall black effect.

[0079] It should be noted that, Figure 9 The planar structure of the light-shielding part 102, the first electrode plate c01, the second electrode plate c02, the third electrode plate c03, and the transition part 115 in the corresponding embodiment is similar to or the same as the planar structure of the light-shielding part 102, the first electrode plate c01, the second electrode plate c02, the third electrode plate c03, and the transition part 115 corresponding to the display panel 100 in the above embodiment. The difference lies in that the first electrode plate c01 is spaced between the third electrode plate c03 and the second electrode plate c02, and the third electrode plate c03 and the second electrode plate c02 overlap with the first electrode plate c01 to form a capacitor c1. Furthermore, the transition part 115 connects the second electrode plate c02 and the third electrode plate c03. Since the third electrode plate c03 is below the first electrode plate c01, compared to the above embodiment, Figure 9 In a corresponding embodiment, the third electrode plate c03 further extends into a contact portion that extends beyond the first electrode plate c01, and the contact portion is connected to the adapter portion 115. The first electrode plate c01 is electrically connected to the first gate 106.

[0080] Figure 10 This is a schematic diagram illustrating yet another structural configuration of the display panel 100 according to an embodiment of this application. Figure 10 The following will describe the parts that differ from the above embodiments in order to avoid redundancy.

[0081] exist Figure 10 In some embodiments of this application, the first gate insulation portion 105 includes a first sublayer 051 and a second sublayer 052 stacked together.

[0082] The display panel 100 also includes a second thin-film transistor t2 located in the gate drive circuit region. The second thin-film transistor t2 includes a protective portion 120, a second active portion 121, a second gate insulating portion 122, a second gate 123, a third electrode 124, and a fourth electrode 125. The protective portion 120 is disposed on the side of the buffer layer 103 away from the substrate 101. The second active portion 121 is disposed on the side of the protective portion 120 away from the substrate 101. The second gate insulating portion 122 is disposed on the side of the second active portion 121 away from the substrate 101. The second gate 123 is disposed on the side of the second gate insulating portion 122 away from the substrate 101. An interlayer dielectric layer 109 covers the second gate 123. The third electrode 124 and the fourth electrode 125 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0083] Optionally, the first sublayer 051 and the protective portion 120 are formed using the same photomask process, and both have the same material and thickness. The second sublayer 152 and the second gate insulating portion 122 are formed using the same photomask process, and both have the same material and thickness.

[0084] The display panel 100 also includes an outer peripheral trace 131 located in the gate drive circuit area. The outer peripheral trace 131 is located on the side of the second thin film transistor t2 away from the substrate 101 and is electrically connected to the second thin film transistor t2.

[0085] Please refer to Figure 11 Accordingly, this application also provides a display device 1000, which includes a display panel 100 as described in any of the above embodiments.

[0086] The display device 1000 of this application embodiment includes a first thin-film transistor t1 and a capacitor c1 located in the pixel opening 2a region. The capacitor c1 includes at least three stacked and spaced-apart plates. With the side of the substrate 101 closest to the anode 201 as a reference, the height difference between the first thin-film transistor t1 and the capacitor c1 is less than 4500 angstroms. By configuring at least three layers of plates, this application not only increases the capacitance but also raises the terrain of the capacitor c1 region, making the topography of the first thin-film transistor t1 and the capacitor c1 more similar, thus improving the flatness of the pixel opening 2a region.

[0087] It should be noted that the structure of the display panel 100 of the display device 1000 in this application embodiment is similar to or the same as the structure of the display panel 100 described in the above embodiments. For details, please refer to... Figures 1 to 10 The explanation is already given, so it will not be repeated here.

[0088] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: substrate; A first thin-film transistor is disposed on the substrate; A capacitor is disposed on the substrate and located on one side of the first thin-film transistor; the capacitor includes a first electrode plate, a second electrode plate and a third electrode plate. In the thickness direction of the display panel, the first electrode plate, the second electrode plate and the third electrode plate are disposed in pairs in different layers. The third electrode plate is located on one side of the first electrode plate. The one of the first electrode plate and the second electrode plate that is farther away from the third electrode plate is electrically connected to the third electrode plate. The anode is disposed on the side of the first thin-film transistor and the capacitor away from the substrate; as well as A pixel definition layer is disposed on the side of the anode away from the substrate, and the pixel definition layer has pixel openings that expose the anode; Wherein, the first thin-film transistor and the capacitor respectively partially overlap with the anode, the capacitor includes at least three stacked and spaced plates, and with the side of the substrate closest to the anode as a reference, the difference between the height of the first thin-film transistor and the height of the capacitor is less than 4500 angstroms; In the display panel viewed from above, the third electrode plate includes a third sub-part and a fourth sub-part connected together. The third sub-part extends along a first direction, and the fourth sub-part extends along a second direction intersecting the first direction. The third sub-part and the fourth sub-part are respectively disposed overlapping the second electrode plate.

2. The display panel according to claim 1, characterized in that, The first thin-film transistor includes a first active portion, and the third electrode plate further includes a second protrusion connecting the intersection of the third sub-part and the fourth sub-part and close to the first active portion, the second protrusion being disposed overlapping the second electrode plate.

3. The display panel according to claim 2, characterized in that, The display panel further includes a light-shielding portion, a buffer layer, and an interlayer dielectric layer; the first thin-film transistor includes a first gate insulating portion, a first gate, a first electrode, and a second electrode; and the capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate is disposed in the same layer as the light-shielding part, the buffer layer covers the first electrode plate and the light-shielding part, the second electrode plate is disposed in the same layer as the first active part, the first gate insulating part is disposed on the side of the first active part away from the substrate, the first gate is disposed on the side of the first gate insulating part away from the substrate, the interlayer dielectric layer covers the first gate and the capacitor, and the first electrode and the second electrode are disposed on the side of the interlayer dielectric layer away from the substrate. In the thickness direction of the display panel, the third electrode plate is located on one side of the first electrode plate, and the one of the first electrode plate and the second electrode plate that is farther away from the third electrode plate is electrically connected to the third electrode plate.

4. The display panel according to claim 3, characterized in that, The display panel further includes a first insulating layer and a transition portion. The first insulating layer covers the first gate and the second electrode plate. The third electrode plate is disposed on the side of the first insulating layer away from the substrate. The interlayer dielectric layer covers the first insulating layer and the third electrode plate. The transition portion, the first electrode and the second electrode are disposed in the same layer. The transition portion connects the first electrode plate and the third electrode plate.

5. The display panel according to claim 3, characterized in that, In the display panel viewed from above, the light-shielding portion is connected to the first electrode plate, and the second electrode plate is spaced apart from the first active portion. The second electrode plate includes a connected first sub-part and a second sub-part. The first sub-part extends along a first direction, and the second sub-part extends along a second direction intersecting the first direction. The first sub-part is located on the side of the first active portion in the second direction, and the second sub-part is located on the side of the first active portion in the first direction. Both the first sub-part and the second sub-part overlap with the first electrode plate.

6. The display panel according to claim 5, characterized in that, The third sub-part overlaps with the first sub-part, and the fourth sub-part overlaps with the second sub-part.

7. The display panel according to claim 6, characterized in that, In the display panel viewed from above, the second electrode plate further includes a first protrusion connecting the intersection of the first sub-part and the second sub-part and close to the first active part. The first protrusion overlaps with the first electrode plate, and the second protrusion overlaps with the first protrusion.

8. The display panel according to claim 6, characterized in that, In the display panel viewed from above, the adapter connecting the first electrode plate and the third electrode plate covers a portion of the fourth sub-part and at least a portion of the third sub-part. The adapter and the second electrode plate are disposed in different layers, and the adapter is connected to the second electrode.

9. The display panel according to claim 4, characterized in that, The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The second active portion is disposed on the side of the buffer layer away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The first insulating layer and the interlayer dielectric layer sequentially cover the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

10. The display panel according to claim 4, characterized in that, The first gate insulation portion includes a first sublayer and a second sublayer stacked together; The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a protective portion, a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The protective portion is disposed on the side of the buffer layer away from the substrate. The second active portion is disposed on the side of the protective portion away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The first insulating layer and the interlayer dielectric layer sequentially cover the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

11. The display panel according to claim 3, characterized in that, The display panel further includes a first insulating layer and a connecting portion. The third electrode plate is disposed on the side of the first electrode plate close to the substrate. The first insulating layer covers the third electrode plate and the substrate. The buffer layer covers the first insulating layer. The connecting portion is disposed on the side of the interlayer dielectric layer away from the substrate, in the same layer as the first electrode. The connecting portion connects the second electrode plate and the third electrode plate.

12. The display panel according to claim 11, characterized in that, The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The second active portion is disposed on the side of the buffer layer away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The interlayer dielectric layer sequentially covers the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

13. The display panel according to claim 11, characterized in that, The first gate insulation portion includes a first sublayer and a second sublayer stacked together; The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a protective portion, a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The protective portion is disposed on the side of the buffer layer away from the substrate. The second active portion is disposed on the side of the protective portion away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The interlayer dielectric layer covers the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

14. The display panel according to any one of claims 1-13, characterized in that, The display panel further includes a first planarization layer and a second planarization layer that sequentially cover the first thin-film transistor and the capacitor, with the anode disposed on the side of the second planarization layer away from the substrate.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1-14.

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