Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a plurality of first electrodes and a plurality of pixel definition structures which are arranged on a substrate, the pixel definition structures are arranged between the adjacent first electrodes, and pixel openings exposing the first electrodes are formed; the pixel defining structure at least comprises a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the surface, away from the substrate, of the first insulating layer is provided with at least two first insulating sunken parts which are sunken towards the direction of the substrate, and the first insulating sunken parts are arranged in the direction parallel to the direction of the substrate; the first insulating recess is located between the pixel opening and the third insulating layer; the second insulating layer at least comprises a first sub-part, and the orthographic projection of the first sub-part on the substrate is located in the range of the orthographic projection of the first insulating layer on the substrate and is located between the two first insulating recesses, namely, the first insulating recesses are located between the pixel openings and the first sub-part.

Description

[0001] This case is a divisional application of patent application 202380011227.3. The original application was filed on October 18, 2023, with the application number 202380011227.3 and the invention title being: Display substrate and its preparation method, and display device. Technical Field

[0002] The embodiments of the present invention relate to, but are not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Technology

[0003] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve weight reduction. Silicon-based OLEDs are fabricated using mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for Virtual Reality (VR) and Augmented Reality (AR). Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] As a first aspect of this disclosure, an embodiment provides a display substrate, including a substrate, a plurality of first electrodes disposed on the substrate, and a plurality of pixel defining structures. The pixel defining structures are disposed between adjacent first electrodes and form pixel openings exposing the first electrodes. In a direction perpendicular to the substrate, each pixel defining structure includes at least a first insulating layer disposed on the substrate, a second insulating layer disposed on a side of the first insulating layer away from the substrate, a third insulating layer disposed on a side of the second insulating layer away from the substrate, and a fourth insulating layer disposed on a side of the third insulating layer away from the substrate. The surface of the first insulating layer away from the substrate has at least two first insulating recesses recessed toward the substrate. In a direction parallel to the substrate, the first insulating... The recess is located between the pixel opening and the third insulating layer; the second insulating layer includes at least a first sub-part, the orthographic projection of the first sub-part on the substrate is within the range of the orthographic projection of the first insulating layer on the substrate, and is located between two first insulating recesses, that is, the first insulating recess is located between the pixel opening and the first sub-part, and the orthographic projections of the first sub-part, the third insulating layer, and the fourth insulating layer on the substrate do not overlap with the orthographic projection of the surface of the first electrode on the side away from the substrate on the substrate; the display substrate also includes an organic light-emitting layer disposed on the side of the first electrode and the pixel definition structure away from the substrate, the organic light-emitting layer includes multiple film layers, at least one film layer is broken at the edge of the fourth insulating layer, and the film layer of the organic light-emitting layer is provided with a distortion region at the break.

[0006] In an exemplary embodiment, the inner wall of the first insulating recess near the substrate is located between the surface of the first electrode away from the substrate and the surface of the first electrode near the substrate.

[0007] In an exemplary embodiment, the first insulating recess is a smooth curved surface.

[0008] In an exemplary embodiment, the maximum distance between the inner wall of the first insulating recess on the side near the substrate and the surface of the first sub-part on the side away from the substrate is 0.01 μm to 0.06 μm.

[0009] In an exemplary embodiment, the endpoint of the first sub-part near the edge of the first insulating recess is connected to the endpoint of the inner wall of the first insulating recess near the side of the first sub-part.

[0010] In an exemplary embodiment, the fourth insulating layer has a protrusion relative to the sidewall of the third insulating layer, and the protrusion and the sidewall of the third insulating layer form a first recess that is recessed in a direction away from the pixel opening.

[0011] In an exemplary embodiment, the first recess has a first depth, the first insulating recess has a recess depth, the first depth is greater than the recess depth, the first depth is the maximum distance between the sidewall of the fourth insulating layer near the pixel opening and the sidewall of the third insulating layer near the pixel opening, and the recess depth is the maximum distance between the inner wall of the first insulating recess near the substrate and the end face of the first sub-part near the substrate in a direction perpendicular to the substrate.

[0012] In an exemplary embodiment, the first depth of the first indentation is 0.05 μm to 0.2 μm.

[0013] In an exemplary embodiment, the first recess has a first height, which is greater than the recess depth. The first height of the first recess is the maximum distance between the surface of the first recess near the substrate and the surface of the first recess away from the substrate.

[0014] In an exemplary embodiment, the first recess is a smooth curved surface.

[0015] In an exemplary embodiment, the surface of the fourth insulating layer on the side away from the substrate is provided with a smooth third recess that is recessed toward the substrate.

[0016] In an exemplary embodiment, a first through hole is provided on the first sub-part, the first through hole is connected to the first insulating recess, and the first through hole and the first insulating recess form a second recess, wherein the curvature of the third recess is less than the curvature of the first recess or the curvature of the second recess.

[0017] In an exemplary embodiment, the first insulating layer has a first width, the first sub-part has a second sub-width, the third insulating layer has a third width, and the fourth insulating layer has a fourth width. The first width, the second sub-width, and the fourth width are the maximum dimensions parallel to the substrate direction, and the third width is the minimum dimension parallel to the substrate direction. The second sub-width is smaller than the first width, the fourth width is smaller than the first width, and the third width is smaller than the fourth width.

[0018] In an exemplary embodiment, the first recess has a first depth, which is the maximum distance between the sidewall of the fourth insulating layer near the pixel opening and the sidewall of the third insulating layer near the pixel opening, and the first depth is half the difference between the fourth width and the third width.

[0019] In an exemplary embodiment, the orthographic projections of the third insulating layer and the fourth insulating layer on the substrate are both located within the range of the orthographic projection of the first sub-part on the substrate.

[0020] In an exemplary embodiment, the side surface of the first insulating layer is attached to the side surface of the first electrode.

[0021] In an exemplary embodiment, the distortion region includes at least one crack, and the orthographic projection of the distortion region on the substrate is located within the orthographic projection range of the pixel definition structure on the substrate.

[0022] In an exemplary embodiment, the display substrate further includes a second electrode disposed on the side of the organic light-emitting layer away from the substrate. The second electrode has a puncture tip disposed in a crack in the distortion region. The orthographic projection of the puncture tip on the substrate does not overlap with the orthographic projection of the first electrode on the substrate. The orthographic projection of the endpoint of the puncture tip on the substrate is located within the range of the orthographic projection of the first insulating layer on the substrate. The endpoint of the puncture tip is the boundary point on the puncture tip closest to the substrate.

[0023] In an exemplary embodiment, the orthographic projection of the end point of the puncture tip onto the substrate is within the range of the orthographic projection of the first sub-part onto the substrate.

[0024] In an exemplary embodiment, the orthographic projection of the end point of the puncture tip on the substrate does not overlap with the orthographic projection of the fourth insulating layer on the substrate.

[0025] In an exemplary embodiment, the second electrode includes at least a first portion and a second portion. The orthographic projection of the first portion onto the substrate is within the range of the orthographic projection of the pixel opening onto the substrate. The orthographic projection of the second portion onto the substrate is within the range of the orthographic projection of the second insulating layer onto the substrate and is located between the endpoints of the two puncture tips. In a direction perpendicular to the substrate, the maximum distance between the second portion and the substrate is greater than the maximum distance between the first portion and the substrate.

[0026] As a second aspect of the present disclosure, the present disclosure provides a display device including the aforementioned display substrate.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this application and form part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application, and do not constitute a limitation on the technical solutions of this application. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0029] Figure 1 This is a schematic diagram of the structure of a display device; Figure 2 This is a schematic diagram of a planar structure of a display substrate; Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate; Figure 4 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure; Figure 5 An enlarged view of a pixel definition structure of a display substrate, as an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram showing the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure; Figure 7A Schematic diagram of pixel definition structure pattern formed for exemplary embodiments of this disclosure Figure 1 ; Figure 7B Schematic diagram of pixel definition structure pattern formed for exemplary embodiments of this disclosure Figure 2 ; Figure 7C Schematic diagram of pixel definition structure pattern formed for exemplary embodiments of this disclosure Figure 3 ; Figure 7D Schematic diagram of pixel definition structure pattern formed for exemplary embodiments of this disclosure Figure 4 ; Figure 7E Schematic diagram of pixel definition structure pattern formed for exemplary embodiments of this disclosure Figure 5 ; Figure 7F Schematic diagram of pixel definition structure pattern formed for exemplary embodiments of this disclosure Figure 6 ; Figure 7G Schematic diagram seven showing the pixel definition structure pattern formed according to an exemplary embodiment of this disclosure; Figure 7HSchematic diagram of pixel definition structure pattern formed for exemplary embodiments of this disclosure Figure 8 ; Figure 8 A schematic diagram showing the formation of an organic light-emitting layer pattern according to an exemplary embodiment of this disclosure; Figure 9 A schematic diagram showing the formation of the second conductive layer pattern according to an exemplary embodiment of this disclosure; Figure 10 This is a schematic diagram of the structure of an organic light-emitting layer, which is an exemplary embodiment of the present disclosure. Figure 11 This is a schematic diagram of the structure of another organic light-emitting layer as an exemplary embodiment of the present disclosure.

[0030] Explanation of reference numerals in the attached figures: 10 - Substrate; 20 - Driving circuit layer; 30 - Light-emitting structure layer; 31-First electrode; 32-Pixel definition structure; 33-Organic light-emitting layer; 34 - Second electrode; 35 - Pixel aperture; 40 - First encapsulation layer; 50 - Color filter structural layer; 60 - Second encapsulation layer; 70 - Cover plate layer; 101 - First insulating layer; 102 - Second insulating layer; 103 - Third insulating layer; 104 - Fourth insulating layer; 105 - First indentation; 106 - Second indentation; 107 - Distortion area; 108 - Puncture tip; 109 - Third indentation; 111 - First photoresist pattern; 112 - Second photoresist pattern; 331 - First device; 332 - Charge generation layer; 333 - Second device. Detailed Implementation

[0031] The embodiments described herein can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0032] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0033] The ordinal numbers "first," "second," and "third" used in this article are used to avoid confusion among the constituent elements, rather than to limit the quantity.

[0034] In this document, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description of the embodiments and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described herein can be appropriately replaced as appropriate.

[0035] In this document, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0036] In this document, a transistor is defined as a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (or drain terminal, drain region, or drain electrode) and the source electrode (or source terminal, source region, or source electrode), through which current can flow. In this document, the channel region refers to the area through which current primarily flows.

[0037] In this paper, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" can sometimes be interchanged. Therefore, in this paper, the "source electrode" and "drain electrode" can be interchanged.

[0038] In this document, "electrical connection" includes the situation where constituent elements are connected together by a component that has some electrical function. There are no particular restrictions on the "component that has some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component that has some electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0039] In this article, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0040] In this article, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0041] In this article, "approximately" refers to values ​​that are not strictly limited and allow for errors in the process and measurement.

[0042] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, an OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), multiple light emission signal lines (E1 to Eo), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver, and clock signals, emission stop signals, etc. of specifications suitable for the light emission signal driver to the light emission signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driver can generate transmit signals to be provided to light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light emission signal driver can sequentially provide transmit signals with off-level pulses to light emission signal lines E1 to Eo. For example, the light emission signal driver can be configured as a shift register and can generate light emission signals by sequentially transmitting light emission stop signals in the form of off-level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. The pixel array can include multiple sub-pixels Pxij. Each sub-pixel Pxij can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emission signal line, where i and j can be natural numbers. A sub-pixel Pxij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0043] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0044] In an exemplary embodiment, a pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or it may include red, green, blue, and white sub-pixels; this disclosure does not limit the scope of the invention. In an exemplary embodiment, the shape of the sub-pixels in a pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement; this disclosure does not limit the scope of the invention.

[0045] Figure 3 This is a cross-sectional schematic diagram of a display substrate, illustrating a structure that achieves full color using a white light + color filter approach. For example... Figure 3 As shown, the display substrate of a silicon-based OLED display device may include: a substrate 10, a driving circuit layer 20 disposed on the substrate 10, a light-emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the substrate 10, a first encapsulation layer 40 disposed on the side of the light-emitting structure layer 30 away from the substrate 10, a color filter structure layer 50 disposed on the side of the first encapsulation layer 40 away from the substrate 10, a second encapsulation layer 60 disposed on the side of the color filter structure layer 50 away from the substrate 10, and a cover plate layer 70 disposed on the side of the second encapsulation layer 60 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, which are not limited herein.

[0046] In an exemplary embodiment, the substrate 10 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 20 can be fabricated on the substrate 10 using silicon semiconductor processes (e.g., CMOS processes). The driving circuit layer 20 can include multiple circuit units, at least one of which can include a pixel driving circuit. The pixel driving circuit is connected to scan signal lines and data signal lines, respectively. At least one pixel driving circuit can include multiple transistors and storage capacitors. Figure 3 The example shown uses a pixel driving circuit comprising only one transistor. The transistor may include a control electrode, a first electrode, and a second electrode. The control electrode, the first electrode, and the second electrode may be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and may also be connected to other electrical structures (such as traces) via the connection electrodes.

[0047] In an exemplary embodiment, the light-emitting structure layer 30 may include multiple light-emitting devices. These devices may be organic light-emitting diodes (OLEDs) or quantum dot light-emitting diodes (QLEDs), etc. This disclosure does not limit the type of light-emitting device. Each light-emitting device may include at least a first electrode, an organic light-emitting layer, and a second electrode. The first electrode is connected to the second electrode of a transistor via a connecting electrode. The organic light-emitting layer is connected to the first electrode, and the second electrode is connected to the organic light-emitting layer and a second power line. The organic light-emitting layer emits light under the drive of the first and second electrodes. The first electrode may be disposed on the side of the driving circuit layer 20 away from the substrate 10, and the organic light-emitting layer and the second electrode are sequentially stacked on the side of the first electrode away from the substrate 10.

[0048] In an exemplary embodiment, the light-emitting structure layer 30 may further include a pixel definition layer, wherein each sub-pixel has a pixel opening on the pixel definition layer, the pixel opening exposing a first electrode, thereby connecting the organic light-emitting layer to the first electrode through the pixel opening.

[0049] In an exemplary embodiment, since the organic light-emitting layer emits light from the pixel opening area set in the pixel definition layer, the sub-pixel may include a pixel light-emitting area and a pixel spacing area. The pixel light-emitting area is the light-emitting area, and the area outside the pixel opening is the pixel spacing area, which is located outside the light-emitting area.

[0050] In an exemplary embodiment, the first encapsulation layer 40 and the second encapsulation layer 60 can be thin-film encapsulation (TFE) to ensure that external moisture cannot enter the organic light-emitting layer. The cover layer 70 can be made of glass or a flexible plastic such as colorless polyimide.

[0051] In an exemplary embodiment, the color filter structure layer 50 may include a black matrix (BM) and color filters (CF). The color filters are respectively disposed in red sub-pixels, green sub-pixels and blue sub-pixels to filter the white light emitted by the light-emitting device into red (R) light, green (G) light and blue (B) light. The black matrix may be located between adjacent color filters.

[0052] In an exemplary embodiment, the organic light-emitting layer is configured to emit white light and can be prepared by vapor deposition or inkjet printing. The organic light-emitting layers of all sub-pixels can be a common layer connected together.

[0053] As silicon-based OLED screens face increasingly higher requirements for resolution and brightness, with brightness exceeding 5000 nits and resolution exceeding 3000 PPI, and subpixel spacing approaching 1μm, issues such as lateral leakage in some layers of the organic light-emitting layer and lateral current crosstalk between adjacent subpixels have become more apparent. Currently, various solutions have been proposed to address the lateral current crosstalk problem, such as adjusting pixel spacing and modifying highly conductive organic film materials. However, research has found that these solutions not only have limited effectiveness in blocking lateral leakage but also affect the voltage of the light-emitting device, reducing luminous efficiency and resulting in significant brightness loss.

[0054] This disclosure provides a display substrate, including a substrate, a plurality of first electrodes disposed on the substrate, and a plurality of pixel defining structures. The pixel defining structures are disposed between adjacent first electrodes and form pixel openings exposing the first electrodes. In a direction perpendicular to the substrate, each pixel defining structure includes at least a first insulating layer disposed on the substrate, a second insulating layer disposed on a side of the first insulating layer away from the substrate, a third insulating layer disposed on a side of the second insulating layer away from the substrate, and a fourth insulating layer disposed on a side of the third insulating layer away from the substrate. The orthographic projections of the first, third, and fourth insulating layers on the substrate do not overlap with the orthographic projections of the first electrodes on the substrate. The orthographic projection of the second insulating layer on the substrate at least partially overlaps with the orthographic projections of the first electrodes on the substrate. A second recess is provided on the surface of the second insulating layer away from the substrate, recessed towards the substrate. The inner wall of the second recess near the substrate is located between the surface of the first electrode away from the substrate and the surface of the first electrode near the substrate. The display substrate provided in this embodiment can isolate the organic light-emitting layer through the pixel definition structure, thereby cutting off lateral leakage current and preventing the second electrode from breaking, thus improving the display effect.

[0055] In an exemplary embodiment, the second depth of the second indentation is 0.01 μm to 0.06 μm, and the second depth is the maximum distance between the inner wall of the second indentation on the side closer to the substrate and the surface of the second insulating layer on the side farther from the substrate.

[0056] In an exemplary embodiment, the surface of the first insulating layer on the side away from the substrate is flush with the surface of the first electrode on the side away from the substrate, and the surface of the first insulating layer on the side away from the substrate is lower than the surface of the first electrode on the side away from the substrate.

[0057] In an exemplary embodiment, the material of the third insulating layer is different from that of the fourth insulating layer, while the material of the second insulating layer is the same as that of the fourth insulating layer.

[0058] In an exemplary embodiment, the fourth insulating layer has a protrusion relative to the sidewall of the third insulating layer, and the protrusion and the sidewall of the third insulating layer form a first recess that is recessed in a direction away from the pixel opening. The first depth of the first recess is greater than the second depth of the second recess. The first depth is the maximum distance between the sidewall of the fourth insulating layer near the pixel opening and the sidewall of the third insulating layer near the pixel opening.

[0059] In an exemplary embodiment, the display substrate further includes an organic light-emitting layer disposed on the side of the first electrode and the pixel definition structure away from the substrate. The organic light-emitting layer includes a plurality of film layers, at least one film layer being broken at the edge of the fourth insulating layer, and the film layer of the organic light-emitting layer forming a distortion region at the break.

[0060] Figure 4 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 5 for Figure 4 A magnified view of the mid-pixel definition structure. (See image below.) Figure 4 and 5 As shown, the display substrate of this exemplary embodiment may include a substrate 10, a plurality of first electrodes 31 and a plurality of pixel definition structures 32 disposed on the substrate 10, an organic light-emitting layer 33 disposed on the side of the first electrodes 31 and pixel definition structures 32 away from the substrate 10, and a second electrode 34 disposed on the side of the organic light-emitting layer 33 away from the substrate 10.

[0061] In an exemplary embodiment, a pixel definition structure 32 is disposed between adjacent first electrodes 31 and forms a pixel opening 35 that exposes the first electrodes 31. The pixel definition structure 32 may include a plurality of inorganic layers stacked on the substrate 10.

[0062] In an exemplary embodiment, the plurality of inorganic layers of the pixel definition structure 32 may include at least a first insulating layer 101 disposed on the substrate 10, a second insulating layer 102 disposed on the side of the first insulating layer 101 away from the substrate 10, a third insulating layer 103 disposed on the side of the second insulating layer 102 away from the substrate 10, and a fourth insulating layer 104 disposed on the side of the third insulating layer 103 away from the substrate 10.

[0063] In an exemplary embodiment, a first insulating layer 101 is disposed between adjacent first electrodes 31, and the side surface of the first insulating layer 101 can be attached to the side surface of the first electrode 31. The orthographic projection of the first insulating layer 101 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10.

[0064] In an exemplary embodiment, the surface of the first insulating layer 101 on the side away from the substrate 10 is substantially flush with the surface of the first electrode 31 on the side away from the substrate 10, and the surface of the first insulating layer 101 on the side away from the substrate 10 is lower than the surface of the first electrode 31 on the side away from the substrate 10.

[0065] In an exemplary embodiment, the first insulating layer 101 has a first width L1, which is the dimension of the first insulating layer 101 in the direction parallel to the substrate 10.

[0066] In an exemplary embodiment, the first width L1 can be approximately 1.0 μm to 1.2 μm. For example, the first width L1 can be approximately 1.1 μm.

[0067] In an exemplary embodiment, the orthographic projection of the second insulating layer 102 on the substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 on the substrate 10, and the second insulating layer 102 has a second width L2, which is the dimension of the second insulating layer 102 in the direction parallel to the substrate 10.

[0068] In an exemplary embodiment, the second width L2 of the second insulating layer 102 is greater than the first width L1 of the first insulating layer 101, i.e., L2>L1.

[0069] In an exemplary embodiment, the difference between the second width L2 and the first width L1 is greater than or equal to 0.1 μm. The second width L2 can be approximately 1.2 μm to 1.6 μm. For example, the second width L2 can be approximately 1.4 μm.

[0070] In an exemplary embodiment, the width of the overlapping area between the second insulating layer 102 and the first electrode 31 is greater than or equal to 0.1 μm, so that the second insulating layer 102 can effectively cover the edge of the first electrode 31. That is, the pixel definition structure 32 does not expose the edge of the first electrode 31 by forming a second insulating layer 102 that is wider than the first insulating layer 101.

[0071] In an exemplary embodiment, the difference between the second width L2 and the first width L1 can be about 0.3 μm, so that the second insulating layer 102 effectively covers one side of the first electrode 31 by about 0.15 μm.

[0072] In an exemplary embodiment, the orthographic projection of the third insulating layer 103 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10, and the orthographic projection of the fourth insulating layer 104 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10.

[0073] In an exemplary embodiment, the material of the third insulating layer 103 may be different from that of the fourth insulating layer 104, while the material of the second insulating layer 102 may be the same as that of the fourth insulating layer 104. This allows for the creation of a recessed structure due to the difference in etching rates between the two materials. For example, both the second insulating layer 102 and the fourth insulating layer 104 may be made of silicon oxide (SiO2). X The material of the third insulating layer 103 can be silicon nitride (SiN). X ).

[0074] In an exemplary embodiment, the third insulating layer 103 has a third width L3, and the fourth insulating layer 104 has a fourth width L4. The fourth width L4 may be greater than the third width L3. The third width L3 and the fourth width L4 are dimensions parallel to the direction of the substrate 10.

[0075] In an exemplary embodiment, the third width L3 may be the minimum width of the third insulating layer 103, and the fourth width L4 may be the maximum width of the fourth insulating layer 104. Alternatively, the third width L3 may be the average width of the third insulating layer 103, and the fourth width L4 may be the average width of the fourth insulating layer 104.

[0076] In an exemplary embodiment, the difference between the fourth width L4 and the third width L3 can be approximately 0.1 μm to 0.4 μm.

[0077] In an exemplary embodiment, the third width L3 can be approximately 0.3 μm to 0.5 μm. In an exemplary embodiment, the third width L3 can be approximately 0.4 μm. The fourth width L4 can be approximately 0.5 μm to 0.7 μm. For example, the fourth width L4 can be approximately 0.6 μm.

[0078] In an exemplary embodiment, the fourth width L4 may be less than the first width L1, i.e., L4 < L1.

[0079] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, i.e., L4 < L2. The difference between the fourth width L4 and the second width L2 is greater than or equal to 0.3 μm.

[0080] In an exemplary embodiment, the fourth insulating layer 104 has a protrusion with respect to the sidewall of the third insulating layer 103, and the protrusion and the sidewall of the third insulating layer 103 form a first recess 105 that is recessed away from the pixel opening 35. The first recess 105 may have a curved surface shape with a curvature.

[0081] In an exemplary embodiment, the first recess 105 may have a first depth ΔL. The first depth ΔL may be the maximum distance between the sidewall of the fourth insulating layer 104 closer to the pixel opening 35 and the sidewall of the third insulating layer 103 closer to the pixel opening 35. The first depth ΔL may be a dimension in the direction parallel to the substrate 10.

[0082] In an exemplary embodiment, the first depth ΔL of the first recess 105 may be half of the difference between the fourth width L4 and the third width L3, where ΔL = (L4 - L3) / 2.

[0083] In an exemplary embodiment, the first depth ΔL of the first recess 105 may be approximately 0.05 μm to 0.2 μm; In an exemplary embodiment, the difference between the second width L2 and the fourth width L4 may be approximately 0.8 μm, such that the orthographic projection of the first recess 105 on the substrate 10 and the orthographic projection of the pixel opening 35 on the substrate 10 do not overlap.

[0084] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, and the third width L3 may be less than the fourth width L4, i.e., L3 < L4 < L2.

[0085] In an exemplary embodiment, a second recess 106 is provided on the surface of the second insulating layer 102 away from the substrate 10, recessed toward the substrate 10. The inner wall of the second recess 106 near the substrate 10 is located between the surface of the first electrode 31 away from the substrate 10 and the surface of the first electrode 31 near the substrate 10. The second recess 106 can be a curved surface shape with curvature. The second recess 106 can have a second depth ΔD, which can be the maximum distance between the inner wall of the second recess 106 near the substrate 10 and the surface of the second insulating layer 102 away from the substrate 10, and the second depth ΔD can be the dimension of the second recess in the direction perpendicular to the substrate 10.

[0086] In an exemplary embodiment, the second depth ΔD of the second recess 106 can be approximately 0.01 μm to 0.06 μm; the cross-sectional size of the second recess 106 gradually increases in the direction away from the substrate 10.

[0087] In an exemplary embodiment, the first depth ΔL of the first indentation 105 is greater than the second depth ΔD of the second indentation 106.

[0088] In an exemplary embodiment, the first height ΔH of the first recess 105 is greater than the second depth ΔD of the second recess 106, and the first height ΔH of the first recess 105 is the maximum distance between the surface of the first recess 105 near the substrate 10 and the surface of the first recess 105 away from the substrate 10.

[0089] In an exemplary embodiment, the surface of the fourth insulating layer 104 away from the substrate 10 is provided with a smooth third recess 109 that is recessed toward the substrate 10. The third recess 109 may be a curved surface shape with curvature. The curvature of the third recess 109 is less than the curvature of the first recess 105 or the curvature of the second recess 106.

[0090] In an exemplary embodiment, the display substrate further includes an organic light-emitting layer 33 disposed on the side of the first electrode 31 and the pixel definition structure 32 away from the substrate 10. The organic light-emitting layer 33 includes multiple film layers, at least one of which is broken at the edge of the fourth insulating layer 104. A distortion region 107 is formed at the break point of the film layer of the organic light-emitting layer 33, as shown in the dashed box. In an exemplary embodiment, the distortion region 107 may include at least one crack, and the organic light-emitting layer 33 on both sides of the crack forms a step difference due to the break.

[0091] In an exemplary embodiment, the orthographic projection of the distortion region 107 on the substrate 10 does not overlap with the orthographic projection of the pixel opening 35 on the substrate 10.

[0092] In an exemplary embodiment, the display substrate further includes a second electrode 34 disposed on the side of the organic light-emitting layer 33 away from the substrate 10. The second electrode 34 is provided with a puncture tip 108, which is disposed in the crack of the distortion region 107. The orthogonal projection of the puncture tip 108 on the substrate 10 does not overlap with the orthogonal projection of the first electrode 31 on the substrate 10.

[0093] The orthographic projection of the end point of the puncture tip 108 onto the substrate 10 is within the range of the orthographic projection of the first insulating layer 101 onto the substrate 10, and the end point of the puncture tip 108 is the boundary point on the puncture tip 108 closest to the substrate 10.

[0094] In an exemplary embodiment, in the pixel definition structure 32, the first insulating layer 101 has a first thickness D1, the second insulating layer 102 has a second thickness D2, the third insulating layer 103 has a third thickness D3, and the fourth insulating layer 104 has a fourth thickness D4. The first thickness D1, the second thickness D2, the third thickness D3, and the fourth thickness D4 are dimensions perpendicular to the substrate 10. The first thickness D1 can be approximately 900 angstroms to 1100 angstroms, for example, the first thickness D1 can be approximately 1000 angstroms. The second thickness D2 can be approximately 300 angstroms to 500 angstroms, for example, the second thickness D2 can be approximately approximately 400 angstroms. The third thickness D3 can be approximately 500 angstroms to 700 angstroms, for example, the third thickness D3 can be approximately approximately 600 angstroms. The fourth thickness D4 can be approximately 100 angstroms to 300 angstroms, for example, the fourth thickness D4 can be approximately approximately 200 angstroms.

[0095] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set on the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0096] In an exemplary embodiment, taking three sub-pixels of a display substrate as an example, the fabrication process of the display substrate may include the following operations.

[0097] A. Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate 10, and patterning the first conductive thin film using a patterning process to form a first conductive layer pattern. The first conductive layer pattern includes at least a first electrode 31 located in each sub-pixel, such as... Figure 6 As shown.

[0098] In an exemplary embodiment, the first electrode 31 can be made of a metallic material or a transparent conductive material. The metallic material can include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material can include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the first electrode 31 can be a single-layer structure or a multilayer composite structure. In an exemplary embodiment, the multilayer composite structure can include a Ti layer, an Al layer, a titanium nitride (TiN) layer, and an ITO layer sequentially disposed along a direction away from the substrate 10, which can meet the conventional requirements of high reflectivity, low roughness, and work function matching for light-emitting devices.

[0099] In an exemplary embodiment, the first electrode 31 has a first electrode thickness, which can be approximately 900 angstroms to 1100 angstroms, and is a dimension perpendicular to the substrate 10. For example, the first thickness D1 can be approximately 1000 angstroms.

[0100] B. Forming a pixel-defined structure pattern. In an exemplary embodiment, the pixel-defined structure pattern includes at least a pixel-defined structure 32 located in each sub-pixel. The pixel-defined structure 32 is disposed between adjacent first electrodes 31 and forms a pixel opening exposing the first electrodes 31. Forming the pixel-defined structure pattern may include: B1. Forming a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern may include: depositing a first insulating film, such as..., on the substrate on which the aforementioned pattern is formed. Figure 7A As shown. Subsequently, the first insulating film is etched using a full-surface etching process to form the first insulating layer 101, as shown. Figure 7B As shown.

[0101] In an exemplary embodiment, the first insulating layer 101 is disposed between adjacent first electrodes 31, and the orthographic projection of the first insulating layer 101 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10. The side surface of the first insulating layer 101 can be attached to the side surface of the first electrode 31.

[0102] In an exemplary embodiment, through a full-surface etch-back process, the surface of the first insulating layer 101 away from the substrate 10 is substantially flush with the surface of the first electrode 31 away from the substrate 10, and the surface of the first insulating layer 101 away from the substrate 10 is lower than the surface of the first electrode 31 away from the substrate 10.

[0103] In an exemplary embodiment, the first insulating layer 101 can be a planarization layer. The side surface of the first insulating layer 101 can be attached to the side surface of the first electrode 31, forming a planar region of a predetermined width at the contact point between the first insulating layer 101 and the first electrode. The first insulating layer 101 has a first width L1, which is a dimension parallel to the direction of the substrate 10. In an exemplary embodiment, the first width L1 can be approximately 1.0 μm to 1.2 μm. For example, the first width L1 can be approximately 1.1 μm.

[0104] In an exemplary embodiment, the first insulating layer 101 may have a first thickness D1. The first thickness D1 may be approximately 900 angstroms to 1100 angstroms. For example, the first thickness D1 may be approximately 1000 angstroms.

[0105] In an exemplary embodiment, the first insulating layer 101 is made of an inorganic material, for example, silicon oxide (SiO2). X ).

[0106] B2. Forming patterns of a second insulating film, a third insulating film, and a fourth insulating film. In an exemplary embodiment, forming the patterns of the second, third, and fourth insulating films may include: sequentially depositing the second, third, and fourth insulating films on a substrate on which the aforementioned patterns are formed, such as... Figure 7C As shown.

[0107] In an exemplary embodiment, the second insulating layer 102 in the pixel definition structure 32 has a second thickness D2, which is the dimension of the second insulating layer 102 in the direction perpendicular to the substrate 10. The second thickness D2 can be approximately 300 angstroms to 500 angstroms. For example, the second thickness D2 can be approximately 400 angstroms. In an exemplary embodiment, the third insulating layer 103 has a third thickness D3, which is the dimension of the third insulating layer 103 in the direction perpendicular to the substrate 10. The third thickness D3 can be approximately 500 angstroms to 700 angstroms. For example, the third thickness D3 can be approximately 600 angstroms. In an exemplary embodiment, the fourth insulating layer 104 has a fourth thickness D4, which is the dimension of the fourth insulating layer 104 in the direction perpendicular to the substrate 10. The fourth thickness D4 can be approximately 100 angstroms to 300 angstroms. For example, the fourth thickness D4 can be approximately 200 angstroms.

[0108] In an exemplary embodiment, the second, third, and fourth insulating films are all inorganic materials. The material of the third insulating film may be different from that of the fourth insulating film, while the material of the second insulating film may be the same as that of the fourth insulating film. For example, both the second and fourth insulating films are made of silicon oxide (SiO2). X The third insulating film is made of silicon nitride (SiN). X ).

[0109] B3. First, photoresist is coated onto the fourth insulating film, and a first photoresist pattern 111 is formed by exposure and development, as shown below. Figure 7D As shown.

[0110] In an exemplary embodiment, the first photoresist pattern 111 has a second width L2, which is the dimension of the second photoresist pattern 112 in a direction parallel to the substrate 10. The second width L2 can be greater than the first width L1. In an exemplary embodiment, the second width L2 can be approximately 1.2 μm to 1.6 μm. For example, the second width L2 can be approximately 1.4 μm.

[0111] Subsequently, the second, third, and fourth insulating films, which were not coated with photoresist, were etched to form the first transition pattern, such as... Figure 7E As shown.

[0112] In an exemplary embodiment, the first transition pattern may include a second insulating layer 102, a third insulating layer 103, and a fourth insulating layer 104 stacked together, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 having substantially the same second width L2.

[0113] In an exemplary embodiment, the orthographic projection of the second insulating layer 102 on the substrate 10 includes the orthographic projection of the first insulating layer 101 on the substrate 10, and the orthographic projection of the second insulating layer 102 on the substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 on the substrate 10.

[0114] In an exemplary embodiment, the orthographic projection of the second insulating layer 102 on the substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 on the substrate 10, and at least partially exposes the first electrode 31.

[0115] In an exemplary embodiment, the difference between the second width L2 of the second insulating layer 102 and the first width L1 of the first insulating layer 101 is greater than or equal to 0.1 μm. The width of the overlapping area between the second insulating layer 102 and the first electrode 31 can be greater than 0.1 μm, so that the second insulating layer 102 can effectively cover the edge of the first electrode 31. That is, the pixel definition structure 32 does not expose the edge of the first electrode 31 by forming a second insulating layer 102 that is wider than the first insulating layer 101.

[0116] In an exemplary embodiment, the difference between the second width L2 and the first width L1 can be about 0.3 μm, so that the second insulating layer 102 effectively covers one side of the first electrode 31 by about 0.15 μm.

[0117] B4. First, the width of the photoresist pattern is reduced using a photoresist indentation method to form a second photoresist pattern 112, as shown below. Figure 7F As shown.

[0118] In an exemplary embodiment, the second photoresist pattern 113 has a fourth width L4, which is the dimension of the third photoresist pattern 113 in the direction parallel to the substrate 10. The fourth width L4 can be approximately 0.5 μm to 0.7 μm, for example, the fourth width L4 can be approximately 0.6 μm.

[0119] Subsequently, the exposed third insulating layer 103 and fourth insulating layer 104 are etched to form the pattern of the second transition pattern, such as... Figure 7G As shown.

[0120] In an exemplary embodiment, the second transition pattern may include a stacked third insulating layer 103 and a fourth insulating layer 104, and the third insulating layer 103 and the fourth insulating layer 104 have substantially the same fourth width L4.

[0121] In an exemplary embodiment, the orthographic projection of the third insulating layer 103 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10, and the orthographic projection of the fourth insulating layer 104 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10.

[0122] In an exemplary embodiment, the fourth width L4 may be less than the first width L1, that is, L4 < L1.

[0123] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, that is, L4 < L2. The difference between the fourth width L4 and the second width L2 may be greater than or equal to 0.3 μm.

[0124] Subsequently, by changing the ratio of the etching gas, the side surface of the third insulating layer 103 is etched such that the fourth insulating layer 104 has a protrusion with respect to the side wall of the third insulating layer 103, and the protrusion and the side wall of the third insulating layer 103 form a first indentation 105. In this etching process, the etching gas will etch the surface of the second insulating layer 102 on the side away from the substrate 10, and a second indentation 106 is formed on the surface of the second insulating layer 102. In this etching process, the etching gas will etch the surface of the fourth insulating layer 104 on the side away from the substrate 10 to form a third indentation 109. After removing the remaining photoresist, a pixel defining structure pattern is formed, as Figure 7H shown.

[0125] In an exemplary embodiment, the pixel defining structure 32 may include a second insulating layer 102, a third insulating layer 103, and a fourth insulating layer 104 sequentially provided on the first insulating layer 101. The orthographic projection of the first insulating layer 101 on the substrate is within the range of the orthographic projection of the second insulating layer 102 on the substrate. The orthographic projection of the fourth insulating layer 1044 on the substrate is within the range of the orthographic projection of the first insulating layer 101 on the substrate. The orthographic projection of the third insulating layer 103 on the substrate is within the range of the orthographic projection of the fourth insulating layer 104 on the substrate.

[0126] In an exemplary embodiment, the first insulating layer 101 has a first width L1, the second insulating layer 102 has a second width L2, the third insulating layer 103 has a third width L3, and the fourth insulating layer 104 has a fourth width L4. In the exemplary embodiment, the first width L1 may be smaller than the second width L2, the fourth width L4 may be smaller than the first width L1, and the third width L3 may be smaller than the fourth width L4, that is, L3 < L4 < L1 < L2. The first width L1, the second width L2, the third width L3, and the fourth width L4 are dimensions in a direction parallel to the substrate 10.

[0127] In the exemplary embodiment, the third width L3 may be the minimum width of the third insulating layer 103, and the fourth width L4 may be the maximum width of the fourth insulating layer 104. Alternatively, the third width L3 may be the average width of the third insulating layer 103, and the fourth width L4 may be the average width of the fourth insulating layer 104.

[0128] In the exemplary embodiment, the difference between the fourth width L4 and the third width L3 may be approximately 0.1 μm to 0.4 μm.

[0129] In the exemplary embodiment, the third width L3 may be approximately 0.3 μm to 0.5 μm. In the exemplary embodiment, the third width L3 may be approximately 0.4 μm.

[0130] In the exemplary embodiment, the fourth insulating layer 104 has a protrusion with respect to the sidewall of the third insulating layer 103. The protrusion and the sidewall of the third insulating layer 103 form a first indentation 105 that is recessed away from the pixel opening 35. The first indentation 105 may be a curved surface shape with a curvature.

[0131] In the exemplary embodiment, the first indentation 105 may have a first depth ΔL. The first depth ΔL may be the maximum distance between the sidewall of the fourth insulating layer 104 closer to the pixel opening 35 and the sidewall of the third insulating layer 103 closer to the pixel opening 35.

[0132] In the exemplary embodiment, the first depth ΔL of the first indentation 105 may be half of the difference between the fourth width L4 and the third width L3, where ΔL = (L4 - L3) / 2.

[0133] In the exemplary embodiment, the first depth ΔL of the first indentation 105 may be approximately 0.05 μm to 0.2 μm; [[ID=*22]] In the exemplary embodiment, the difference between the second width L2 and the fourth width L4 may be approximately 0.8 μm, such that the orthographic projection of the first indentation 105 on the substrate 10 does not overlap with the orthographic projection of the pixel opening 35 on the substrate 10.

[0134] In an exemplary embodiment, a second recess 106 is provided on the surface of the second insulating layer 102 away from the substrate 10, recessed toward the substrate 10. The inner wall of the second recess 106 near the substrate 10 is located between the surface of the first electrode 31 away from the substrate 10 and the surface of the first electrode 31 near the substrate 10. The second recess 106 can be a curved surface shape with curvature. The second recess 106 can have a second depth ΔD, which can be the maximum distance between the inner wall of the second recess 106 near the substrate 10 and the surface of the second insulating layer 102 away from the substrate 10, and the second depth ΔD can be the dimension of the second recess in the direction perpendicular to the substrate 10.

[0135] In an exemplary embodiment, the second depth ΔD of the second recess 106 can be approximately 0.01 μm to 0.06 μm; the cross-sectional size of the second recess 106 gradually increases in the direction away from the substrate 10.

[0136] In an exemplary embodiment, the first depth ΔL of the first indentation 105 is greater than the second depth ΔD of the second indentation 106.

[0137] In an exemplary embodiment, the first height ΔH of the first recess 105 is greater than the second depth ΔD of the second recess 106, and the first height ΔH of the first recess 105 is the maximum distance between the surface of the first recess 105 near the substrate 10 and the surface of the first recess 105 away from the substrate 10.

[0138] In an exemplary embodiment, the surface of the fourth insulating layer 104 away from the substrate 10 is provided with a smooth third recess 109 that is recessed toward the substrate 10. The third recess 109 may be a curved surface shape with curvature. The curvature of the third recess 109 is less than the curvature of the first recess 105 or the curvature of the second recess 106.

[0139] C. Forming an organic light-emitting layer pattern. In an exemplary embodiment, forming an organic light-emitting layer pattern may include: forming an organic light-emitting layer pattern by means of vapor deposition or the like, wherein the organic light-emitting layer 33 of each sub-pixel is connected to the first electrode 31 of the sub-pixel through a pixel opening 35, such as... Figure 8 As shown.

[0140] In an exemplary embodiment, the organic light-emitting layer 33 may include multiple film layers, at least one of which is broken at the edge of the fourth insulating layer 104. In an exemplary embodiment, the film layers of the organic light-emitting layer 33 have a distortion region 107 at the break point, as shown in the dashed box, where a break in the film layers of the organic light-emitting layer 33 occurs. In an exemplary embodiment, the distortion region 107 may include at least one crack, and the organic light-emitting layer 33 on both sides of the crack forms a step difference due to the break.

[0141] In an exemplary embodiment, the orthographic projection of the distortion region 107 on the substrate 10 does not overlap with the orthographic projection of the pixel opening 35 on the substrate 10.

[0142] D. Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: forming a second electrode 34 by means of evaporation or deposition, wherein the second electrode 34 is disposed on the side of the organic light-emitting layer 33 away from the substrate 10, and is a full-surface structure, such as... Figure 9 As shown.

[0143] In an exemplary embodiment, since the organic light-emitting layer 33 has a distortion region 107, the second electrode 34 is provided with a puncture tip 108, which is disposed in the crack of the distortion region 107.

[0144] The orthographic projection of the end point of the puncture tip 108 onto the substrate 10 is within the range of the orthographic projection of the first insulating layer 101 onto the substrate 10, and the end point of the puncture tip 108 is the boundary point on the puncture tip 108 closest to the substrate 10.

[0145] In an exemplary embodiment, the orthographic projection of the puncture tip 108 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10.

[0146] In an exemplary embodiment, the second electrode 34 can be made of a metallic material or a transparent conductive material. The metallic material can include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or alloys of the above metals. The transparent conductive material can include indium zinc oxide (IZO). In an exemplary embodiment, the second electrode 34 can be a single-layer structure or a multi-layer composite structure, such as Mg / Ag.

[0147] In an exemplary embodiment, an optical coupling layer pattern can be formed after the second conductive layer pattern is formed. The optical coupling layer is disposed on the second electrode 34. The refractive index of the optical coupling layer can be greater than the refractive index of the second electrode 34, which is beneficial for light extraction and increases light extraction efficiency. The material of the optical coupling layer can be an organic material, an inorganic material, or a combination of organic and inorganic materials. It can be a single layer, a multilayer layer, or a composite layer. This disclosure does not limit the specific material used.

[0148] At this point, the display substrate is complete. The display substrate may include a substrate 10, a first electrode 31, a pixel definition structure 32, an organic light-emitting layer 33, and a second electrode 34. The organic light-emitting layer 33 emits light under the drive of the first electrode 31 and the second electrode 34.

[0149] Subsequent fabrication processes may include forming the first encapsulation layer 40, the color filter structure layer 50, the second encapsulation layer 60, and the cover plate layer 70, which will not be elaborated here.

[0150] The display substrate provided in this disclosure, by setting a pixel definition structure including multiple insulating layers, and forming a second recess on the second insulating layer of the pixel definition structure, with the inner wall of the second recess near the substrate located between the upper and lower surfaces of the first electrode, can ensure that while the pixel definition structure isolates the organic light-emitting layer, the second electrode is prevented from breaking, thus ensuring the continuity of the second electrode. The pixel definition structure proposed in this disclosure, by forming a first recess on the sidewall of the pixel definition structure, causes the organic light-emitting layer to break at the edge of the pixel definition structure, effectively blocking the lateral current in the organic light-emitting layer. The pixel definition structure proposed in this disclosure causes the organic light-emitting layer to form a distortion region, and the orthogonal projection of the distortion region on the substrate does not overlap with the orthogonal projection of the pixel opening on the substrate, that is, the distortion region is located outside the pixel opening, far from the effective light-emitting area, improving luminous efficiency and reducing brightness loss. The pixel definition structure proposed in this disclosure ensures that the orthographic projection of the puncture tip of the second electrode on the substrate does not overlap with the orthographic projection of the first electrode on the substrate. That is, the puncture tip is located outside the area where the first electrode is located, which can effectively avoid short circuits between the second electrode and the first electrode. By setting the puncture tip in the area where the flat first insulating layer is located, the continuity of the second electrode can be further guaranteed, and there will be no loose connection or disconnection.

[0151] The organic light-emitting layer is disconnected at the edge of the pixel definition structure, which can effectively avoid crosstalk caused by the transfer of charge carriers in the charge generation layer. This can greatly reduce the risk of vertical leakage in organic light-emitting devices, improve luminous efficiency, and enhance display effects.

[0152] Figure 10 This is a schematic diagram of the structure of an organic light-emitting layer as an exemplary embodiment of this disclosure. Figure 10As shown, the organic light-emitting layer 33 may include a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, and an electron injection layer disposed between the first electrode and the second electrode.

[0153] Figure 11 This is a schematic structural diagram of another organic light-emitting layer according to an exemplary embodiment of the present disclosure. As Figure 11 shown, the organic light-emitting layer 33 may include a first device 33-1, a charge generation layer 33-2, and a second device 33-3 disposed between the first electrode and the second electrode. Both the first device 33-1 and the second device 33-3 include a stacked hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0154] In an exemplary embodiment, in a direction perpendicular to the substrate 10, the first device 33-1 and the charge generation layer 33-2 have a first device thickness T1, and the second stacked device 33-3 has a second thickness T2. The first device thickness T1 may be less than the second device thickness T2, that is, T1 < T2.

[0155] In an exemplary embodiment, the first device thickness T1 may be less than half of the second device thickness T2, T1 < 1 / 2 * T2, to ensure that while the inscribed structure effectively separates the organic light-emitting layer 33, it will not cause virtual connection or breakage of the second electrode 34.

[0156] In an exemplary embodiment, a third thickness D3 may be less than the first device thickness T1, and the third thickness D3 may be greater than half of the first device thickness T1, that is, 1 / 2 * T1 < D3 < T1, to ensure that at least one film layer in the organic light-emitting layer 33 is disconnected at a position corresponding to the pixel definition structure 32, especially to separate the charge generation layer 33-2 in the organic light-emitting layer 33.

[0157] In an exemplary embodiment, the total thickness of the organic light-emitting layer 33 may be about 2900 Å to 3100 Å, where the first device thickness T1 may be about 900 Å, and the second device thickness T2 may be about 2100 Å.

[0158] It has been found through research that not only does the width of the inorganic layer in the pixel definition structure affect the efficiency and lifespan of the light-emitting device, but also the thickness of the organic light-emitting layer is a factor affecting the quality of the light-emitting device. By setting the thickness relationship between the third insulating layer and the organic light-emitting layer, the present disclosure not only further effectively blocks lateral leakage between pixels, but also can reduce longitudinal leakage caused by distortion of the organic light-emitting layer.

[0159] Exemplary embodiments also disclose a method for fabricating a display substrate. In an exemplary embodiment, the fabrication method includes: forming a plurality of first electrodes and a plurality of pixel definition structures on a substrate; the pixel definition structures are disposed between adjacent first electrodes and form pixel openings exposing the first electrodes; in a direction perpendicular to the substrate, the pixel definition structure includes at least a first insulating layer disposed on the substrate, a second insulating layer disposed on a side of the first insulating layer away from the substrate, a third insulating layer disposed on a side of the second insulating layer away from the substrate, and a fourth insulating layer disposed on a side of the third insulating layer away from the substrate, wherein the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the substrate do not overlap with the orthographic projections of the first electrodes on the substrate, and the orthographic projection of the second insulating layer on the substrate at least partially overlaps with the orthographic projections of the first electrodes on the substrate; the surface of the second insulating layer away from the substrate is provided with a second recess recessed toward the substrate, the inner wall of the second recess near the substrate is located between the surface of the first electrode away from the substrate and the surface of the first electrode near the substrate.

[0160] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0161] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, The device includes a substrate, a plurality of first electrodes disposed on the substrate, and a plurality of pixel definition structures, wherein the pixel definition structures are disposed between adjacent first electrodes and form pixel openings that expose the first electrodes; In a direction perpendicular to the substrate, the pixel definition structure includes at least a first insulating layer disposed on the substrate, a second insulating layer disposed on the side of the first insulating layer away from the substrate, a third insulating layer disposed on the side of the second insulating layer away from the substrate, and a fourth insulating layer disposed on the side of the third insulating layer away from the substrate. The surface of the first insulating layer away from the substrate has at least two first insulating recesses recessed towards the substrate. In a direction parallel to the substrate, the first insulating recesses are located between the pixel opening and the third insulating layer. The second insulating layer includes at least a first sub-part on the substrate. The orthographic projection is located within the range of the orthographic projection of the first insulating layer on the substrate, and is located between the two first insulating recesses, that is, the first insulating recess is located between the pixel opening and the first sub-part. The orthographic projections of the first sub-part, the third insulating layer, and the fourth insulating layer on the substrate do not overlap with the orthographic projection of the surface of the first electrode on the side away from the substrate on the substrate. The display substrate also includes an organic light-emitting layer disposed on the side of the first electrode and the pixel definition structure away from the substrate. The organic light-emitting layer includes multiple film layers, at least one film layer is broken at the edge of the fourth insulating layer, and the film layer of the organic light-emitting layer has a distortion region at the break.

2. The display substrate according to claim 1, characterized in that, The inner wall of the first insulating recess near the substrate is located between the surface of the first electrode away from the substrate and the surface of the first electrode near the substrate.

3. The display substrate according to claim 1, characterized in that, The first insulating recess is a smooth curved surface.

4. The display substrate according to claim 1, characterized in that, The maximum distance between the inner wall of the first insulating recess on the side closer to the substrate and the surface of the first sub-part on the side farther from the substrate is 0.01 μm to 0.06 μm.

5. The display substrate according to claim 1, characterized in that, The endpoint of the first sub-part near the edge of the first insulating recess is connected to the endpoint of the inner wall of the first insulating recess near the side of the first sub-part.

6. The display substrate according to claim 1, characterized in that, The fourth insulating layer has a protrusion relative to the sidewall of the third insulating layer, and the protrusion and the sidewall of the third insulating layer form a first recess that is recessed in a direction away from the pixel opening.

7. The display substrate according to claim 6, characterized in that, The first indentation has a first depth, the first insulating indentation has a recess depth, the first depth is greater than the recess depth, the first depth is the maximum distance between the sidewall of the fourth insulating layer near the pixel opening and the sidewall of the third insulating layer near the pixel opening, and the recess depth is the maximum distance between the inner wall of the first insulating indentation near the substrate and the end face of the first sub-part near the substrate in a direction perpendicular to the substrate.

8. The display substrate according to claim 7, characterized in that, The first depth of the first indentation is 0.05 μm to 0.2 μm.

9. The display substrate according to claim 7, characterized in that, The first recess has a first height, which is greater than the recess depth. The first height of the first recess is the maximum distance between the surface of the first recess near the substrate and the surface of the first recess away from the substrate.

10. The display substrate according to claim 6, characterized in that, The first depression is a smooth curved surface.

11. The display substrate according to claim 6, characterized in that, The surface of the fourth insulating layer away from the substrate has a smooth third recess that is recessed toward the substrate.

12. The display substrate according to claim 11, characterized in that, The first sub-part is provided with a first through hole, which communicates with the first insulating recess, and the first through hole and the first insulating recess constitute a second recess. The curvature of the third recess is less than the curvature of the first recess or the curvature of the second recess.

13. The display substrate according to claim 1, characterized in that, The first insulating layer has a first width, the first sub-part has a second sub-width, the third insulating layer has a third width, and the fourth insulating layer has a fourth width. The first width, the second sub-width, and the fourth width are the maximum dimensions parallel to the substrate direction, and the third width is the minimum dimension parallel to the substrate direction. The second sub-width is smaller than the first width, the fourth width is smaller than the first width, and the third width is smaller than the fourth width.

14. The display substrate according to claim 13, characterized in that, The first indentation has a first depth, which is the maximum distance between the sidewall of the fourth insulating layer near the pixel opening and the sidewall of the third insulating layer near the pixel opening, and the first depth is half the difference between the fourth width and the third width.

15. The display substrate according to claim 1, characterized in that, The orthographic projections of the third insulating layer and the fourth insulating layer on the substrate are both within the range of the orthographic projection of the first sub-part on the substrate.

16. The display substrate according to claim 1, characterized in that, The side surface of the first insulating layer is in contact with the side surface of the first electrode.

17. The display substrate according to claim 1, characterized in that, The distortion region includes at least one crack, and the orthographic projection of the distortion region on the substrate is located within the orthographic projection range of the pixel definition structure on the substrate.

18. The display substrate according to claim 17, characterized in that, The display substrate further includes a second electrode disposed on the side of the organic light-emitting layer away from the substrate. The second electrode has a puncture tip disposed in the crack of the distortion area. The orthographic projection of the puncture tip on the substrate does not overlap with the orthographic projection of the first electrode on the substrate. The orthographic projection of the endpoint of the puncture tip on the substrate is located within the range of the orthographic projection of the first insulating layer on the substrate. The endpoint of the puncture tip is the boundary point of the puncture tip closest to the substrate.

19. The display substrate according to claim 18, characterized in that, The orthographic projection of the tip of the puncture tip onto the substrate is within the range of the orthographic projection of the first sub-part onto the substrate.

20. The display substrate according to claim 18, characterized in that, The orthographic projection of the tip of the puncture tip onto the substrate does not overlap with the orthographic projection of the fourth insulating layer onto the substrate.

21. The display substrate according to claim 18, characterized in that, The second electrode includes at least a first part and a second part. The orthographic projection of the first part onto the substrate is within the range of the orthographic projection of the pixel opening onto the substrate. The orthographic projection of the second part onto the substrate is within the range of the orthographic projection of the second insulating layer onto the substrate and is located between the endpoints of the two puncture tips. In the direction perpendicular to the substrate, the maximum distance between the second part and the substrate is greater than the maximum distance between the first part and the substrate.

22. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 21.

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