Micro-OLED chip packaging structure, packaging method and Micro-OLED display device

Abstract

The invention discloses a Micro-OLED (Organic Light Emitting Diode) chip packaging structure, a Micro-OLED chip packaging method and a Micro-OLED display device. The packaging structure comprises a semiconductor wafer which is provided with a conductive through hole penetrating to a metal bonding pad on the front surface of the semiconductor wafer; the plurality of metal bumps are formed on the back surface of the semiconductor wafer and are electrically connected with the metal bonding pads on the front surface through the conductive through holes and the metal rewiring layer on the back surface; the Micro-OLED light emitting layer is formed on the front surface of the semiconductor wafer; and the transparent cover plate is bonded with the front surface of the semiconductor wafer through a supporting wall. According to the invention, the wafer-level chip size packaging process sequence of the Micro-OLED is optimized as follows: the through holes and the salient points are firstly manufactured on the back surface, and then the OLED is manufactured on the front surface. According to the method, the metal bonding pads are allowed to be led out from the two sides, three sides or four sides of the chip, and particularly, the large-current power supply / ground bonding pads are arranged at the four corners of the chip, so that the internal current distribution of the chip is remarkably optimized, the IR voltage drop is reduced, and thinner and smaller Micro-OLED wafer-level packaging with better electrical performance is realized.

Description

Technical Field

[0001] This invention relates to the field of micro-display device packaging technology, specifically to a Micro-OLED chip packaging structure, packaging method, and Micro-OLED display device. Background Technology

[0002] Micro-OLED (micro organic light-emitting diode) displays have broad application prospects in near-eye displays (such as AR / VR devices) and electronic viewfinders due to their advantages such as high resolution, high contrast and fast response.

[0003] Currently, the mainstream Micro-OLED packaging technology uses flexible printed circuit board packaging. For example... Figure 1 The FPC (Flexible Printed Circuit) package shown is a technology that concentrates all the chip's metal pads on one side, achieves electrical connection with the outside through leads on the FPC, and is then covered with a glass cover for protection. Figure 1 The FPC bonding pad area, chip edge, and display pixel area are defined in this context.

[0004] However, the aforementioned FPC packaging technology has the following inherent drawbacks: 1. Uneven power distribution leads to poor display uniformity: Because all electrical signals (including high-current power and ground lines) can only be accessed from one side, for large-area Micro-OLED chips, the current will generate a significant IR (Infrared) voltage drop on the internal metal traces. Pixels farther from the access point have lower operating voltages, resulting in uneven brightness and severely affecting display quality. Systems often require complex circuits and algorithms for compensation, increasing cost and power consumption.

[0005] 2. Low packaging efficiency: FPC packaging is a back-end process performed on a single chip, which cannot achieve wafer-level batch processing, resulting in low production efficiency and high cost.

[0006] 3. Complex process: When adding a cover plate, space needs to be reserved for the FPC of each chip. Usually, the glass cover plate needs to be cut or slotted twice. The process steps are complicated and the yield control is difficult.

[0007] 4. Larger package size and weight: FPC and related bonding materials increase the overall thickness and weight of the module, which does not meet the requirements of wearable devices to be thinner and lighter.

[0008] Therefore, there is an urgent need for a Micro-OLED packaging solution that can improve display uniformity, increase production efficiency, simplify processes, and achieve thinner packaging. Summary of the Invention

[0009] To address the problems existing in the prior art, the present invention provides a Micro-OLED chip packaging structure.

[0010] This invention provides a Micro-OLED chip packaging structure, comprising: A semiconductor wafer is provided with conductive vias that extend to the metal pads on the front side of the semiconductor wafer; Multiple metal bumps are formed on the back side of the semiconductor wafer and electrically connected to the metal pads on the front side through the conductive vias and the metal redistribution layer on the back side. A Micro-OLED light-emitting layer is formed on the front side of the semiconductor wafer; A transparent cover plate is bonded to the front side of the semiconductor wafer via a support wall, and a cavity is formed between the transparent cover plate, the support wall and the front side of the semiconductor wafer to accommodate the Micro-OLED light-emitting layer. The metal pads are arranged on the side of the corresponding chip on the front side of the semiconductor wafer, and the electrical signals are introduced from the side of the chip through the metal bumps.

[0011] Furthermore, the metal pads can be arranged on two, three, or four sides of the chip to enable multi-sided signal input.

[0012] Furthermore, to optimize high-current paths, metal pads used to provide power and ground signals can be preferentially arranged in the four corner areas of the chip.

[0013] Furthermore, to reduce the packaging thickness and drilling difficulty, the thickness of the semiconductor wafer is reduced to between 100μm and 200μm.

[0014] The present invention also provides a wafer-level chip packaging method for Micro-OLED displays, comprising the steps of: S1: Metal pads are formed on the front side of a semiconductor wafer after the semiconductor front-end process is completed. The metal pads are designed to be arranged on the side of the chip. S2: Thin the back side of the semiconductor wafer; S3: Conductive vias are fabricated from the back of the semiconductor wafer to the metal pads on the front, and a metal redistribution layer and metal bumps are formed on the back. S4: Fabricate a Micro-OLED light-emitting layer on the front side of a semiconductor wafer; S5: Bond the transparent cover plate to the front side of the semiconductor wafer through the support wall to form a sealed cavity; S6: The bonded semiconductor wafer and cover plate are cut together to obtain a single packaged Micro-OLED display chip.

[0015] Furthermore, before step S4, step S3a is included: planarizing the back side of the semiconductor wafer that has completed step S3 to facilitate wafer adsorption and transport in the subsequent OLED process; and removing the planarization layer after step S4 and before step S5.

[0016] Furthermore, the planarization process involves coating the back of the semiconductor wafer with photoresist or temporarily bonding a support substrate.

[0017] Furthermore, in step S2, the wafer thickness is reduced from the initial 600-800 μm to 100-200 μm.

[0018] The present invention provides a Micro-OLED display device, including the chip packaging structure as described above.

[0019] The beneficial effects of this invention are as follows: significantly improve display uniformity: by arranging power / ground pads on multiple sides (especially the four corners), the IR voltage drop of the internal interconnects of the chip is greatly reduced, fundamentally improving the consistency of the pixel operating voltage at the physical level, thereby obtaining a more uniform display image and reducing the dependence on the back-end compensation circuit.

[0020] Achieving high-efficiency wafer-level packaging: The entire packaging process (drilling, wiring, ball bonding, cover bonding, dicing) is completed at the wafer level, which can process all chips on the entire wafer at one time, and the production efficiency is much higher than that of single FPC packaging.

[0021] Simplified process and cost savings: A full-length glass cover plate matched to the chip size is used, and it is cut in one step after bonding with the wafer, eliminating the need for complex secondary processing of the cover plate. At the same time, the narrower dicing requirements save the effective wafer area.

[0022] Achieving ultra-thin and lightweight packaging: By thinning the back of the wafer and removing redundant structures such as FPC, the thickness of the packaged chip is significantly reduced and its weight is significantly reduced, perfectly meeting the needs of wearable devices such as AR / VR.

[0023] Strong process integration: The proposed integrated process flow of back-side interconnect first and OLED later, supplemented by back-side planarization technology, successfully solved the key technical problem of wafer-level chip-scale packaging (WLCSP) compatibility with OLED process, providing a practical solution for advanced packaging of Micro-OLED. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of Micro-OLED using FPC packaging in the prior art.

[0026] Figures 2a-2d The above-view schematic diagram shows the metal pads of the present invention being arranged on one side, two sides, three sides, and four sides of the chip.

[0027] Figure 3 This is a schematic diagram of the wafer-level chip layout and packaging alignment marks of the present invention.

[0028] Figure 4 This is a cross-sectional view of the completed packaging structure of the present invention.

[0029] Figure 5 This is a schematic diagram of the metal bumps and rewiring layout on the back of the packaging structure of the present invention (taking four-corner power supply as an example).

[0030] Figure 6 This is a process flow diagram of the packaging method of the present invention. Detailed Implementation

[0031] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0032] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Since this invention pertains to electrical devices, connection and interconnection both refer to conductive interconnections. Because the accompanying drawings describe the same device, the same reference numerals denote the same components.

[0033] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0034] Example 1: See Figures 2b-2d and Figure 4 The Micro-OLED WLCSP packaging structure provided by this invention includes, from bottom to top: Metal bumps: located at the bottom layer, serving as interfaces for soldering to an external circuit board (such as a PCB). Height C1 is approximately 0.16 mm. Semiconductor wafer: its back side is thinned, with a typical thickness C2 of approximately 0.15 mm. Conductive vias are formed in the wafer, electrically connecting the back side and the front side. A metal redistribution layer is also present on the back side for connecting the vias and the metal bumps. Micro-OLED light-emitting layer: fabricated on the front side of the wafer, including an anode, an organic light-emitting functional layer, and a cathode. Support wall: located around the OLED light-emitting layer, with a typical thickness C3 of approximately 0.04 mm, used to define the cavity height. Cavity: enclosed by the support wall, with a typical height C5 of approximately 0.04 mm, used to protect the OLED layer. Transparent cover: typically glass, bonded and sealed to the wafer via the support wall, with a typical thickness C4 of approximately 0.4 mm. The total package height C is typically approximately 0.75 mm.

[0035] like Figures 2b-2d As shown in the diagram, the chip edge, bonding pads, CSP balls, and display pixel area indicate that the chip's input and output metal pads are no longer limited to a single side. They can be flexibly distributed according to circuit design requirements. Figure 2a chip unit, Figure 2b Two adjacent sides (bilateral) Figure 2c Three sides (three sides) or Figure 2d All four sides (four sides).

[0036] like Figure 5 As shown, the chip-scale package (CSP) includes backside metal, CSP balls, bonding pads, ELVDD (anode power), and ELVSS (cathode power). In a preferred embodiment, the pads for the power supply (ELVDD) and ground (ELVSS), which require high current drive, are placed at the four corners of the chip and connected to the metal bumps at the four corners via back-side rewiring. This multi-sided access method allows current to be injected from all sides of the chip, minimizing the path and effectively balancing the voltage distribution inside the chip.

[0037] refer to Figure 3 The invention demonstrates the Chip Scale Package (CSP) alignment mark, which enables highly efficient wafer-level packaging: the entire packaging process (drilling, wiring, ball bonding, cover bonding, and dicing) is completed at the wafer level, allowing all chips on the entire wafer to be processed at once, resulting in production efficiency far exceeding that of single-chip FPC packaging.

[0038] Example 2: This invention provides a packaging method for a Micro-OLED chip, see [link to documentation]. Figure 6 The encapsulation method mainly includes the following steps: S1: A metal pad is formed on the front side of a semiconductor wafer after the semiconductor front-end process is completed. The metal pad is designed to be arranged on at least two sides of the chip. S2: Thin the back side of the semiconductor wafer; S3: Conductive vias are fabricated from the back of the semiconductor wafer to the metal pads on the front, and a metal redistribution layer and metal bumps are formed on the back. S4: Fabricate a Micro-OLED light-emitting layer on the front side of a semiconductor wafer; S5: Bond the transparent cover plate to the front side of the semiconductor wafer through the support wall to form a sealed cavity; S6: The bonded semiconductor wafer and cover plate are cut together to obtain a single packaged Micro-OLED display chip.

[0039] In one embodiment, specifically: Semiconductor front-end fabrication and pad design: Driving circuits such as thin-film transistors are fabricated on silicon-based or other semiconductor wafers. At the top layer of the circuit, a metal pad layer is designed according to the WLCSP specification. The key to this invention is that the pad layout design at this stage is prepared for multi-sided pin routing.

[0040] Backside wafer thinning: The backside of the wafer is mechanically ground and chemically mechanically polished to reduce its thickness from the standard thickness of 600-800 μm to 100-200 μm, for example, from approximately 750 μm to a target thickness of 150 μm. This reduces the difficulty of subsequent drilling and also reduces the chip weight.

[0041] WLCSP (Wafer-Level Chip Scale Package) backside interconnect process: a. Back-side via fabrication: Through-holes are fabricated from the back side of the wafer using processes such as deep reactive ion etching until the metal pads on the front side are exposed.

[0042] b. Via metallization and redistribution: A conductive material (such as copper) is filled into the via, and a metal layer is deposited and patterned on the back side of the wafer to form a redistribution layer, which redistributes the electrical signals from the via to preset bump locations.

[0043] c. Ball placement: Forming metal bumps (such as solder balls) on the pads of the redistribution layer.

[0044] In one preferred embodiment, back-side planarization is also included: since bumps already exist on the back side, the wafer cannot be placed flat on the carrier of the subsequent OLED evaporation equipment. Therefore, a thick layer of photoresist is coated on the back side of the wafer or a flat auxiliary substrate is temporarily bonded to "embed" or cover the bumps, forming a temporary flat back side for transport and adsorption.

[0045] Micro-OLED manufacturing process: Thin films such as OLED anode, organic light-emitting layer, and cathode are sequentially fabricated on the front side of the wafer. This process is carried out in a vacuum evaporation equipment.

[0046] Remove planarization layer: After the OLED process is completed, remove the photoresist or temporary bonding auxiliary substrate applied in step 4 to expose the metal bumps on the back side.

[0047] Cover bonding and encapsulation: A support wall (such as photoresist) is made around the OLED area on the front side of the wafer, and then the entire transparent glass cover is aligned with and bonded to form a sealed cavity to protect the OLED layer.

[0048] Wafer-level dicing: Using a dicing machine or laser, the bonded wafer-cover composite is diced into individual micro display chips in one go.

[0049] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A Micro-OLED chip packaging structure, characterized in that, include: A semiconductor wafer is provided with conductive vias that extend to the metal pads on the front side of the semiconductor wafer; Multiple metal bumps are formed on the back side of the semiconductor wafer and electrically connected to the metal pads on the front side through the conductive vias and the metal redistribution layer on the back side. A Micro-OLED light-emitting layer is formed on the front side of the semiconductor wafer; A transparent cover plate is bonded to the front side of the semiconductor wafer via a support wall, and a cavity is formed between the transparent cover plate, the support wall and the front side of the semiconductor wafer to accommodate the Micro-OLED light-emitting layer. The metal pads are arranged on the side of the corresponding chip on the front side of the semiconductor wafer, and the electrical signals are introduced from the side of the chip through the metal bumps.

2. The packaging structure according to claim 1, characterized in that, The metal pads are arranged on two, three, or four sides of the chip.

3. The packaging structure according to claim 1, characterized in that, Metal pads for providing power and ground signals are arranged in the four corner areas of the chip.

4. The packaging structure according to claim 1, characterized in that, The thickness of the semiconductor wafer is reduced to between 100 μm and 200 μm.

5. The packaging structure according to claim 1, characterized in that, Before forming the Micro-OLED light-emitting layer, the back side of the semiconductor wafer with metal bumps is planarized, and the planarization process includes covering with an organic material layer or a temporary bonding support plate.

6. A wafer-level chip packaging method for Micro-OLED displays, characterized in that, Including the following steps: S1: Metal pads are formed on the front side of a semiconductor wafer after the semiconductor front-end process is completed. The metal pads are designed to be arranged on the side of the chip. S2: Thin the back side of the semiconductor wafer; S3: Conductive vias are fabricated from the back of the semiconductor wafer to the metal pads on the front, and a metal redistribution layer and metal bumps are formed on the back. S4: Fabricate a Micro-OLED light-emitting layer on the front side of a semiconductor wafer; S5: Bond the transparent cover plate to the front side of the semiconductor wafer through the support wall to form a sealed cavity; S6: The bonded semiconductor wafer and cover plate are cut together to obtain a single packaged Micro-OLED display chip.

7. The packaging method according to claim 6, characterized in that, Before step S4, the following steps are also included: The back side of the semiconductor wafer that has completed step S3 is planarized to facilitate wafer adsorption and transport in subsequent OLED processes. The planarization layer is removed after step S4 and before step S5.

8. The packaging method according to claim 7, characterized in that, The planarization process involves coating the back of the semiconductor wafer with photoresist or temporarily bonding a support substrate.

9. The packaging method according to claim 6, characterized in that, In step S2, the wafer thickness is reduced from the initial 600-800 μm to 100-200 μm.

10. A Micro-OLED display device, characterized in that, Includes the chip packaging structure as described in any one of claims 1-5.

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