Semiconductor power insulation packaging device

Abstract

The invention relates to the field of semiconductor packaging, in particular to a semiconductor power insulation packaging device. The device comprises: a housing; the ceramic substrate is located in the shell, the upper surface and the lower surface, opposite to each other, of the ceramic substrate are made of copper foil materials, a layout circuit and a functional bonding pad are etched on the upper surface, the layout circuit is electrically connected with the functional bonding pad, and the lower surface of the ceramic substrate is exposed out of the shell; one end of the pin assembly penetrates into the shell and is welded to the functional bonding pad, and the other end of the pin assembly penetrates out of the shell; the power driving part is positioned in the shell, is arranged on the upper surface and is electrically connected with the layout circuit; the temperature control detection piece is located in the shell and arranged on the functional bonding pad so as to be electrically connected with the pin assembly. Temperature monitoring, insulation protection and efficient heat dissipation are integrated in the same packaging body, heat generated by device work can be effectively released, the working state of the device can be monitored in real time, performance reduction or failure caused by sudden temperature rise and untimely heat dissipation of the chip is avoided, function application is flexible, and efficient insulation heat dissipation requirements of different environments are met.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and in particular to a semiconductor power insulating package device. Background Technology

[0002] As a crucial pillar of national economic development, the development of power electronic devices—the foundation of power electronics technology—is paramount. With the continuous advancement and improvement of high-power semiconductor packaging technology, power electronic devices have been widely applied in traditional fields such as industrial manufacturing and transportation, as well as high-tech fields such as new energy and aerospace. Semiconductor power insulated packages combine power devices with various circuits and components into an independent whole through insulation methods. Utilizing the functions of different chip modules, various power electronic devices and systems can be flexibly constructed. In the current context of emphasizing resource conservation and the development of new energy sources, such as the booming development of wind and photovoltaic power generation, the application of power electronic devices has demonstrated strong growth momentum, providing powerful support for the development of various industries.

[0003] To adapt to the diverse application needs of the semiconductor industry, existing power packaged devices employ several conventional methods. Conventional packaged devices utilize external circuitry with thermistors for temperature monitoring and protection, sensing temperature changes to ensure operation within a suitable temperature range. For insulation, thermal paste is applied to the back of the device, and a heatsink is installed. Thermal paste enhances heat conduction, while the heatsink helps dissipate heat generated by the device, improving insulation performance. These measures, to some extent, meet certain application requirements and are widely used in power electronic systems, becoming common technical approaches.

[0004] However, existing technologies have significant drawbacks. Complex and redundant operations result in inflexible device applications, requiring additional external circuitry and heat dissipation devices, thus increasing the circuit footprint. This makes it difficult for these devices to adapt to scenarios with high space and flexibility requirements, limiting their application scope. Furthermore, this approach cannot achieve integrated insulation and temperature monitoring, failing to meet the industry's demand for power packaged devices with broad adaptability and flexible functionality, and cannot effectively prevent performance degradation or failure caused by sudden temperature rises and inadequate heat dissipation. Summary of the Invention

[0005] The purpose of this application is to overcome the above-mentioned technical problems and provide a semiconductor power insulating package device that integrates temperature monitoring, insulation protection and efficient heat dissipation into the same package. It can effectively release the heat generated by the device during operation, monitor the device's operating status in real time, and prevent the chip from degrading or failing due to sudden temperature rise and untimely heat dissipation. It has flexible functions and applications and can adapt to the efficient insulation and heat dissipation requirements of different environments.

[0006] This application discloses a semiconductor power-isolated packaged device, which specifically adopts the following solution: A semiconductor power insulated package includes: a housing; a ceramic substrate located within the housing, with its upper and lower surfaces both made of copper foil, the upper surface having etched layout circuitry and functional pads, the layout circuitry electrically connected to the functional pads, and the lower surface exposed outside the housing; a pin assembly, one end of which is inserted into the housing and soldered to the functional pads, and the other end of which extends out of the housing; a power driver located within the housing and disposed on the upper surface, electrically connected to the layout circuitry; and a temperature control sensor located within the housing and disposed on the functional pads, electrically connected to the pin assembly.

[0007] By adopting the above technical solution, using a ceramic substrate instead of a conventional lead frame as the chip carrier can meet the insulation requirements of device applications. At the same time, temperature monitoring devices can be integrated to realize the multi-functional application of a single packaged device, expand the packaging application density of power semiconductor power devices, and enable the package to have insulation performance and efficient heat dissipation in high-frequency characteristic applications. Specifically: the upper surface of the ceramic substrate is etched with circuit patterns and functional pads, facilitating the assembly and connection of power drivers and pin assemblies; the power drivers are located on the upper surface and electrically connected to the circuit patterns, enabling corresponding power drive functions; the temperature control detection device is located on the functional pads and electrically connected to the pin assemblies, enabling real-time monitoring of the device's operating status, especially the heat rise monitoring of high-power devices during the conduction and turn-off processes, preventing performance degradation or failure due to sudden temperature rise of the chip inside the package and insufficient heat dissipation during continuous operation; the lower surface of the ceramic substrate is exposed to the housing, which facilitates the timely release of heat generated inside the device from the package and its safe dissipation around the heat-generating equipment or in the environment; the overall structure simplifies the cumbersome operation of adding temperature control devices to the external circuits and adding thermal grease insulation to the bottom of the power devices in conventional packaged devices, optimizing the product assembly technology and process, not only achieving insulation, temperature monitoring and efficient heat dissipation, but also enabling the packaged devices to meet high reliability requirements in high-voltage and high-current applications, suitable for high-end server power supplies, inverter circuits, motor-driven energy storage and charging piles and other technologies.

[0008] Optionally, a condensation pipe is provided on one end of the lower surface, wherein the condensation pipe is composed of multiple parallel and interconnected microchannels, and the two ends of the condensation pipe correspond to the liquid inlet and outlet.

[0009] By adopting the above technical solution, a condensation channel composed of multiple parallel and interconnected microchannels is set on the lower surface of the ceramic substrate, and an inlet and outlet for the liquid are provided. This allows the liquid to flow and condense, providing forced cooling for device operation and meeting the needs of devices in application scenarios that carry high voltage and high current density.

[0010] Optionally, a first equal-diameter circular hole with partial etching is formed on the end of the upper surface away from the functional pad.

[0011] By adopting the above technical solution, a first equal-diameter circular hole with half-etching is opened at the end of the upper surface of the ceramic substrate away from the functional pad. This can release residual stress during assembly, strengthen the bonding strength with the shell during the packaging process, and prevent moisture penetration that could cause device failure.

[0012] Optionally, a second equal-diameter circular hole is partially etched on the lower surface.

[0013] By adopting the above technical solution, a second equal-diameter circular hole with semi-etched surface is opened on the lower surface of the ceramic substrate, which can release the residual stress of assembly and connect with heat sink fins to achieve efficient heat dissipation, thus avoiding the functional failure of the device caused by water vapor penetration.

[0014] Optionally, the housing may have a step and a groove at one end near the pin assembly.

[0015] By adopting the above technical solution, a step is set at the end of the housing near the pin assembly, which can increase the creepage distance of the device. The slot can expand the electrical clearance and insulation strength of the device, thereby meeting the application requirements of internally insulated encapsulated devices with high voltage and high current density.

[0016] Optionally, the power drive includes an insulated gate bipolar transistor chip and a fast recovery diode chip that are electrically connected, both of which are soldered to the upper surface and electrically connected to the layout circuitry; the temperature control detection device is a thermistor for over-temperature monitoring.

[0017] By adopting the above technical solution, the power drive component uses electrically connected insulated gate bipolar transistor chips and fast recovery diode chips, which are soldered onto the upper surface electrical connection circuitry to achieve the intended power drive function. The temperature control detection component uses a thermistor for over-temperature monitoring, which can monitor over-temperature during the circuit operation process, avoiding device overheating or circuit overheating that could lead to shutdown and device failure. Combined with a ceramic substrate with etched circuitry and functional pads, pin components, and a housing, the semiconductor power insulated packaged device can integrate temperature monitoring function while meeting insulation requirements, enabling multi-functional applications of a single packaged device, expanding the packaging application density of power semiconductor devices, and providing insulation performance and efficient heat dissipation during high-frequency applications.

[0018] Optionally, the insulated gate bipolar transistor chip, the fast recovery diode chip, and the layout circuit are electrically connected to each other via ultrasonically wedge-bonded aluminum wire.

[0019] By adopting the above technical solution, ultrasonic wedge welding of aluminum wire is used to realize the electrical connection between the insulated gate bipolar transistor chip, the fast recovery diode chip and the circuit layout. This enables the electrical interconnection and lead-out of the chip's intended function, meeting the circuit function requirements of the device.

[0020] Optionally, through holes are provided at opposite positions on the housing and the ceramic substrate.

[0021] By adopting the above technical solution, through holes are provided at relative positions on the housing and the ceramic substrate, which facilitates subsequent fixing with other devices and ensures the normal and stable operation of the device.

[0022] Optionally, a V-groove is provided at the bend of the pin assembly near the functional pad.

[0023] By adopting the above technical solution, a V-groove is set at the bend of the pin assembly near the functional pad, which can optimize the bonding strength between the pin assembly and the housing and improve the overall reliability and performance of the semiconductor power insulated package device.

[0024] Optionally, an insulating dielectric layer is disposed on the ceramic substrate between the upper surface and the lower surface.

[0025] By adopting the above technical solution, an insulating dielectric layer is set between the upper and lower surfaces of the ceramic substrate, which can meet the insulation requirements of the device, enabling the package to have insulation performance in high-frequency applications, while meeting the insulation requirements of the device application, and enabling the packaged device to achieve high reliability in high voltage and high current application scenarios.

[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. Using a ceramic substrate instead of a conventional lead frame as a chip carrier can meet the insulation requirements of device applications. At the same time, temperature monitoring devices can be integrated to realize the multi-functional application of a single packaged device, expand the packaging application density of power semiconductor power devices, and enable the package to have insulation performance and efficient heat dissipation in high-frequency characteristic applications. 2. The upper surface of the ceramic substrate is etched with circuit patterns and functional pads, facilitating the assembly and connection of power drive components and pin assemblies. The power drive components are located on the upper surface and electrically connected to the circuit patterns, enabling corresponding power drive functions. The temperature control detection component is located on the functional pads and electrically connected to the pin assemblies, enabling real-time monitoring of the device's operating status, especially the heat rise monitoring of high-power devices during the conduction and turn-off processes. This prevents the device from experiencing a sudden drop in performance or failure due to a rapid increase in chip temperature within the package and insufficient heat dissipation during continuous operation. The lower surface of the ceramic substrate is exposed to the housing, which facilitates the timely release of heat generated inside the device from the package and its safe dissipation around the heat-generating equipment or in the environment. The overall structure simplifies the cumbersome operations of adding temperature control components to the external circuitry and adding thermal grease insulation to the bottom of the power device in conventional packaged devices. It optimizes the product assembly technology and process, enabling not only insulation, temperature monitoring, and efficient heat dissipation, but also high reliability requirements for packaged devices in high-voltage and high-current applications. It is suitable for high-end server power supplies, inverter circuits, motor-driven energy storage, and charging piles. 3. A condensation channel consisting of multiple parallel and interconnected microchannels is provided on the lower surface of the ceramic substrate, with liquid inlet and outlet. This allows the liquid to flow and condense, providing forced cooling for device operation and meeting the requirements of the device in applications that carry high voltage and high current density. 4. Semi-etched equal-diameter circular holes are opened on the upper and lower surfaces of the ceramic substrate to release residual assembly stress, strengthen the bonding strength with the housing, and prevent moisture penetration that could cause device failure. Attached Figure Description

[0027] Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor power insulated package device disclosed in an embodiment of this application; Figure 2 for Figure 1 An exploded view of a semiconductor power-insulated packaged device; Figure 3 for Figure 1 A three-dimensional structural schematic diagram of a semiconductor power-insulated packaged device from another angle; Figure 4 for Figure 1 A schematic diagram of the exploded structure of a semiconductor power insulating packaged device after the casing has been removed.

[0028] Explanation of reference numerals in the attached figures: 10. Housing; 11. Step; 12. Groove; 20. Ceramic substrate; 21. Upper surface; 211. Functional pad; 212. First equal-diameter circular hole; 22. Lower surface; 221. Condensation channel; 2211. Microchannel; 222. Second equal-diameter circular hole; 23. Through hole; 30. Pin assembly; 31. V-groove; 40. Power drive; 41. Insulated gate bipolar transistor chip; 42. Fast recovery diode chip; 50. Temperature control detection device; 60. Ultrasonic wedge-welded aluminum wire. Detailed Implementation

[0029] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to and includes any or all possible combinations of one or more of the listed items.

[0030] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0031] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0032] See Figure 1 and Figure 2 This is a semiconductor power insulated package device disclosed in the embodiments of this application, including a housing 10, a ceramic substrate 20, a pin assembly 30, a power drive component 40, and a temperature control detection component 50.

[0033] The ceramic substrate 20 is located inside the housing 10, which is encased in epoxy resin to provide physical and chemical protection for the internal components. One end of the pin assembly 30 is soldered to the functional pad 211 on the upper surface 21 of the ceramic substrate 20 inside the housing 10, and the other end extends out of the housing 10, realizing the electrical connection between the device and the external circuit. The power drive 40 and the temperature control detection 50 are both inside the housing 10. The power drive 40 is located on the upper surface 21 of the ceramic substrate 20 and is electrically connected to the layout circuit. The temperature control detection 50 is located on the functional pad 211 and is electrically connected to the pin assembly 30. This arrangement enables the device to realize the functions of power drive and temperature detection, and achieves electrical interconnection through the circuit on the ceramic substrate 20, improving the integration, avoiding complex external circuits, reducing the circuit application area, and making the device application more flexible.

[0034] See also Figure 3 The upper surface 21 and lower surface 22 of the ceramic substrate 20 are both made of copper foil, with an insulating dielectric layer in between to ensure electrical insulation between the upper surface 21 and the lower surface 22, thereby improving the safety and reliability of the device. The upper surface 21 is etched to form layout circuitry and functional pads 211, with the layout circuitry electrically connecting to the functional pads 211. Copper foil has good electrical and thermal conductivity, meeting the requirements for circuit transmission and heat dissipation. The etching process on the upper surface 21 can precisely form the required circuitry and pads, facilitating the connection between the power drive component 40 and the pin assembly 30. Of course, in other embodiments, other metal foils with good conductivity, such as aluminum foil, can also be used, but copper foil has certain advantages in terms of conductivity and cost.

[0035] See Figure 2 and Figure 4 A semi-etched first equal-diameter circular hole 212, such as 0.4 mm in diameter, is formed on the end of the upper surface 21 away from the functional pad 211. These holes can release residual assembly stress, strengthen the bonding strength with the housing 10, and prevent moisture penetration that could cause device failure. Alternatively, other shapes of holes, such as square holes, can also be used.

[0036] See Figure 3The lower surface 22 is exposed outside the housing 10 for heat dissipation. A condensation channel 221 can also be provided at one end of the lower surface 22. The condensation channel 221 consists of multiple parallel and interconnected microchannels 2211, with the two ends of the condensation channel 221 corresponding to the liquid inlet and outlet. Condensation is achieved through the flow of liquid through the inlet and outlet, providing forced cooling for device operation and improving heat dissipation efficiency. Of course, other heat dissipation methods such as heat sink fins can be used instead, but the condensation channel 221 has advantages in terms of heat dissipation effect and space utilization. Additionally, a semi-etched second equal-diameter circular hole 222, such as one with a diameter of 0.4 mm, can also be formed on the lower surface 22, also for residual stress relief.

[0037] See Figure 2 , Figure 3 and Figure 4 One end of the pin assembly 30 is inserted into the housing 10 and soldered to the functional pad 211, while the other end extends out of the housing 10. The pin assembly 30 may include multiple parallel pins. The temperature control sensor 50 is located inside the housing 10 and is disposed on the functional pad 211 to electrically connect to the pin assembly 30.

[0038] The temperature control detection component 50 is a thermistor used for over-temperature monitoring. The thermistor can sense temperature changes in the device in real time. The temperature control detection component 50 can be attached to the functional pad 211 using a preset solder paste printing pattern, and electrically connected to two pins. These two pins transmit temperature information to the external circuit, enabling temperature monitoring of the device and preventing system crashes and device failures caused by device overheating or circuit overheating. Alternatively, in other embodiments, a single thermistor chip can be used, bonded to the functional pad 211 with conductive paste, and then bonded to the surface of the thermistor chip and the functional pad 211 using electrical connection wires such as aluminum wires, achieving the same temperature control detection function.

[0039] In addition, the pin assembly 30 has a bend at one end near the functional pad 211, and a V-groove 31 is provided at the bend. This structural design can enhance the bonding strength between the pin assembly 30 and the housing 10.

[0040] See Figure 2 and Figure 4 The power drive unit 40 is located inside the housing 10 and is electrically connected to the circuit layout on the upper surface 21 of the ceramic substrate 20. The power drive unit 40 includes an insulated gate bipolar transistor chip 41 and a fast recovery diode chip 42 that are electrically connected to each other. The two can be first attached to the solder paste pre-printed on the upper surface 21 of the ceramic substrate 20, and then soldered to the ceramic substrate 20 after reflow soldering.

[0041] The insulated gate bipolar transistor chip 41 and the fast recovery diode chip 42 are ultrasonically bonded to the layout circuit via ultrasonic wedge bonding aluminum wire 60, realizing the electrical interconnection and lead-out of the power drive unit 40 with the intended function.

[0042] See Figure 3 The housing 10 has a step 11 near the pin assembly 30 to increase the creepage distance. The step 11 meets the requirements of high voltage and high current operation, improving the insulation performance of the device. Of course, in this embodiment, one or more steps 11 can be used. Additionally, the housing 10 near the pin assembly 30 also has several slots 12 to expand the electrical clearance and insulation strength of the device, meeting the requirements of internally insulated packaged devices with high voltage and high current density. The positions of the step 11 and the slots 12 are as follows... Figure 3 As shown.

[0043] In addition, see Figure 2 and Figure 4 Through holes 23 are provided at opposite positions on the housing 10 and the ceramic substrate 20 for fixing. Through the through holes 23, it is easy to fix it to other devices in the future to ensure the normal and stable operation of the device.

[0044] The implementation principle of this embodiment is as follows: Using a ceramic substrate 20 as a carrier, the power drive component 40 and the temperature control detection component 50 are integrated into the same package, achieving integrated temperature monitoring, insulation protection, and efficient heat dissipation. The upper surface 21 of the ceramic substrate 20 is etched with circuit patterns and functional pads 211, facilitating electrical connections and layout of the device; the lower surface 22 is exposed for heat dissipation and can be equipped with condensation pipes 221 for forced cooling, improving heat dissipation efficiency. The special design of the pin assembly 30 ensures the reliability of electrical connections, and the stepped design 11 of the housing 10 increases the creepage distance and improves insulation performance. The temperature control detection component 50 monitors the device temperature in real time, avoiding performance degradation or failure caused by sudden temperature rises and untimely heat dissipation. Overall, this device has wide adaptability and flexible functional applications, meeting the efficient insulation and heat dissipation requirements of different environments. Compared with existing technologies, it reduces external circuitry and complex operations, improving device performance and reliability.

[0045] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A semiconductor power-isolated packaged device, characterized in that, include: Shell (10); A ceramic substrate (20) is located inside the housing (10), and its upper surface (21) and lower surface (22) are both made of copper foil. The upper surface (21) is etched with layout circuits and functional pads (211), and the layout circuits are electrically connected to the functional pads (211). The lower surface (22) is exposed outside the housing (10). The pin assembly (30) has one end inserted into the housing (10) and soldered to the functional pad (211), and the other end protruding from the housing (10). A power drive unit (40) is located inside the housing (10) and is disposed on the upper surface (21) and electrically connected to the layout circuitry; A temperature control detection element (50) is located inside the housing (10) and disposed on the functional pad (211) to electrically connect to the pin assembly (30).

2. The semiconductor power-isolated packaged device according to claim 1, characterized in that, A condensation pipe (221) is provided on one end of the lower surface (22), wherein the condensation pipe (221) is composed of multiple parallel and interconnected microchannels (2211), and the two ends of the condensation pipe (221) correspond to the liquid inlet and outlet.

3. The semiconductor power-isolated packaged device according to claim 1, characterized in that, A first equal-diameter circular hole (212) is partially etched on the upper surface (21) at the end away from the functional pad (211).

4. The semiconductor power-isolated packaged device according to claim 3, characterized in that, A second equal-diameter circular hole (222) is partially etched on the lower surface (22).

5. The semiconductor power-isolated packaged device according to claim 1, characterized in that, The housing (10) has a step (11) and a slot (12) at one end near the pin assembly (30).

6. The semiconductor power-isolated packaged device according to claim 1, characterized in that, The power drive (40) includes an insulated gate bipolar transistor chip (41) and a fast recovery diode chip (42) that are electrically connected, both of which are soldered on the upper surface (21) and electrically connected to the layout circuitry; The temperature control detection element (50) is a thermistor used for over-temperature monitoring.

7. The semiconductor power-isolated packaged device according to claim 6, characterized in that, The insulated gate bipolar transistor chip (41), the fast recovery diode chip (42), and the layout circuit are electrically connected to each other via ultrasonically wedge-bonded aluminum wire (60).

8. The semiconductor power-isolated packaged device according to claim 1, characterized in that, Through holes (23) are provided at opposite positions on the housing (10) and the ceramic substrate (20).

9. The semiconductor power-isolated packaged device according to claim 1, characterized in that, The pin assembly (30) has a V-groove (31) at the bend near the functional pad (211).

10. The semiconductor power-isolated packaged device according to claim 1, characterized in that, An insulating dielectric layer is disposed on the ceramic substrate (20) between the upper surface (21) and the lower surface (22).

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