Semiconductor die assembly and method of manufacturing the same

Abstract

Semiconductor die assemblies and methods of making the same are provided. The method includes receiving a first wafer including a first semiconductor device and a first interconnect structure disposed over and coupled to the first semiconductor device; forming a barrier liner on a portion of the first interconnect structure; forming a test pad on the barrier pad; performing a first test on the first semiconductor device through the test pad; forming a first bonding structure over the first interconnect structure; receiving a second wafer including a second semiconductor device and a second interconnect structure over and coupled to the second semiconductor device; forming a second bonding structure over the second interconnect structure; bonding the first wafer to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; and performing a second test on the wafer assembly.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor die assemblies and methods for manufacturing the same. Background Technology

[0002] As integrated circuit technology continues to advance, efforts are being made to improve performance and density, refine size specifications, and reduce costs. One approach explored by designers to achieve these benefits is the implementation of stacked three-dimensional (3D) integrated circuits. Some areas suitable for considering 3D integrated circuits include stacking two or more chips manufactured using different manufacturing processes, or stacking chips manufactured using the same manufacturing process, to reduce the footprint of the integrated circuit device. Summary of the Invention

[0003] Some embodiments of this application provide a method for manufacturing a semiconductor die assembly, comprising: receiving a first wafer, the first wafer including a first semiconductor device and a first interconnect structure disposed above and electrically coupled to the first semiconductor device; forming a first barrier pad on a portion of the first interconnect structure; forming a first test pad on the first barrier pad; performing a first test on the first semiconductor device through the first test pad; forming a first bonding structure above the first interconnect structure; receiving a second wafer, the second wafer including a second semiconductor device and a second interconnect structure located above and coupled to the second semiconductor device; forming a second bonding structure above the second interconnect structure; bonding the first wafer to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; and performing a second test on the wafer assembly.

[0004] Other embodiments of this application provide a method for manufacturing a semiconductor die assembly, comprising: forming a passivation layer on a first wafer including an interconnect structure; depositing a first conductive layer in and over the passivation layer; removing a portion of the first conductive layer to form a test pad over the portion of the interconnect structure; performing a first test on the first wafer through the test pad; removing the test pad in response to the first wafer meeting the test specifications of the first test; forming a first bonding structure over the passivation layer; forming a second bonding structure over a second wafer; bonding the first wafer to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; and performing a second test on the wafer assembly.

[0005] Further embodiments of this application provide a semiconductor die assembly, comprising: a first die including a first semiconductor device and a first interconnect structure disposed above the first semiconductor device; a passivation layer covering the first interconnect structure; a barrier pad laterally surrounded by the passivation layer and in contact with the first interconnect structure; a bonding structure disposed above the passivation layer and the barrier pad; and a second die disposed on the bonding structure and including a second semiconductor device and a second interconnect structure. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0008] Figure 2 This is a top view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0010] Figure 16 This is a top view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0011] Figure 17 , Figure 18 , Figure 19A and Figure 19B This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0012] Figure 20 This is a flowchart of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0013] Figure 21 and Figure 22 This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0014] Figure 23 This is a flowchart of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0015] Figure 24 and Figure 25 This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0016] Figure 26 This is a flowchart of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0017] Figure 27 and Figure 28 This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0018] Figure 29 This is a flowchart of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0019] Figure 30 and Figure 31 This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0020] Figure 32 This is a flowchart of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure.

[0021] Figures 33 to 36 This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0024] As used herein, terms such as “first,” “second,” and “third” describe individual elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Terms such as “first,” “second,” and “third,” when used herein, do not imply order, sequence, or importance unless the context clearly indicates otherwise.

[0025] While the numerical ranges and parameters illustrating the broad scope of embodiments of this disclosure are approximate, the numerical values ​​described in specific embodiments are reported as precisely as possible. However, any numerical value inherently includes some error that is necessarily caused by normal deviations found in the corresponding test measurements. Furthermore, as used herein, the terms “substantially,” “about,” or “approximately” generally mean within a value or range that can be considered by one of ordinary skill in the art (e.g., within 10%, 5%, 1%, or 0.5% of a given value or range). Alternatively, the terms “substantially,” “about,” or “approximately” mean within an acceptable standard error of the average value as considered by one of ordinary skill in the art. One of ordinary skill in the art will understand that acceptable standard errors can vary depending on the technology. Except in operational / working instances, or unless otherwise expressly stated, all numerical ranges, quantities, values, and percentages disclosed herein, such as the amount of material used therein, duration, temperature, operating conditions, ratios of quantities, etc., should be understood to be modified by the terms “substantially,” “about,” or “approximately” in all instances. Therefore, unless indicated to the contrary, the numerical parameters set forth in embodiments of this disclosure and the appended claims are approximate values ​​that can vary as needed. At a minimum, each numerical parameter should be interpreted based on the number of significant figures reported and by applying standard rounding techniques. Ranges may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise stated.

[0026] In current processes used to manufacture bonded wafer structures (such as wafer-on-wafer structures), the functional performance of individual wafers is typically unknown before bonding. Circuit probe testing, for example, can only be performed after the wafers have been bonded together to form the bonded wafer structure and contact pads have been formed on the bonded wafer structure. However, if one of the wafers used to form the bonded wafer structure is defective, the entire bonded wafer structure may also be defective and may need to be discarded. This can significantly reduce productivity and increase the costs associated with manufacturing the bonded wafer structure.

[0027] Therefore, there is a need for bonding wafer structures and methods for manufacturing bonding wafer structures that enable improved testing of individual wafers before they are bonded together to form a bonding wafer structure. Various embodiments disclosed herein include forming one or more contact pads over the interconnect structure of the wafers before bonding one wafer to another to form a bonding wafer structure. The presence of such contact pads makes it possible to perform comprehensive testing on the individual wafers, including circuit probe testing, before forming the bonding wafer structure. Such testing enables earlier identification of defective wafers, resulting in improved yields and reduced costs for manufacturing the bonding wafer structure.

[0028] Figure 1 This is a flowchart of a method 100 for manufacturing a semiconductor die assembly 10 according to some embodiments of the present disclosure. Figure 2 and Figure 16 This is a top view of an intermediate stage of a method 100 for manufacturing a semiconductor die assembly 10 according to some embodiments of the present disclosure. Figures 3 to 15 and Figures 17 to 19B This is a cross-sectional view of an intermediate stage of a method 100 for manufacturing a semiconductor die assembly 10 according to some embodiments of the present disclosure. In the following description, reference is made to... Figure 1 The process steps shown are discussed. Figures 2 to 19B The manufacturing stages are shown. It should be understood that... Figure 1 Additional steps are provided before, during, and after the steps shown, and for additional embodiments of method 100, some of the steps described below may be replaced or eliminated. The order of the steps may be changed.

[0029] refer to Figure 2 ,according to Figure 1In step S102, a first wafer W1 is received. In some embodiments, the first wafer W1 includes a plurality of first semiconductor dies 200 arranged in columns and rows. The first semiconductor dies 200 are spaced apart from each other by scribe lines 201, which will be cut in a subsequent die-cutting operation to separate the first semiconductor dies 200 from each other. The first semiconductor dies 200 may include any type of integrated circuit, such as processors, logic circuits, memory circuits, analog circuits, digital circuits, mixed-signal circuits, etc.

[0030] Figure 3 This is a cross-sectional view of a portion of the first wafer W1. In some embodiments, Figure 3 It is along Figure 2 A cross-sectional view taken along line A-A'. In some embodiments, each of the first semiconductor die 200 includes a substrate 202, a respective semiconductor device 204, and a first interconnect structure 206. The substrate 202 may be a semiconductor substrate comprising silicon, germanium, gallium arsenide, silicon carbide, or another semiconductor material used for semiconductor device processing. However, embodiments of this disclosure are not limited thereto, and other suitable materials may be used to form the substrate 202. The semiconductor device 204 may be disposed in and / or on the substrate 202. The semiconductor device 204 may include active devices (e.g., transistors, diodes, etc.), passive devices (e.g., resistors, capacitors, inductors, etc.), or combinations thereof. The semiconductor device 204 may be formed in and / or on the substrate 202 during a front-end process (FEOL) stage.

[0031] A first interconnect structure 206 may be disposed above the substrate 202 and the semiconductor device 204. In some embodiments, the first interconnect structure 206 electrically connects the semiconductor device 204 to form an integrated circuit. In some embodiments, the first interconnect structure 206 includes a plurality of wires 2062 and a plurality of conductive vias 2064 stacked alternately. The wires 2062 and conductive vias 2064 may include metals such as copper (Cu), aluminum (Al), aluminum-copper alloys, etc.

[0032] In some embodiments, the conductor 2062 and the conductive via 2064 are laterally surrounded by one or more dielectric layers, such as an intermetallic layer (IMD), interlayer dielectric layers (ILD1 to ILD). N and etch stop layer ESL1 to ESL N Where N is an integer. In some embodiments, the interlayer dielectric layers ILD1 to ILD N and etch stop layer ESL1 to ESL NThe layers are stacked alternately. Intermetallic layers (IMDs) are disposed between the etch stop layer (ESL1) and the substrate 202, and between the etch stop layer (ESL1) and the semiconductor device 204. Conductors 2062 can extend horizontally in the X direction and in the Y direction perpendicular to the X direction. Conductive vias 2064 can extend vertically (i.e., in the Z direction) to intersect dielectric layers ILD1 to ILD2 between two adjacent layers. N Electrical connections are provided between the conductors 2062 in the structure. For example, conductive vias 2064 allow interlayer dielectric layers (ILDs) to be connected. N-2 The conductor 2062 is electrically connected to the interlayer dielectric layer (ILD). N Another conductor in the circuit is 2062.

[0033] In some embodiments, the interlayer dielectric layers ILD1 to ILD N and etch stop layer ESL1 to ESL N Including different dielectric materials. Etching stop layers ESL1 to ESL N Composed of interlayer dielectric layers ILD1 to ILD N Different etching selectivity is achieved by forming dielectric materials with varying etching selectivity. For example, interlayer dielectric layers ILD1 to ILD... N The material can be selected relative to the etch stop layer ESL1 to ESL. N Regarding a certain etchant, it exhibits high etching selectivity. For example, in some embodiments, the interlayer dielectric layers ILD1 to ILD... N Includes oxides, and etch stop layers ESL1 to ESL N Including nitrides. Intermetallic layer IMD, interlayer dielectric layers ILD1 to ILD. N and etch stop layer ESL1 to ESL N They can be collectively referred to as dielectric stack 208.

[0034] In some embodiments, the first interconnect structure 206 further includes the conductors 2062 and the interlayer dielectric layers ILD1 to ILD. N Between, located between conductor 2062 and etch stop layer ESL1 to ESL N Between, located between conductive via 2064 and interlayer dielectric layers ILD1 to ILD N Between and located between conductive via 2064 and etch stop layers ESL1 to ESL N The conductive pad 2066 is used to bond the conductor 2062 and the conductive via 2064 to the dielectric layers ILD1 to ILD. The conductive pad 2066 can be formed of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. N and etch stop layer ESL1 to ESL NThe conductive pad 2066 also prevents metal from diffusing from the conductor 2062 and the conductive via 2064 to the adjacent dielectric layers ILD1 to ILD2. N and adjacent etch stop layers ESL1 to ESL N In the middle. First interconnect structure 206, dielectric layers ILD1 to ILD N and etch stop layer ESL1 to ESL N It can be formed on top of substrate 202 and semiconductor device 204 during the back-to-office (BEOL) stage.

[0035] In some embodiments, the first semiconductor die 200 further includes one or more contact plugs 205 for connecting the semiconductor device 204 to the first interconnect structure 206. The contact plugs 205 are disposed between the semiconductor device 204 and the first interconnect structure 206 and are laterally surrounded by an intermetallic layer (IMD). The contact plugs 205 may include a metal such as tungsten (W). A dielectric stack 208 may cover the substrate 202 and the semiconductor device 204 and laterally surround the contact plugs 205 and the first interconnect structure 206.

[0036] refer to Figure 4 ,according to Figure 1 In step S104, a passivation layer 210 is deposited over the first wafer W1. In some embodiments, the passivation layer 210 is deposited over the first interconnect structure 206 and the dielectric stack 208. The passivation layer 210 may be adjacent to the topmost interlayer dielectric layer ILD. N Contact the topmost conductor, 2062T. (Reference) Figure 3 and Figure 4 The topmost interlayer dielectric layer (ILD) N This can be the dielectric layer of the dielectric stack 208 furthest from the substrate 200 and / or the semiconductor device 204. The topmost conductor 2062T can be the first interconnect structure 206 furthest from... Figure 3 The farthest wires of the substrate 200 and / or semiconductor device 204 shown.

[0037] refer to Figure 4 The passivation layer 210 can be a single-layer structure or a multi-layer structure. In some embodiments, the passivation layer 210 includes two layers, such as a bottom layer 212 and a top layer 214. The bottom layer 212 is disposed between the top layer 214 and the topmost conductor 2062T, and between the top layer 214 and the topmost dielectric layer ILD. N However, the embodiments disclosed herein are not limited thereto, and the passivation layer 210 may include more than two layers.

[0038] In some embodiments, the bottom layer 212 and the top layer 214 comprise different dielectric materials. For example, in some embodiments, the bottom layer 212 comprises a nitride, and the top layer 214 comprises an oxide. The bottom layer 212 has a thickness T1. The top layer 214 may have a thickness T2 greater than the thickness T1 of the bottom layer 212. The bottom layer 212 and the top layer 214 may be formed, respectively, by sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, combinations thereof, or other suitable techniques.

[0039] After depositing the passivation layer 210, a patterned mask layer 310 is formed on the top layer 214. The patterned mask layer 310 may include openings 312 to expose a portion of the upper surface 2142 of the top layer 214. The formation of the patterned mask layer 310 may include forming a mask layer and a blanket photoresist layer on the top layer 214; and a patterned blanket photoresist layer. The pattern of the photoresist layer is then transferred to the mask layer to form the patterned mask layer 310.

[0040] refer to Figure 5 ,according to Figure 1 In step S106, a plurality of trenches 216 are formed in the passivation layer 210. The trenches 216 penetrate the passivation layer 210 and are formed by one or more etching operations using a patterned mask layer 310 as an etching mask. At least a portion of the topmost conductor 2062T in each first semiconductor die 200 is exposed through the trenches 216. During the etching operation, the top layer 214 and the bottom layer 212 are etched sequentially to form the trenches 216. The etching operation may include wet etching, dry etching, combinations thereof, etc.

[0041] After the etching operation, the bottom layer 212 includes sidewalls 2122 exposed through trench 216, wherein the angle α between the sidewalls 2122 and the upper surface 2063 of the topmost conductor 2062T can be equal to or greater than 90 degrees. Furthermore, after the etching operation, the top layer 214 may include sidewalls 2144 exposed through trench 216 and connected to the sidewalls 2122 of the bottom layer 212. After forming the trench 216, the patterned mask layer 310 is removed using a suitable operation.

[0042] refer to Figure 6 ,according to Figure 1In step S108, a first conductive layer 220 is deposited in trench 216 and over top layer 214. The first conductive layer 220 may conform to the upper surface 2142 and sidewalls 2144 of top layer 214, the sidewalls 2122 of bottom layer 212, and the upper surface 2063 of the topmost conductor 2062T exposed through trench 216. The first conductive layer 220 may comprise titanium, titanium nitride, tantalum, tantalum nitride, or another suitable conductive material. The first conductive layer 220 may be formed by, for example, PVD, CVA, ALD, or another suitable technique.

[0043] Still referencing Figure 6 ,according to Figure 1 In step S110, a second conductive layer 230 is deposited on the first conductive layer 220. In some embodiments, the second conductive layer 230 is conformally fitted to the first conductive layer 220. The second conductive layer 230 may include aluminum, copper, aluminum alloy, copper alloy, etc. The second conductive layer 230 can be formed by, for example, sputtering, CVD, PVD, ALD, or another suitable technique. The first conductive layer 220 may, for example, serve as an oxygen barrier to prevent oxygen in the passivation layer 210 from reaching and oxidizing the second conductive layer 230.

[0044] Subsequently, a patterned mask layer 320 is formed on a portion of the second conductive layer 230. In some embodiments, each of the patterned mask layers 320 overlaps perpendicularly with one of the trenches 216. The patterned mask layers 320 may also overlap with portions of the passivation layer 210 surrounding the trenches 216. The formation of the patterned mask layers 320 may be substantially the same as the formation of the patterned mask layers 310. The patterned mask layers 320 may be used to pattern the first conductive layer 220 and the second conductive layer 230. The patterned mask layers 320 may overlap with a portion of the topmost interconnect line 2062T of the first interconnect structure 206.

[0045] refer to Figure 7 ,according to Figure 1 In step S112, portions of the first conductive layer 220 and the second conductive layer 230 are removed to form a barrier pad 222 and a test pad 232. The barrier pad 222 and the test pad 232 can be formed using a patterned mask layer 320 as an etching mask through one or more etching operations. In some embodiments, an etching operation is performed to sequentially remove portions of the second conductive layer 230 and the first conductive layer 220 not covered by the patterned mask layer 320. The removed portions of the first conductive layer 220 and the second conductive layer 230 are offset from the portion of the topmost conductor 2062T exposed through the trench 216.

[0046] According to some embodiments, such as Figure 7As shown, each barrier pad 222 includes a central section 2222, a peripheral section 2224, and a middle section 2226. The central section 2222 is disposed, for example, in a trench 216 and contacts the topmost conductor 2062T. The peripheral section 2224 may be disposed on the upper surface 2142 of the top layer 214. The middle section 2226 is disposed, for example, in the trench 216 and connects the central section 2222 to the peripheral section 2224. The middle section 2226 may be conformally fitted to the sidewall 2122 of the bottom layer 212 and the sidewall 2144 of the top layer 214.

[0047] The top layer 214 can be partially removed during the patterning of the first conductive layer 220 and the second conductive layer 230. Therefore, after the etching operation, the top layer 214 has a non-uniform thickness. In some embodiments, during the formation of the barrier pad 222 and the test pad 232, the portion of the top layer 214 exposed by the patterned mask layer 320 is removed. After the etching operation, the portion of the top layer 214 located below the barrier pad 222 and the test pad 232 has a thickness T2, and the remaining portion of the top layer 214 exposed through the barrier pad 222 and the test pad 232 has a thickness T3 less than the thickness T2. The top layer 214 may at least partially and laterally surround the barrier pad 222 and the test pad 232. After the formation of the barrier pad 222 and the test pad 232, the patterned mask layer 320 is removed using appropriate operations.

[0048] refer to Figure 8 According to step S114, the first semiconductor die 200 is tested via test pads 232. Tests can be performed to determine the functionality of the first semiconductor die 200. In some embodiments, the test is performed by coupling the first semiconductor die 200 to a test apparatus 300 via test pads 232. The test apparatus 300 includes a plurality of test probes 302. The test apparatus 300 can be physically and electrically coupled to each first semiconductor die 200 via one of the test probes 302. In some embodiments, the test probes 300 are arranged in columns and rows for parallel testing of all first semiconductor dies 200 on the entire first wafer W1 at once, for efficiency and to minimize test time.

[0049] The testing apparatus 300 may be operable to perform one or more wafer-level tests to determine the performance and reliability of a first semiconductor die 200 on a first wafer W1 under various conditions. Wafer-level tests may include acceptance tests, characterization tests, aging / stress tests, etc. The testing apparatus 300 may be configured to generate test signals to be sent to the first semiconductor die 200 and to collect test results from the first semiconductor die 200. Each test probe 302 is used to send a test signal to a corresponding test pad 232 and receive test results from the corresponding test pad 232. The testing apparatus 300 may also be configured to analyze the test results and identify good dies and defective dies. In some embodiments, a first semiconductor die 200 that successfully meets the test specifications is identified as a known good die. On the other hand, a first semiconductor die 200 that fails to meet the test specifications is determined to be a defective die. The test specifications may include the conditions and sequence of tests and an acceptable range of parameters. After a subsequent die sawing operation, defective dies may be marked as excluded from the packaging operation. Therefore, packaging costs can be saved.

[0050] The test probe 302 has sufficient rigidity to prevent substantial deformation or movement during testing, thereby avoiding test failure. During testing, the test probe 302 may press or squeeze the test pad 232 to electrically connect to the first semiconductor die 200, which may cause damage to the test pad 232. According to some embodiments, such as Figure 9 As shown, after the test is performed, probe marker 234 remains on the test area of ​​test pad 232. Probe marker 234 may include probes from... Figure 8 One or more grooves extending inward from the boundary of the test pad 232 shown. The probe mark 234 may also include... Figure 8 The test pad 232 shown has one or more protrusions extending outward from its boundary. The test pad 232, including the probe marker 234, may have a non-smooth and rough upper surface 2322 above the central section 2222 of the barrier pad 222.

[0051] refer to Figure 10 ,according to Figure 1In step S116, a capping layer 240 is deposited over the passivation layer 210. The capping layer 240 is deposited on the top layer 214 and the test pad 232. In some embodiments, the capping layer 240 is conformally oriented to the top layer 214, the barrier pad 222, and the test pad 232. The interface between the capping layer 240 and the top layer 214 is lower than the interface between the barrier pad 222 and the top layer 214. The capping layer 240 may comprise the same material as the top layer 214. For example, the capping layer 240 comprises an oxide. The capping layer 240 can be formed by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), spin coating, combinations thereof, etc.

[0052] Subsequently, according to Figure 1 In step S118, an etch stop layer 242 is deposited on the capping layer 240. The etch stop layer 242 may be conformal to the capping layer 240. In some embodiments, the etch stop layer 242 is formed of a dielectric material having an etch selectivity different from that of an adjacent layer (e.g., the capping layer 240). For example, in some embodiments, the etch stop layer 242 comprises silicon nitride. However, embodiments of this disclosure are not limited thereto, and other suitable materials may be used to form the etch stop layer 242. The etch stop layer 242 may be deposited by, for example, CVD, PECVD, or combinations thereof.

[0053] refer to Figures 11 to 15 ,according to Figure 1 In step S120, a first bonding structure 250 is formed over the first wafer W1. In some embodiments, the first bonding structure 250 is disposed over the first interconnect structure 206. The first bonding structure 250 may be electrically coupled to the first interconnect structure 206. The first bonding structure 250 may be disposed on the front side of the first wafer W1. The front side of the first wafer W1 is the location for fabricating the semiconductor device 204.

[0054] refer to Figure 11 A bonding dielectric layer 252 is deposited over the etch stop layer 242. In some embodiments, the bonding dielectric layer 252 is formed of a dielectric material having an etch selectivity different from that of the etch stop layer 242. The bonding dielectric layer 252 may include, for example, but not limited to, oxides. The bonding dielectric layer 252 may be deposited using CVD, ALD, or another deposition technique. In some embodiments, a planarization operation is performed on the bonding dielectric layer 252. After the planarization operation, the bonding dielectric layer 252 may have a substantially flat top surface. The planarization operation may include chemical mechanical polishing (CMP).

[0055] Subsequently, a patterned mask layer 330 is formed on at least a portion of the bonding dielectric layer 252. The formation of the patterned mask layer 330 may be substantially the same as the formation of the patterned mask layer 310. In some embodiments, the patterned mask layer 330 includes at least one opening 332 in each first semiconductor die 200. The opening 332 may be disposed on the portion of the topmost conductor 2062T not covered by the barrier pad 222 and the test pad 232.

[0056] refer to Figure 12 One or more etching operations are performed to etch the bonding dielectric layer 252, etch stop layer 242, capping layer 240, and passivation layer 210 through opening 332, thereby forming a via 260 to expose a portion of the topmost conductor 2062T. The etching operations may include wet etching, dry etching, combinations thereof, etc. After forming the via 260, the patterned mask layer 330 is removed using a suitable operation.

[0057] refer to Figure 13 A patterned mask layer 340 is formed on at least a portion of the bonding dielectric layer 252. The formation of the patterned mask layer 340 may be substantially the same as the formation of the patterned mask layer 320. The patterned mask layer 340 may include a plurality of openings 342 respectively connected to the through-hole 260.

[0058] refer to Figure 13 and Figure 14 Through-hole trenches 260 are formed by etching an etch stop layer 242 and a bonding dielectric layer 252 through opening 342. Each of the via trenches 260 may include an upper trench 264U and a lower through-hole 262L connected to each other. In some embodiments, the upper trench 264U is laterally surrounded or defined by the etch stop layer 242 and the bonding dielectric layer 252, and the lower through-hole 262L is laterally surrounded or defined by a passivation layer 210 and a capping layer 240. The upper trench 264U has a width Wa. The lower through-hole 262L may have a width Wb smaller than the width Wa of the upper trench 264U. In some embodiments, the via trenches 260 are formed using a dual damascene process, and the dual damascene process is, for example, a via-then-trench method. However, embodiments of the present disclosure are not limited thereto, and the via trenches 260 may be formed using a trench-then-via method. After forming the through-hole trench 260, the patterned mask layer 340 is removed using appropriate operations.

[0059] refer to Figure 15A bonding interconnect structure 254 is formed in the via trench 260. Thus, the first bonding structure 250 is fully formed. The first bonding structure 250 may include a bonding dielectric layer 252 and bonding interconnect structures 254 that are at least laterally surrounded by the bonding dielectric layer 252. Each bonding interconnect structure 254 may also be electrically coupled to the underlying first semiconductor die 200. In some embodiments, each bonding interconnect structure 254 penetrates the bonding dielectric layer 252, the etch stop layer 242, the capping layer 240, and the passivation layer 210, and contacts the underlying first interconnect structure 206. In cross-sectional view, the bonding interconnect structure 254 may have a T-shape. In some embodiments, the bonding interconnect structure 254 is spaced apart from the barrier pad 222. In some embodiments, the bonding interconnect structure 254 and the barrier pad 222 are not in direct contact.

[0060] In some embodiments, the bonding interconnect structure 254 is formed by depositing, sputtering, plating, or a combination thereof by filling the via trench 260 with a conductive material. Examples of conductive materials include, but are not limited to, copper, aluminum, aluminum-copper alloys, etc. The via trench 260 can be filled with a conductive material, and a planarization operation (e.g., chemical mechanical planarization or etch-back process) can then be performed to remove excess conductive material, thereby forming the bonding interconnect structure 254 having a top surface 2542 flush with the top surface 2522 of the bonding dielectric layer 252.

[0061] In some embodiments, the first bonding structure 250 may further include a diffusion barrier liner 256 formed in the via trench 260 prior to the formation of the bonding interconnect structure 254. The diffusion barrier liner 256 may be disposed between the bonding interconnect structure 254 and adjacent dielectric layers (i.e., passivation layer 210, capping layer 240, etch stop layer 242, and bonding dielectric layer 252). The diffusion barrier liner 256 may also be disposed between the bonding interconnect structure 254 and a portion of the topmost conductor 2062T. The diffusion barrier liner 256 serves to prevent conductive material in the bonding interconnect structure 254 from diffusing into adjacent dielectric layers. The diffusion barrier layer 256 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The diffusion barrier layer 256 is deposited in the via trench 260, for example, using PVD, CVD, ALD, or another suitable method.

[0062] refer to Figure 16 ,according to Figure 1 In step S142, a second wafer W2 is received. In some embodiments, the second wafer W2 includes a plurality of second semiconductor dies 400 arranged in columns and rows. A scribe line 401 is provided between every two adjacent second semiconductor dies 400. The second semiconductor dies 400 may include any type of integrated circuit. The functions provided by the second semiconductor dies 400 may be the same as or different from the functions of the first semiconductor die 200.

[0063] Figure 17 This is a cross-sectional view of a portion of a second semiconductor die 400. In some embodiments, the second semiconductor die 400 includes a substrate 402, various semiconductor devices 404, a second interconnect structure 406, and a dielectric stack 408. The semiconductor devices 404 may be disposed in and / or on the substrate 402. The second interconnect structure 406 is disposed above and electrically coupled to the semiconductor devices 404. The second interconnect structure 406 may include alternating conductors 4062 and conductive vias 4064 laterally surrounded by the dielectric stack 408. In some embodiments, the materials, configuration, and formation methods of the second interconnect structure 406 and the dielectric stack 408 are similar to those of the first interconnect structure 206 and the dielectric stack 208, respectively.

[0064] The second interconnect structure 406 may further include conductive pads 4066 located between the conductor 4062 and the dielectric stack 408, between the conductive via 4064 and the dielectric stack 408, and between the conductive via 4064 and the underlying conductor 4062. The conductive pads 4066 may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. In some embodiments, the second semiconductor die 400 further includes one or more contact plugs 405 for connecting the semiconductor device 404 to the second interconnect structure 406. The contact plugs 405 may be disposed between the semiconductor device 404 and the second interconnect structure 406. The contact plugs 405 may include a metal such as tungsten.

[0065] A dielectric stack 408 covers a substrate 402 and a semiconductor device 404, and laterally surrounds a contact plug 405 and a second interconnect structure 406. The dielectric stack 408 may include an intermetallic layer IMD and a series of interlayer dielectric layers ILD1 to ILD4 and etch stop layers ESL1 to ESL3 arranged in an alternating manner. The intermetallic layer IMD may laterally surround the contact plug 405, and the interlayer dielectric layers ILD1 to ILD4 may laterally surround the second interconnect structure 406. The intermetallic layer includes a dielectric material, such as an oxide. In some embodiments, the interlayer dielectric layers ILD1 to ILD4 include oxides, and the etch stop layers ESL1 to ESL3 include nitrides. Figure 17 In the figure, three interlayer dielectric layers ILD1 to ILD3 and three etch stop layers ESL1 to ESL3 are shown above the substrate 402 and the semiconductor device 404, but the actual number of interlayer dielectric layers and etch stop layers is not limited to this.

[0066] Still referencing Figure 17 ,according to Figure 1In step S144, a passivation layer 410 is deposited on the second wafer W2. In some embodiments, the passivation layer 410 includes a bottom layer 412 and a top layer 414 sequentially deposited over the second interconnect structure 406 and the dielectric stack 408. The bottom layer 412 may be in contact with the topmost interlayer dielectric layer ILD4 and the topmost conductor 4062T of the second interconnect structure 406. In some embodiments, the bottom layer 412 comprises a nitride, and the top layer 414 comprises an oxide.

[0067] Next step, according to Figure 1 In step S146, an etch stop layer 420 is deposited over the passivation layer 410. In some embodiments, the etch stop layer 420 covers the entirety of the top layer 414. The etch stop layer 420 is formed of a dielectric material different from the dielectric material of the top layer 414. In some embodiments, the etch stop layer 420 comprises a nitride. The etch stop layer 420 can be deposited by, for example, CVD, PECVD, or a combination thereof.

[0068] refer to Figure 18 ,according to Figure 1 In step S148, a second bonding structure 430 is formed over the second wafer W2. The second bonding structure 430 may be similar to the first bonding structure 250. In some embodiments, the second bonding structure 430 is disposed on the front side of the second wafer W2, wherein the front side is the location where the semiconductor device 404 is fabricated. The second bonding structure 430 may include a bonding dielectric layer 432 located on the etch stop layer 420 and a bonding interconnect structure 434 located at least in the bonding dielectric layer 432. In some embodiments, the bonding interconnect structure 434 penetrates the bonding dielectric layer 432, the etch stop layer 420 and the passivation layer 410, and connects to the underlying second interconnect structure 406 to form an electrical connection with the underlying semiconductor device 404. The formation of the second bonding structure 430 may include: depositing the bonding dielectric layer 432 on the entire top surface of the etch stop layer 420; and etching the bonding dielectric layer 432, the etch stop layer 420 and the passivation layer 410 to form a via trench 440 exposing the topmost conductor 4062T. Subsequently, the via trench 440 is filled with conductive material by deposition, sputtering, plating, or a combination thereof to form a bonding interconnect structure 434.

[0069] refer to Figure 19A ,according to Figure 1 In step S162, the first wafer W1 and the second wafer W2 are bonded to form a wafer assembly WA. In some embodiments, the first wafer W1 and the second wafer W2 are bonded together front-to-front via a first bonding structure 250 and a second bonding structure 430. During the bonding operation, the second wafer W2 is... Figure 18The orientation is flipped (i.e., rotated 180 degrees) and positioned above the first wafer W1. Therefore, the front side of the first wafer W1 faces the front side of the second wafer W2. Subsequently, the bonding interconnect structure 434 above the second wafer W2 is aligned with the bonding interconnect structure 254 above the first wafer W1. After alignment, a bonding force can be applied to the second wafer W2 to press it against the first wafer W1. Therefore, the bonding dielectric layer 432 contacts the bonding dielectric layer 252, and the bonding interconnect structure 434 contacts the bonding interconnect structure 254.

[0070] Bonding the first wafer W1 to the second wafer W2 can be achieved through hybrid bonding. In hybrid bonding, the bonding interconnect structure 434 above the second wafer W2 is bonded to the bonding interconnect structure 254 above the first wafer W1 via metal-to-metal bonding. Furthermore, the bonding dielectric layer 432 above the second wafer W2 is bonded to the bonding dielectric layer 252 above the first wafer W1 via dielectric-to-dielectric bonding (such as a fusion operation). After the hybrid operation, each first semiconductor die 200 can be electrically coupled to the upper second semiconductor die 400 via the bonding of the interconnect structures 254 and 434 disposed therebetween. The first die 200, a barrier pad 222 connected to the first die 200, a test pad 232, a second die 400 located on and aligned with the first die 200, portions of a first bonding structure 250 and a second bonding structure 430 between the first die 200 and the second die 400, and portions of passivation layers 210 and 410, a cover layer 240, and etch stop layers 242 and 420 located between the first die 200 and the second die 400 are collectively referred to as a die stack DS. According to some embodiments, only one of the semiconductor dies 200 and 400 (e.g., the first semiconductor die 200) undergoes a pre-bonding test operation before the semiconductor dies 200 and 400 are bonded to form a wafer assembly WA.

[0071] After the wafer assembly WA is fully formed, according to Figure 1 In step S164, testing is performed on the wafer assembly WA. Testing can be performed to determine the functionality of the die stack DS in the wafer assembly WA. The testing of the die stack DS is referred to as die stack testing. In some embodiments, prior to testing, a plurality of substrate vias (not shown) are formed in the die stack DS in the wafer assembly WA. The substrate vias can be formed in a first wafer W1 and a second wafer W2, and electrically coupled to a first interconnect structure 206 and a second interconnect structure 406. Testing can be performed by coupling the die stack DS in the wafer assembly WA to a test apparatus (not shown) through the substrate vias.

[0072] The testing apparatus may be operable to perform one or more wafer-level tests to determine the performance and reliability of the die stack DS under various conditions. The testing apparatus may be further operable to identify good and defective die stacks within a wafer assembly WA. In some embodiments, die stack DS that successfully meet test specifications or have passed all wafer-level tests are identified as known good die stacks, and die stack DS that fail to meet test specifications or fail the test procedure are identified as defective die stacks. After a die sawing operation, defective die stacks can be marked for exclusion from the packaging operation. Therefore, packaging costs can be saved. A die stack DS including a marked first semiconductor die 200 (i.e., a defective die) may fail the test procedure in die stack testing. When a second semiconductor die is defective, a die stack DS including an unmarked first semiconductor die 200 (i.e., a known good die) may fail the test procedure in die stack testing.

[0073] After completing the test, according to Figure 1 In step S166, a die-cutting operation is performed on the wafer assembly WA. Therefore, multiple semiconductor die assemblies 10 are fully formed, such as... Figure 19B As shown in the image. Reference Figure 19A and Figure 19B The die dicing operation can be performed by dicing along the scribing trace 201 of the first wafer W1 and the scribing trace 401 of the second wafer W2 to separate individual die stacks DS from the wafer assembly WA. After the die dicing operation, the bonding pad 232 can remain in the die stack DS. Each semiconductor die assembly 10 may include an individual die stack DS. For example, each semiconductor die assembly 10 may include a first die 200, a barrier pad 222 and a test pad 232 connected to the first die 200, a second die 400 vertically stacked on the first die 200, portions of a first bonding structure 250 and a second bonding structure 430, passivation layers 210 and 410, a cover layer 240, and etch stop layers 242 and 420 between the first die 200 and the second die 400.

[0074] After the die sawing operation, well-packaged die stacks are produced, and defective die stacks can be discarded, so the additional costs and efforts are not wasted on defective die stacks.

[0075] Figure 20 This is a flowchart of a method 500 for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure. Figure 20 Method 500 is similar to Figure 1 Method 100, in addition to method 500, also includes step S122 between steps S114 and S116. Figure 1 and Figure 20 Similar reference numerals in the text indicate similar steps, procedures, or components.

[0076] In step S122, test pad 232 is removed, as follows: Figure 21 As shown in the diagram. Test pad 232 can be removed by an etching operation, such as wet etching. However, embodiments of this disclosure are not limited thereto, and test pad 232 can be removed using other suitable techniques. After removal of test pad 232, barrier pad 222 is exposed. Therefore, the subsequently formed capping layer 240 conforms to the top layer 214 and barrier pad 222, as shown in the diagram. Figure 22 As shown in the image. Because test pad 232 was removed, compared to... Figure 19A Compared to the cover layer 240 of the die stack DS shown, the cover layer 240 and therefore the die stack DS can have a reduced thickness.

[0077] Figure 23 This is a flowchart of a method 600 for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure. Figure 23 Method 600 is similar to Figure 20 Method 500, in addition to method 600, also includes step S124 between steps S116 and S118. Figure 20 and Figure 23 Similar reference numerals in the text indicate similar steps, procedures, or components.

[0078] In step S124, a planarization operation is performed on the cover layer 240, such as... Figure 24 As shown in the diagram. Planarization operations can include, for example, CMP operations, polishing operations, etching operations, or combinations thereof. After the planarization operation, the capping layer 240 has a substantially flat top surface 2402. Therefore, the subsequently formed etch stop layer 250 also has a substantially flat lower surface 2502, as shown in the diagram. Figure 25 As shown in the image.

[0079] Figure 26 This is a flowchart of a method 700 for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure. Figure 26 Method 700 is similar to Figure 1 Method 100, in addition to method 700, also includes step S126 between steps S114 and S116. Figure 1 and Figure 26 Similar reference numerals in the text indicate similar steps, procedures, or components.

[0080] In step S126, the test pad 232 and the blocking pad 222 are removed, as follows: Figure 27As shown in the diagram. Test pads 232 and barrier pads 222 can be removed by one or more etching operations or other suitable techniques. After removing test pads 232 and barrier pads 222, a portion of the topmost conductor 2062T is exposed. Therefore, the subsequently formed capping layer 240 conforms to a portion of the top layer 214 and the topmost conductor 2062T, as shown in the diagram. Figure 28 As shown in the diagram. Due to the removal of the blocking pad 222 and test pad 232, with... Figure 19A Compared to the cover layer 240 of the die stack DS shown, the cover layer 240 and therefore the die stack DS can have a reduced thickness.

[0081] Figure 29 This is a flowchart of a method 800 for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure. Figure 29 Method 800 is similar to Figure 26 Method 700, in addition to method 800, also includes step S128 between steps S116 and S118. Figure 26 and Figure 29 Similar reference numerals in the text indicate similar steps, procedures, or components.

[0082] In step S128, a planarization operation is performed on the cover layer 240, such as... Figure 30 As shown in the diagram. Planarization operations can include, for example, CMP operations, polishing operations, etching operations, or combinations thereof. After the planarization operation, the capping layer 240 has a substantially flat top surface 2402. Therefore, the subsequently formed etch stop layer 250 also has a substantially flat lower surface 2502, as shown in the diagram. Figure 31 As shown in the image.

[0083] Figure 32 This is a flowchart of a method 900 for manufacturing a semiconductor die assembly according to some embodiments of the present disclosure. Figure 32 Method 900 is similar to Figure 1 Method 100, in addition to method 900, also includes steps S150, S152 and S154 between steps S144 and S148. Figure 1 and Figure 32 Similar reference numerals in the text indicate similar steps, procedures, or components.

[0084] refer to Figure 32 and Figure 33In step S150, a barrier pad 440 and a test pad 450 are formed over the second wafer W2. In some embodiments, the barrier pad 440 and the test pad 450 are formed in and over the passivation layer 410. Each barrier pad 440 may separate the test pad 450 from the passivation layer 410. The barrier pad 440 may be configured to prevent metal atoms from diffusing from the test pad 450 to the passivation layer 410. The barrier pad 440 may also separate the test pad 450 from the topmost conductor 4062T. The barrier pad 440 and the test pad 450 may be formed by: one or more etching operations to form trenches exposing portions of the topmost conductor 4062T; subsequently forming a barrier layer and a conductive layer; and then patterning the barrier layer and the conductive layer through the passivation layer 410. The etching operation and patterning of the barrier layer and the conductive layer may each include wet etching, dry etching, combinations thereof, etc. In some embodiments, the thickness of the top layer 414 may remain constant through the etching operation. However, the embodiments disclosed herein are not limited thereto, and the portion of the top layer 414 not covered by the barrier pad 440 and test pad 450 may have a reduced thickness. The barrier layer may be formed, for example, by PVD, CVA, ALD, or another suitable technique. The second conductive layer 230 may be formed, for example, by sputtering, CVD, PVD, ALD, or another suitable technique. In some embodiments, the diffusion barrier pad 440 comprises titanium, titanium nitride, tantalum, or tantalum nitride. The test pad 450 may comprise a conductive material such as copper, aluminum, an aluminum-copper alloy, etc.

[0085] Still referencing Figure 33 The method proceeds to step S152, where the second wafer W2 is tested via test pads 450. In some embodiments, a second test is performed on all second semiconductor dies 400 on the second wafer W2. The second test can be performed using a test apparatus 304 comprising a plurality of test probes 306. The test apparatus 304 and the test probes 306 can be similar to those referenced above. Figure 8 The tests are as described. The test is performed by aligning each test probe 306 and its corresponding test pad 450 on the second wafer W2; and then forcefully pushing the test probe 306 against the corresponding test pad 450 to couple the test probe 306 to the test pad 450. Thus, probe marks 452 are formed by the test probe 306.

[0086] The testing apparatus 304 is configured to send test signals to the second semiconductor device 400 via test probes 306 and test pads 450 and to receive test results from the second semiconductor device 400. The test results may include information about the second semiconductor device 400. The testing apparatus 304 may also be configured to analyze the test results to determine whether the second semiconductor die 400 meets test specifications. In some embodiments, a second semiconductor die 400 that meets the test specifications is identified as a known good die, and a second semiconductor die 400 that does not meet the test specifications is identified as a defective die.

[0087] After the test is completed, the method proceeds to step S154, where a capping layer 460 is deposited over the passivation layer 410 and the test pad 450, as shown below. Figure 35 As shown in the diagram. In some embodiments, the capping layer 460 is conformally fitted with the top layer 414, the barrier pad 440, and the test pad 450. The capping layer 460 may comprise an oxide. The capping layer 460 may be formed by any suitable method, such as CVD, spin coating, or a combination thereof.

[0088] Still referencing Figure 35 In some embodiments, the second bonding structure 430 formed in step S148 is located on the back side of the second wafer W2. The back side of the second wafer W2 may be the side without the semiconductor device 404. The second bonding structure 430 may include a bonding dielectric layer 432 disposed under the second substrate 402 and a bonding interconnect structure 434 disposed at least in the bonding dielectric layer 432. In some embodiments, the bonding dielectric layer 432 is disposed on and conformally to the lower surface 4022 of the second substrate 402. The bonding interconnect structure 434 may penetrate the bonding dielectric layer 432 and the dielectric stack 408 and be electrically coupled to the second interconnect structure 406.

[0089] During the bonding of the first wafer W1 to the second wafer W2 (i.e., Figure 32 In step S162), the second wafer W2 is positioned on the first wafer W1, with the front side of the first wafer W1 facing the back side of the second wafer W2, thus forming a front-to-back arrangement. Therefore, the first wafer W1 and the second wafer W2 are joined by a front-to-back bonding, as shown below. Figure 36 As shown in the diagram. The first wafer W1 and the second wafer W2 can also be joined, for example, by back-to-back bonding or back-to-front bonding.

[0090] According to some embodiments of this disclosure, a method for manufacturing a semiconductor die assembly includes the following steps: receiving a first wafer, the first wafer including a first semiconductor device and a first interconnect structure disposed above and electrically coupled to the first semiconductor device; forming a first passivation layer above the first interconnect structure; forming a first barrier layer in the first passivation layer; forming a first test pad on the first barrier layer; performing a first test on the first semiconductor device through the first test pad; forming a first bonding structure above the first passivation layer and the first barrier layer; receiving a second wafer, the second wafer including a second semiconductor device and a second interconnect structure electrically coupled to the second semiconductor device; forming a second bonding structure above the second interconnect structure; bonding the first wafer to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; and performing a second test on the wafer assembly.

[0091] According to some embodiments of this disclosure, a method of manufacturing a semiconductor die assembly includes the following steps: forming a passivation layer on a first wafer including an interconnect structure; depositing a first conductive layer in and over the passivation layer; removing a portion of the first conductive layer offset from a portion of the interconnect structure to form a test pad over a portion of the interconnect structure; performing a first test on the first wafer through the test pad; removing the test pad in response to the first wafer meeting the test specifications of the first test; forming a first bonding structure over the passivation layer; forming a second bonding structure over a second wafer; bonding the first wafer to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; and performing a second test on the wafer assembly.

[0092] According to some embodiments of the present disclosure, a semiconductor die stack includes: a first die including a first semiconductor device and a first interconnect structure disposed above the first semiconductor device; a passivation layer covering the first interconnect structure; a barrier pad laterally surrounded by the passivation layer and in contact with the first interconnect structure; a bonding structure disposed above the passivation layer and the barrier pad; and a second die disposed on the bonding structure and including a second semiconductor device and a second interconnect structure.

[0093] Some embodiments of this application provide a method for manufacturing a semiconductor die assembly, comprising: receiving a first wafer, the first wafer including a first semiconductor device and a first interconnect structure disposed above and electrically coupled to the first semiconductor device; forming a first barrier pad on a portion of the first interconnect structure; forming a first test pad on the first barrier pad; performing a first test on the first semiconductor device through the first test pad; forming a first bonding structure above the first interconnect structure; receiving a second wafer, the second wafer including a second semiconductor device and a second interconnect structure located above and coupled to the second semiconductor device; forming a second bonding structure above the second interconnect structure; bonding the first wafer to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; and performing a second test on the wafer assembly.

[0094] In some embodiments, the method further includes, before forming the first bonding structure: depositing a first passivation layer covering the first wafer, wherein the first barrier pad and the first test pad are partially and laterally surrounded by the first passivation layer; and depositing a first overlay layer over the first passivation layer, the first barrier pad, and the first test pad, wherein the first overlay layer is conformally oriented with the first passivation layer, the first barrier pad, and the first test pad. In some embodiments, the method further includes performing a planarization operation on the first overlay layer, wherein after the planarization operation, the first overlay layer has a flat top surface. In some embodiments, the method further includes, before forming the second bonding structure on the second wafer: depositing a second passivation layer over the second interconnect structure; forming a second barrier pad in the second passivation layer; forming a second test pad on the second barrier pad; and performing a third test on the second semiconductor device through the second test pad. In some embodiments, the method further includes, after performing the third test and before forming the second bonding structure over the second wafer: depositing a second overlay layer over the second passivation layer and the second test pad, wherein the second overlay layer is conformally oriented with the second passivation layer, the second barrier pad, and the second test pad. In some embodiments, the method further includes, after performing the third test and before forming the second bonding structure over the second wafer: removing the second test pad; and depositing a second overlay layer over the second passivation layer and the second barrier pad, wherein the second overlay layer is conformal to the second passivation layer and the second barrier pad. In some embodiments, the method further includes performing a planarization operation on the second overlay layer, wherein after the planarization operation, the second overlay layer has a flat top surface. In some embodiments, the method further includes, after performing the third test and before forming the second bonding structure over the second wafer: removing the second test pad and the second barrier pad; and depositing a second overlay layer over the second passivation layer and the second interconnect structure, wherein the second overlay layer is conformal to the portion of the second passivation layer and the second interconnect structure exposed through the second passivation layer. In some embodiments, the method further includes performing a planarization operation on the second overlay layer, wherein after the planarization operation, the second overlay layer has a flat top surface. In some embodiments, bonding the first wafer to the second wafer includes dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, the first wafer and the second wafer are bonded by front-side-to-front bonding. In some embodiments, the first wafer and the second wafer are joined by front-to-back bonding.

[0095] Other embodiments of this application provide a method for manufacturing a semiconductor die assembly, comprising: forming a passivation layer on a first wafer including an interconnect structure; depositing a first conductive layer in and over the passivation layer; removing a portion of the first conductive layer to form a test pad over the portion of the interconnect structure; performing a first test on the first wafer through the test pad; removing the test pad in response to the first wafer meeting the test specifications of the first test; forming a first bonding structure over the passivation layer; forming a second bonding structure over a second wafer; bonding the first wafer to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; and performing a second test on the wafer assembly.

[0096] In some embodiments, the first wafer and the second wafer are joined by a hybrid bonding process. In some embodiments, the method further includes depositing a capping layer conformally to the passivation layer prior to forming the first bonding structure. In some embodiments, the method further includes performing a planarization operation on the capping layer, wherein, after the planarization operation, the capping layer has a flat top surface. In some embodiments, forming the first bonding structure includes: depositing a bonding dielectric layer over the passivation layer; etching the bonding dielectric layer and the passivation layer to form a through-hole exposing a portion of the interconnect structure; etching the bonding dielectric layer to form a second trench connected to the through-hole; and depositing a conductive material in the through-hole and the second trench to form a bonding interconnect structure in the bonding dielectric layer and the passivation layer.

[0097] Further embodiments of this application provide a semiconductor die assembly, comprising: a first die including a first semiconductor device and a first interconnect structure disposed above the first semiconductor device; a passivation layer covering the first interconnect structure; a barrier pad laterally surrounded by the passivation layer and in contact with the first interconnect structure; a bonding structure disposed above the passivation layer and the barrier pad; and a second die disposed on the bonding structure and including a second semiconductor device and a second interconnect structure.

[0098] In some embodiments, the semiconductor die assembly further includes test pads disposed above the barrier pads. In some embodiments, the test pads have a roughened top surface.

[0099] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for manufacturing a semiconductor die assembly, comprising: Receive a first wafer, the first wafer including a first semiconductor device and a first interconnect structure disposed above the first semiconductor device and electrically coupled to the first semiconductor device; A first barrier pad is formed on a portion of the first interconnect structure; A first test pad is formed on the first barrier pad; The first test is performed on the first semiconductor device through the first test pad; A first bonding structure is formed above the first interconnect structure; Receive a second wafer, the second wafer including a second semiconductor device and a second interconnect structure located above the second semiconductor device and electrically coupled to the second semiconductor device; A second bonding structure is formed above the second interconnect structure; The first wafer is bonded to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; as well as A second test was performed on the wafer assembly.

2. The method of claim 1, further comprising, before forming the first joining structure: A first passivation layer is deposited covering the first wafer, wherein... The first barrier pad and the first test pad are partially and laterally surrounded by the first passivation layer; as well as A first overlay is deposited over the first passivation layer, the first barrier pad, and the first test pad, wherein the first overlay is conformal to the first passivation layer, the first barrier pad, and the first test pad.

3. The method according to claim 2, further comprising performing a planarization operation on the first overlay layer, wherein, After the planarization operation, the first cover layer has a flat top surface.

4. The method of claim 1, further comprising, before forming the second bonding structure on the second wafer: A second passivation layer is deposited over the second interconnect structure; A second barrier pad is formed in the second passivation layer; A second test pad is formed on the second barrier pad; and The second semiconductor device is subjected to a third test through the second test pad.

5. The method of claim 4, further comprising, after performing the third test and before forming the second bonding structure over the second wafer: A second overlay layer is deposited over the second passivation layer and the second test pad, wherein, The second cover layer is conformal with the second passivation layer, the second barrier pad, and the second test pad.

6. The method of claim 4, further comprising, after performing the third test and before forming the second bonding structure over the second wafer: Remove the second test pad; and A second capping layer is deposited over the second passivation layer and the second barrier liner, wherein, The second cover layer is conformal to the second passivation layer and the second barrier pad.

7. The method of claim 6, further comprising performing a planarization operation on the second overlay layer, wherein, After the planarization operation, the second cover layer has a flat top surface.

8. The method of claim 4, further comprising, after the third test and before forming the second bonding structure over the second wafer: Remove the second test pad and the second barrier pad; and A second capping layer is deposited over the second passivation layer and the second interconnect structure, wherein, The second cover layer conforms to the second passivation layer and the portion of the second interconnect structure exposed through the second passivation layer.

9. A method for manufacturing a semiconductor die assembly, comprising: A passivation layer is formed on a first wafer including interconnect structures; A first conductive layer is deposited in and over the passivation layer; A portion of the first conductive layer is removed to form a test pad over the portion of the interconnect structure; The first test is performed on the first wafer through the test pads; In response to the first wafer meeting the test specifications of the first test, the test pads are removed; A first bonding structure is formed over the passivation layer; A second bonding structure is formed above the second wafer; The first wafer is bonded to the second wafer by connecting the first bonding structure and the second bonding structure to form a wafer assembly; as well as A second test was performed on the wafer assembly.

10. A semiconductor die assembly, comprising: The first die includes a first semiconductor device and a first interconnect structure disposed above the first semiconductor device; A passivation layer covers the first interconnect structure; A barrier pad is laterally surrounded by the passivation layer and contacts the first interconnect structure; A bonding structure is disposed above the passivation layer and the barrier pad; as well as The second die is disposed on the bonding structure and includes a second semiconductor device and a second interconnect structure.

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