Method of forming a semiconductor device and semiconductor device
By forming a curvature control layer on the wafer to adjust the curvature, the problem of uneven electrode layer thickness in the chemical mechanical polishing process is solved, which improves the uniformity of the electrode layer and the electrical performance of semiconductor devices, thereby increasing device yield and storage capacity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 新存科技(武汉)有限责任公司
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-10
AI Technical Summary
Existing chemical mechanical polishing processes suffer from thickness inhomogeneity when forming the top electrode layer of 3D cross-point memory, leading to unstable electrical performance and affecting the yield and storage capacity of semiconductor devices.
By forming a curvature control layer on the wafer, the curvature of the wafer is increased, making the thickness of the electrode layer more uniform in different areas. Stress is applied using the curvature control layer to adjust the curvature of the wafer, ensuring that the central area is fully ground during the grinding process, while the outer area is avoided from being over-ground.
It improves the uniformity of electrode layer thickness, enhances the electrical performance of semiconductor devices, increases device yield and storage capacity, and solves the performance bottleneck caused by thickness non-uniformity.
Smart Images
Figure CN122373365A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor device and a semiconductor device. Background Technology
[0002] The development of artificial intelligence and in-memory computing technologies has placed higher demands on data storage and computing capabilities. Current von Neumann computing architectures require extensive data reading and storage between Dynamic Random Access Memory (DRAM) and Solid State Drives (SSDs). A significant performance gap exists between these two, hindering performance improvements in the current von Neumann computing system. Storage Class Memory (SCM) has been proposed as a bridge between DRAM and SSDs to improve the current storage architecture. SCM needs to achieve speeds significantly faster than NAND and excellent non-volatility. Among the emerging SCM technologies, 3D Xpoint memory is the most promising, offering advantages such as large capacity, high speed, non-volatility, and good cycle performance. Recently, research on high-capacity non-volatile memory technologies to mitigate the weaknesses of 3D Xpoint memory has become active, such as Phase Change Memory (Phase Change Memory) and Selector Only Memory (SOM).
[0003] In both phase-change memory (PCM) and select-only memory (SMI) process routes, there is a crucial step: after etching to form the memory cell, chemical mechanical polishing (CMP) is used to remove the mask layer and stop at the top electrode layer. The top electrode layer has a significant impact on electrical properties such as word line leakage current (WL LKG), read / write window (RWM), and endurance. Therefore, the uniformity of the top electrode layer thickness is extremely critical in current CMP processes. Summary of the Invention
[0004] This application provides a method for forming a semiconductor device and a semiconductor device, which improves the uniformity of electrode layer thickness to enhance the electrical performance of the semiconductor device.
[0005] This application provides a method for forming a semiconductor device, comprising: forming a wafer, the wafer including an electrode layer and a mask layer located on the electrode layer, the wafer having a front side and a back side disposed opposite to each other, the front side being the surface of the mask layer facing away from the electrode layer, the wafer including a first region and a second region, the second region being located outside the first region, the electrode layer having a greater thickness in the first region than in the second region, and the first region of the wafer being curved toward the front side; forming a curvature control layer, the curvature control layer being located on at least one of the front side and the back side of the wafer to increase the curvature of the wafer; and polishing the mask layer and a portion of the electrode layer.
[0006] In some embodiments, the curvature control layer is located on the back side of the wafer, and the curvature control layer is used to apply tensile stress to the wafer.
[0007] In some embodiments, the material of the curvature control layer includes silicon nitride.
[0008] In some embodiments, the curvature control layer is located on the front side of the wafer, and the curvature control layer is used to apply compressive stress to the wafer.
[0009] In some embodiments, the material of the curvature control layer located on the front side includes silicon oxide.
[0010] In some embodiments, the curvature adjustment layer located on the front side is located in the second region.
[0011] In some embodiments, the thickness of the curvature control layer in the second region is greater than or equal to 0, and the thickness of the curvature control layer in the first region is greater than the thickness of the curvature control layer in the second region.
[0012] In some embodiments, the second region further includes a first sub-region and a second sub-region, the first sub-region being located between the first region and the second sub-region; prior to polishing, the electrode layer has a greater thickness in the first sub-region than in the second sub-region, and the curvature control layer gradually decreases in thickness from the first region, the first sub-region to the second sub-region.
[0013] In some embodiments, the method for forming the semiconductor device further includes removing the curvature control layer after polishing.
[0014] This application also provides a semiconductor device formed by the semiconductor device forming method in any of the above embodiments.
[0015] In the semiconductor device formation method of this application embodiment, since the thickness of the electrode layer in the first region of the wafer is greater than the thickness in the second region, the first region of the wafer is bent towards the front side. This application embodiment increases the curvature of the wafer by forming a curvature control layer on at least one side of the wafer, further bending the first region of the wafer towards the front side. This allows for more thorough contact between the electrode layer and the polishing pad in the first region during the polishing process on the front side. Consequently, the electrode layer is polished to a greater thickness in the first region and a smaller thickness in the second region, thereby improving the uniformity of the electrode layer thickness in different regions.
[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0019] Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device provided in some embodiments of this application; Figure 2 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application; Figure 3 This is a thickness distribution cloud map of the electrode layer on the wafer before the grinding process; Figure 4 This is a thickness distribution cloud map of the electrode layer on the wafer after grinding; Figure 5 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application; Figures 6 to 14 These are schematic diagrams illustrating the structure of a semiconductor device during its fabrication process, provided in some embodiments of this application. Figure 15 It is a characterization diagram of the curvature of the wafer along the diameter direction before and after the formation of the curvature control layer; Figure 16 This is a comparison diagram of the radial distribution of electrode layer thickness before and after grinding. Detailed Implementation
[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0021] Please see Figure 1 , Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device provided in some embodiments of this application.
[0022] The semiconductor device includes a first conductive line L1 and a second conductive line L2 arranged in opposite directions, and a memory cell 10 located between the first conductive line L1 and the second conductive line L2, the memory cell 10 being situated at the intersection of the first conductive line L1 and the second conductive line L2. The memory cell 10 includes a first electrode 11, a second electrode 12, and a memory functional layer 13, the memory functional layer 13 being located between the first electrode 11 and the second electrode 12. The first conductive line L1 extends along a first direction X, the second conductive line L2 extends along a second direction Y, and the first electrode 11, the second electrode 12, and the memory functional layer 13 are stacked along a third direction. Both the first direction X and the second direction Y are perpendicular to the third direction Z, and the first direction X and the second direction Y intersect each other.
[0023] The semiconductor device may further include a substrate, a second conductive line L2 located on the substrate, and a first conductive line L1 located on the side of the second conductive line L2 away from the substrate. A first electrode 11 is located on the side of the second electrode 12 away from the substrate, the second electrode 12 is connected to the second conductive line L2, and the first electrode 11 is connected to the first conductive line L1.
[0024] The semiconductor device can be a phase change memory or a selector only memory (SOM).
[0025] In some embodiments, the semiconductor device is a select-only memory, and the storage function layer 13 includes a bidirectional threshold switch layer. The material of the bidirectional threshold switch layer may include a chalcogenide compound, which includes at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, and Ge-As-S.
[0026] Please see Figure 2 , Figure 2 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 1The difference in this embodiment is that the semiconductor device is a phase-change memory, and the semiconductor device includes two stacked memory cells 10. It should be noted that the number of stacked layers of memory cells 10 is not limited in this embodiment.
[0027] Each memory cell 10 includes a first electrode 11, a second electrode 12, and a memory functional layer 13. The memory functional layer 13 includes a gate layer 131, a third electrode 132, and a phase change layer 133. The third electrode 132 is located between the gate layer 131 and the phase change layer 133. When the first electrode 11 serves as the top electrode layer of the memory cell 10, the phase change layer 133 is located between the first electrode 11 and the third electrode 132, and the gate layer 131 is located between the second electrode 12 and the third electrode 132. Therefore, regardless of whether the memory cell 10 is a single-layer or multi-layer structure, the first electrode 11 of the memory cell 10 always serves as the top electrode layer.
[0028] In some embodiments, the materials of the first electrode 11, the second electrode 12, and the third electrode 132 include carbon. The material of the phase change layer 133 may include a first chalcogenide, and the material of the gate layer 131 may include a second chalcogenide, wherein the first chalcogenide and the second chalcogenide are made of different materials.
[0029] For example, the first chalcogenide compound includes at least one of germanium-tellurium (Ge-Te) compound, antimony-tellurium (Sb-Te) compound, germanium-antimony-tellurium (Ge-Sb-Te) compound, silicon-antimony-tellurium (Si-Sb-Te) compound, titanium-antimony-tellurium (Ti-Sb-Te) compound, aluminum-antimony-tellurium (Al-Sb-Te) compound, germanium-antimony-selenium (Ge-Sb-Se), germanium-selenium-gallium (Ge-Sb-Ga), and germanium-selenium-bismuth (Ge-Sb-Bi). The second chalcogenide compound includes at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, and Ge-As-S.
[0030] The semiconductor device before polishing can be referred to as a wafer. The wafer includes a front side (device side, facing the polishing pad during subsequent polishing) and a back side arranged opposite to each other. After the memory stack and the mask layer on the memory stack are formed on the front side, a self-aligned double patterning (SADP) etching process is performed using the mask layer as a mask. The memory stack includes an electrode layer connected to the mask layer. The mask layer needs to be removed in the subsequent chemical mechanical polishing (CMP) process to expose the electrode layer. Conductive lines are then formed on the electrode layer.
[0031] Currently, in the actual mass production process of 3D PCM, the electrode layer deposited by Physical Vapor Deposition (PVD) exhibits significant thickness distribution defects in different regions of the wafer, meaning the electrode layer is significantly thicker in the central region than in the peripheral region. This thickness difference causes inherent wafer curvature, specifically, the central region bends towards the front of the wafer (i.e., the side of the mask layer away from the electrode layer), resulting in insufficient contact between the peripheral region of the wafer and the polishing pad, posing a significant challenge to subsequent CMP processes.
[0032] To address the issue of insufficient edge polishing, increasing CMP polishing pressure and time can be employed. However, this approach can trigger a significant loading effect, leading to overpolishing of the outermost area and even damage to the outermost electrode layer. This not only fails to improve the uniformity of electrode layer thickness but also further deteriorates the performance, ultimately resulting in decreased semiconductor device yield and unstable storage capacity. This has become a key technological bottleneck restricting the large-scale mass production of semiconductor devices.
[0033] Please see Figure 3 and Figure 4 , Figure 3 This is a thickness distribution cloud map of the electrode layer on the wafer before the grinding process. Figure 4 This is a thickness distribution cloud map of the electrode layer on the wafer after grinding. The color scale in the image is used to visually represent the thickness gradient of the electrode layer. Red represents the maximum thickness, purple represents the minimum thickness, and intermediate colors such as yellow, green, and blue correspond to intermediate thickness values. It should be noted that the electrode layer represented here is the electrode layer in contact with the mask layer, that is, the electrode layer closest to the front side of the wafer.
[0034] Depend on Figure 3 It can be seen that before the grinding process, the electrode layer is significantly thicker in the central region of the wafer than in the peripheral region. From... Figure 4 As can be seen from the data, after the grinding process, the overall thickness of the electrode layer is reduced, but the thickness of the electrode layer in the central region is still very large, showing obvious uneven thickness distribution.
[0035] Based on this, embodiments of this application provide a method for forming a semiconductor device. Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic flowchart illustrating a method for forming a semiconductor device according to some embodiments of this application. The method for forming the semiconductor device includes: Step S1: Form a wafer, the wafer including an electrode layer and a mask layer located on the electrode layer, the wafer having a front side and a back side disposed opposite to each other, the front side being the surface of the mask layer facing away from the electrode layer, the wafer including a first region and a second region, the second region being located outside the first region, the electrode layer having a greater thickness in the first region than in the second region, and the first region of the wafer being bent toward the front side; Step S2: Form a curvature control layer, the curvature control layer being located on at least one of the front and back sides of the wafer, to increase the curvature of the wafer; Step S3: Grind the mask layer and part of the electrode layer.
[0036] In the semiconductor device formation method of this application embodiment, since the thickness of the electrode layer in the first region of the wafer is greater than the thickness in the second region, the first region of the wafer is bent towards the front side. This application embodiment increases the curvature of the wafer by forming a curvature control layer on at least one side of the wafer, further bending the first region of the wafer towards the front side. This allows for more thorough contact between the electrode layer and the polishing pad in the first region during the polishing process on the front side. Consequently, the electrode layer is polished to a greater thickness in the first region and a smaller thickness in the second region, thereby improving the uniformity of the electrode layer thickness in different regions.
[0037] The following description, in conjunction with the accompanying drawings, illustrates a method for forming a semiconductor device according to embodiments of this application, and uses the forming method as an example. Figure 2 The following explanation will be based on semiconductor devices.
[0038] Please see Figures 6 to 14 , Figures 6 to 14 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.
[0039] Step S1: Forming wafer 100A, wafer 100A including electrode layer 11b and mask layer M located on electrode layer 11b, wafer 100A having a front side 101 and a back side 102 disposed opposite to each other, the front side 101 being the surface of mask layer M facing away from electrode layer 11b, wafer 100A including a first region WC and a second region WF, the second region WF being located around the first region WC, the thickness of electrode layer 11b in the first region WC being greater than the thickness in the second region WF, and the first region WC of wafer 100A being bent toward the front side 101.
[0040] It should be noted that, for the sake of simplicity, the thickness difference of electrode layer 11b in different regions is not shown in the figure.
[0041] Please see Figure 6and Figure 7 The method for forming wafer 100A may include the following steps.
[0042] See Figure 6 A substrate 20 is provided; a storage stack 10a is formed on the substrate 20, the storage stack 10a including a second initial electrode layer 12a, an initial storage function layer 13a and a first initial electrode layer 11a.
[0043] The formation process of the second initial electrode layer 12a, the initial storage function layer 13a and the first initial electrode layer 11a may include a deposition process. The deposition process may employ, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering and other methods.
[0044] In some embodiments, if the wafer 100A has a single-layer memory cell structure, then the second initial electrode layer 12a, the initial memory function layer 13a, and the first initial electrode layer 11a are sequentially formed on the substrate 20.
[0045] exist Figure 6 In this embodiment, wafer 100A has a dual-layer memory cell structure. First, the lower-layer memory cell 10 is formed, and then the upper-layer memory stack 10a is formed above the lower-layer memory cell 10. It should be noted that the formation process of the lower-layer memory cell 10 can refer to the formation process of the upper-layer memory cell.
[0046] See Figure 7 The storage stack 10a is etched to form the storage cell layer 10b.
[0047] The etching process for the memory stack 10a can employ a self-aligned dual patterning process. After the etching process is completed, wafer 100A includes a memory cell layer 10b and a mask layer M located on the memory cell layer 10b. The memory cell layer 10b includes an electrode layer 11b (i.e., the first electrode layer 11b), a memory function layer 13b, and a second electrode layer 12b that are in contact with the mask layer M. Specifically, the first initial electrode layer 11a is etched to form the first electrode layer 11b, the initial memory function layer 13ba is etched to form the memory function layer 13b, and the second initial electrode layer 12a is etched to form the second electrode layer 12b.
[0048] It should be noted that, since this application mainly focuses on the first electrode layer 11b in contact with the mask layer M, the first electrode layer 11b in the memory cell layer 10b will be referred to as electrode layer 11b in the following text.
[0049] The method for forming the semiconductor device further includes: removing a portion of the memory cell layer 10b of the second region WF and filling it with an insulating layer 30. In some embodiments, the insulating layer 30 may be made of silicon oxide.
[0050] Please refer to 9. Figure 9 yes Figure 7 A schematic diagram of wafer bending corresponding to semiconductor devices.
[0051] Wafer 100A has a front side 101 and a back side 102 disposed opposite to each other. The front side 101 is the surface of the mask layer M on the side opposite to the electrode layer 11b. Wafer 100A includes a first region WC and a second region WF, with the second region WF located on the periphery of the first region WC.
[0052] Due to the "edge effect" in the deposition process Figure 6 The central region of the wafer (i.e., the first region WC) has a more uniform distance from the target, resulting in higher atomic deposition efficiency and more complete deposition of the target material. However, the peripheral region of wafer 100A (i.e., the second region WF) has a deviation in distance from the target, leading to lower atomic deposition efficiency and an inherent defect in the first initial electrode layer 11a after deposition: thicker at the center and thinner at the periphery. After the first initial electrode layer 11a is etched, the first electrode layer 11b (i.e., electrode layer 11b) is formed. Figure 7 The thickness of the middle electrode layer 11b is greater in the first region WC and less in the second region WF, that is, the thickness of the electrode layer 11b in the first region WC is greater than the thickness in the second region WF.
[0053] like Figure 9 As shown, the uneven thickness of the electrode layer 11b before polishing can also cause inherent bending of the wafer 100A (the first region WC bends toward the front side 101), which in turn poses a challenge to the subsequent polishing process.
[0054] Step S2: Form a curvature control layer 40, wherein the curvature control layer 40 is located on at least one of the front side 101 and the back side 102 of the wafer 100B to increase the curvature of the wafer 100B.
[0055] Please see Figure 10 , Figure 10 This is a schematic diagram of the curvature control layer distribution on the back side of the wafer. Figure 1 For ease of distinction, the wafer after the curvature adjustment layer 40 is formed (i.e., the wafer with increased curvature) is referred to as wafer 100B.
[0056] By setting up a curvature control layer 40, the inherent bending tendency of wafer 100B is precisely enhanced by applying tensile or compressive stress to the wafer (causing the first region WC to bend further towards the front side 101). This significantly increases the contact pressure and contact area between the central region and the polishing pad, allowing the central region to receive more thorough polishing and compensating for any deficiencies in its polishing. Simultaneously, the stress effect of the curvature control layer 40 can also adjust the contact state of the peripheral region, preventing over-polishing of the peripheral region. Ultimately, this ensures uniform contact between the entire wafer 100B and the polishing pad during CMP polishing, laying the foundation for achieving uniform TE layer thickness in the subsequent process.
[0057] It should be noted that, as mentioned earlier, increasing CMP grinding pressure and time can lead to over-grinding of the peripheral areas. Furthermore, the material in the peripheral areas differs from that in the central areas; for example... Figure 7 As shown, in the peripheral region, the front surface 101 of wafer 100A is mostly composed of insulating layer 30 (silicon oxide), while in the central region, the front surface 101 of wafer 100A is mostly composed of mask layer M (silicon nitride) and electrode layer 11b (carbon). Therefore, the polishing rate in the peripheral region is faster, making it more prone to over-polishing. This ultimately leads to depressions in the insulating layer 30 and damage to the electrode layer 11b at the edges, thus affecting the electrical performance and yield of the device. Therefore, the stress effect of the curvature control layer 40 can also simultaneously adjust the contact state of the peripheral region, making the peripheral region further away from the front surface 101 to avoid over-polishing of the peripheral region.
[0058] In some embodiments, see Figure 10 The curvature adjustment layer 40 is located on the back side 102 of the wafer 100B. The curvature adjustment layer 40 is used to apply tensile stress to the back side 102, so that the wafer 100B is bent towards the thin film (i.e., the curvature adjustment layer 40) side, thus making the front side 101 more convex, thereby increasing the curvature of the wafer 100B.
[0059] It is understandable that the tensile stress is perpendicular to the contact surface between the curvature control layer 40 and the wafer 100B, and points from the wafer 100B side toward the curvature control layer 40.
[0060] In some embodiments, the curvature control layer 40 is made of silicon nitride, and the silicon nitride can be deposited using plasma-enhanced chemical vapor deposition (PECVD) to apply tensile stress to the wafer. Specifically, the curvature control layer 40 can be made of silicon-rich silicon nitride.
[0061] In other embodiments, physical vapor deposition (PVD) can be used to deposit metals (such as tungsten, titanium, etc.) to form a metal thin film as curvature control layer 40.
[0062] In this embodiment, the curvature control layer 40 is located on the back side 102 of the wafer 100B, which can avoid process interference between the curvature control layer 40 and the mask layer M and electrode layer 11b on the front side 101, and at the same time facilitate the removal of the curvature control layer 40 after subsequent grinding.
[0063] exist Figure 10 In this embodiment, the curvature adjustment layer 40 is located in the first region WC and the second region WF, that is, on the entire back surface 102 of the wafer 100B. Furthermore, the curvature adjustment layer 40 has a uniform thickness at all locations on the back surface 102.
[0064] Please see Figure 11 , Figure 11 This is a schematic diagram of the curvature control layer distribution on the back side of the wafer. Figure 2 .and Figure 10 The difference is that the curvature control layer 40 has a different thickness distribution, but the similarity is that the curvature control layer 40 also applies tensile stress to the wafer 100B.
[0065] The thickness of the curvature control layer 40 in the first region WC differs from its thickness in the second region WF. Specifically, the thickness of the curvature control layer 40 in the first region WC is greater than its thickness in the second region WF. Its thickness is non-uniformly distributed, with the central region being thicker than the edge regions. This introduces greater stress into the central region of wafer 100B, causing wafer 100B to bulge further towards the front surface 101, thus improving warpage distribution. Pressing the front surface 101 of the first region WC firmly against the polishing pad enhances the contact between the first region WC and the polishing pad, while maintaining moderate contact pressure between the second region WF and the polishing pad. This ensures less polishing in the outer regions, effectively reducing over-polishing in the outer regions and balancing sufficient polishing in the central region with reasonable polishing in the outer regions.
[0066] exist Figure 11 In this embodiment, a partitioned deposition process can be used to ensure that the stress regulation is located only in the first region, while the curvature regulation layer has a thickness of 0 in the second region. This distribution achieves differentiated stress distribution, thereby saving material costs while precisely controlling the 100B curvature of the wafer.
[0067] It should be noted that, although Figure 11 Ellipses are used to represent the curvature control layer 40 located in the first region WC. However, in the actual deposition process, the thickness of the curvature control layer 40 in its region is theoretically uniform. That is to say, Figure 11The curvature control layer 40 located in the first region WC has a uniform thickness.
[0068] Please see Figure 12 , Figure 12 This is a schematic diagram of the curvature control layer distribution on the back side of the wafer. Figure 2 .and Figure 10 The difference lies in the location of the curvature control layer 40 and the type of stress generated by the curvature control layer 40. Figure 12 The curvature control layer applies compressive stress to wafer 100B.
[0069] The curvature control layer 40 is located on the front side 101 of the wafer 100B. The curvature control layer 40 is used to apply compressive stress to the wafer 100B. The wafer 100B is bent as a whole toward the side away from the thin film (i.e., the curvature control layer 40). Therefore, the wafer 100B is further bent toward the front side 101 to increase the curvature of the wafer 100B.
[0070] It is understandable that the compressive stress is perpendicular to the contact surface between the curvature control layer 40 and the wafer 100B, and points from the curvature control layer 40 side to the wafer 100B side.
[0071] In some embodiments, the curvature control layer 40 is made of silicon oxide and can be deposited using plasma-enhanced chemical vapor deposition (PECVD) to deposit silicon oxide or nitrogen-rich silicon nitride, or a metal thin film (e.g., aluminum, copper, etc.) can be formed using physical sputtering to apply compressive stress to the wafer 100B.
[0072] In some embodiments, the curvature adjustment layer 40 is located only in the second region WF to avoid the curvature adjustment layer 40 affecting the grinding of the electrode layer and mask layer in the first region WC.
[0073] In some embodiments, the curvature adjustment layer 40 may be located simultaneously on the front side 101 and the back side 102. The curvature adjustment layer 40 located on the back side 102 is used to apply tensile stress to the wafer 100B, and the curvature adjustment layer 40 located on the front side 101 is used to apply compressive stress to the wafer 100B. The materials of the curvature adjustment layer 40 located on the front side 101 and the curvature adjustment layer 40 located on the back side 102 may be different.
[0074] Please see Figure 13 , Figure 13 This is a top view schematic diagram of a wafer provided in some embodiments of this application. The wafer includes a first region WC disposed around a center and a second region WF disposed around the first region WC.
[0075] In some embodiments, the second region WF further includes a first sub-region WD and a second sub-region WE, wherein the first sub-region WD is located between the first region WC and the second sub-region WE. That is, the first region WC is the central region, the first sub-region WD is the transition region, and the second sub-region WE is the edge region.
[0076] Taking a 150mm radius wafer as an example, the first region WC is the region with radius R1 from 0 to 40mm, the first sub-region WD is the region with radius R2 from 40mm to 100mm, and the second sub-region WE is the region with radius R3 from 100mm to 150mm.
[0077] Before grinding, the thickness of the electrode layer 11b in the first sub-region WD is greater than the thickness in the second sub-region WE, that is, the thickness of the electrode layer 11b decreases from the center region to the edge region.
[0078] In some embodiments, it can be combined Figure 10 and Figure 13 Corresponding to the gradual change in thickness of the electrode layer 11b, the thickness of the curvature control layer 40 on the back side 102 gradually decreases from the first region WC, the first sub-region WD to the second sub-region WE, thereby achieving precise curvature control of the three regions.
[0079] Specifically, 1) It enables gradient and uniform control of wafer convexity: The thickness of the curvature control layer gradually decreases from the center to the edge, which makes the stress in the central region of the wafer stronger and the stress in the edge region milder. This avoids excessive wafer warping, edge lifting, or uneven deformation caused by excessive edge stress, resulting in a smooth, continuous, and controllable convex shape for the entire wafer facing forward. 2) It improves stress distribution and reduces the risk of edge breakage and interlayer delamination: The uniform and gradual thickness change avoids stress concentration caused by abrupt thickness changes, reducing the risk of cracks, delamination, or film delamination in the wafer edge region, and improving structural stability and yield. 3) It improves the overall flatness and assembly compatibility of the device: The smooth and gradual thickness design makes the wafer surface curvature change continuous, which is beneficial for subsequent packaging, bonding, and other processes, improves the fit with other structures, and reduces assembly stress.
[0080] Step S3: Grind the mask layer M and part of the electrode layer 11b.
[0081] Please see Figure 8 and Figure 14 , Figure 8 This is a schematic diagram of the cross-sectional structure of the semiconductor device after grinding. Figure 14 This is a schematic diagram of the grinding process for wafer 100B.
[0082] A retaining ring 60 surrounds the outer side of the polishing pad 50. Its function is to limit the flow range of the polishing slurry, prevent the polishing slurry from overflowing from the edge of the polishing pad 50, and ensure that the amount of polishing slurry on the surface of the polishing pad 50 is sufficient and evenly distributed. The inner diameter of the retaining ring 60 is precisely matched with the size of the wafer 100B. It fits around the outer periphery of the edge of the wafer 100B and presses down and rotates synchronously with the polishing head 70, confining the wafer 100B within a fixed polishing area and ensuring that the wafer 100B and the polishing pad 50 are aligned.
[0083] The pressure of the polishing head 70 is applied synchronously to the fixing ring 60, causing it to press down onto the surface of the polishing pad 50 at the same time as the edge of the wafer 100B. At this time, the polishing fluid is between the upper surface of the polishing pad 50 and the lower surface of the wafer 100B (front side 101 of the wafer 100B).
[0084] The grinding pressure difference at the edge of wafer 100B can be compensated by adjusting the equipment, thus alleviating the problem of insufficient edge grinding. However, this can lead to over-grinding in the edge area and excessive thickness of the electrode layer in the center area. Therefore, in this application, the curvature of wafer 100B is increased after curvature adjustment to ensure sufficient contact between the center area of wafer 100B and the grinding pad 50, while reducing contact between the outer area and the grinding pad 50. This improves the uniformity of the electrode layer 11b thickness and reduces the depression phenomenon in the outer area structure.
[0085] The method for forming the semiconductor device may further include: etching the memory cell layer 10b to form a plurality of memory cells 10 arranged in an array, as can be referred to Figure 2 In this process, electrode layer 11b is etched to form first electrode 11, and second electrode layer 12b is etched to form second electrode 12.
[0086] Please see Figure 15 and Figure 16 , Figure 15 This is a characterization diagram of the wafer's curvature along the diameter direction before and after the formation of the curvature control layer. Figure 16 This is a comparison diagram of the radial distribution of electrode layer thickness before and after grinding.
[0087] See Figure 15 The horizontal axis represents the radial position of wafer 100B (center is 0, ±150mm to the left and right). The vertical axis represents the curvature value (unit: μm, the more negative the value, the more it bends towards the back side 102, and the more positive the value, the more it bends towards the front side 101). The cloud map below shows the global warp distribution of wafer 100B. In the color scale on the right, red represents positive curvature (convex towards the front side 101), and blue represents negative curvature (concave towards the back side 102), visually displaying the global curvature gradient.
[0088] Looking at the curves, the upper blue / orange dotted line represents the initial curvature before curvature adjustment, with an overall curvature towards the front (101), a relatively small curvature, and an asymmetrical curvature on the left and right sides. The lower yellow dotted line represents the curvature after curvature adjustment, with the central area's curvature significantly shifting towards the front (101) and the edge area's curvature significantly shifting towards the back (102).
[0089] See Figure 16 The horizontal axis represents the radial position of wafer 100B (the center is approximately 60–80 mm), and the vertical axis represents the thickness of electrode layer 11b. The red curve represents the thickness distribution of electrode layer 11b before polishing, and the green curve represents the thickness distribution of electrode layer 11b after the formation of curvature control layer 40 and after polishing.
[0090] Before regulation, the thickness in the central region was significantly higher (approximately 136–142), while the thickness in the peripheral region was lower (approximately 122–128), exhibiting a typical distribution of "thick in the center and thin at the edge".
[0091] After adjustment, the thickness in the central region decreased significantly, while the thickness in the edge region increased, resulting in a more concentrated thickness distribution and less fluctuation across the entire region. This demonstrates the technical effect of more thorough grinding in the central region and suppression of over-grinding in the edge region. The green curve is flatter overall, indicating a significant improvement in the thickness uniformity of electrode layer 11b.
[0092] The method for forming the semiconductor device further includes removing the curvature control layer after grinding.
[0093] The process for removing the curvature control layer may include removing the curvature control layer by wet etching or dry etching.
[0094] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0096] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0097] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A method for forming a semiconductor device, characterized in that, include: A wafer is formed, the wafer including an electrode layer and a mask layer located on the electrode layer, the wafer having a front side and a back side disposed opposite to each other, the front side being the surface of the mask layer facing away from the electrode layer, the wafer including a first region and a second region, the second region being located outside the first region, the electrode layer having a greater thickness in the first region than in the second region, and the first region of the wafer being bent toward the front side; A curvature control layer is formed, the curvature control layer being located on at least one of the front and back sides of the wafer, to increase the curvature of the wafer; The mask layer and part of the electrode layer are polished.
2. The method for forming a semiconductor device according to claim 1, characterized in that, The curvature control layer is located on the back side of the wafer, and the curvature control layer is used to apply tensile stress to the wafer.
3. The method for forming a semiconductor device according to claim 2, characterized in that, The material of the curvature control layer includes silicon nitride.
4. The method for forming a semiconductor device according to claim 1 or 2, characterized in that, The curvature control layer is located on the front side of the wafer, and the curvature control layer is used to apply compressive stress to the wafer.
5. The method for forming a semiconductor device according to claim 4, characterized in that, The material of the curvature control layer located on the front side includes silicon oxide.
6. The method for forming a semiconductor device according to claim 4, characterized in that, The curvature adjustment layer located on the front side is situated in the second region.
7. The method for forming a semiconductor device according to claim 2, characterized in that, The curvature adjustment layer has a thickness greater than or equal to 0 in the second region, and the curvature adjustment layer has a thickness greater than the curvature adjustment layer in the first region.
8. The method for forming a semiconductor device according to claim 7, characterized in that, The second region also includes a first sub-region and a second sub-region, wherein the first sub-region is located between the first region and the second sub-region; Before grinding, the electrode layer is thicker in the first sub-region than in the second sub-region, and the curvature adjustment layer gradually decreases in thickness from the first region, the first sub-region to the second sub-region.
9. The method for forming a semiconductor device according to claim 1, characterized in that, The method for forming the semiconductor device further includes removing the curvature control layer after grinding.
10. A semiconductor device, characterized in that, Formed by the method of forming a semiconductor device according to any one of claims 1 to 9.